1 /* 2 * Marvell 88E6xxx Switch Global 2 Registers support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #ifndef _MV88E6XXX_GLOBAL2_H 16 #define _MV88E6XXX_GLOBAL2_H 17 18 #include "chip.h" 19 20 /* Offset 0x00: Interrupt Source Register */ 21 #define MV88E6XXX_G2_INT_SRC 0x00 22 #define MV88E6XXX_G2_INT_SRC_WDOG 0x8000 23 #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x4000 24 #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000 25 #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x1000 26 #define MV88E6352_G2_INT_SRC_SERDES 0x0800 27 #define MV88E6352_G2_INT_SRC_PHY 0x001f 28 #define MV88E6390_G2_INT_SRC_PHY 0x07fe 29 30 #define MV88E6XXX_G2_INT_SOURCE_WATCHDOG 15 31 32 /* Offset 0x01: Interrupt Mask Register */ 33 #define MV88E6XXX_G2_INT_MASK 0x01 34 #define MV88E6XXX_G2_INT_MASK_WDOG 0x8000 35 #define MV88E6XXX_G2_INT_MASK_JAM_LIMIT 0x4000 36 #define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH 0x2000 37 #define MV88E6XXX_G2_INT_MASK_WAKE_EVENT 0x1000 38 #define MV88E6352_G2_INT_MASK_SERDES 0x0800 39 #define MV88E6352_G2_INT_MASK_PHY 0x001f 40 #define MV88E6390_G2_INT_MASK_PHY 0x07fe 41 42 /* Offset 0x02: MGMT Enable Register 2x */ 43 #define MV88E6XXX_G2_MGMT_EN_2X 0x02 44 45 /* Offset 0x03: MGMT Enable Register 0x */ 46 #define MV88E6XXX_G2_MGMT_EN_0X 0x03 47 48 /* Offset 0x04: Flow Control Delay Register */ 49 #define MV88E6XXX_G2_FLOW_CTL 0x04 50 51 /* Offset 0x05: Switch Management Register */ 52 #define MV88E6XXX_G2_SWITCH_MGMT 0x05 53 #define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA 0x8000 54 #define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS 0x4000 55 #define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x2000 56 #define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080 57 #define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008 58 59 /* Offset 0x06: Device Mapping Table Register */ 60 #define MV88E6XXX_G2_DEVICE_MAPPING 0x06 61 #define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x8000 62 #define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK 0x1f00 63 #define MV88E6352_G2_DEVICE_MAPPING_PORT_MASK 0x000f 64 #define MV88E6390_G2_DEVICE_MAPPING_PORT_MASK 0x001f 65 66 /* Offset 0x07: Trunk Mask Table Register */ 67 #define MV88E6XXX_G2_TRUNK_MASK 0x07 68 #define MV88E6XXX_G2_TRUNK_MASK_UPDATE 0x8000 69 #define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK 0x7000 70 #define MV88E6XXX_G2_TRUNK_MASK_HASH 0x0800 71 72 /* Offset 0x08: Trunk Mapping Table Register */ 73 #define MV88E6XXX_G2_TRUNK_MAPPING 0x08 74 #define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE 0x8000 75 #define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK 0x7800 76 77 /* Offset 0x09: Ingress Rate Command Register */ 78 #define MV88E6XXX_G2_IRL_CMD 0x09 79 #define MV88E6XXX_G2_IRL_CMD_BUSY 0x8000 80 #define MV88E6352_G2_IRL_CMD_OP_MASK 0x7000 81 #define MV88E6352_G2_IRL_CMD_OP_NOOP 0x0000 82 #define MV88E6352_G2_IRL_CMD_OP_INIT_ALL 0x1000 83 #define MV88E6352_G2_IRL_CMD_OP_INIT_RES 0x2000 84 #define MV88E6352_G2_IRL_CMD_OP_WRITE_REG 0x3000 85 #define MV88E6352_G2_IRL_CMD_OP_READ_REG 0x4000 86 #define MV88E6390_G2_IRL_CMD_OP_MASK 0x6000 87 #define MV88E6390_G2_IRL_CMD_OP_READ_REG 0x0000 88 #define MV88E6390_G2_IRL_CMD_OP_INIT_ALL 0x2000 89 #define MV88E6390_G2_IRL_CMD_OP_INIT_RES 0x4000 90 #define MV88E6390_G2_IRL_CMD_OP_WRITE_REG 0x6000 91 #define MV88E6352_G2_IRL_CMD_PORT_MASK 0x0f00 92 #define MV88E6390_G2_IRL_CMD_PORT_MASK 0x1f00 93 #define MV88E6XXX_G2_IRL_CMD_RES_MASK 0x00e0 94 #define MV88E6XXX_G2_IRL_CMD_REG_MASK 0x000f 95 96 /* Offset 0x0A: Ingress Rate Data Register */ 97 #define MV88E6XXX_G2_IRL_DATA 0x0a 98 #define MV88E6XXX_G2_IRL_DATA_MASK 0xffff 99 100 /* Offset 0x0B: Cross-chip Port VLAN Register */ 101 #define MV88E6XXX_G2_PVT_ADDR 0x0b 102 #define MV88E6XXX_G2_PVT_ADDR_BUSY 0x8000 103 #define MV88E6XXX_G2_PVT_ADDR_OP_MASK 0x7000 104 #define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES 0x1000 105 #define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN 0x3000 106 #define MV88E6XXX_G2_PVT_ADDR_OP_READ 0x4000 107 #define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff 108 109 /* Offset 0x0C: Cross-chip Port VLAN Data Register */ 110 #define MV88E6XXX_G2_PVT_DATA 0x0c 111 #define MV88E6XXX_G2_PVT_DATA_MASK 0x7f 112 113 /* Offset 0x0D: Switch MAC/WoL/WoF Register */ 114 #define MV88E6XXX_G2_SWITCH_MAC 0x0d 115 #define MV88E6XXX_G2_SWITCH_MAC_UPDATE 0x8000 116 #define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK 0x1f00 117 #define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK 0x00ff 118 119 /* Offset 0x0E: ATU Stats Register */ 120 #define MV88E6XXX_G2_ATU_STATS 0x0e 121 122 /* Offset 0x0F: Priority Override Table */ 123 #define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f 124 #define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE 0x8000 125 #define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET 0x1000 126 #define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00 127 #define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN 0x0080 128 #define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030 129 #define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN 0x0008 130 #define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK 0x0007 131 132 /* Offset 0x14: EEPROM Command */ 133 #define MV88E6XXX_G2_EEPROM_CMD 0x14 134 #define MV88E6XXX_G2_EEPROM_CMD_BUSY 0x8000 135 #define MV88E6XXX_G2_EEPROM_CMD_OP_MASK 0x7000 136 #define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE 0x3000 137 #define MV88E6XXX_G2_EEPROM_CMD_OP_READ 0x4000 138 #define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD 0x6000 139 #define MV88E6XXX_G2_EEPROM_CMD_RUNNING 0x0800 140 #define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN 0x0400 141 #define MV88E6352_G2_EEPROM_CMD_ADDR_MASK 0x00ff 142 #define MV88E6390_G2_EEPROM_CMD_DATA_MASK 0x00ff 143 144 /* Offset 0x15: EEPROM Data */ 145 #define MV88E6352_G2_EEPROM_DATA 0x15 146 #define MV88E6352_G2_EEPROM_DATA_MASK 0xffff 147 148 /* Offset 0x15: EEPROM Addr */ 149 #define MV88E6390_G2_EEPROM_ADDR 0x15 150 #define MV88E6390_G2_EEPROM_ADDR_MASK 0xffff 151 152 /* Offset 0x16: AVB Command Register */ 153 #define MV88E6352_G2_AVB_CMD 0x16 154 #define MV88E6352_G2_AVB_CMD_BUSY 0x8000 155 #define MV88E6352_G2_AVB_CMD_OP_READ 0x4000 156 #define MV88E6352_G2_AVB_CMD_OP_READ_INCR 0x6000 157 #define MV88E6352_G2_AVB_CMD_OP_WRITE 0x3000 158 #define MV88E6390_G2_AVB_CMD_OP_READ 0x0000 159 #define MV88E6390_G2_AVB_CMD_OP_READ_INCR 0x4000 160 #define MV88E6390_G2_AVB_CMD_OP_WRITE 0x6000 161 #define MV88E6352_G2_AVB_CMD_PORT_MASK 0x0f00 162 #define MV88E6352_G2_AVB_CMD_PORT_TAIGLOBAL 0xe 163 #define MV88E6352_G2_AVB_CMD_PORT_PTPGLOBAL 0xf 164 #define MV88E6390_G2_AVB_CMD_PORT_MASK 0x1f00 165 #define MV88E6390_G2_AVB_CMD_PORT_TAIGLOBAL 0x1e 166 #define MV88E6390_G2_AVB_CMD_PORT_PTPGLOBAL 0x1f 167 #define MV88E6352_G2_AVB_CMD_BLOCK_PTP 0 168 #define MV88E6352_G2_AVB_CMD_BLOCK_AVB 1 169 #define MV88E6352_G2_AVB_CMD_BLOCK_QAV 2 170 #define MV88E6352_G2_AVB_CMD_BLOCK_QVB 3 171 #define MV88E6352_G2_AVB_CMD_BLOCK_MASK 0x00e0 172 #define MV88E6352_G2_AVB_CMD_ADDR_MASK 0x001f 173 174 /* Offset 0x17: AVB Data Register */ 175 #define MV88E6352_G2_AVB_DATA 0x17 176 177 /* Offset 0x18: SMI PHY Command Register */ 178 #define MV88E6XXX_G2_SMI_PHY_CMD 0x18 179 #define MV88E6XXX_G2_SMI_PHY_CMD_BUSY 0x8000 180 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK 0x6000 181 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL 0x0000 182 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL 0x2000 183 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP 0x4000 184 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK 0x1000 185 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45 0x0000 186 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22 0x1000 187 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK 0x0c00 188 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA 0x0400 189 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA 0x0800 190 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR 0x0000 191 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA 0x0400 192 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC 0x0800 193 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA 0x0c00 194 #define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK 0x03e0 195 #define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK 0x001f 196 #define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK 0x03ff 197 198 /* Offset 0x19: SMI PHY Data Register */ 199 #define MV88E6XXX_G2_SMI_PHY_DATA 0x19 200 201 /* Offset 0x1A: Scratch and Misc. Register */ 202 #define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a 203 #define MV88E6XXX_G2_SCRATCH_MISC_UPDATE 0x8000 204 #define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK 0x7f00 205 #define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff 206 207 /* Offset 0x1B: Watch Dog Control Register */ 208 #define MV88E6352_G2_WDOG_CTL 0x1b 209 #define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT 0x0080 210 #define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT 0x0040 211 #define MV88E6352_G2_WDOG_CTL_QC_ENABLE 0x0020 212 #define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY 0x0010 213 #define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE 0x0008 214 #define MV88E6352_G2_WDOG_CTL_FORCE_IRQ 0x0004 215 #define MV88E6352_G2_WDOG_CTL_HISTORY 0x0002 216 #define MV88E6352_G2_WDOG_CTL_SWRESET 0x0001 217 218 /* Offset 0x1B: Watch Dog Control Register */ 219 #define MV88E6390_G2_WDOG_CTL 0x1b 220 #define MV88E6390_G2_WDOG_CTL_UPDATE 0x8000 221 #define MV88E6390_G2_WDOG_CTL_PTR_MASK 0x7f00 222 #define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE 0x0000 223 #define MV88E6390_G2_WDOG_CTL_PTR_INT_STS 0x1000 224 #define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE 0x1100 225 #define MV88E6390_G2_WDOG_CTL_PTR_EVENT 0x1200 226 #define MV88E6390_G2_WDOG_CTL_PTR_HISTORY 0x1300 227 #define MV88E6390_G2_WDOG_CTL_DATA_MASK 0x00ff 228 #define MV88E6390_G2_WDOG_CTL_CUT_THROUGH 0x0008 229 #define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER 0x0004 230 #define MV88E6390_G2_WDOG_CTL_EGRESS 0x0002 231 #define MV88E6390_G2_WDOG_CTL_FORCE_IRQ 0x0001 232 233 /* Offset 0x1C: QoS Weights Register */ 234 #define MV88E6XXX_G2_QOS_WEIGHTS 0x1c 235 #define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE 0x8000 236 #define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK 0x3f00 237 #define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK 0x7f00 238 #define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK 0x00ff 239 240 /* Offset 0x1D: Misc Register */ 241 #define MV88E6XXX_G2_MISC 0x1d 242 #define MV88E6XXX_G2_MISC_5_BIT_PORT 0x4000 243 #define MV88E6352_G2_NOEGR_POLICY 0x2000 244 #define MV88E6390_G2_LAG_ID_4 0x2000 245 246 /* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */ 247 /* Offset 0x02: Misc Configuration */ 248 #define MV88E6352_G2_SCRATCH_MISC_CFG 0x02 249 #define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI 0x80 250 /* Offset 0x60-0x61: GPIO Configuration */ 251 #define MV88E6352_G2_SCRATCH_GPIO_CFG0 0x60 252 #define MV88E6352_G2_SCRATCH_GPIO_CFG1 0x61 253 /* Offset 0x62-0x63: GPIO Direction */ 254 #define MV88E6352_G2_SCRATCH_GPIO_DIR0 0x62 255 #define MV88E6352_G2_SCRATCH_GPIO_DIR1 0x63 256 #define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT 0 257 #define MV88E6352_G2_SCRATCH_GPIO_DIR_IN 1 258 /* Offset 0x64-0x65: GPIO Data */ 259 #define MV88E6352_G2_SCRATCH_GPIO_DATA0 0x64 260 #define MV88E6352_G2_SCRATCH_GPIO_DATA1 0x65 261 /* Offset 0x68-0x6F: GPIO Pin Control */ 262 #define MV88E6352_G2_SCRATCH_GPIO_PCTL0 0x68 263 #define MV88E6352_G2_SCRATCH_GPIO_PCTL1 0x69 264 #define MV88E6352_G2_SCRATCH_GPIO_PCTL2 0x6A 265 #define MV88E6352_G2_SCRATCH_GPIO_PCTL3 0x6B 266 #define MV88E6352_G2_SCRATCH_GPIO_PCTL4 0x6C 267 #define MV88E6352_G2_SCRATCH_GPIO_PCTL5 0x6D 268 #define MV88E6352_G2_SCRATCH_GPIO_PCTL6 0x6E 269 #define MV88E6352_G2_SCRATCH_GPIO_PCTL7 0x6F 270 #define MV88E6352_G2_SCRATCH_CONFIG_DATA0 0x70 271 #define MV88E6352_G2_SCRATCH_CONFIG_DATA1 0x71 272 #define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU BIT(2) 273 #define MV88E6352_G2_SCRATCH_CONFIG_DATA2 0x72 274 #define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK 0x3 275 276 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO 0 277 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG 1 278 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ 2 279 280 #ifdef CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 281 282 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip) 283 { 284 return 0; 285 } 286 287 int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); 288 int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val); 289 int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update); 290 int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask); 291 292 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 293 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 294 295 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, 296 struct mii_bus *bus, 297 int addr, int reg, u16 *val); 298 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, 299 struct mii_bus *bus, 300 int addr, int reg, u16 val); 301 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr); 302 303 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, 304 struct ethtool_eeprom *eeprom, u8 *data); 305 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, 306 struct ethtool_eeprom *eeprom, u8 *data); 307 308 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, 309 struct ethtool_eeprom *eeprom, u8 *data); 310 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 311 struct ethtool_eeprom *eeprom, u8 *data); 312 313 int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev, 314 int src_port, u16 data); 315 int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip); 316 317 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip); 318 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip); 319 320 int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip, 321 struct mii_bus *bus); 322 void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip, 323 struct mii_bus *bus); 324 325 int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 326 int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 327 328 int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip); 329 330 int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip); 331 332 int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target, 333 int port); 334 335 extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops; 336 extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops; 337 338 extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops; 339 extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops; 340 341 extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops; 342 343 int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, 344 bool external); 345 346 #else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */ 347 348 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip) 349 { 350 if (chip->info->global2_addr) { 351 dev_err(chip->dev, "this chip requires CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 enabled\n"); 352 return -EOPNOTSUPP; 353 } 354 355 return 0; 356 } 357 358 static inline int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 359 { 360 return -EOPNOTSUPP; 361 } 362 363 static inline int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 364 { 365 return -EOPNOTSUPP; 366 } 367 368 static inline int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update) 369 { 370 return -EOPNOTSUPP; 371 } 372 373 static inline int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask) 374 { 375 return -EOPNOTSUPP; 376 } 377 378 static inline int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, 379 int port) 380 { 381 return -EOPNOTSUPP; 382 } 383 384 static inline int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, 385 int port) 386 { 387 return -EOPNOTSUPP; 388 } 389 390 static inline int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, 391 struct mii_bus *bus, 392 int addr, int reg, u16 *val) 393 { 394 return -EOPNOTSUPP; 395 } 396 397 static inline int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, 398 struct mii_bus *bus, 399 int addr, int reg, u16 val) 400 { 401 return -EOPNOTSUPP; 402 } 403 404 static inline int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, 405 u8 *addr) 406 { 407 return -EOPNOTSUPP; 408 } 409 410 static inline int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, 411 struct ethtool_eeprom *eeprom, 412 u8 *data) 413 { 414 return -EOPNOTSUPP; 415 } 416 417 static inline int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, 418 struct ethtool_eeprom *eeprom, 419 u8 *data) 420 { 421 return -EOPNOTSUPP; 422 } 423 424 static inline int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, 425 struct ethtool_eeprom *eeprom, 426 u8 *data) 427 { 428 return -EOPNOTSUPP; 429 } 430 431 static inline int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 432 struct ethtool_eeprom *eeprom, 433 u8 *data) 434 { 435 return -EOPNOTSUPP; 436 } 437 438 static inline int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, 439 int src_dev, int src_port, u16 data) 440 { 441 return -EOPNOTSUPP; 442 } 443 444 static inline int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip) 445 { 446 return -EOPNOTSUPP; 447 } 448 449 static inline int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip) 450 { 451 return -EOPNOTSUPP; 452 } 453 454 static inline void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip) 455 { 456 } 457 458 static inline int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip, 459 struct mii_bus *bus) 460 { 461 return 0; 462 } 463 464 static inline void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip, 465 struct mii_bus *bus) 466 { 467 } 468 469 static inline int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 470 { 471 return -EOPNOTSUPP; 472 } 473 474 static inline int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 475 { 476 return -EOPNOTSUPP; 477 } 478 479 static inline int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip) 480 { 481 return -EOPNOTSUPP; 482 } 483 484 static const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {}; 485 static const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {}; 486 487 static const struct mv88e6xxx_avb_ops mv88e6352_avb_ops = {}; 488 static const struct mv88e6xxx_avb_ops mv88e6390_avb_ops = {}; 489 490 static const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops = {}; 491 492 static inline int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, 493 bool external) 494 { 495 return -EOPNOTSUPP; 496 } 497 498 static inline int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip) 499 { 500 return -EOPNOTSUPP; 501 } 502 503 static inline int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, 504 int target, int port) 505 { 506 return -EOPNOTSUPP; 507 } 508 509 #endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */ 510 511 #endif /* _MV88E6XXX_GLOBAL2_H */ 512