1 /* 2 * Marvell 88E6xxx Switch Global 2 Registers support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #ifndef _MV88E6XXX_GLOBAL2_H 16 #define _MV88E6XXX_GLOBAL2_H 17 18 #include "chip.h" 19 20 #define MV88E6XXX_G2 0x1c 21 22 /* Offset 0x00: Interrupt Source Register */ 23 #define MV88E6XXX_G2_INT_SOURCE 0x00 24 #define MV88E6XXX_G2_INT_SOURCE_WATCHDOG 15 25 26 /* Offset 0x01: Interrupt Mask Register */ 27 #define MV88E6XXX_G2_INT_MASK 0x01 28 29 /* Offset 0x02: MGMT Enable Register 2x */ 30 #define MV88E6XXX_G2_MGMT_EN_2X 0x02 31 32 /* Offset 0x03: MGMT Enable Register 0x */ 33 #define MV88E6XXX_G2_MGMT_EN_0X 0x03 34 35 /* Offset 0x04: Flow Control Delay Register */ 36 #define MV88E6XXX_G2_FLOW_CTL 0x04 37 38 /* Offset 0x05: Switch Management Register */ 39 #define MV88E6XXX_G2_SWITCH_MGMT 0x05 40 #define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA 0x8000 41 #define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS 0x4000 42 #define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x2000 43 #define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080 44 #define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008 45 46 /* Offset 0x06: Device Mapping Table Register */ 47 #define MV88E6XXX_G2_DEVICE_MAPPING 0x06 48 #define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x8000 49 #define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK 0x1f00 50 #define MV88E6XXX_G2_DEVICE_MAPPING_PORT_MASK 0x000f 51 52 /* Offset 0x07: Trunk Mask Table Register */ 53 #define MV88E6XXX_G2_TRUNK_MASK 0x07 54 #define MV88E6XXX_G2_TRUNK_MASK_UPDATE 0x8000 55 #define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK 0x7000 56 #define MV88E6XXX_G2_TRUNK_MASK_HASH 0x0800 57 58 /* Offset 0x08: Trunk Mapping Table Register */ 59 #define MV88E6XXX_G2_TRUNK_MAPPING 0x08 60 #define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE 0x8000 61 #define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK 0x7800 62 63 /* Offset 0x09: Ingress Rate Command Register */ 64 #define MV88E6XXX_G2_IRL_CMD 0x09 65 #define MV88E6XXX_G2_IRL_CMD_BUSY 0x8000 66 #define MV88E6352_G2_IRL_CMD_OP_MASK 0x7000 67 #define MV88E6352_G2_IRL_CMD_OP_NOOP 0x0000 68 #define MV88E6352_G2_IRL_CMD_OP_INIT_ALL 0x1000 69 #define MV88E6352_G2_IRL_CMD_OP_INIT_RES 0x2000 70 #define MV88E6352_G2_IRL_CMD_OP_WRITE_REG 0x3000 71 #define MV88E6352_G2_IRL_CMD_OP_READ_REG 0x4000 72 #define MV88E6390_G2_IRL_CMD_OP_MASK 0x6000 73 #define MV88E6390_G2_IRL_CMD_OP_READ_REG 0x0000 74 #define MV88E6390_G2_IRL_CMD_OP_INIT_ALL 0x2000 75 #define MV88E6390_G2_IRL_CMD_OP_INIT_RES 0x4000 76 #define MV88E6390_G2_IRL_CMD_OP_WRITE_REG 0x6000 77 #define MV88E6352_G2_IRL_CMD_PORT_MASK 0x0f00 78 #define MV88E6390_G2_IRL_CMD_PORT_MASK 0x1f00 79 #define MV88E6XXX_G2_IRL_CMD_RES_MASK 0x00e0 80 #define MV88E6XXX_G2_IRL_CMD_REG_MASK 0x000f 81 82 /* Offset 0x0A: Ingress Rate Data Register */ 83 #define MV88E6XXX_G2_IRL_DATA 0x0a 84 #define MV88E6XXX_G2_IRL_DATA_MASK 0xffff 85 86 /* Offset 0x0B: Cross-chip Port VLAN Register */ 87 #define MV88E6XXX_G2_PVT_ADDR 0x0b 88 #define MV88E6XXX_G2_PVT_ADDR_BUSY 0x8000 89 #define MV88E6XXX_G2_PVT_ADDR_OP_MASK 0x7000 90 #define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES 0x1000 91 #define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN 0x3000 92 #define MV88E6XXX_G2_PVT_ADDR_OP_READ 0x4000 93 #define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff 94 95 /* Offset 0x0C: Cross-chip Port VLAN Data Register */ 96 #define MV88E6XXX_G2_PVT_DATA 0x0c 97 #define MV88E6XXX_G2_PVT_DATA_MASK 0x7f 98 99 /* Offset 0x0D: Switch MAC/WoL/WoF Register */ 100 #define MV88E6XXX_G2_SWITCH_MAC 0x0d 101 #define MV88E6XXX_G2_SWITCH_MAC_UPDATE 0x8000 102 #define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK 0x1f00 103 #define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK 0x00ff 104 105 /* Offset 0x0E: ATU Stats Register */ 106 #define MV88E6XXX_G2_ATU_STATS 0x0e 107 108 /* Offset 0x0F: Priority Override Table */ 109 #define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f 110 #define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE 0x8000 111 #define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET 0x1000 112 #define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00 113 #define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN 0x0080 114 #define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030 115 #define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN 0x0008 116 #define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK 0x0007 117 118 /* Offset 0x14: EEPROM Command */ 119 #define MV88E6XXX_G2_EEPROM_CMD 0x14 120 #define MV88E6XXX_G2_EEPROM_CMD_BUSY 0x8000 121 #define MV88E6XXX_G2_EEPROM_CMD_OP_MASK 0x7000 122 #define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE 0x3000 123 #define MV88E6XXX_G2_EEPROM_CMD_OP_READ 0x4000 124 #define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD 0x6000 125 #define MV88E6XXX_G2_EEPROM_CMD_RUNNING 0x0800 126 #define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN 0x0400 127 #define MV88E6352_G2_EEPROM_CMD_ADDR_MASK 0x00ff 128 #define MV88E6390_G2_EEPROM_CMD_DATA_MASK 0x00ff 129 130 /* Offset 0x15: EEPROM Data */ 131 #define MV88E6352_G2_EEPROM_DATA 0x15 132 #define MV88E6352_G2_EEPROM_DATA_MASK 0xffff 133 134 /* Offset 0x15: EEPROM Addr */ 135 #define MV88E6390_G2_EEPROM_ADDR 0x15 136 #define MV88E6390_G2_EEPROM_ADDR_MASK 0xffff 137 138 /* Offset 0x16: AVB Command Register */ 139 #define MV88E6352_G2_AVB_CMD 0x16 140 141 /* Offset 0x17: AVB Data Register */ 142 #define MV88E6352_G2_AVB_DATA 0x17 143 144 /* Offset 0x18: SMI PHY Command Register */ 145 #define MV88E6XXX_G2_SMI_PHY_CMD 0x18 146 #define MV88E6XXX_G2_SMI_PHY_CMD_BUSY 0x8000 147 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK 0x6000 148 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL 0x0000 149 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL 0x2000 150 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP 0x4000 151 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK 0x1000 152 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45 0x0000 153 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22 0x1000 154 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK 0x0c00 155 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA 0x0400 156 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA 0x0800 157 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR 0x0000 158 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA 0x0400 159 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC 0x0800 160 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA 0x0c00 161 #define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK 0x03e0 162 #define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK 0x001f 163 #define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK 0x03ff 164 165 /* Offset 0x19: SMI PHY Data Register */ 166 #define MV88E6XXX_G2_SMI_PHY_DATA 0x19 167 168 /* Offset 0x1A: Scratch and Misc. Register */ 169 #define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a 170 #define MV88E6XXX_G2_SCRATCH_MISC_UPDATE 0x8000 171 #define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK 0x7f00 172 #define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff 173 174 /* Offset 0x1B: Watch Dog Control Register */ 175 #define MV88E6352_G2_WDOG_CTL 0x1b 176 #define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT 0x0080 177 #define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT 0x0040 178 #define MV88E6352_G2_WDOG_CTL_QC_ENABLE 0x0020 179 #define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY 0x0010 180 #define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE 0x0008 181 #define MV88E6352_G2_WDOG_CTL_FORCE_IRQ 0x0004 182 #define MV88E6352_G2_WDOG_CTL_HISTORY 0x0002 183 #define MV88E6352_G2_WDOG_CTL_SWRESET 0x0001 184 185 /* Offset 0x1B: Watch Dog Control Register */ 186 #define MV88E6390_G2_WDOG_CTL 0x1b 187 #define MV88E6390_G2_WDOG_CTL_UPDATE 0x8000 188 #define MV88E6390_G2_WDOG_CTL_PTR_MASK 0x7f00 189 #define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE 0x0000 190 #define MV88E6390_G2_WDOG_CTL_PTR_INT_STS 0x1000 191 #define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE 0x1100 192 #define MV88E6390_G2_WDOG_CTL_PTR_EVENT 0x1200 193 #define MV88E6390_G2_WDOG_CTL_PTR_HISTORY 0x1300 194 #define MV88E6390_G2_WDOG_CTL_DATA_MASK 0x00ff 195 #define MV88E6390_G2_WDOG_CTL_CUT_THROUGH 0x0008 196 #define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER 0x0004 197 #define MV88E6390_G2_WDOG_CTL_EGRESS 0x0002 198 #define MV88E6390_G2_WDOG_CTL_FORCE_IRQ 0x0001 199 200 /* Offset 0x1C: QoS Weights Register */ 201 #define MV88E6XXX_G2_QOS_WEIGHTS 0x1c 202 #define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE 0x8000 203 #define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK 0x3f00 204 #define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK 0x7f00 205 #define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK 0x00ff 206 207 /* Offset 0x1D: Misc Register */ 208 #define MV88E6XXX_G2_MISC 0x1d 209 #define MV88E6XXX_G2_MISC_5_BIT_PORT 0x4000 210 #define MV88E6352_G2_NOEGR_POLICY 0x2000 211 #define MV88E6390_G2_LAG_ID_4 0x2000 212 213 #ifdef CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 214 215 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip) 216 { 217 return 0; 218 } 219 220 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 221 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 222 223 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, 224 struct mii_bus *bus, 225 int addr, int reg, u16 *val); 226 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, 227 struct mii_bus *bus, 228 int addr, int reg, u16 val); 229 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr); 230 231 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, 232 struct ethtool_eeprom *eeprom, u8 *data); 233 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, 234 struct ethtool_eeprom *eeprom, u8 *data); 235 236 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, 237 struct ethtool_eeprom *eeprom, u8 *data); 238 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 239 struct ethtool_eeprom *eeprom, u8 *data); 240 241 int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev, 242 int src_port, u16 data); 243 int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip); 244 245 int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip); 246 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip); 247 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip); 248 int mv88e6095_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 249 250 extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops; 251 extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops; 252 253 #else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */ 254 255 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip) 256 { 257 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) { 258 dev_err(chip->dev, "this chip requires CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 enabled\n"); 259 return -EOPNOTSUPP; 260 } 261 262 return 0; 263 } 264 265 static inline int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, 266 int port) 267 { 268 return -EOPNOTSUPP; 269 } 270 271 static inline int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, 272 int port) 273 { 274 return -EOPNOTSUPP; 275 } 276 277 static inline int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, 278 struct mii_bus *bus, 279 int addr, int reg, u16 *val) 280 { 281 return -EOPNOTSUPP; 282 } 283 284 static inline int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, 285 struct mii_bus *bus, 286 int addr, int reg, u16 val) 287 { 288 return -EOPNOTSUPP; 289 } 290 291 static inline int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, 292 u8 *addr) 293 { 294 return -EOPNOTSUPP; 295 } 296 297 static inline int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, 298 struct ethtool_eeprom *eeprom, 299 u8 *data) 300 { 301 return -EOPNOTSUPP; 302 } 303 304 static inline int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, 305 struct ethtool_eeprom *eeprom, 306 u8 *data) 307 { 308 return -EOPNOTSUPP; 309 } 310 311 static inline int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, 312 struct ethtool_eeprom *eeprom, 313 u8 *data) 314 { 315 return -EOPNOTSUPP; 316 } 317 318 static inline int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 319 struct ethtool_eeprom *eeprom, 320 u8 *data) 321 { 322 return -EOPNOTSUPP; 323 } 324 325 static inline int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, 326 int src_dev, int src_port, u16 data) 327 { 328 return -EOPNOTSUPP; 329 } 330 331 static inline int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip) 332 { 333 return -EOPNOTSUPP; 334 } 335 336 static inline int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip) 337 { 338 return -EOPNOTSUPP; 339 } 340 341 static inline int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip) 342 { 343 return -EOPNOTSUPP; 344 } 345 346 static inline void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip) 347 { 348 } 349 350 static inline int mv88e6095_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 351 { 352 return -EOPNOTSUPP; 353 } 354 355 static const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {}; 356 static const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {}; 357 358 #endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */ 359 360 #endif /* _MV88E6XXX_GLOBAL2_H */ 361