1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Switch Global 2 Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11 #ifndef _MV88E6XXX_GLOBAL2_H 12 #define _MV88E6XXX_GLOBAL2_H 13 14 #include "chip.h" 15 16 /* Offset 0x00: Interrupt Source Register */ 17 #define MV88E6XXX_G2_INT_SRC 0x00 18 #define MV88E6XXX_G2_INT_SRC_WDOG 0x8000 19 #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x4000 20 #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000 21 #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x1000 22 #define MV88E6352_G2_INT_SRC_SERDES 0x0800 23 #define MV88E6352_G2_INT_SRC_PHY 0x001f 24 #define MV88E6390_G2_INT_SRC_PHY 0x07fe 25 26 #define MV88E6XXX_G2_INT_SOURCE_WATCHDOG 15 27 28 /* Offset 0x01: Interrupt Mask Register */ 29 #define MV88E6XXX_G2_INT_MASK 0x01 30 #define MV88E6XXX_G2_INT_MASK_WDOG 0x8000 31 #define MV88E6XXX_G2_INT_MASK_JAM_LIMIT 0x4000 32 #define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH 0x2000 33 #define MV88E6XXX_G2_INT_MASK_WAKE_EVENT 0x1000 34 #define MV88E6352_G2_INT_MASK_SERDES 0x0800 35 #define MV88E6352_G2_INT_MASK_PHY 0x001f 36 #define MV88E6390_G2_INT_MASK_PHY 0x07fe 37 38 /* Offset 0x02: MGMT Enable Register 2x */ 39 #define MV88E6XXX_G2_MGMT_EN_2X 0x02 40 41 /* Offset 0x03: MGMT Enable Register 0x */ 42 #define MV88E6XXX_G2_MGMT_EN_0X 0x03 43 44 /* Offset 0x04: Flow Control Delay Register */ 45 #define MV88E6XXX_G2_FLOW_CTL 0x04 46 47 /* Offset 0x05: Switch Management Register */ 48 #define MV88E6XXX_G2_SWITCH_MGMT 0x05 49 #define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA 0x8000 50 #define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS 0x4000 51 #define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x2000 52 #define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080 53 #define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008 54 55 /* Offset 0x06: Device Mapping Table Register */ 56 #define MV88E6XXX_G2_DEVICE_MAPPING 0x06 57 #define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x8000 58 #define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK 0x1f00 59 #define MV88E6352_G2_DEVICE_MAPPING_PORT_MASK 0x000f 60 #define MV88E6390_G2_DEVICE_MAPPING_PORT_MASK 0x001f 61 62 /* Offset 0x07: Trunk Mask Table Register */ 63 #define MV88E6XXX_G2_TRUNK_MASK 0x07 64 #define MV88E6XXX_G2_TRUNK_MASK_UPDATE 0x8000 65 #define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK 0x7000 66 #define MV88E6XXX_G2_TRUNK_MASK_HASH 0x0800 67 68 /* Offset 0x08: Trunk Mapping Table Register */ 69 #define MV88E6XXX_G2_TRUNK_MAPPING 0x08 70 #define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE 0x8000 71 #define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK 0x7800 72 73 /* Offset 0x09: Ingress Rate Command Register */ 74 #define MV88E6XXX_G2_IRL_CMD 0x09 75 #define MV88E6XXX_G2_IRL_CMD_BUSY 0x8000 76 #define MV88E6352_G2_IRL_CMD_OP_MASK 0x7000 77 #define MV88E6352_G2_IRL_CMD_OP_NOOP 0x0000 78 #define MV88E6352_G2_IRL_CMD_OP_INIT_ALL 0x1000 79 #define MV88E6352_G2_IRL_CMD_OP_INIT_RES 0x2000 80 #define MV88E6352_G2_IRL_CMD_OP_WRITE_REG 0x3000 81 #define MV88E6352_G2_IRL_CMD_OP_READ_REG 0x4000 82 #define MV88E6390_G2_IRL_CMD_OP_MASK 0x6000 83 #define MV88E6390_G2_IRL_CMD_OP_READ_REG 0x0000 84 #define MV88E6390_G2_IRL_CMD_OP_INIT_ALL 0x2000 85 #define MV88E6390_G2_IRL_CMD_OP_INIT_RES 0x4000 86 #define MV88E6390_G2_IRL_CMD_OP_WRITE_REG 0x6000 87 #define MV88E6352_G2_IRL_CMD_PORT_MASK 0x0f00 88 #define MV88E6390_G2_IRL_CMD_PORT_MASK 0x1f00 89 #define MV88E6XXX_G2_IRL_CMD_RES_MASK 0x00e0 90 #define MV88E6XXX_G2_IRL_CMD_REG_MASK 0x000f 91 92 /* Offset 0x0A: Ingress Rate Data Register */ 93 #define MV88E6XXX_G2_IRL_DATA 0x0a 94 #define MV88E6XXX_G2_IRL_DATA_MASK 0xffff 95 96 /* Offset 0x0B: Cross-chip Port VLAN Register */ 97 #define MV88E6XXX_G2_PVT_ADDR 0x0b 98 #define MV88E6XXX_G2_PVT_ADDR_BUSY 0x8000 99 #define MV88E6XXX_G2_PVT_ADDR_OP_MASK 0x7000 100 #define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES 0x1000 101 #define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN 0x3000 102 #define MV88E6XXX_G2_PVT_ADDR_OP_READ 0x4000 103 #define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff 104 #define MV88E6XXX_G2_PVT_ADRR_DEV_TRUNK 0x1f 105 106 /* Offset 0x0C: Cross-chip Port VLAN Data Register */ 107 #define MV88E6XXX_G2_PVT_DATA 0x0c 108 #define MV88E6XXX_G2_PVT_DATA_MASK 0x7f 109 110 /* Offset 0x0D: Switch MAC/WoL/WoF Register */ 111 #define MV88E6XXX_G2_SWITCH_MAC 0x0d 112 #define MV88E6XXX_G2_SWITCH_MAC_UPDATE 0x8000 113 #define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK 0x1f00 114 #define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK 0x00ff 115 116 /* Offset 0x0E: ATU Stats Register */ 117 #define MV88E6XXX_G2_ATU_STATS 0x0e 118 #define MV88E6XXX_G2_ATU_STATS_BIN_0 (0x0 << 14) 119 #define MV88E6XXX_G2_ATU_STATS_BIN_1 (0x1 << 14) 120 #define MV88E6XXX_G2_ATU_STATS_BIN_2 (0x2 << 14) 121 #define MV88E6XXX_G2_ATU_STATS_BIN_3 (0x3 << 14) 122 #define MV88E6XXX_G2_ATU_STATS_MODE_ALL (0x0 << 12) 123 #define MV88E6XXX_G2_ATU_STATS_MODE_ALL_DYNAMIC (0x1 << 12) 124 #define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL (0x2 << 12) 125 #define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL_DYNAMIC (0x3 << 12) 126 #define MV88E6XXX_G2_ATU_STATS_MASK 0x0fff 127 128 /* Offset 0x0F: Priority Override Table */ 129 #define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f 130 #define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE 0x8000 131 #define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET 0x1000 132 #define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00 133 #define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN 0x0080 134 #define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030 135 #define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN 0x0008 136 #define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK 0x0007 137 138 /* Offset 0x14: EEPROM Command */ 139 #define MV88E6XXX_G2_EEPROM_CMD 0x14 140 #define MV88E6XXX_G2_EEPROM_CMD_BUSY 0x8000 141 #define MV88E6XXX_G2_EEPROM_CMD_OP_MASK 0x7000 142 #define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE 0x3000 143 #define MV88E6XXX_G2_EEPROM_CMD_OP_READ 0x4000 144 #define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD 0x6000 145 #define MV88E6XXX_G2_EEPROM_CMD_RUNNING 0x0800 146 #define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN 0x0400 147 #define MV88E6352_G2_EEPROM_CMD_ADDR_MASK 0x00ff 148 #define MV88E6390_G2_EEPROM_CMD_DATA_MASK 0x00ff 149 150 /* Offset 0x15: EEPROM Data */ 151 #define MV88E6352_G2_EEPROM_DATA 0x15 152 #define MV88E6352_G2_EEPROM_DATA_MASK 0xffff 153 154 /* Offset 0x15: EEPROM Addr */ 155 #define MV88E6390_G2_EEPROM_ADDR 0x15 156 #define MV88E6390_G2_EEPROM_ADDR_MASK 0xffff 157 158 /* Offset 0x16: AVB Command Register */ 159 #define MV88E6352_G2_AVB_CMD 0x16 160 #define MV88E6352_G2_AVB_CMD_BUSY 0x8000 161 #define MV88E6352_G2_AVB_CMD_OP_READ 0x4000 162 #define MV88E6352_G2_AVB_CMD_OP_READ_INCR 0x6000 163 #define MV88E6352_G2_AVB_CMD_OP_WRITE 0x3000 164 #define MV88E6390_G2_AVB_CMD_OP_READ 0x0000 165 #define MV88E6390_G2_AVB_CMD_OP_READ_INCR 0x4000 166 #define MV88E6390_G2_AVB_CMD_OP_WRITE 0x6000 167 #define MV88E6352_G2_AVB_CMD_PORT_MASK 0x0f00 168 #define MV88E6352_G2_AVB_CMD_PORT_TAIGLOBAL 0xe 169 #define MV88E6165_G2_AVB_CMD_PORT_PTPGLOBAL 0xf 170 #define MV88E6352_G2_AVB_CMD_PORT_PTPGLOBAL 0xf 171 #define MV88E6390_G2_AVB_CMD_PORT_MASK 0x1f00 172 #define MV88E6390_G2_AVB_CMD_PORT_TAIGLOBAL 0x1e 173 #define MV88E6390_G2_AVB_CMD_PORT_PTPGLOBAL 0x1f 174 #define MV88E6352_G2_AVB_CMD_BLOCK_PTP 0 175 #define MV88E6352_G2_AVB_CMD_BLOCK_AVB 1 176 #define MV88E6352_G2_AVB_CMD_BLOCK_QAV 2 177 #define MV88E6352_G2_AVB_CMD_BLOCK_QVB 3 178 #define MV88E6352_G2_AVB_CMD_BLOCK_MASK 0x00e0 179 #define MV88E6352_G2_AVB_CMD_ADDR_MASK 0x001f 180 181 /* Offset 0x17: AVB Data Register */ 182 #define MV88E6352_G2_AVB_DATA 0x17 183 184 /* Offset 0x18: SMI PHY Command Register */ 185 #define MV88E6XXX_G2_SMI_PHY_CMD 0x18 186 #define MV88E6XXX_G2_SMI_PHY_CMD_BUSY 0x8000 187 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK 0x6000 188 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL 0x0000 189 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL 0x2000 190 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP 0x4000 191 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK 0x1000 192 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45 0x0000 193 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22 0x1000 194 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK 0x0c00 195 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA 0x0400 196 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA 0x0800 197 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR 0x0000 198 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA 0x0400 199 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC 0x0800 200 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA 0x0c00 201 #define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK 0x03e0 202 #define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK 0x001f 203 #define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK 0x03ff 204 205 /* Offset 0x19: SMI PHY Data Register */ 206 #define MV88E6XXX_G2_SMI_PHY_DATA 0x19 207 208 /* Offset 0x1A: Scratch and Misc. Register */ 209 #define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a 210 #define MV88E6XXX_G2_SCRATCH_MISC_UPDATE 0x8000 211 #define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK 0x7f00 212 #define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff 213 214 /* Offset 0x1B: Watch Dog Control Register */ 215 #define MV88E6250_G2_WDOG_CTL 0x1b 216 #define MV88E6250_G2_WDOG_CTL_QC_HISTORY 0x0100 217 #define MV88E6250_G2_WDOG_CTL_QC_EVENT 0x0080 218 #define MV88E6250_G2_WDOG_CTL_QC_ENABLE 0x0040 219 #define MV88E6250_G2_WDOG_CTL_EGRESS_HISTORY 0x0020 220 #define MV88E6250_G2_WDOG_CTL_EGRESS_EVENT 0x0010 221 #define MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE 0x0008 222 #define MV88E6250_G2_WDOG_CTL_FORCE_IRQ 0x0004 223 #define MV88E6250_G2_WDOG_CTL_HISTORY 0x0002 224 #define MV88E6250_G2_WDOG_CTL_SWRESET 0x0001 225 226 /* Offset 0x1B: Watch Dog Control Register */ 227 #define MV88E6352_G2_WDOG_CTL 0x1b 228 #define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT 0x0080 229 #define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT 0x0040 230 #define MV88E6352_G2_WDOG_CTL_QC_ENABLE 0x0020 231 #define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY 0x0010 232 #define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE 0x0008 233 #define MV88E6352_G2_WDOG_CTL_FORCE_IRQ 0x0004 234 #define MV88E6352_G2_WDOG_CTL_HISTORY 0x0002 235 #define MV88E6352_G2_WDOG_CTL_SWRESET 0x0001 236 237 /* Offset 0x1B: Watch Dog Control Register */ 238 #define MV88E6390_G2_WDOG_CTL 0x1b 239 #define MV88E6390_G2_WDOG_CTL_UPDATE 0x8000 240 #define MV88E6390_G2_WDOG_CTL_PTR_MASK 0x7f00 241 #define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE 0x0000 242 #define MV88E6390_G2_WDOG_CTL_PTR_INT_STS 0x1000 243 #define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE 0x1100 244 #define MV88E6390_G2_WDOG_CTL_PTR_EVENT 0x1200 245 #define MV88E6390_G2_WDOG_CTL_PTR_HISTORY 0x1300 246 #define MV88E6390_G2_WDOG_CTL_DATA_MASK 0x00ff 247 #define MV88E6390_G2_WDOG_CTL_CUT_THROUGH 0x0008 248 #define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER 0x0004 249 #define MV88E6390_G2_WDOG_CTL_EGRESS 0x0002 250 #define MV88E6390_G2_WDOG_CTL_FORCE_IRQ 0x0001 251 252 /* Offset 0x1C: QoS Weights Register */ 253 #define MV88E6XXX_G2_QOS_WEIGHTS 0x1c 254 #define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE 0x8000 255 #define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK 0x3f00 256 #define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK 0x7f00 257 #define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK 0x00ff 258 259 /* Offset 0x1D: Misc Register */ 260 #define MV88E6XXX_G2_MISC 0x1d 261 #define MV88E6XXX_G2_MISC_5_BIT_PORT 0x4000 262 #define MV88E6352_G2_NOEGR_POLICY 0x2000 263 #define MV88E6390_G2_LAG_ID_4 0x2000 264 265 /* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */ 266 /* Offset 0x02: Misc Configuration */ 267 #define MV88E6352_G2_SCRATCH_MISC_CFG 0x02 268 #define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI 0x80 269 /* Offset 0x60-0x61: GPIO Configuration */ 270 #define MV88E6352_G2_SCRATCH_GPIO_CFG0 0x60 271 #define MV88E6352_G2_SCRATCH_GPIO_CFG1 0x61 272 /* Offset 0x62-0x63: GPIO Direction */ 273 #define MV88E6352_G2_SCRATCH_GPIO_DIR0 0x62 274 #define MV88E6352_G2_SCRATCH_GPIO_DIR1 0x63 275 #define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT 0 276 #define MV88E6352_G2_SCRATCH_GPIO_DIR_IN 1 277 /* Offset 0x64-0x65: GPIO Data */ 278 #define MV88E6352_G2_SCRATCH_GPIO_DATA0 0x64 279 #define MV88E6352_G2_SCRATCH_GPIO_DATA1 0x65 280 /* Offset 0x68-0x6F: GPIO Pin Control */ 281 #define MV88E6352_G2_SCRATCH_GPIO_PCTL0 0x68 282 #define MV88E6352_G2_SCRATCH_GPIO_PCTL1 0x69 283 #define MV88E6352_G2_SCRATCH_GPIO_PCTL2 0x6A 284 #define MV88E6352_G2_SCRATCH_GPIO_PCTL3 0x6B 285 #define MV88E6352_G2_SCRATCH_GPIO_PCTL4 0x6C 286 #define MV88E6352_G2_SCRATCH_GPIO_PCTL5 0x6D 287 #define MV88E6352_G2_SCRATCH_GPIO_PCTL6 0x6E 288 #define MV88E6352_G2_SCRATCH_GPIO_PCTL7 0x6F 289 #define MV88E6352_G2_SCRATCH_CONFIG_DATA0 0x70 290 #define MV88E6352_G2_SCRATCH_CONFIG_DATA1 0x71 291 #define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU BIT(2) 292 #define MV88E6352_G2_SCRATCH_CONFIG_DATA2 0x72 293 #define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK 0x3 294 295 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO 0 296 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG 1 297 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ 2 298 299 int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); 300 int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val); 301 int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg, 302 int bit, int val); 303 304 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 305 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 306 307 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, 308 struct mii_bus *bus, 309 int addr, int reg, u16 *val); 310 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, 311 struct mii_bus *bus, 312 int addr, int reg, u16 val); 313 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr); 314 315 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, 316 struct ethtool_eeprom *eeprom, u8 *data); 317 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, 318 struct ethtool_eeprom *eeprom, u8 *data); 319 320 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, 321 struct ethtool_eeprom *eeprom, u8 *data); 322 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 323 struct ethtool_eeprom *eeprom, u8 *data); 324 325 int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev, 326 int src_port, u16 data); 327 int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip); 328 329 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip); 330 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip); 331 332 int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip, 333 struct mii_bus *bus); 334 void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip, 335 struct mii_bus *bus); 336 337 int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 338 int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 339 340 int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip); 341 342 int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num, 343 bool hash, u16 mask); 344 int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id, 345 u16 map); 346 int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip); 347 348 int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target, 349 int port); 350 351 extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops; 352 extern const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops; 353 extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops; 354 355 extern const struct mv88e6xxx_avb_ops mv88e6165_avb_ops; 356 extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops; 357 extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops; 358 359 extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops; 360 361 int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, 362 bool external); 363 int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin); 364 int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats); 365 366 #endif /* _MV88E6XXX_GLOBAL2_H */ 367