1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Marvell 88E6xxx Switch Global 2 Registers support
4  *
5  * Copyright (c) 2008 Marvell Semiconductor
6  *
7  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9  */
10 
11 #ifndef _MV88E6XXX_GLOBAL2_H
12 #define _MV88E6XXX_GLOBAL2_H
13 
14 #include "chip.h"
15 
16 /* Offset 0x00: Interrupt Source Register */
17 #define MV88E6XXX_G2_INT_SRC			0x00
18 #define MV88E6XXX_G2_INT_SRC_WDOG		0x8000
19 #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT		0x4000
20 #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH	0x2000
21 #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT		0x1000
22 #define MV88E6352_G2_INT_SRC_SERDES		0x0800
23 #define MV88E6352_G2_INT_SRC_PHY		0x001f
24 #define MV88E6390_G2_INT_SRC_PHY		0x07fe
25 
26 #define MV88E6XXX_G2_INT_SOURCE_WATCHDOG	15
27 
28 /* Offset 0x01: Interrupt Mask Register */
29 #define MV88E6XXX_G2_INT_MASK			0x01
30 #define MV88E6XXX_G2_INT_MASK_WDOG		0x8000
31 #define MV88E6XXX_G2_INT_MASK_JAM_LIMIT		0x4000
32 #define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH	0x2000
33 #define MV88E6XXX_G2_INT_MASK_WAKE_EVENT	0x1000
34 #define MV88E6352_G2_INT_MASK_SERDES		0x0800
35 #define MV88E6352_G2_INT_MASK_PHY		0x001f
36 #define MV88E6390_G2_INT_MASK_PHY		0x07fe
37 
38 /* Offset 0x02: MGMT Enable Register 2x */
39 #define MV88E6XXX_G2_MGMT_EN_2X		0x02
40 
41 /* Offset 0x03: MGMT Enable Register 0x */
42 #define MV88E6XXX_G2_MGMT_EN_0X		0x03
43 
44 /* Offset 0x04: Flow Control Delay Register */
45 #define MV88E6XXX_G2_FLOW_CTL	0x04
46 
47 /* Offset 0x05: Switch Management Register */
48 #define MV88E6XXX_G2_SWITCH_MGMT			0x05
49 #define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA	0x8000
50 #define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS		0x4000
51 #define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG		0x2000
52 #define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI	0x0080
53 #define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU		0x0008
54 
55 /* Offset 0x06: Device Mapping Table Register */
56 #define MV88E6XXX_G2_DEVICE_MAPPING		0x06
57 #define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE	0x8000
58 #define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK	0x1f00
59 #define MV88E6352_G2_DEVICE_MAPPING_PORT_MASK	0x000f
60 #define MV88E6390_G2_DEVICE_MAPPING_PORT_MASK	0x001f
61 
62 /* Offset 0x07: Trunk Mask Table Register */
63 #define MV88E6XXX_G2_TRUNK_MASK			0x07
64 #define MV88E6XXX_G2_TRUNK_MASK_UPDATE		0x8000
65 #define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK	0x7000
66 #define MV88E6XXX_G2_TRUNK_MASK_HASH		0x0800
67 
68 /* Offset 0x08: Trunk Mapping Table Register */
69 #define MV88E6XXX_G2_TRUNK_MAPPING		0x08
70 #define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE	0x8000
71 #define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK	0x7800
72 
73 /* Offset 0x09: Ingress Rate Command Register */
74 #define MV88E6XXX_G2_IRL_CMD			0x09
75 #define MV88E6XXX_G2_IRL_CMD_BUSY		0x8000
76 #define MV88E6352_G2_IRL_CMD_OP_MASK		0x7000
77 #define MV88E6352_G2_IRL_CMD_OP_NOOP		0x0000
78 #define MV88E6352_G2_IRL_CMD_OP_INIT_ALL	0x1000
79 #define MV88E6352_G2_IRL_CMD_OP_INIT_RES	0x2000
80 #define MV88E6352_G2_IRL_CMD_OP_WRITE_REG	0x3000
81 #define MV88E6352_G2_IRL_CMD_OP_READ_REG	0x4000
82 #define MV88E6390_G2_IRL_CMD_OP_MASK		0x6000
83 #define MV88E6390_G2_IRL_CMD_OP_READ_REG	0x0000
84 #define MV88E6390_G2_IRL_CMD_OP_INIT_ALL	0x2000
85 #define MV88E6390_G2_IRL_CMD_OP_INIT_RES	0x4000
86 #define MV88E6390_G2_IRL_CMD_OP_WRITE_REG	0x6000
87 #define MV88E6352_G2_IRL_CMD_PORT_MASK		0x0f00
88 #define MV88E6390_G2_IRL_CMD_PORT_MASK		0x1f00
89 #define MV88E6XXX_G2_IRL_CMD_RES_MASK		0x00e0
90 #define MV88E6XXX_G2_IRL_CMD_REG_MASK		0x000f
91 
92 /* Offset 0x0A: Ingress Rate Data Register */
93 #define MV88E6XXX_G2_IRL_DATA		0x0a
94 #define MV88E6XXX_G2_IRL_DATA_MASK	0xffff
95 
96 /* Offset 0x0B: Cross-chip Port VLAN Register */
97 #define MV88E6XXX_G2_PVT_ADDR			0x0b
98 #define MV88E6XXX_G2_PVT_ADDR_BUSY		0x8000
99 #define MV88E6XXX_G2_PVT_ADDR_OP_MASK		0x7000
100 #define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES	0x1000
101 #define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN	0x3000
102 #define MV88E6XXX_G2_PVT_ADDR_OP_READ		0x4000
103 #define MV88E6XXX_G2_PVT_ADDR_PTR_MASK		0x01ff
104 
105 /* Offset 0x0C: Cross-chip Port VLAN Data Register */
106 #define MV88E6XXX_G2_PVT_DATA		0x0c
107 #define MV88E6XXX_G2_PVT_DATA_MASK	0x7f
108 
109 /* Offset 0x0D: Switch MAC/WoL/WoF Register */
110 #define MV88E6XXX_G2_SWITCH_MAC			0x0d
111 #define MV88E6XXX_G2_SWITCH_MAC_UPDATE		0x8000
112 #define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK	0x1f00
113 #define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK	0x00ff
114 
115 /* Offset 0x0E: ATU Stats Register */
116 #define MV88E6XXX_G2_ATU_STATS				0x0e
117 #define MV88E6XXX_G2_ATU_STATS_BIN_0			(0x0 << 14)
118 #define MV88E6XXX_G2_ATU_STATS_BIN_1			(0x1 << 14)
119 #define MV88E6XXX_G2_ATU_STATS_BIN_2			(0x2 << 14)
120 #define MV88E6XXX_G2_ATU_STATS_BIN_3			(0x3 << 14)
121 #define MV88E6XXX_G2_ATU_STATS_MODE_ALL			(0x0 << 12)
122 #define MV88E6XXX_G2_ATU_STATS_MODE_ALL_DYNAMIC		(0x1 << 12)
123 #define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL		(0x2 << 12)
124 #define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL_DYNAMIC	(0x3 << 12)
125 #define MV88E6XXX_G2_ATU_STATS_MASK			0x0fff
126 
127 /* Offset 0x0F: Priority Override Table */
128 #define MV88E6XXX_G2_PRIO_OVERRIDE		0x0f
129 #define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE	0x8000
130 #define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET	0x1000
131 #define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK	0x0f00
132 #define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN	0x0080
133 #define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK	0x0030
134 #define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN	0x0008
135 #define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK	0x0007
136 
137 /* Offset 0x14: EEPROM Command */
138 #define MV88E6XXX_G2_EEPROM_CMD			0x14
139 #define MV88E6XXX_G2_EEPROM_CMD_BUSY		0x8000
140 #define MV88E6XXX_G2_EEPROM_CMD_OP_MASK		0x7000
141 #define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE	0x3000
142 #define MV88E6XXX_G2_EEPROM_CMD_OP_READ		0x4000
143 #define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD		0x6000
144 #define MV88E6XXX_G2_EEPROM_CMD_RUNNING		0x0800
145 #define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN	0x0400
146 #define MV88E6352_G2_EEPROM_CMD_ADDR_MASK	0x00ff
147 #define MV88E6390_G2_EEPROM_CMD_DATA_MASK	0x00ff
148 
149 /* Offset 0x15: EEPROM Data */
150 #define MV88E6352_G2_EEPROM_DATA	0x15
151 #define MV88E6352_G2_EEPROM_DATA_MASK	0xffff
152 
153 /* Offset 0x15: EEPROM Addr */
154 #define MV88E6390_G2_EEPROM_ADDR	0x15
155 #define MV88E6390_G2_EEPROM_ADDR_MASK	0xffff
156 
157 /* Offset 0x16: AVB Command Register */
158 #define MV88E6352_G2_AVB_CMD			0x16
159 #define MV88E6352_G2_AVB_CMD_BUSY		0x8000
160 #define MV88E6352_G2_AVB_CMD_OP_READ		0x4000
161 #define MV88E6352_G2_AVB_CMD_OP_READ_INCR	0x6000
162 #define MV88E6352_G2_AVB_CMD_OP_WRITE		0x3000
163 #define MV88E6390_G2_AVB_CMD_OP_READ		0x0000
164 #define MV88E6390_G2_AVB_CMD_OP_READ_INCR	0x4000
165 #define MV88E6390_G2_AVB_CMD_OP_WRITE		0x6000
166 #define MV88E6352_G2_AVB_CMD_PORT_MASK		0x0f00
167 #define MV88E6352_G2_AVB_CMD_PORT_TAIGLOBAL	0xe
168 #define MV88E6165_G2_AVB_CMD_PORT_PTPGLOBAL	0xf
169 #define MV88E6352_G2_AVB_CMD_PORT_PTPGLOBAL	0xf
170 #define MV88E6390_G2_AVB_CMD_PORT_MASK		0x1f00
171 #define MV88E6390_G2_AVB_CMD_PORT_TAIGLOBAL	0x1e
172 #define MV88E6390_G2_AVB_CMD_PORT_PTPGLOBAL	0x1f
173 #define MV88E6352_G2_AVB_CMD_BLOCK_PTP		0
174 #define MV88E6352_G2_AVB_CMD_BLOCK_AVB		1
175 #define MV88E6352_G2_AVB_CMD_BLOCK_QAV		2
176 #define MV88E6352_G2_AVB_CMD_BLOCK_QVB		3
177 #define MV88E6352_G2_AVB_CMD_BLOCK_MASK		0x00e0
178 #define MV88E6352_G2_AVB_CMD_ADDR_MASK		0x001f
179 
180 /* Offset 0x17: AVB Data Register */
181 #define MV88E6352_G2_AVB_DATA		0x17
182 
183 /* Offset 0x18: SMI PHY Command Register */
184 #define MV88E6XXX_G2_SMI_PHY_CMD			0x18
185 #define MV88E6XXX_G2_SMI_PHY_CMD_BUSY			0x8000
186 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK		0x6000
187 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL		0x0000
188 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL		0x2000
189 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP		0x4000
190 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK		0x1000
191 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45		0x0000
192 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22		0x1000
193 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK		0x0c00
194 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA	0x0400
195 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA	0x0800
196 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR	0x0000
197 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA	0x0400
198 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC	0x0800
199 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA	0x0c00
200 #define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK		0x03e0
201 #define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK		0x001f
202 #define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK		0x03ff
203 
204 /* Offset 0x19: SMI PHY Data Register */
205 #define MV88E6XXX_G2_SMI_PHY_DATA	0x19
206 
207 /* Offset 0x1A: Scratch and Misc. Register */
208 #define MV88E6XXX_G2_SCRATCH_MISC_MISC		0x1a
209 #define MV88E6XXX_G2_SCRATCH_MISC_UPDATE	0x8000
210 #define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK	0x7f00
211 #define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK	0x00ff
212 
213 /* Offset 0x1B: Watch Dog Control Register */
214 #define MV88E6250_G2_WDOG_CTL			0x1b
215 #define MV88E6250_G2_WDOG_CTL_QC_HISTORY	0x0100
216 #define MV88E6250_G2_WDOG_CTL_QC_EVENT		0x0080
217 #define MV88E6250_G2_WDOG_CTL_QC_ENABLE		0x0040
218 #define MV88E6250_G2_WDOG_CTL_EGRESS_HISTORY	0x0020
219 #define MV88E6250_G2_WDOG_CTL_EGRESS_EVENT	0x0010
220 #define MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE	0x0008
221 #define MV88E6250_G2_WDOG_CTL_FORCE_IRQ		0x0004
222 #define MV88E6250_G2_WDOG_CTL_HISTORY		0x0002
223 #define MV88E6250_G2_WDOG_CTL_SWRESET		0x0001
224 
225 /* Offset 0x1B: Watch Dog Control Register */
226 #define MV88E6352_G2_WDOG_CTL			0x1b
227 #define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT	0x0080
228 #define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT	0x0040
229 #define MV88E6352_G2_WDOG_CTL_QC_ENABLE		0x0020
230 #define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY	0x0010
231 #define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE	0x0008
232 #define MV88E6352_G2_WDOG_CTL_FORCE_IRQ		0x0004
233 #define MV88E6352_G2_WDOG_CTL_HISTORY		0x0002
234 #define MV88E6352_G2_WDOG_CTL_SWRESET		0x0001
235 
236 /* Offset 0x1B: Watch Dog Control Register */
237 #define MV88E6390_G2_WDOG_CTL				0x1b
238 #define MV88E6390_G2_WDOG_CTL_UPDATE			0x8000
239 #define MV88E6390_G2_WDOG_CTL_PTR_MASK			0x7f00
240 #define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE		0x0000
241 #define MV88E6390_G2_WDOG_CTL_PTR_INT_STS		0x1000
242 #define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE		0x1100
243 #define MV88E6390_G2_WDOG_CTL_PTR_EVENT			0x1200
244 #define MV88E6390_G2_WDOG_CTL_PTR_HISTORY		0x1300
245 #define MV88E6390_G2_WDOG_CTL_DATA_MASK			0x00ff
246 #define MV88E6390_G2_WDOG_CTL_CUT_THROUGH		0x0008
247 #define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER		0x0004
248 #define MV88E6390_G2_WDOG_CTL_EGRESS			0x0002
249 #define MV88E6390_G2_WDOG_CTL_FORCE_IRQ			0x0001
250 
251 /* Offset 0x1C: QoS Weights Register */
252 #define MV88E6XXX_G2_QOS_WEIGHTS		0x1c
253 #define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE		0x8000
254 #define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK	0x3f00
255 #define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK	0x7f00
256 #define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK	0x00ff
257 
258 /* Offset 0x1D: Misc Register */
259 #define MV88E6XXX_G2_MISC		0x1d
260 #define MV88E6XXX_G2_MISC_5_BIT_PORT	0x4000
261 #define MV88E6352_G2_NOEGR_POLICY	0x2000
262 #define MV88E6390_G2_LAG_ID_4		0x2000
263 
264 /* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */
265 /* Offset 0x02: Misc Configuration */
266 #define MV88E6352_G2_SCRATCH_MISC_CFG		0x02
267 #define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI	0x80
268 /* Offset 0x60-0x61: GPIO Configuration */
269 #define MV88E6352_G2_SCRATCH_GPIO_CFG0		0x60
270 #define MV88E6352_G2_SCRATCH_GPIO_CFG1		0x61
271 /* Offset 0x62-0x63: GPIO Direction */
272 #define MV88E6352_G2_SCRATCH_GPIO_DIR0		0x62
273 #define MV88E6352_G2_SCRATCH_GPIO_DIR1		0x63
274 #define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT	0
275 #define MV88E6352_G2_SCRATCH_GPIO_DIR_IN	1
276 /* Offset 0x64-0x65: GPIO Data */
277 #define MV88E6352_G2_SCRATCH_GPIO_DATA0		0x64
278 #define MV88E6352_G2_SCRATCH_GPIO_DATA1		0x65
279 /* Offset 0x68-0x6F: GPIO Pin Control */
280 #define MV88E6352_G2_SCRATCH_GPIO_PCTL0		0x68
281 #define MV88E6352_G2_SCRATCH_GPIO_PCTL1		0x69
282 #define MV88E6352_G2_SCRATCH_GPIO_PCTL2		0x6A
283 #define MV88E6352_G2_SCRATCH_GPIO_PCTL3		0x6B
284 #define MV88E6352_G2_SCRATCH_GPIO_PCTL4		0x6C
285 #define MV88E6352_G2_SCRATCH_GPIO_PCTL5		0x6D
286 #define MV88E6352_G2_SCRATCH_GPIO_PCTL6		0x6E
287 #define MV88E6352_G2_SCRATCH_GPIO_PCTL7		0x6F
288 #define MV88E6352_G2_SCRATCH_CONFIG_DATA0	0x70
289 #define MV88E6352_G2_SCRATCH_CONFIG_DATA1	0x71
290 #define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU	BIT(2)
291 #define MV88E6352_G2_SCRATCH_CONFIG_DATA2	0x72
292 #define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK	0x3
293 
294 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO	0
295 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG	1
296 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ	2
297 
298 #ifdef CONFIG_NET_DSA_MV88E6XXX_GLOBAL2
299 
300 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
301 {
302 	return 0;
303 }
304 
305 int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
306 int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
307 int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg,
308 			  int bit, int val);
309 
310 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
311 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
312 
313 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
314 			      struct mii_bus *bus,
315 			      int addr, int reg, u16 *val);
316 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
317 			       struct mii_bus *bus,
318 			       int addr, int reg, u16 val);
319 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
320 
321 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
322 			     struct ethtool_eeprom *eeprom, u8 *data);
323 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
324 			     struct ethtool_eeprom *eeprom, u8 *data);
325 
326 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
327 			      struct ethtool_eeprom *eeprom, u8 *data);
328 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
329 			      struct ethtool_eeprom *eeprom, u8 *data);
330 
331 int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
332 			   int src_port, u16 data);
333 int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip);
334 
335 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip);
336 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip);
337 
338 int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
339 				struct mii_bus *bus);
340 void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
341 				struct mii_bus *bus);
342 
343 int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
344 int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
345 
346 int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip);
347 
348 int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip);
349 
350 int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target,
351 				      int port);
352 
353 extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops;
354 extern const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops;
355 extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops;
356 
357 extern const struct mv88e6xxx_avb_ops mv88e6165_avb_ops;
358 extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops;
359 extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops;
360 
361 extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops;
362 
363 int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
364 				      bool external);
365 int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin);
366 int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats);
367 
368 #else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
369 
370 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
371 {
372 	if (chip->info->global2_addr) {
373 		dev_err(chip->dev, "this chip requires CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 enabled\n");
374 		return -EOPNOTSUPP;
375 	}
376 
377 	return 0;
378 }
379 
380 static inline int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
381 {
382 	return -EOPNOTSUPP;
383 }
384 
385 static inline int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
386 {
387 	return -EOPNOTSUPP;
388 }
389 
390 static inline int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip,
391 					int reg, int bit, int val)
392 {
393 	return -EOPNOTSUPP;
394 }
395 
396 static inline int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip,
397 					    int port)
398 {
399 	return -EOPNOTSUPP;
400 }
401 
402 static inline int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip,
403 					    int port)
404 {
405 	return -EOPNOTSUPP;
406 }
407 
408 static inline int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
409 					    struct mii_bus *bus,
410 					    int addr, int reg, u16 *val)
411 {
412 	return -EOPNOTSUPP;
413 }
414 
415 static inline int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
416 					     struct mii_bus *bus,
417 					     int addr, int reg, u16 val)
418 {
419 	return -EOPNOTSUPP;
420 }
421 
422 static inline int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip,
423 					      u8 *addr)
424 {
425 	return -EOPNOTSUPP;
426 }
427 
428 static inline int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
429 					   struct ethtool_eeprom *eeprom,
430 					   u8 *data)
431 {
432 	return -EOPNOTSUPP;
433 }
434 
435 static inline int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
436 					   struct ethtool_eeprom *eeprom,
437 					   u8 *data)
438 {
439 	return -EOPNOTSUPP;
440 }
441 
442 static inline int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
443 					    struct ethtool_eeprom *eeprom,
444 					    u8 *data)
445 {
446 	return -EOPNOTSUPP;
447 }
448 
449 static inline int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
450 					    struct ethtool_eeprom *eeprom,
451 					    u8 *data)
452 {
453 	return -EOPNOTSUPP;
454 }
455 
456 static inline int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip,
457 					 int src_dev, int src_port, u16 data)
458 {
459 	return -EOPNOTSUPP;
460 }
461 
462 static inline int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
463 {
464 	return -EOPNOTSUPP;
465 }
466 
467 static inline int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
468 {
469 	return -EOPNOTSUPP;
470 }
471 
472 static inline void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
473 {
474 }
475 
476 static inline int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
477 					      struct mii_bus *bus)
478 {
479 	return 0;
480 }
481 
482 static inline void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
483 					      struct mii_bus *bus)
484 {
485 }
486 
487 static inline int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
488 {
489 	return -EOPNOTSUPP;
490 }
491 
492 static inline int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
493 {
494 	return -EOPNOTSUPP;
495 }
496 
497 static inline int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip)
498 {
499 	return -EOPNOTSUPP;
500 }
501 
502 static const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {};
503 static const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops = {};
504 static const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {};
505 
506 static const struct mv88e6xxx_avb_ops mv88e6165_avb_ops = {};
507 static const struct mv88e6xxx_avb_ops mv88e6352_avb_ops = {};
508 static const struct mv88e6xxx_avb_ops mv88e6390_avb_ops = {};
509 
510 static const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops = {};
511 
512 static inline int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
513 						    bool external)
514 {
515 	return -EOPNOTSUPP;
516 }
517 
518 static inline int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip)
519 {
520 	return -EOPNOTSUPP;
521 }
522 
523 static inline int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
524 						    int target, int port)
525 {
526 	return -EOPNOTSUPP;
527 }
528 
529 static inline int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip,
530 					     u16 kind, u16 bin)
531 {
532 	return -EOPNOTSUPP;
533 }
534 
535 static inline int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip,
536 					     u16 *stats)
537 {
538 	return -EOPNOTSUPP;
539 }
540 
541 #endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
542 
543 #endif /* _MV88E6XXX_GLOBAL2_H */
544