1 /* 2 * Marvell 88E6xxx Switch Global 2 Registers support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #ifndef _MV88E6XXX_GLOBAL2_H 16 #define _MV88E6XXX_GLOBAL2_H 17 18 #include "chip.h" 19 20 /* Offset 0x00: Interrupt Source Register */ 21 #define MV88E6XXX_G2_INT_SRC 0x00 22 #define MV88E6XXX_G2_INT_SRC_WDOG 0x8000 23 #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x4000 24 #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000 25 #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x1000 26 #define MV88E6352_G2_INT_SRC_SERDES 0x0800 27 #define MV88E6352_G2_INT_SRC_PHY 0x001f 28 #define MV88E6390_G2_INT_SRC_PHY 0x07fe 29 30 #define MV88E6XXX_G2_INT_SOURCE_WATCHDOG 15 31 32 /* Offset 0x01: Interrupt Mask Register */ 33 #define MV88E6XXX_G2_INT_MASK 0x01 34 #define MV88E6XXX_G2_INT_MASK_WDOG 0x8000 35 #define MV88E6XXX_G2_INT_MASK_JAM_LIMIT 0x4000 36 #define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH 0x2000 37 #define MV88E6XXX_G2_INT_MASK_WAKE_EVENT 0x1000 38 #define MV88E6352_G2_INT_MASK_SERDES 0x0800 39 #define MV88E6352_G2_INT_MASK_PHY 0x001f 40 #define MV88E6390_G2_INT_MASK_PHY 0x07fe 41 42 /* Offset 0x02: MGMT Enable Register 2x */ 43 #define MV88E6XXX_G2_MGMT_EN_2X 0x02 44 45 /* Offset 0x03: MGMT Enable Register 0x */ 46 #define MV88E6XXX_G2_MGMT_EN_0X 0x03 47 48 /* Offset 0x04: Flow Control Delay Register */ 49 #define MV88E6XXX_G2_FLOW_CTL 0x04 50 51 /* Offset 0x05: Switch Management Register */ 52 #define MV88E6XXX_G2_SWITCH_MGMT 0x05 53 #define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA 0x8000 54 #define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS 0x4000 55 #define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x2000 56 #define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080 57 #define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008 58 59 /* Offset 0x06: Device Mapping Table Register */ 60 #define MV88E6XXX_G2_DEVICE_MAPPING 0x06 61 #define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x8000 62 #define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK 0x1f00 63 #define MV88E6XXX_G2_DEVICE_MAPPING_PORT_MASK 0x000f 64 65 /* Offset 0x07: Trunk Mask Table Register */ 66 #define MV88E6XXX_G2_TRUNK_MASK 0x07 67 #define MV88E6XXX_G2_TRUNK_MASK_UPDATE 0x8000 68 #define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK 0x7000 69 #define MV88E6XXX_G2_TRUNK_MASK_HASH 0x0800 70 71 /* Offset 0x08: Trunk Mapping Table Register */ 72 #define MV88E6XXX_G2_TRUNK_MAPPING 0x08 73 #define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE 0x8000 74 #define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK 0x7800 75 76 /* Offset 0x09: Ingress Rate Command Register */ 77 #define MV88E6XXX_G2_IRL_CMD 0x09 78 #define MV88E6XXX_G2_IRL_CMD_BUSY 0x8000 79 #define MV88E6352_G2_IRL_CMD_OP_MASK 0x7000 80 #define MV88E6352_G2_IRL_CMD_OP_NOOP 0x0000 81 #define MV88E6352_G2_IRL_CMD_OP_INIT_ALL 0x1000 82 #define MV88E6352_G2_IRL_CMD_OP_INIT_RES 0x2000 83 #define MV88E6352_G2_IRL_CMD_OP_WRITE_REG 0x3000 84 #define MV88E6352_G2_IRL_CMD_OP_READ_REG 0x4000 85 #define MV88E6390_G2_IRL_CMD_OP_MASK 0x6000 86 #define MV88E6390_G2_IRL_CMD_OP_READ_REG 0x0000 87 #define MV88E6390_G2_IRL_CMD_OP_INIT_ALL 0x2000 88 #define MV88E6390_G2_IRL_CMD_OP_INIT_RES 0x4000 89 #define MV88E6390_G2_IRL_CMD_OP_WRITE_REG 0x6000 90 #define MV88E6352_G2_IRL_CMD_PORT_MASK 0x0f00 91 #define MV88E6390_G2_IRL_CMD_PORT_MASK 0x1f00 92 #define MV88E6XXX_G2_IRL_CMD_RES_MASK 0x00e0 93 #define MV88E6XXX_G2_IRL_CMD_REG_MASK 0x000f 94 95 /* Offset 0x0A: Ingress Rate Data Register */ 96 #define MV88E6XXX_G2_IRL_DATA 0x0a 97 #define MV88E6XXX_G2_IRL_DATA_MASK 0xffff 98 99 /* Offset 0x0B: Cross-chip Port VLAN Register */ 100 #define MV88E6XXX_G2_PVT_ADDR 0x0b 101 #define MV88E6XXX_G2_PVT_ADDR_BUSY 0x8000 102 #define MV88E6XXX_G2_PVT_ADDR_OP_MASK 0x7000 103 #define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES 0x1000 104 #define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN 0x3000 105 #define MV88E6XXX_G2_PVT_ADDR_OP_READ 0x4000 106 #define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff 107 108 /* Offset 0x0C: Cross-chip Port VLAN Data Register */ 109 #define MV88E6XXX_G2_PVT_DATA 0x0c 110 #define MV88E6XXX_G2_PVT_DATA_MASK 0x7f 111 112 /* Offset 0x0D: Switch MAC/WoL/WoF Register */ 113 #define MV88E6XXX_G2_SWITCH_MAC 0x0d 114 #define MV88E6XXX_G2_SWITCH_MAC_UPDATE 0x8000 115 #define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK 0x1f00 116 #define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK 0x00ff 117 118 /* Offset 0x0E: ATU Stats Register */ 119 #define MV88E6XXX_G2_ATU_STATS 0x0e 120 121 /* Offset 0x0F: Priority Override Table */ 122 #define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f 123 #define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE 0x8000 124 #define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET 0x1000 125 #define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00 126 #define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN 0x0080 127 #define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030 128 #define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN 0x0008 129 #define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK 0x0007 130 131 /* Offset 0x14: EEPROM Command */ 132 #define MV88E6XXX_G2_EEPROM_CMD 0x14 133 #define MV88E6XXX_G2_EEPROM_CMD_BUSY 0x8000 134 #define MV88E6XXX_G2_EEPROM_CMD_OP_MASK 0x7000 135 #define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE 0x3000 136 #define MV88E6XXX_G2_EEPROM_CMD_OP_READ 0x4000 137 #define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD 0x6000 138 #define MV88E6XXX_G2_EEPROM_CMD_RUNNING 0x0800 139 #define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN 0x0400 140 #define MV88E6352_G2_EEPROM_CMD_ADDR_MASK 0x00ff 141 #define MV88E6390_G2_EEPROM_CMD_DATA_MASK 0x00ff 142 143 /* Offset 0x15: EEPROM Data */ 144 #define MV88E6352_G2_EEPROM_DATA 0x15 145 #define MV88E6352_G2_EEPROM_DATA_MASK 0xffff 146 147 /* Offset 0x15: EEPROM Addr */ 148 #define MV88E6390_G2_EEPROM_ADDR 0x15 149 #define MV88E6390_G2_EEPROM_ADDR_MASK 0xffff 150 151 /* Offset 0x16: AVB Command Register */ 152 #define MV88E6352_G2_AVB_CMD 0x16 153 154 /* Offset 0x17: AVB Data Register */ 155 #define MV88E6352_G2_AVB_DATA 0x17 156 157 /* Offset 0x18: SMI PHY Command Register */ 158 #define MV88E6XXX_G2_SMI_PHY_CMD 0x18 159 #define MV88E6XXX_G2_SMI_PHY_CMD_BUSY 0x8000 160 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK 0x6000 161 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL 0x0000 162 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL 0x2000 163 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP 0x4000 164 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK 0x1000 165 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45 0x0000 166 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22 0x1000 167 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK 0x0c00 168 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA 0x0400 169 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA 0x0800 170 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR 0x0000 171 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA 0x0400 172 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC 0x0800 173 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA 0x0c00 174 #define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK 0x03e0 175 #define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK 0x001f 176 #define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK 0x03ff 177 178 /* Offset 0x19: SMI PHY Data Register */ 179 #define MV88E6XXX_G2_SMI_PHY_DATA 0x19 180 181 /* Offset 0x1A: Scratch and Misc. Register */ 182 #define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a 183 #define MV88E6XXX_G2_SCRATCH_MISC_UPDATE 0x8000 184 #define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK 0x7f00 185 #define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff 186 187 /* Offset 0x1B: Watch Dog Control Register */ 188 #define MV88E6352_G2_WDOG_CTL 0x1b 189 #define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT 0x0080 190 #define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT 0x0040 191 #define MV88E6352_G2_WDOG_CTL_QC_ENABLE 0x0020 192 #define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY 0x0010 193 #define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE 0x0008 194 #define MV88E6352_G2_WDOG_CTL_FORCE_IRQ 0x0004 195 #define MV88E6352_G2_WDOG_CTL_HISTORY 0x0002 196 #define MV88E6352_G2_WDOG_CTL_SWRESET 0x0001 197 198 /* Offset 0x1B: Watch Dog Control Register */ 199 #define MV88E6390_G2_WDOG_CTL 0x1b 200 #define MV88E6390_G2_WDOG_CTL_UPDATE 0x8000 201 #define MV88E6390_G2_WDOG_CTL_PTR_MASK 0x7f00 202 #define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE 0x0000 203 #define MV88E6390_G2_WDOG_CTL_PTR_INT_STS 0x1000 204 #define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE 0x1100 205 #define MV88E6390_G2_WDOG_CTL_PTR_EVENT 0x1200 206 #define MV88E6390_G2_WDOG_CTL_PTR_HISTORY 0x1300 207 #define MV88E6390_G2_WDOG_CTL_DATA_MASK 0x00ff 208 #define MV88E6390_G2_WDOG_CTL_CUT_THROUGH 0x0008 209 #define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER 0x0004 210 #define MV88E6390_G2_WDOG_CTL_EGRESS 0x0002 211 #define MV88E6390_G2_WDOG_CTL_FORCE_IRQ 0x0001 212 213 /* Offset 0x1C: QoS Weights Register */ 214 #define MV88E6XXX_G2_QOS_WEIGHTS 0x1c 215 #define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE 0x8000 216 #define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK 0x3f00 217 #define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK 0x7f00 218 #define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK 0x00ff 219 220 /* Offset 0x1D: Misc Register */ 221 #define MV88E6XXX_G2_MISC 0x1d 222 #define MV88E6XXX_G2_MISC_5_BIT_PORT 0x4000 223 #define MV88E6352_G2_NOEGR_POLICY 0x2000 224 #define MV88E6390_G2_LAG_ID_4 0x2000 225 226 #ifdef CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 227 228 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip) 229 { 230 return 0; 231 } 232 233 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 234 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 235 236 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, 237 struct mii_bus *bus, 238 int addr, int reg, u16 *val); 239 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, 240 struct mii_bus *bus, 241 int addr, int reg, u16 val); 242 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr); 243 244 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, 245 struct ethtool_eeprom *eeprom, u8 *data); 246 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, 247 struct ethtool_eeprom *eeprom, u8 *data); 248 249 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, 250 struct ethtool_eeprom *eeprom, u8 *data); 251 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 252 struct ethtool_eeprom *eeprom, u8 *data); 253 254 int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev, 255 int src_port, u16 data); 256 int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip); 257 258 int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip); 259 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip); 260 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip); 261 262 int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 263 int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 264 265 int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip); 266 267 extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops; 268 extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops; 269 270 #else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */ 271 272 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip) 273 { 274 if (chip->info->global2_addr) { 275 dev_err(chip->dev, "this chip requires CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 enabled\n"); 276 return -EOPNOTSUPP; 277 } 278 279 return 0; 280 } 281 282 static inline int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, 283 int port) 284 { 285 return -EOPNOTSUPP; 286 } 287 288 static inline int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, 289 int port) 290 { 291 return -EOPNOTSUPP; 292 } 293 294 static inline int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, 295 struct mii_bus *bus, 296 int addr, int reg, u16 *val) 297 { 298 return -EOPNOTSUPP; 299 } 300 301 static inline int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, 302 struct mii_bus *bus, 303 int addr, int reg, u16 val) 304 { 305 return -EOPNOTSUPP; 306 } 307 308 static inline int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, 309 u8 *addr) 310 { 311 return -EOPNOTSUPP; 312 } 313 314 static inline int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, 315 struct ethtool_eeprom *eeprom, 316 u8 *data) 317 { 318 return -EOPNOTSUPP; 319 } 320 321 static inline int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, 322 struct ethtool_eeprom *eeprom, 323 u8 *data) 324 { 325 return -EOPNOTSUPP; 326 } 327 328 static inline int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, 329 struct ethtool_eeprom *eeprom, 330 u8 *data) 331 { 332 return -EOPNOTSUPP; 333 } 334 335 static inline int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 336 struct ethtool_eeprom *eeprom, 337 u8 *data) 338 { 339 return -EOPNOTSUPP; 340 } 341 342 static inline int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, 343 int src_dev, int src_port, u16 data) 344 { 345 return -EOPNOTSUPP; 346 } 347 348 static inline int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip) 349 { 350 return -EOPNOTSUPP; 351 } 352 353 static inline int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip) 354 { 355 return -EOPNOTSUPP; 356 } 357 358 static inline int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip) 359 { 360 return -EOPNOTSUPP; 361 } 362 363 static inline void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip) 364 { 365 } 366 367 static inline int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 368 { 369 return -EOPNOTSUPP; 370 } 371 372 static inline int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 373 { 374 return -EOPNOTSUPP; 375 } 376 377 static inline int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip) 378 { 379 return -EOPNOTSUPP; 380 } 381 382 static const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {}; 383 static const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {}; 384 385 #endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */ 386 387 #endif /* _MV88E6XXX_GLOBAL2_H */ 388