1 /* 2 * Marvell 88E6xxx Switch Global 2 Registers support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #ifndef _MV88E6XXX_GLOBAL2_H 16 #define _MV88E6XXX_GLOBAL2_H 17 18 #include "chip.h" 19 20 /* Offset 0x00: Interrupt Source Register */ 21 #define MV88E6XXX_G2_INT_SRC 0x00 22 #define MV88E6XXX_G2_INT_SRC_WDOG 0x8000 23 #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x4000 24 #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000 25 #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x1000 26 #define MV88E6352_G2_INT_SRC_SERDES 0x0800 27 #define MV88E6352_G2_INT_SRC_PHY 0x001f 28 #define MV88E6390_G2_INT_SRC_PHY 0x07fe 29 30 #define MV88E6XXX_G2_INT_SOURCE_WATCHDOG 15 31 32 /* Offset 0x01: Interrupt Mask Register */ 33 #define MV88E6XXX_G2_INT_MASK 0x01 34 #define MV88E6XXX_G2_INT_MASK_WDOG 0x8000 35 #define MV88E6XXX_G2_INT_MASK_JAM_LIMIT 0x4000 36 #define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH 0x2000 37 #define MV88E6XXX_G2_INT_MASK_WAKE_EVENT 0x1000 38 #define MV88E6352_G2_INT_MASK_SERDES 0x0800 39 #define MV88E6352_G2_INT_MASK_PHY 0x001f 40 #define MV88E6390_G2_INT_MASK_PHY 0x07fe 41 42 /* Offset 0x02: MGMT Enable Register 2x */ 43 #define MV88E6XXX_G2_MGMT_EN_2X 0x02 44 45 /* Offset 0x03: MGMT Enable Register 0x */ 46 #define MV88E6XXX_G2_MGMT_EN_0X 0x03 47 48 /* Offset 0x04: Flow Control Delay Register */ 49 #define MV88E6XXX_G2_FLOW_CTL 0x04 50 51 /* Offset 0x05: Switch Management Register */ 52 #define MV88E6XXX_G2_SWITCH_MGMT 0x05 53 #define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA 0x8000 54 #define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS 0x4000 55 #define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x2000 56 #define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080 57 #define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008 58 59 /* Offset 0x06: Device Mapping Table Register */ 60 #define MV88E6XXX_G2_DEVICE_MAPPING 0x06 61 #define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x8000 62 #define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK 0x1f00 63 #define MV88E6352_G2_DEVICE_MAPPING_PORT_MASK 0x000f 64 #define MV88E6390_G2_DEVICE_MAPPING_PORT_MASK 0x001f 65 66 /* Offset 0x07: Trunk Mask Table Register */ 67 #define MV88E6XXX_G2_TRUNK_MASK 0x07 68 #define MV88E6XXX_G2_TRUNK_MASK_UPDATE 0x8000 69 #define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK 0x7000 70 #define MV88E6XXX_G2_TRUNK_MASK_HASH 0x0800 71 72 /* Offset 0x08: Trunk Mapping Table Register */ 73 #define MV88E6XXX_G2_TRUNK_MAPPING 0x08 74 #define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE 0x8000 75 #define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK 0x7800 76 77 /* Offset 0x09: Ingress Rate Command Register */ 78 #define MV88E6XXX_G2_IRL_CMD 0x09 79 #define MV88E6XXX_G2_IRL_CMD_BUSY 0x8000 80 #define MV88E6352_G2_IRL_CMD_OP_MASK 0x7000 81 #define MV88E6352_G2_IRL_CMD_OP_NOOP 0x0000 82 #define MV88E6352_G2_IRL_CMD_OP_INIT_ALL 0x1000 83 #define MV88E6352_G2_IRL_CMD_OP_INIT_RES 0x2000 84 #define MV88E6352_G2_IRL_CMD_OP_WRITE_REG 0x3000 85 #define MV88E6352_G2_IRL_CMD_OP_READ_REG 0x4000 86 #define MV88E6390_G2_IRL_CMD_OP_MASK 0x6000 87 #define MV88E6390_G2_IRL_CMD_OP_READ_REG 0x0000 88 #define MV88E6390_G2_IRL_CMD_OP_INIT_ALL 0x2000 89 #define MV88E6390_G2_IRL_CMD_OP_INIT_RES 0x4000 90 #define MV88E6390_G2_IRL_CMD_OP_WRITE_REG 0x6000 91 #define MV88E6352_G2_IRL_CMD_PORT_MASK 0x0f00 92 #define MV88E6390_G2_IRL_CMD_PORT_MASK 0x1f00 93 #define MV88E6XXX_G2_IRL_CMD_RES_MASK 0x00e0 94 #define MV88E6XXX_G2_IRL_CMD_REG_MASK 0x000f 95 96 /* Offset 0x0A: Ingress Rate Data Register */ 97 #define MV88E6XXX_G2_IRL_DATA 0x0a 98 #define MV88E6XXX_G2_IRL_DATA_MASK 0xffff 99 100 /* Offset 0x0B: Cross-chip Port VLAN Register */ 101 #define MV88E6XXX_G2_PVT_ADDR 0x0b 102 #define MV88E6XXX_G2_PVT_ADDR_BUSY 0x8000 103 #define MV88E6XXX_G2_PVT_ADDR_OP_MASK 0x7000 104 #define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES 0x1000 105 #define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN 0x3000 106 #define MV88E6XXX_G2_PVT_ADDR_OP_READ 0x4000 107 #define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff 108 109 /* Offset 0x0C: Cross-chip Port VLAN Data Register */ 110 #define MV88E6XXX_G2_PVT_DATA 0x0c 111 #define MV88E6XXX_G2_PVT_DATA_MASK 0x7f 112 113 /* Offset 0x0D: Switch MAC/WoL/WoF Register */ 114 #define MV88E6XXX_G2_SWITCH_MAC 0x0d 115 #define MV88E6XXX_G2_SWITCH_MAC_UPDATE 0x8000 116 #define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK 0x1f00 117 #define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK 0x00ff 118 119 /* Offset 0x0E: ATU Stats Register */ 120 #define MV88E6XXX_G2_ATU_STATS 0x0e 121 122 /* Offset 0x0F: Priority Override Table */ 123 #define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f 124 #define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE 0x8000 125 #define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET 0x1000 126 #define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00 127 #define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN 0x0080 128 #define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030 129 #define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN 0x0008 130 #define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK 0x0007 131 132 /* Offset 0x14: EEPROM Command */ 133 #define MV88E6XXX_G2_EEPROM_CMD 0x14 134 #define MV88E6XXX_G2_EEPROM_CMD_BUSY 0x8000 135 #define MV88E6XXX_G2_EEPROM_CMD_OP_MASK 0x7000 136 #define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE 0x3000 137 #define MV88E6XXX_G2_EEPROM_CMD_OP_READ 0x4000 138 #define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD 0x6000 139 #define MV88E6XXX_G2_EEPROM_CMD_RUNNING 0x0800 140 #define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN 0x0400 141 #define MV88E6352_G2_EEPROM_CMD_ADDR_MASK 0x00ff 142 #define MV88E6390_G2_EEPROM_CMD_DATA_MASK 0x00ff 143 144 /* Offset 0x15: EEPROM Data */ 145 #define MV88E6352_G2_EEPROM_DATA 0x15 146 #define MV88E6352_G2_EEPROM_DATA_MASK 0xffff 147 148 /* Offset 0x15: EEPROM Addr */ 149 #define MV88E6390_G2_EEPROM_ADDR 0x15 150 #define MV88E6390_G2_EEPROM_ADDR_MASK 0xffff 151 152 /* Offset 0x16: AVB Command Register */ 153 #define MV88E6352_G2_AVB_CMD 0x16 154 #define MV88E6352_G2_AVB_CMD_BUSY 0x8000 155 #define MV88E6352_G2_AVB_CMD_OP_READ 0x4000 156 #define MV88E6352_G2_AVB_CMD_OP_READ_INCR 0x6000 157 #define MV88E6352_G2_AVB_CMD_OP_WRITE 0x3000 158 #define MV88E6390_G2_AVB_CMD_OP_READ 0x0000 159 #define MV88E6390_G2_AVB_CMD_OP_READ_INCR 0x4000 160 #define MV88E6390_G2_AVB_CMD_OP_WRITE 0x6000 161 #define MV88E6352_G2_AVB_CMD_PORT_MASK 0x0f00 162 #define MV88E6352_G2_AVB_CMD_PORT_TAIGLOBAL 0xe 163 #define MV88E6165_G2_AVB_CMD_PORT_PTPGLOBAL 0xf 164 #define MV88E6352_G2_AVB_CMD_PORT_PTPGLOBAL 0xf 165 #define MV88E6390_G2_AVB_CMD_PORT_MASK 0x1f00 166 #define MV88E6390_G2_AVB_CMD_PORT_TAIGLOBAL 0x1e 167 #define MV88E6390_G2_AVB_CMD_PORT_PTPGLOBAL 0x1f 168 #define MV88E6352_G2_AVB_CMD_BLOCK_PTP 0 169 #define MV88E6352_G2_AVB_CMD_BLOCK_AVB 1 170 #define MV88E6352_G2_AVB_CMD_BLOCK_QAV 2 171 #define MV88E6352_G2_AVB_CMD_BLOCK_QVB 3 172 #define MV88E6352_G2_AVB_CMD_BLOCK_MASK 0x00e0 173 #define MV88E6352_G2_AVB_CMD_ADDR_MASK 0x001f 174 175 /* Offset 0x17: AVB Data Register */ 176 #define MV88E6352_G2_AVB_DATA 0x17 177 178 /* Offset 0x18: SMI PHY Command Register */ 179 #define MV88E6XXX_G2_SMI_PHY_CMD 0x18 180 #define MV88E6XXX_G2_SMI_PHY_CMD_BUSY 0x8000 181 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK 0x6000 182 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL 0x0000 183 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL 0x2000 184 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP 0x4000 185 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK 0x1000 186 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45 0x0000 187 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22 0x1000 188 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK 0x0c00 189 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA 0x0400 190 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA 0x0800 191 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR 0x0000 192 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA 0x0400 193 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC 0x0800 194 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA 0x0c00 195 #define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK 0x03e0 196 #define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK 0x001f 197 #define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK 0x03ff 198 199 /* Offset 0x19: SMI PHY Data Register */ 200 #define MV88E6XXX_G2_SMI_PHY_DATA 0x19 201 202 /* Offset 0x1A: Scratch and Misc. Register */ 203 #define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a 204 #define MV88E6XXX_G2_SCRATCH_MISC_UPDATE 0x8000 205 #define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK 0x7f00 206 #define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff 207 208 /* Offset 0x1B: Watch Dog Control Register */ 209 #define MV88E6352_G2_WDOG_CTL 0x1b 210 #define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT 0x0080 211 #define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT 0x0040 212 #define MV88E6352_G2_WDOG_CTL_QC_ENABLE 0x0020 213 #define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY 0x0010 214 #define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE 0x0008 215 #define MV88E6352_G2_WDOG_CTL_FORCE_IRQ 0x0004 216 #define MV88E6352_G2_WDOG_CTL_HISTORY 0x0002 217 #define MV88E6352_G2_WDOG_CTL_SWRESET 0x0001 218 219 /* Offset 0x1B: Watch Dog Control Register */ 220 #define MV88E6390_G2_WDOG_CTL 0x1b 221 #define MV88E6390_G2_WDOG_CTL_UPDATE 0x8000 222 #define MV88E6390_G2_WDOG_CTL_PTR_MASK 0x7f00 223 #define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE 0x0000 224 #define MV88E6390_G2_WDOG_CTL_PTR_INT_STS 0x1000 225 #define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE 0x1100 226 #define MV88E6390_G2_WDOG_CTL_PTR_EVENT 0x1200 227 #define MV88E6390_G2_WDOG_CTL_PTR_HISTORY 0x1300 228 #define MV88E6390_G2_WDOG_CTL_DATA_MASK 0x00ff 229 #define MV88E6390_G2_WDOG_CTL_CUT_THROUGH 0x0008 230 #define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER 0x0004 231 #define MV88E6390_G2_WDOG_CTL_EGRESS 0x0002 232 #define MV88E6390_G2_WDOG_CTL_FORCE_IRQ 0x0001 233 234 /* Offset 0x1C: QoS Weights Register */ 235 #define MV88E6XXX_G2_QOS_WEIGHTS 0x1c 236 #define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE 0x8000 237 #define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK 0x3f00 238 #define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK 0x7f00 239 #define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK 0x00ff 240 241 /* Offset 0x1D: Misc Register */ 242 #define MV88E6XXX_G2_MISC 0x1d 243 #define MV88E6XXX_G2_MISC_5_BIT_PORT 0x4000 244 #define MV88E6352_G2_NOEGR_POLICY 0x2000 245 #define MV88E6390_G2_LAG_ID_4 0x2000 246 247 /* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */ 248 /* Offset 0x02: Misc Configuration */ 249 #define MV88E6352_G2_SCRATCH_MISC_CFG 0x02 250 #define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI 0x80 251 /* Offset 0x60-0x61: GPIO Configuration */ 252 #define MV88E6352_G2_SCRATCH_GPIO_CFG0 0x60 253 #define MV88E6352_G2_SCRATCH_GPIO_CFG1 0x61 254 /* Offset 0x62-0x63: GPIO Direction */ 255 #define MV88E6352_G2_SCRATCH_GPIO_DIR0 0x62 256 #define MV88E6352_G2_SCRATCH_GPIO_DIR1 0x63 257 #define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT 0 258 #define MV88E6352_G2_SCRATCH_GPIO_DIR_IN 1 259 /* Offset 0x64-0x65: GPIO Data */ 260 #define MV88E6352_G2_SCRATCH_GPIO_DATA0 0x64 261 #define MV88E6352_G2_SCRATCH_GPIO_DATA1 0x65 262 /* Offset 0x68-0x6F: GPIO Pin Control */ 263 #define MV88E6352_G2_SCRATCH_GPIO_PCTL0 0x68 264 #define MV88E6352_G2_SCRATCH_GPIO_PCTL1 0x69 265 #define MV88E6352_G2_SCRATCH_GPIO_PCTL2 0x6A 266 #define MV88E6352_G2_SCRATCH_GPIO_PCTL3 0x6B 267 #define MV88E6352_G2_SCRATCH_GPIO_PCTL4 0x6C 268 #define MV88E6352_G2_SCRATCH_GPIO_PCTL5 0x6D 269 #define MV88E6352_G2_SCRATCH_GPIO_PCTL6 0x6E 270 #define MV88E6352_G2_SCRATCH_GPIO_PCTL7 0x6F 271 #define MV88E6352_G2_SCRATCH_CONFIG_DATA0 0x70 272 #define MV88E6352_G2_SCRATCH_CONFIG_DATA1 0x71 273 #define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU BIT(2) 274 #define MV88E6352_G2_SCRATCH_CONFIG_DATA2 0x72 275 #define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK 0x3 276 277 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO 0 278 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG 1 279 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ 2 280 281 #ifdef CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 282 283 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip) 284 { 285 return 0; 286 } 287 288 int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); 289 int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val); 290 int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update); 291 int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask); 292 293 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 294 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 295 296 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, 297 struct mii_bus *bus, 298 int addr, int reg, u16 *val); 299 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, 300 struct mii_bus *bus, 301 int addr, int reg, u16 val); 302 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr); 303 304 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, 305 struct ethtool_eeprom *eeprom, u8 *data); 306 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, 307 struct ethtool_eeprom *eeprom, u8 *data); 308 309 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, 310 struct ethtool_eeprom *eeprom, u8 *data); 311 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 312 struct ethtool_eeprom *eeprom, u8 *data); 313 314 int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev, 315 int src_port, u16 data); 316 int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip); 317 318 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip); 319 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip); 320 321 int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip, 322 struct mii_bus *bus); 323 void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip, 324 struct mii_bus *bus); 325 326 int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 327 int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 328 329 int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip); 330 331 int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip); 332 333 int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target, 334 int port); 335 336 extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops; 337 extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops; 338 339 extern const struct mv88e6xxx_avb_ops mv88e6165_avb_ops; 340 extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops; 341 extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops; 342 343 extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops; 344 345 int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, 346 bool external); 347 348 #else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */ 349 350 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip) 351 { 352 if (chip->info->global2_addr) { 353 dev_err(chip->dev, "this chip requires CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 enabled\n"); 354 return -EOPNOTSUPP; 355 } 356 357 return 0; 358 } 359 360 static inline int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 361 { 362 return -EOPNOTSUPP; 363 } 364 365 static inline int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 366 { 367 return -EOPNOTSUPP; 368 } 369 370 static inline int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update) 371 { 372 return -EOPNOTSUPP; 373 } 374 375 static inline int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask) 376 { 377 return -EOPNOTSUPP; 378 } 379 380 static inline int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, 381 int port) 382 { 383 return -EOPNOTSUPP; 384 } 385 386 static inline int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, 387 int port) 388 { 389 return -EOPNOTSUPP; 390 } 391 392 static inline int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, 393 struct mii_bus *bus, 394 int addr, int reg, u16 *val) 395 { 396 return -EOPNOTSUPP; 397 } 398 399 static inline int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, 400 struct mii_bus *bus, 401 int addr, int reg, u16 val) 402 { 403 return -EOPNOTSUPP; 404 } 405 406 static inline int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, 407 u8 *addr) 408 { 409 return -EOPNOTSUPP; 410 } 411 412 static inline int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, 413 struct ethtool_eeprom *eeprom, 414 u8 *data) 415 { 416 return -EOPNOTSUPP; 417 } 418 419 static inline int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, 420 struct ethtool_eeprom *eeprom, 421 u8 *data) 422 { 423 return -EOPNOTSUPP; 424 } 425 426 static inline int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, 427 struct ethtool_eeprom *eeprom, 428 u8 *data) 429 { 430 return -EOPNOTSUPP; 431 } 432 433 static inline int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 434 struct ethtool_eeprom *eeprom, 435 u8 *data) 436 { 437 return -EOPNOTSUPP; 438 } 439 440 static inline int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, 441 int src_dev, int src_port, u16 data) 442 { 443 return -EOPNOTSUPP; 444 } 445 446 static inline int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip) 447 { 448 return -EOPNOTSUPP; 449 } 450 451 static inline int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip) 452 { 453 return -EOPNOTSUPP; 454 } 455 456 static inline void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip) 457 { 458 } 459 460 static inline int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip, 461 struct mii_bus *bus) 462 { 463 return 0; 464 } 465 466 static inline void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip, 467 struct mii_bus *bus) 468 { 469 } 470 471 static inline int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 472 { 473 return -EOPNOTSUPP; 474 } 475 476 static inline int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 477 { 478 return -EOPNOTSUPP; 479 } 480 481 static inline int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip) 482 { 483 return -EOPNOTSUPP; 484 } 485 486 static const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {}; 487 static const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {}; 488 489 static const struct mv88e6xxx_avb_ops mv88e6165_avb_ops = {}; 490 static const struct mv88e6xxx_avb_ops mv88e6352_avb_ops = {}; 491 static const struct mv88e6xxx_avb_ops mv88e6390_avb_ops = {}; 492 493 static const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops = {}; 494 495 static inline int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, 496 bool external) 497 { 498 return -EOPNOTSUPP; 499 } 500 501 static inline int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip) 502 { 503 return -EOPNOTSUPP; 504 } 505 506 static inline int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, 507 int target, int port) 508 { 509 return -EOPNOTSUPP; 510 } 511 512 #endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */ 513 514 #endif /* _MV88E6XXX_GLOBAL2_H */ 515