1ec561276SVivien Didelot /* 21d90016dSVivien Didelot * Marvell 88E6xxx Switch Global 2 Registers support 3ec561276SVivien Didelot * 4ec561276SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 5ec561276SVivien Didelot * 64333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 74333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8ec561276SVivien Didelot * 9ec561276SVivien Didelot * This program is free software; you can redistribute it and/or modify 10ec561276SVivien Didelot * it under the terms of the GNU General Public License as published by 11ec561276SVivien Didelot * the Free Software Foundation; either version 2 of the License, or 12ec561276SVivien Didelot * (at your option) any later version. 13ec561276SVivien Didelot */ 14ec561276SVivien Didelot 15ec561276SVivien Didelot #ifndef _MV88E6XXX_GLOBAL2_H 16ec561276SVivien Didelot #define _MV88E6XXX_GLOBAL2_H 17ec561276SVivien Didelot 184d5f2ba7SVivien Didelot #include "chip.h" 19ec561276SVivien Didelot 201d90016dSVivien Didelot /* Offset 0x00: Interrupt Source Register */ 21d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_SRC 0x00 22d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_SRC_WDOG 0x8000 23d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x4000 24d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000 25d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x1000 26d6c5e6afSVivien Didelot #define MV88E6352_G2_INT_SRC_SERDES 0x0800 27d6c5e6afSVivien Didelot #define MV88E6352_G2_INT_SRC_PHY 0x001f 28d6c5e6afSVivien Didelot #define MV88E6390_G2_INT_SRC_PHY 0x07fe 29d6c5e6afSVivien Didelot 301d90016dSVivien Didelot #define MV88E6XXX_G2_INT_SOURCE_WATCHDOG 15 311d90016dSVivien Didelot 321d90016dSVivien Didelot /* Offset 0x01: Interrupt Mask Register */ 331d90016dSVivien Didelot #define MV88E6XXX_G2_INT_MASK 0x01 34d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_MASK_WDOG 0x8000 35d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_MASK_JAM_LIMIT 0x4000 36d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH 0x2000 37d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_MASK_WAKE_EVENT 0x1000 38d6c5e6afSVivien Didelot #define MV88E6352_G2_INT_MASK_SERDES 0x0800 39d6c5e6afSVivien Didelot #define MV88E6352_G2_INT_MASK_PHY 0x001f 40d6c5e6afSVivien Didelot #define MV88E6390_G2_INT_MASK_PHY 0x07fe 416bff47beSVivien Didelot 426bff47beSVivien Didelot /* Offset 0x02: MGMT Enable Register 2x */ 436bff47beSVivien Didelot #define MV88E6XXX_G2_MGMT_EN_2X 0x02 446bff47beSVivien Didelot 456bff47beSVivien Didelot /* Offset 0x03: MGMT Enable Register 0x */ 466bff47beSVivien Didelot #define MV88E6XXX_G2_MGMT_EN_0X 0x03 476bff47beSVivien Didelot 481d90016dSVivien Didelot /* Offset 0x04: Flow Control Delay Register */ 491d90016dSVivien Didelot #define MV88E6XXX_G2_FLOW_CTL 0x04 506bff47beSVivien Didelot 516bff47beSVivien Didelot /* Offset 0x05: Switch Management Register */ 526bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT 0x05 536bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA 0x8000 546bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS 0x4000 556bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x2000 566bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080 576bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008 58067e474aSVivien Didelot 59067e474aSVivien Didelot /* Offset 0x06: Device Mapping Table Register */ 60067e474aSVivien Didelot #define MV88E6XXX_G2_DEVICE_MAPPING 0x06 61067e474aSVivien Didelot #define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x8000 62067e474aSVivien Didelot #define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK 0x1f00 63067e474aSVivien Didelot #define MV88E6XXX_G2_DEVICE_MAPPING_PORT_MASK 0x000f 6456dc7347SVivien Didelot 6556dc7347SVivien Didelot /* Offset 0x07: Trunk Mask Table Register */ 6656dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MASK 0x07 6756dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MASK_UPDATE 0x8000 6856dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK 0x7000 6956dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MASK_HASH 0x0800 7056dc7347SVivien Didelot 7156dc7347SVivien Didelot /* Offset 0x08: Trunk Mapping Table Register */ 7256dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MAPPING 0x08 7356dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE 0x8000 7456dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK 0x7800 75cd8da8bbSVivien Didelot 76cd8da8bbSVivien Didelot /* Offset 0x09: Ingress Rate Command Register */ 77cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_CMD 0x09 78cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_CMD_BUSY 0x8000 79cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_MASK 0x7000 80cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_NOOP 0x0000 81cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_INIT_ALL 0x1000 82cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_INIT_RES 0x2000 83cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_WRITE_REG 0x3000 84cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_READ_REG 0x4000 85cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_OP_MASK 0x6000 86cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_OP_READ_REG 0x0000 87cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_OP_INIT_ALL 0x2000 88cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_OP_INIT_RES 0x4000 89cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_OP_WRITE_REG 0x6000 90cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_PORT_MASK 0x0f00 91cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_PORT_MASK 0x1f00 92cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_CMD_RES_MASK 0x00e0 93cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_CMD_REG_MASK 0x000f 94cd8da8bbSVivien Didelot 95cd8da8bbSVivien Didelot /* Offset 0x0A: Ingress Rate Data Register */ 96cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_DATA 0x0a 97cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_DATA_MASK 0xffff 98cd8da8bbSVivien Didelot 9967d1ea8eSVivien Didelot /* Offset 0x0B: Cross-chip Port VLAN Register */ 10067d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR 0x0b 10167d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_BUSY 0x8000 10267d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_OP_MASK 0x7000 10367d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES 0x1000 10467d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN 0x3000 10567d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_OP_READ 0x4000 10667d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff 10767d1ea8eSVivien Didelot 10867d1ea8eSVivien Didelot /* Offset 0x0C: Cross-chip Port VLAN Data Register */ 10967d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_DATA 0x0c 11067d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_DATA_MASK 0x7f 11167d1ea8eSVivien Didelot 112ed44152fSVivien Didelot /* Offset 0x0D: Switch MAC/WoL/WoF Register */ 113ed44152fSVivien Didelot #define MV88E6XXX_G2_SWITCH_MAC 0x0d 114ed44152fSVivien Didelot #define MV88E6XXX_G2_SWITCH_MAC_UPDATE 0x8000 115ed44152fSVivien Didelot #define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK 0x1f00 116ed44152fSVivien Didelot #define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK 0x00ff 117ed44152fSVivien Didelot 1181d90016dSVivien Didelot /* Offset 0x0E: ATU Stats Register */ 1191d90016dSVivien Didelot #define MV88E6XXX_G2_ATU_STATS 0x0e 1201d90016dSVivien Didelot 1211d90016dSVivien Didelot /* Offset 0x0F: Priority Override Table */ 1221d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f 1231d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE 0x8000 1241d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET 0x1000 1251d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00 1261d90016dSVivien Didelot #define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN 0x0080 1271d90016dSVivien Didelot #define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030 1281d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN 0x0008 1291d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK 0x0007 1307fc8c9d5SVivien Didelot 1317fc8c9d5SVivien Didelot /* Offset 0x14: EEPROM Command */ 1327fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD 0x14 1337fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_BUSY 0x8000 1347fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_OP_MASK 0x7000 1357fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE 0x3000 1367fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_OP_READ 0x4000 1377fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD 0x6000 1387fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_RUNNING 0x0800 1397fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN 0x0400 1407fc8c9d5SVivien Didelot #define MV88E6352_G2_EEPROM_CMD_ADDR_MASK 0x00ff 1417fc8c9d5SVivien Didelot #define MV88E6390_G2_EEPROM_CMD_DATA_MASK 0x00ff 1427fc8c9d5SVivien Didelot 1437fc8c9d5SVivien Didelot /* Offset 0x15: EEPROM Data */ 1447fc8c9d5SVivien Didelot #define MV88E6352_G2_EEPROM_DATA 0x15 1457fc8c9d5SVivien Didelot #define MV88E6352_G2_EEPROM_DATA_MASK 0xffff 1467fc8c9d5SVivien Didelot 1477fc8c9d5SVivien Didelot /* Offset 0x15: EEPROM Addr */ 1487fc8c9d5SVivien Didelot #define MV88E6390_G2_EEPROM_ADDR 0x15 1497fc8c9d5SVivien Didelot #define MV88E6390_G2_EEPROM_ADDR_MASK 0xffff 1507fc8c9d5SVivien Didelot 1511d90016dSVivien Didelot /* Offset 0x16: AVB Command Register */ 1521d90016dSVivien Didelot #define MV88E6352_G2_AVB_CMD 0x16 1530d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_BUSY 0x8000 1540d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_OP_READ 0x4000 1550d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_OP_READ_INCR 0x6000 1560d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_OP_WRITE 0x3000 1570d632c3dSBrandon Streiff #define MV88E6390_G2_AVB_CMD_OP_READ 0x0000 1580d632c3dSBrandon Streiff #define MV88E6390_G2_AVB_CMD_OP_READ_INCR 0x4000 1590d632c3dSBrandon Streiff #define MV88E6390_G2_AVB_CMD_OP_WRITE 0x6000 1600d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_PORT_MASK 0x0f00 1610d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_PORT_TAIGLOBAL 0xe 1620d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_PORT_PTPGLOBAL 0xf 1630d632c3dSBrandon Streiff #define MV88E6390_G2_AVB_CMD_PORT_MASK 0x1f00 1640d632c3dSBrandon Streiff #define MV88E6390_G2_AVB_CMD_PORT_TAIGLOBAL 0x1e 1650d632c3dSBrandon Streiff #define MV88E6390_G2_AVB_CMD_PORT_PTPGLOBAL 0x1f 1660d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_BLOCK_PTP 0 1670d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_BLOCK_AVB 1 1680d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_BLOCK_QAV 2 1690d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_BLOCK_QVB 3 1700d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_BLOCK_MASK 0x00e0 1710d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_ADDR_MASK 0x001f 1721d90016dSVivien Didelot 1731d90016dSVivien Didelot /* Offset 0x17: AVB Data Register */ 1741d90016dSVivien Didelot #define MV88E6352_G2_AVB_DATA 0x17 175d23a83f2SVivien Didelot 176e289ef0dSVivien Didelot /* Offset 0x18: SMI PHY Command Register */ 177e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD 0x18 178e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_BUSY 0x8000 179e289ef0dSVivien Didelot #define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK 0x6000 180e289ef0dSVivien Didelot #define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL 0x0000 181e289ef0dSVivien Didelot #define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL 0x2000 182e289ef0dSVivien Didelot #define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP 0x4000 183e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK 0x1000 184e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45 0x0000 185e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22 0x1000 186e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK 0x0c00 187e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA 0x0400 188e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA 0x0800 189e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR 0x0000 190e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA 0x0400 191e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC 0x0800 192e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA 0x0c00 193e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK 0x03e0 194e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK 0x001f 195e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK 0x03ff 196e289ef0dSVivien Didelot 197e289ef0dSVivien Didelot /* Offset 0x19: SMI PHY Data Register */ 198e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_DATA 0x19 199e289ef0dSVivien Didelot 2001d90016dSVivien Didelot /* Offset 0x1A: Scratch and Misc. Register */ 2011d90016dSVivien Didelot #define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a 2021d90016dSVivien Didelot #define MV88E6XXX_G2_SCRATCH_MISC_UPDATE 0x8000 2031d90016dSVivien Didelot #define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK 0x7f00 2041d90016dSVivien Didelot #define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff 2053b19df73SVivien Didelot 2063b19df73SVivien Didelot /* Offset 0x1B: Watch Dog Control Register */ 2073b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL 0x1b 2083b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT 0x0080 2093b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT 0x0040 2103b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_QC_ENABLE 0x0020 2113b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY 0x0010 2123b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE 0x0008 2133b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_FORCE_IRQ 0x0004 2143b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_HISTORY 0x0002 2153b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_SWRESET 0x0001 2163b19df73SVivien Didelot 2173b19df73SVivien Didelot /* Offset 0x1B: Watch Dog Control Register */ 2183b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL 0x1b 2193b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_UPDATE 0x8000 2203b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_MASK 0x7f00 2213b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE 0x0000 2223b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_INT_STS 0x1000 2233b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE 0x1100 2243b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_EVENT 0x1200 2253b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_HISTORY 0x1300 2263b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_DATA_MASK 0x00ff 2273b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_CUT_THROUGH 0x0008 2283b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER 0x0004 2293b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_EGRESS 0x0002 2303b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_FORCE_IRQ 0x0001 2313b19df73SVivien Didelot 2321d90016dSVivien Didelot /* Offset 0x1C: QoS Weights Register */ 2331d90016dSVivien Didelot #define MV88E6XXX_G2_QOS_WEIGHTS 0x1c 2341d90016dSVivien Didelot #define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE 0x8000 2351d90016dSVivien Didelot #define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK 0x3f00 2361d90016dSVivien Didelot #define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK 0x7f00 2371d90016dSVivien Didelot #define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK 0x00ff 2381d90016dSVivien Didelot 2391d90016dSVivien Didelot /* Offset 0x1D: Misc Register */ 2401d90016dSVivien Didelot #define MV88E6XXX_G2_MISC 0x1d 2411d90016dSVivien Didelot #define MV88E6XXX_G2_MISC_5_BIT_PORT 0x4000 2421d90016dSVivien Didelot #define MV88E6352_G2_NOEGR_POLICY 0x2000 2431d90016dSVivien Didelot #define MV88E6390_G2_LAG_ID_4 0x2000 244d23a83f2SVivien Didelot 245a73ccd61SBrandon Streiff /* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */ 246a73ccd61SBrandon Streiff /* Offset 0x02: Misc Configuration */ 247a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_MISC_CFG 0x02 248a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI 0x80 249a73ccd61SBrandon Streiff /* Offset 0x60-0x61: GPIO Configuration */ 250a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_CFG0 0x60 251a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_CFG1 0x61 252a73ccd61SBrandon Streiff /* Offset 0x62-0x63: GPIO Direction */ 253a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_DIR0 0x62 254a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_DIR1 0x63 255a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT 0 256a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_DIR_IN 1 257a73ccd61SBrandon Streiff /* Offset 0x64-0x65: GPIO Data */ 258a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_DATA0 0x64 259a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_DATA1 0x65 260a73ccd61SBrandon Streiff /* Offset 0x68-0x6F: GPIO Pin Control */ 261a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL0 0x68 262a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL1 0x69 263a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL2 0x6A 264a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL3 0x6B 265a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL4 0x6C 266a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL5 0x6D 267a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL6 0x6E 268a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL7 0x6F 2692510babcSAndrew Lunn #define MV88E6352_G2_SCRATCH_CONFIG_DATA0 0x70 2702510babcSAndrew Lunn #define MV88E6352_G2_SCRATCH_CONFIG_DATA1 0x71 2712510babcSAndrew Lunn #define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU BIT(2) 2722510babcSAndrew Lunn #define MV88E6352_G2_SCRATCH_CONFIG_DATA2 0x72 2732510babcSAndrew Lunn #define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK 0x3 274a73ccd61SBrandon Streiff 275a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO 0 276a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG 1 277a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ 2 278a73ccd61SBrandon Streiff 279ca070c10SVivien Didelot #ifdef CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 280ca070c10SVivien Didelot 281ca070c10SVivien Didelot static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip) 282ca070c10SVivien Didelot { 283ca070c10SVivien Didelot return 0; 284ca070c10SVivien Didelot } 285ca070c10SVivien Didelot 286b000be95SBrandon Streiff int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); 287b000be95SBrandon Streiff int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val); 288b000be95SBrandon Streiff int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update); 289b000be95SBrandon Streiff int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask); 290b000be95SBrandon Streiff 291cd8da8bbSVivien Didelot int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 292cd8da8bbSVivien Didelot int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 293cd8da8bbSVivien Didelot 294ee26a228SAndrew Lunn int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, 295ee26a228SAndrew Lunn struct mii_bus *bus, 296ee26a228SAndrew Lunn int addr, int reg, u16 *val); 297ee26a228SAndrew Lunn int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, 298ee26a228SAndrew Lunn struct mii_bus *bus, 299ee26a228SAndrew Lunn int addr, int reg, u16 val); 300ec561276SVivien Didelot int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr); 30198fc3c6fSVivien Didelot 30298fc3c6fSVivien Didelot int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, 30398fc3c6fSVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 30498fc3c6fSVivien Didelot int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, 30598fc3c6fSVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 30698fc3c6fSVivien Didelot 307ec561276SVivien Didelot int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, 308ec561276SVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 309ec561276SVivien Didelot int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 310ec561276SVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 31198fc3c6fSVivien Didelot 31217a1594eSVivien Didelot int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev, 31317a1594eSVivien Didelot int src_port, u16 data); 31481228996SVivien Didelot int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip); 31581228996SVivien Didelot 316ec561276SVivien Didelot int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip); 317dc30c35bSAndrew Lunn int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip); 318dc30c35bSAndrew Lunn void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip); 31951c901a7SVivien Didelot 3206f88284fSAndrew Lunn int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip, 3216f88284fSAndrew Lunn struct mii_bus *bus); 3226f88284fSAndrew Lunn void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip, 3236f88284fSAndrew Lunn struct mii_bus *bus); 3246f88284fSAndrew Lunn 32551c901a7SVivien Didelot int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 32651c901a7SVivien Didelot int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 327ec561276SVivien Didelot 3289e907d73SVivien Didelot int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip); 3299e907d73SVivien Didelot 330b28f872dSVivien Didelot int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip); 331b28f872dSVivien Didelot 332fcd25166SAndrew Lunn extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops; 33361303736SAndrew Lunn extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops; 334fcd25166SAndrew Lunn 3350d632c3dSBrandon Streiff extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops; 3360d632c3dSBrandon Streiff extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops; 3370d632c3dSBrandon Streiff 338a73ccd61SBrandon Streiff extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops; 339a73ccd61SBrandon Streiff 3402510babcSAndrew Lunn int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, 3412510babcSAndrew Lunn bool external); 3422510babcSAndrew Lunn 343ca070c10SVivien Didelot #else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */ 344ca070c10SVivien Didelot 345ca070c10SVivien Didelot static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip) 346ca070c10SVivien Didelot { 3479069c13aSVivien Didelot if (chip->info->global2_addr) { 348ca070c10SVivien Didelot dev_err(chip->dev, "this chip requires CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 enabled\n"); 349ca070c10SVivien Didelot return -EOPNOTSUPP; 350ca070c10SVivien Didelot } 351ca070c10SVivien Didelot 352ca070c10SVivien Didelot return 0; 353ca070c10SVivien Didelot } 354ca070c10SVivien Didelot 35546182452SArnd Bergmann static inline int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 356b000be95SBrandon Streiff { 357b000be95SBrandon Streiff return -EOPNOTSUPP; 358b000be95SBrandon Streiff } 359b000be95SBrandon Streiff 36046182452SArnd Bergmann static inline int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 361b000be95SBrandon Streiff { 362b000be95SBrandon Streiff return -EOPNOTSUPP; 363b000be95SBrandon Streiff } 364b000be95SBrandon Streiff 36546182452SArnd Bergmann static inline int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update) 366b000be95SBrandon Streiff { 367b000be95SBrandon Streiff return -EOPNOTSUPP; 368b000be95SBrandon Streiff } 369b000be95SBrandon Streiff 37046182452SArnd Bergmann static inline int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask) 371b000be95SBrandon Streiff { 372b000be95SBrandon Streiff return -EOPNOTSUPP; 373b000be95SBrandon Streiff } 374b000be95SBrandon Streiff 375cd8da8bbSVivien Didelot static inline int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, 376cd8da8bbSVivien Didelot int port) 377cd8da8bbSVivien Didelot { 378cd8da8bbSVivien Didelot return -EOPNOTSUPP; 379cd8da8bbSVivien Didelot } 380cd8da8bbSVivien Didelot 381cd8da8bbSVivien Didelot static inline int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, 382cd8da8bbSVivien Didelot int port) 383cd8da8bbSVivien Didelot { 384cd8da8bbSVivien Didelot return -EOPNOTSUPP; 385cd8da8bbSVivien Didelot } 386cd8da8bbSVivien Didelot 387ca070c10SVivien Didelot static inline int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, 388ee26a228SAndrew Lunn struct mii_bus *bus, 389ca070c10SVivien Didelot int addr, int reg, u16 *val) 390ca070c10SVivien Didelot { 391ca070c10SVivien Didelot return -EOPNOTSUPP; 392ca070c10SVivien Didelot } 393ca070c10SVivien Didelot 394ca070c10SVivien Didelot static inline int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, 395ee26a228SAndrew Lunn struct mii_bus *bus, 396ca070c10SVivien Didelot int addr, int reg, u16 val) 397ca070c10SVivien Didelot { 398ca070c10SVivien Didelot return -EOPNOTSUPP; 399ca070c10SVivien Didelot } 400ca070c10SVivien Didelot 401ca070c10SVivien Didelot static inline int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, 402ca070c10SVivien Didelot u8 *addr) 403ca070c10SVivien Didelot { 404ca070c10SVivien Didelot return -EOPNOTSUPP; 405ca070c10SVivien Didelot } 406ca070c10SVivien Didelot 40798fc3c6fSVivien Didelot static inline int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, 40898fc3c6fSVivien Didelot struct ethtool_eeprom *eeprom, 40998fc3c6fSVivien Didelot u8 *data) 41098fc3c6fSVivien Didelot { 41198fc3c6fSVivien Didelot return -EOPNOTSUPP; 41298fc3c6fSVivien Didelot } 41398fc3c6fSVivien Didelot 41498fc3c6fSVivien Didelot static inline int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, 41598fc3c6fSVivien Didelot struct ethtool_eeprom *eeprom, 41698fc3c6fSVivien Didelot u8 *data) 41798fc3c6fSVivien Didelot { 41898fc3c6fSVivien Didelot return -EOPNOTSUPP; 41998fc3c6fSVivien Didelot } 42098fc3c6fSVivien Didelot 421ca070c10SVivien Didelot static inline int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, 422ca070c10SVivien Didelot struct ethtool_eeprom *eeprom, 423ca070c10SVivien Didelot u8 *data) 424ca070c10SVivien Didelot { 425ca070c10SVivien Didelot return -EOPNOTSUPP; 426ca070c10SVivien Didelot } 427ca070c10SVivien Didelot 428ca070c10SVivien Didelot static inline int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 429ca070c10SVivien Didelot struct ethtool_eeprom *eeprom, 430ca070c10SVivien Didelot u8 *data) 431ca070c10SVivien Didelot { 432ca070c10SVivien Didelot return -EOPNOTSUPP; 433ca070c10SVivien Didelot } 434ca070c10SVivien Didelot 43559b2c314SArnd Bergmann static inline int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, 43659b2c314SArnd Bergmann int src_dev, int src_port, u16 data) 43717a1594eSVivien Didelot { 43817a1594eSVivien Didelot return -EOPNOTSUPP; 43917a1594eSVivien Didelot } 44017a1594eSVivien Didelot 44159b2c314SArnd Bergmann static inline int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip) 44281228996SVivien Didelot { 44381228996SVivien Didelot return -EOPNOTSUPP; 44481228996SVivien Didelot } 44581228996SVivien Didelot 446ca070c10SVivien Didelot static inline int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip) 447ca070c10SVivien Didelot { 448ca070c10SVivien Didelot return -EOPNOTSUPP; 449ca070c10SVivien Didelot } 450ca070c10SVivien Didelot 451dc30c35bSAndrew Lunn static inline int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip) 452dc30c35bSAndrew Lunn { 453dc30c35bSAndrew Lunn return -EOPNOTSUPP; 454dc30c35bSAndrew Lunn } 455dc30c35bSAndrew Lunn 456dc30c35bSAndrew Lunn static inline void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip) 457dc30c35bSAndrew Lunn { 458dc30c35bSAndrew Lunn } 459dc30c35bSAndrew Lunn 4606f88284fSAndrew Lunn static inline int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip, 4616f88284fSAndrew Lunn struct mii_bus *bus) 4626f88284fSAndrew Lunn { 4636f88284fSAndrew Lunn return 0; 4646f88284fSAndrew Lunn } 4656f88284fSAndrew Lunn 4666f88284fSAndrew Lunn static inline void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip, 4676f88284fSAndrew Lunn struct mii_bus *bus) 4686f88284fSAndrew Lunn { 4696f88284fSAndrew Lunn } 4706f88284fSAndrew Lunn 47151c901a7SVivien Didelot static inline int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 47251c901a7SVivien Didelot { 47351c901a7SVivien Didelot return -EOPNOTSUPP; 47451c901a7SVivien Didelot } 47551c901a7SVivien Didelot 47651c901a7SVivien Didelot static inline int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 4776e55f698SAndrew Lunn { 4786e55f698SAndrew Lunn return -EOPNOTSUPP; 4796e55f698SAndrew Lunn } 4806e55f698SAndrew Lunn 4819e907d73SVivien Didelot static inline int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip) 4829e907d73SVivien Didelot { 4839e907d73SVivien Didelot return -EOPNOTSUPP; 4849e907d73SVivien Didelot } 4859e907d73SVivien Didelot 486fcd25166SAndrew Lunn static const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {}; 48761303736SAndrew Lunn static const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {}; 488fcd25166SAndrew Lunn 4890d632c3dSBrandon Streiff static const struct mv88e6xxx_avb_ops mv88e6352_avb_ops = {}; 4900d632c3dSBrandon Streiff static const struct mv88e6xxx_avb_ops mv88e6390_avb_ops = {}; 4910d632c3dSBrandon Streiff 492a73ccd61SBrandon Streiff static const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops = {}; 493a73ccd61SBrandon Streiff 4942510babcSAndrew Lunn static inline int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, 4952510babcSAndrew Lunn bool external) 4962510babcSAndrew Lunn { 4972510babcSAndrew Lunn return -EOPNOTSUPP; 4982510babcSAndrew Lunn } 4992510babcSAndrew Lunn 500b28f872dSVivien Didelot static inline int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip) 501b28f872dSVivien Didelot { 502b28f872dSVivien Didelot return -EOPNOTSUPP; 503b28f872dSVivien Didelot } 504b28f872dSVivien Didelot 505ca070c10SVivien Didelot #endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */ 506ca070c10SVivien Didelot 507ec561276SVivien Didelot #endif /* _MV88E6XXX_GLOBAL2_H */ 508