1ec561276SVivien Didelot /* 21d90016dSVivien Didelot * Marvell 88E6xxx Switch Global 2 Registers support 3ec561276SVivien Didelot * 4ec561276SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 5ec561276SVivien Didelot * 64333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 74333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8ec561276SVivien Didelot * 9ec561276SVivien Didelot * This program is free software; you can redistribute it and/or modify 10ec561276SVivien Didelot * it under the terms of the GNU General Public License as published by 11ec561276SVivien Didelot * the Free Software Foundation; either version 2 of the License, or 12ec561276SVivien Didelot * (at your option) any later version. 13ec561276SVivien Didelot */ 14ec561276SVivien Didelot 15ec561276SVivien Didelot #ifndef _MV88E6XXX_GLOBAL2_H 16ec561276SVivien Didelot #define _MV88E6XXX_GLOBAL2_H 17ec561276SVivien Didelot 184d5f2ba7SVivien Didelot #include "chip.h" 19ec561276SVivien Didelot 201d90016dSVivien Didelot #define MV88E6XXX_G2 0x1c 21d23a83f2SVivien Didelot 221d90016dSVivien Didelot /* Offset 0x00: Interrupt Source Register */ 231d90016dSVivien Didelot #define MV88E6XXX_G2_INT_SOURCE 0x00 241d90016dSVivien Didelot #define MV88E6XXX_G2_INT_SOURCE_WATCHDOG 15 251d90016dSVivien Didelot 261d90016dSVivien Didelot /* Offset 0x01: Interrupt Mask Register */ 271d90016dSVivien Didelot #define MV88E6XXX_G2_INT_MASK 0x01 286bff47beSVivien Didelot 296bff47beSVivien Didelot /* Offset 0x02: MGMT Enable Register 2x */ 306bff47beSVivien Didelot #define MV88E6XXX_G2_MGMT_EN_2X 0x02 316bff47beSVivien Didelot 326bff47beSVivien Didelot /* Offset 0x03: MGMT Enable Register 0x */ 336bff47beSVivien Didelot #define MV88E6XXX_G2_MGMT_EN_0X 0x03 346bff47beSVivien Didelot 351d90016dSVivien Didelot /* Offset 0x04: Flow Control Delay Register */ 361d90016dSVivien Didelot #define MV88E6XXX_G2_FLOW_CTL 0x04 376bff47beSVivien Didelot 386bff47beSVivien Didelot /* Offset 0x05: Switch Management Register */ 396bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT 0x05 406bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA 0x8000 416bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS 0x4000 426bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x2000 436bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080 446bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008 45067e474aSVivien Didelot 46067e474aSVivien Didelot /* Offset 0x06: Device Mapping Table Register */ 47067e474aSVivien Didelot #define MV88E6XXX_G2_DEVICE_MAPPING 0x06 48067e474aSVivien Didelot #define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x8000 49067e474aSVivien Didelot #define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK 0x1f00 50067e474aSVivien Didelot #define MV88E6XXX_G2_DEVICE_MAPPING_PORT_MASK 0x000f 5156dc7347SVivien Didelot 5256dc7347SVivien Didelot /* Offset 0x07: Trunk Mask Table Register */ 5356dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MASK 0x07 5456dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MASK_UPDATE 0x8000 5556dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK 0x7000 5656dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MASK_HASH 0x0800 5756dc7347SVivien Didelot 5856dc7347SVivien Didelot /* Offset 0x08: Trunk Mapping Table Register */ 5956dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MAPPING 0x08 6056dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE 0x8000 6156dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK 0x7800 62cd8da8bbSVivien Didelot 63cd8da8bbSVivien Didelot /* Offset 0x09: Ingress Rate Command Register */ 64cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_CMD 0x09 65cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_CMD_BUSY 0x8000 66cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_MASK 0x7000 67cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_NOOP 0x0000 68cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_INIT_ALL 0x1000 69cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_INIT_RES 0x2000 70cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_WRITE_REG 0x3000 71cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_READ_REG 0x4000 72cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_OP_MASK 0x6000 73cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_OP_READ_REG 0x0000 74cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_OP_INIT_ALL 0x2000 75cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_OP_INIT_RES 0x4000 76cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_OP_WRITE_REG 0x6000 77cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_PORT_MASK 0x0f00 78cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_PORT_MASK 0x1f00 79cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_CMD_RES_MASK 0x00e0 80cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_CMD_REG_MASK 0x000f 81cd8da8bbSVivien Didelot 82cd8da8bbSVivien Didelot /* Offset 0x0A: Ingress Rate Data Register */ 83cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_DATA 0x0a 84cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_DATA_MASK 0xffff 85cd8da8bbSVivien Didelot 8667d1ea8eSVivien Didelot /* Offset 0x0B: Cross-chip Port VLAN Register */ 8767d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR 0x0b 8867d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_BUSY 0x8000 8967d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_OP_MASK 0x7000 9067d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES 0x1000 9167d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN 0x3000 9267d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_OP_READ 0x4000 9367d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff 9467d1ea8eSVivien Didelot 9567d1ea8eSVivien Didelot /* Offset 0x0C: Cross-chip Port VLAN Data Register */ 9667d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_DATA 0x0c 9767d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_DATA_MASK 0x7f 9867d1ea8eSVivien Didelot 99ed44152fSVivien Didelot /* Offset 0x0D: Switch MAC/WoL/WoF Register */ 100ed44152fSVivien Didelot #define MV88E6XXX_G2_SWITCH_MAC 0x0d 101ed44152fSVivien Didelot #define MV88E6XXX_G2_SWITCH_MAC_UPDATE 0x8000 102ed44152fSVivien Didelot #define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK 0x1f00 103ed44152fSVivien Didelot #define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK 0x00ff 104ed44152fSVivien Didelot 1051d90016dSVivien Didelot /* Offset 0x0E: ATU Stats Register */ 1061d90016dSVivien Didelot #define MV88E6XXX_G2_ATU_STATS 0x0e 1071d90016dSVivien Didelot 1081d90016dSVivien Didelot /* Offset 0x0F: Priority Override Table */ 1091d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f 1101d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE 0x8000 1111d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET 0x1000 1121d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00 1131d90016dSVivien Didelot #define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN 0x0080 1141d90016dSVivien Didelot #define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030 1151d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN 0x0008 1161d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK 0x0007 1177fc8c9d5SVivien Didelot 1187fc8c9d5SVivien Didelot /* Offset 0x14: EEPROM Command */ 1197fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD 0x14 1207fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_BUSY 0x8000 1217fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_OP_MASK 0x7000 1227fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE 0x3000 1237fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_OP_READ 0x4000 1247fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD 0x6000 1257fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_RUNNING 0x0800 1267fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN 0x0400 1277fc8c9d5SVivien Didelot #define MV88E6352_G2_EEPROM_CMD_ADDR_MASK 0x00ff 1287fc8c9d5SVivien Didelot #define MV88E6390_G2_EEPROM_CMD_DATA_MASK 0x00ff 1297fc8c9d5SVivien Didelot 1307fc8c9d5SVivien Didelot /* Offset 0x15: EEPROM Data */ 1317fc8c9d5SVivien Didelot #define MV88E6352_G2_EEPROM_DATA 0x15 1327fc8c9d5SVivien Didelot #define MV88E6352_G2_EEPROM_DATA_MASK 0xffff 1337fc8c9d5SVivien Didelot 1347fc8c9d5SVivien Didelot /* Offset 0x15: EEPROM Addr */ 1357fc8c9d5SVivien Didelot #define MV88E6390_G2_EEPROM_ADDR 0x15 1367fc8c9d5SVivien Didelot #define MV88E6390_G2_EEPROM_ADDR_MASK 0xffff 1377fc8c9d5SVivien Didelot 1381d90016dSVivien Didelot /* Offset 0x16: AVB Command Register */ 1391d90016dSVivien Didelot #define MV88E6352_G2_AVB_CMD 0x16 1401d90016dSVivien Didelot 1411d90016dSVivien Didelot /* Offset 0x17: AVB Data Register */ 1421d90016dSVivien Didelot #define MV88E6352_G2_AVB_DATA 0x17 143d23a83f2SVivien Didelot 144e289ef0dSVivien Didelot /* Offset 0x18: SMI PHY Command Register */ 145e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD 0x18 146e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_BUSY 0x8000 147e289ef0dSVivien Didelot #define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK 0x6000 148e289ef0dSVivien Didelot #define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL 0x0000 149e289ef0dSVivien Didelot #define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL 0x2000 150e289ef0dSVivien Didelot #define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP 0x4000 151e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK 0x1000 152e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45 0x0000 153e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22 0x1000 154e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK 0x0c00 155e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA 0x0400 156e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA 0x0800 157e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR 0x0000 158e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA 0x0400 159e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC 0x0800 160e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA 0x0c00 161e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK 0x03e0 162e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK 0x001f 163e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK 0x03ff 164e289ef0dSVivien Didelot 165e289ef0dSVivien Didelot /* Offset 0x19: SMI PHY Data Register */ 166e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_DATA 0x19 167e289ef0dSVivien Didelot 1681d90016dSVivien Didelot /* Offset 0x1A: Scratch and Misc. Register */ 1691d90016dSVivien Didelot #define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a 1701d90016dSVivien Didelot #define MV88E6XXX_G2_SCRATCH_MISC_UPDATE 0x8000 1711d90016dSVivien Didelot #define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK 0x7f00 1721d90016dSVivien Didelot #define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff 1733b19df73SVivien Didelot 1743b19df73SVivien Didelot /* Offset 0x1B: Watch Dog Control Register */ 1753b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL 0x1b 1763b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT 0x0080 1773b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT 0x0040 1783b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_QC_ENABLE 0x0020 1793b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY 0x0010 1803b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE 0x0008 1813b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_FORCE_IRQ 0x0004 1823b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_HISTORY 0x0002 1833b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_SWRESET 0x0001 1843b19df73SVivien Didelot 1853b19df73SVivien Didelot /* Offset 0x1B: Watch Dog Control Register */ 1863b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL 0x1b 1873b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_UPDATE 0x8000 1883b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_MASK 0x7f00 1893b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE 0x0000 1903b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_INT_STS 0x1000 1913b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE 0x1100 1923b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_EVENT 0x1200 1933b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_HISTORY 0x1300 1943b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_DATA_MASK 0x00ff 1953b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_CUT_THROUGH 0x0008 1963b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER 0x0004 1973b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_EGRESS 0x0002 1983b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_FORCE_IRQ 0x0001 1993b19df73SVivien Didelot 2001d90016dSVivien Didelot /* Offset 0x1C: QoS Weights Register */ 2011d90016dSVivien Didelot #define MV88E6XXX_G2_QOS_WEIGHTS 0x1c 2021d90016dSVivien Didelot #define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE 0x8000 2031d90016dSVivien Didelot #define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK 0x3f00 2041d90016dSVivien Didelot #define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK 0x7f00 2051d90016dSVivien Didelot #define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK 0x00ff 2061d90016dSVivien Didelot 2071d90016dSVivien Didelot /* Offset 0x1D: Misc Register */ 2081d90016dSVivien Didelot #define MV88E6XXX_G2_MISC 0x1d 2091d90016dSVivien Didelot #define MV88E6XXX_G2_MISC_5_BIT_PORT 0x4000 2101d90016dSVivien Didelot #define MV88E6352_G2_NOEGR_POLICY 0x2000 2111d90016dSVivien Didelot #define MV88E6390_G2_LAG_ID_4 0x2000 212d23a83f2SVivien Didelot 213ca070c10SVivien Didelot #ifdef CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 214ca070c10SVivien Didelot 215ca070c10SVivien Didelot static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip) 216ca070c10SVivien Didelot { 217ca070c10SVivien Didelot return 0; 218ca070c10SVivien Didelot } 219ca070c10SVivien Didelot 220cd8da8bbSVivien Didelot int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 221cd8da8bbSVivien Didelot int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 222cd8da8bbSVivien Didelot 223ee26a228SAndrew Lunn int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, 224ee26a228SAndrew Lunn struct mii_bus *bus, 225ee26a228SAndrew Lunn int addr, int reg, u16 *val); 226ee26a228SAndrew Lunn int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, 227ee26a228SAndrew Lunn struct mii_bus *bus, 228ee26a228SAndrew Lunn int addr, int reg, u16 val); 229ec561276SVivien Didelot int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr); 23098fc3c6fSVivien Didelot 23198fc3c6fSVivien Didelot int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, 23298fc3c6fSVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 23398fc3c6fSVivien Didelot int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, 23498fc3c6fSVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 23598fc3c6fSVivien Didelot 236ec561276SVivien Didelot int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, 237ec561276SVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 238ec561276SVivien Didelot int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 239ec561276SVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 24098fc3c6fSVivien Didelot 24117a1594eSVivien Didelot int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev, 24217a1594eSVivien Didelot int src_port, u16 data); 24381228996SVivien Didelot int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip); 24481228996SVivien Didelot 245ec561276SVivien Didelot int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip); 246dc30c35bSAndrew Lunn int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip); 247dc30c35bSAndrew Lunn void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip); 2486e55f698SAndrew Lunn int mv88e6095_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 249ec561276SVivien Didelot 250fcd25166SAndrew Lunn extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops; 25161303736SAndrew Lunn extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops; 252fcd25166SAndrew Lunn 253ca070c10SVivien Didelot #else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */ 254ca070c10SVivien Didelot 255ca070c10SVivien Didelot static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip) 256ca070c10SVivien Didelot { 257ca070c10SVivien Didelot if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) { 258ca070c10SVivien Didelot dev_err(chip->dev, "this chip requires CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 enabled\n"); 259ca070c10SVivien Didelot return -EOPNOTSUPP; 260ca070c10SVivien Didelot } 261ca070c10SVivien Didelot 262ca070c10SVivien Didelot return 0; 263ca070c10SVivien Didelot } 264ca070c10SVivien Didelot 265cd8da8bbSVivien Didelot static inline int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, 266cd8da8bbSVivien Didelot int port) 267cd8da8bbSVivien Didelot { 268cd8da8bbSVivien Didelot return -EOPNOTSUPP; 269cd8da8bbSVivien Didelot } 270cd8da8bbSVivien Didelot 271cd8da8bbSVivien Didelot static inline int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, 272cd8da8bbSVivien Didelot int port) 273cd8da8bbSVivien Didelot { 274cd8da8bbSVivien Didelot return -EOPNOTSUPP; 275cd8da8bbSVivien Didelot } 276cd8da8bbSVivien Didelot 277ca070c10SVivien Didelot static inline int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, 278ee26a228SAndrew Lunn struct mii_bus *bus, 279ca070c10SVivien Didelot int addr, int reg, u16 *val) 280ca070c10SVivien Didelot { 281ca070c10SVivien Didelot return -EOPNOTSUPP; 282ca070c10SVivien Didelot } 283ca070c10SVivien Didelot 284ca070c10SVivien Didelot static inline int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, 285ee26a228SAndrew Lunn struct mii_bus *bus, 286ca070c10SVivien Didelot int addr, int reg, u16 val) 287ca070c10SVivien Didelot { 288ca070c10SVivien Didelot return -EOPNOTSUPP; 289ca070c10SVivien Didelot } 290ca070c10SVivien Didelot 291ca070c10SVivien Didelot static inline int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, 292ca070c10SVivien Didelot u8 *addr) 293ca070c10SVivien Didelot { 294ca070c10SVivien Didelot return -EOPNOTSUPP; 295ca070c10SVivien Didelot } 296ca070c10SVivien Didelot 29798fc3c6fSVivien Didelot static inline int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, 29898fc3c6fSVivien Didelot struct ethtool_eeprom *eeprom, 29998fc3c6fSVivien Didelot u8 *data) 30098fc3c6fSVivien Didelot { 30198fc3c6fSVivien Didelot return -EOPNOTSUPP; 30298fc3c6fSVivien Didelot } 30398fc3c6fSVivien Didelot 30498fc3c6fSVivien Didelot static inline int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, 30598fc3c6fSVivien Didelot struct ethtool_eeprom *eeprom, 30698fc3c6fSVivien Didelot u8 *data) 30798fc3c6fSVivien Didelot { 30898fc3c6fSVivien Didelot return -EOPNOTSUPP; 30998fc3c6fSVivien Didelot } 31098fc3c6fSVivien Didelot 311ca070c10SVivien Didelot static inline int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, 312ca070c10SVivien Didelot struct ethtool_eeprom *eeprom, 313ca070c10SVivien Didelot u8 *data) 314ca070c10SVivien Didelot { 315ca070c10SVivien Didelot return -EOPNOTSUPP; 316ca070c10SVivien Didelot } 317ca070c10SVivien Didelot 318ca070c10SVivien Didelot static inline int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 319ca070c10SVivien Didelot struct ethtool_eeprom *eeprom, 320ca070c10SVivien Didelot u8 *data) 321ca070c10SVivien Didelot { 322ca070c10SVivien Didelot return -EOPNOTSUPP; 323ca070c10SVivien Didelot } 324ca070c10SVivien Didelot 32559b2c314SArnd Bergmann static inline int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, 32659b2c314SArnd Bergmann int src_dev, int src_port, u16 data) 32717a1594eSVivien Didelot { 32817a1594eSVivien Didelot return -EOPNOTSUPP; 32917a1594eSVivien Didelot } 33017a1594eSVivien Didelot 33159b2c314SArnd Bergmann static inline int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip) 33281228996SVivien Didelot { 33381228996SVivien Didelot return -EOPNOTSUPP; 33481228996SVivien Didelot } 33581228996SVivien Didelot 336ca070c10SVivien Didelot static inline int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip) 337ca070c10SVivien Didelot { 338ca070c10SVivien Didelot return -EOPNOTSUPP; 339ca070c10SVivien Didelot } 340ca070c10SVivien Didelot 341dc30c35bSAndrew Lunn static inline int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip) 342dc30c35bSAndrew Lunn { 343dc30c35bSAndrew Lunn return -EOPNOTSUPP; 344dc30c35bSAndrew Lunn } 345dc30c35bSAndrew Lunn 346dc30c35bSAndrew Lunn static inline void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip) 347dc30c35bSAndrew Lunn { 348dc30c35bSAndrew Lunn } 349dc30c35bSAndrew Lunn 3506e55f698SAndrew Lunn static inline int mv88e6095_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 3516e55f698SAndrew Lunn { 3526e55f698SAndrew Lunn return -EOPNOTSUPP; 3536e55f698SAndrew Lunn } 3546e55f698SAndrew Lunn 355fcd25166SAndrew Lunn static const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {}; 35661303736SAndrew Lunn static const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {}; 357fcd25166SAndrew Lunn 358ca070c10SVivien Didelot #endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */ 359ca070c10SVivien Didelot 360ec561276SVivien Didelot #endif /* _MV88E6XXX_GLOBAL2_H */ 361