12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2ec561276SVivien Didelot /* 31d90016dSVivien Didelot * Marvell 88E6xxx Switch Global 2 Registers support 4ec561276SVivien Didelot * 5ec561276SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 6ec561276SVivien Didelot * 74333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 84333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9ec561276SVivien Didelot */ 10ec561276SVivien Didelot 11ec561276SVivien Didelot #ifndef _MV88E6XXX_GLOBAL2_H 12ec561276SVivien Didelot #define _MV88E6XXX_GLOBAL2_H 13ec561276SVivien Didelot 144d5f2ba7SVivien Didelot #include "chip.h" 15ec561276SVivien Didelot 161d90016dSVivien Didelot /* Offset 0x00: Interrupt Source Register */ 17d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_SRC 0x00 18d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_SRC_WDOG 0x8000 19d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x4000 20d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000 21d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x1000 22d6c5e6afSVivien Didelot #define MV88E6352_G2_INT_SRC_SERDES 0x0800 23d6c5e6afSVivien Didelot #define MV88E6352_G2_INT_SRC_PHY 0x001f 24d6c5e6afSVivien Didelot #define MV88E6390_G2_INT_SRC_PHY 0x07fe 25d6c5e6afSVivien Didelot 261d90016dSVivien Didelot #define MV88E6XXX_G2_INT_SOURCE_WATCHDOG 15 271d90016dSVivien Didelot 281d90016dSVivien Didelot /* Offset 0x01: Interrupt Mask Register */ 291d90016dSVivien Didelot #define MV88E6XXX_G2_INT_MASK 0x01 30d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_MASK_WDOG 0x8000 31d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_MASK_JAM_LIMIT 0x4000 32d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH 0x2000 33d6c5e6afSVivien Didelot #define MV88E6XXX_G2_INT_MASK_WAKE_EVENT 0x1000 34d6c5e6afSVivien Didelot #define MV88E6352_G2_INT_MASK_SERDES 0x0800 35d6c5e6afSVivien Didelot #define MV88E6352_G2_INT_MASK_PHY 0x001f 36d6c5e6afSVivien Didelot #define MV88E6390_G2_INT_MASK_PHY 0x07fe 376bff47beSVivien Didelot 386bff47beSVivien Didelot /* Offset 0x02: MGMT Enable Register 2x */ 396bff47beSVivien Didelot #define MV88E6XXX_G2_MGMT_EN_2X 0x02 406bff47beSVivien Didelot 41de776d0dSPavana Sharma /* Offset 0x02: MAC LINK change IRQ Register for MV88E6393X */ 42de776d0dSPavana Sharma #define MV88E6393X_G2_MACLINK_INT_SRC 0x02 43de776d0dSPavana Sharma 446bff47beSVivien Didelot /* Offset 0x03: MGMT Enable Register 0x */ 456bff47beSVivien Didelot #define MV88E6XXX_G2_MGMT_EN_0X 0x03 466bff47beSVivien Didelot 47de776d0dSPavana Sharma /* Offset 0x03: MAC LINK change IRQ Mask Register for MV88E6393X */ 48de776d0dSPavana Sharma #define MV88E6393X_G2_MACLINK_INT_MASK 0x03 49de776d0dSPavana Sharma 501d90016dSVivien Didelot /* Offset 0x04: Flow Control Delay Register */ 511d90016dSVivien Didelot #define MV88E6XXX_G2_FLOW_CTL 0x04 526bff47beSVivien Didelot 536bff47beSVivien Didelot /* Offset 0x05: Switch Management Register */ 546bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT 0x05 556bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA 0x8000 566bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS 0x4000 576bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x2000 586bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080 596bff47beSVivien Didelot #define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008 60067e474aSVivien Didelot 61de776d0dSPavana Sharma #define MV88E6393X_G2_EGRESS_MONITOR_DEST 0x05 62de776d0dSPavana Sharma 63067e474aSVivien Didelot /* Offset 0x06: Device Mapping Table Register */ 64067e474aSVivien Didelot #define MV88E6XXX_G2_DEVICE_MAPPING 0x06 65067e474aSVivien Didelot #define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x8000 66067e474aSVivien Didelot #define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK 0x1f00 67c7f047b6SVivien Didelot #define MV88E6352_G2_DEVICE_MAPPING_PORT_MASK 0x000f 68c7f047b6SVivien Didelot #define MV88E6390_G2_DEVICE_MAPPING_PORT_MASK 0x001f 6956dc7347SVivien Didelot 7056dc7347SVivien Didelot /* Offset 0x07: Trunk Mask Table Register */ 7156dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MASK 0x07 7256dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MASK_UPDATE 0x8000 7356dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK 0x7000 7456dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MASK_HASH 0x0800 7556dc7347SVivien Didelot 7656dc7347SVivien Didelot /* Offset 0x08: Trunk Mapping Table Register */ 7756dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MAPPING 0x08 7856dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE 0x8000 7956dc7347SVivien Didelot #define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK 0x7800 80cd8da8bbSVivien Didelot 81cd8da8bbSVivien Didelot /* Offset 0x09: Ingress Rate Command Register */ 82cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_CMD 0x09 83cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_CMD_BUSY 0x8000 84cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_MASK 0x7000 85cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_NOOP 0x0000 86cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_INIT_ALL 0x1000 87cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_INIT_RES 0x2000 88cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_WRITE_REG 0x3000 89cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_OP_READ_REG 0x4000 90cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_OP_MASK 0x6000 91cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_OP_READ_REG 0x0000 92cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_OP_INIT_ALL 0x2000 93cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_OP_INIT_RES 0x4000 94cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_OP_WRITE_REG 0x6000 95cd8da8bbSVivien Didelot #define MV88E6352_G2_IRL_CMD_PORT_MASK 0x0f00 96cd8da8bbSVivien Didelot #define MV88E6390_G2_IRL_CMD_PORT_MASK 0x1f00 97cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_CMD_RES_MASK 0x00e0 98cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_CMD_REG_MASK 0x000f 99cd8da8bbSVivien Didelot 100cd8da8bbSVivien Didelot /* Offset 0x0A: Ingress Rate Data Register */ 101cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_DATA 0x0a 102cd8da8bbSVivien Didelot #define MV88E6XXX_G2_IRL_DATA_MASK 0xffff 103cd8da8bbSVivien Didelot 10467d1ea8eSVivien Didelot /* Offset 0x0B: Cross-chip Port VLAN Register */ 10567d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR 0x0b 10667d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_BUSY 0x8000 10767d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_OP_MASK 0x7000 10867d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES 0x1000 10967d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN 0x3000 11067d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_OP_READ 0x4000 11167d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff 11278e70dbcSTobias Waldekranz #define MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK 0x1f 11367d1ea8eSVivien Didelot 11467d1ea8eSVivien Didelot /* Offset 0x0C: Cross-chip Port VLAN Data Register */ 11567d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_DATA 0x0c 11667d1ea8eSVivien Didelot #define MV88E6XXX_G2_PVT_DATA_MASK 0x7f 11767d1ea8eSVivien Didelot 118ed44152fSVivien Didelot /* Offset 0x0D: Switch MAC/WoL/WoF Register */ 119ed44152fSVivien Didelot #define MV88E6XXX_G2_SWITCH_MAC 0x0d 120ed44152fSVivien Didelot #define MV88E6XXX_G2_SWITCH_MAC_UPDATE 0x8000 121ed44152fSVivien Didelot #define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK 0x1f00 122ed44152fSVivien Didelot #define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK 0x00ff 123ed44152fSVivien Didelot 1241d90016dSVivien Didelot /* Offset 0x0E: ATU Stats Register */ 1251d90016dSVivien Didelot #define MV88E6XXX_G2_ATU_STATS 0x0e 1266239a386SAndrew Lunn #define MV88E6XXX_G2_ATU_STATS_BIN_0 (0x0 << 14) 1276239a386SAndrew Lunn #define MV88E6XXX_G2_ATU_STATS_BIN_1 (0x1 << 14) 1286239a386SAndrew Lunn #define MV88E6XXX_G2_ATU_STATS_BIN_2 (0x2 << 14) 1296239a386SAndrew Lunn #define MV88E6XXX_G2_ATU_STATS_BIN_3 (0x3 << 14) 1306239a386SAndrew Lunn #define MV88E6XXX_G2_ATU_STATS_MODE_ALL (0x0 << 12) 1316239a386SAndrew Lunn #define MV88E6XXX_G2_ATU_STATS_MODE_ALL_DYNAMIC (0x1 << 12) 1326239a386SAndrew Lunn #define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL (0x2 << 12) 1336239a386SAndrew Lunn #define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL_DYNAMIC (0x3 << 12) 1346239a386SAndrew Lunn #define MV88E6XXX_G2_ATU_STATS_MASK 0x0fff 1351d90016dSVivien Didelot 1361d90016dSVivien Didelot /* Offset 0x0F: Priority Override Table */ 1371d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f 1381d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE 0x8000 1391d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET 0x1000 1401d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00 1411d90016dSVivien Didelot #define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN 0x0080 1421d90016dSVivien Didelot #define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030 1431d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN 0x0008 1441d90016dSVivien Didelot #define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK 0x0007 1457fc8c9d5SVivien Didelot 1467fc8c9d5SVivien Didelot /* Offset 0x14: EEPROM Command */ 1477fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD 0x14 1487fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_BUSY 0x8000 1497fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_OP_MASK 0x7000 1507fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE 0x3000 1517fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_OP_READ 0x4000 1527fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD 0x6000 1537fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_RUNNING 0x0800 1547fc8c9d5SVivien Didelot #define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN 0x0400 1557fc8c9d5SVivien Didelot #define MV88E6352_G2_EEPROM_CMD_ADDR_MASK 0x00ff 1567fc8c9d5SVivien Didelot #define MV88E6390_G2_EEPROM_CMD_DATA_MASK 0x00ff 1577fc8c9d5SVivien Didelot 1587fc8c9d5SVivien Didelot /* Offset 0x15: EEPROM Data */ 1597fc8c9d5SVivien Didelot #define MV88E6352_G2_EEPROM_DATA 0x15 1607fc8c9d5SVivien Didelot #define MV88E6352_G2_EEPROM_DATA_MASK 0xffff 1617fc8c9d5SVivien Didelot 1627fc8c9d5SVivien Didelot /* Offset 0x15: EEPROM Addr */ 1637fc8c9d5SVivien Didelot #define MV88E6390_G2_EEPROM_ADDR 0x15 1647fc8c9d5SVivien Didelot #define MV88E6390_G2_EEPROM_ADDR_MASK 0xffff 1657fc8c9d5SVivien Didelot 1661d90016dSVivien Didelot /* Offset 0x16: AVB Command Register */ 1671d90016dSVivien Didelot #define MV88E6352_G2_AVB_CMD 0x16 1680d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_BUSY 0x8000 1690d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_OP_READ 0x4000 1700d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_OP_READ_INCR 0x6000 1710d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_OP_WRITE 0x3000 1720d632c3dSBrandon Streiff #define MV88E6390_G2_AVB_CMD_OP_READ 0x0000 1730d632c3dSBrandon Streiff #define MV88E6390_G2_AVB_CMD_OP_READ_INCR 0x4000 1740d632c3dSBrandon Streiff #define MV88E6390_G2_AVB_CMD_OP_WRITE 0x6000 1750d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_PORT_MASK 0x0f00 1760d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_PORT_TAIGLOBAL 0xe 177a469a612SAndrew Lunn #define MV88E6165_G2_AVB_CMD_PORT_PTPGLOBAL 0xf 1780d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_PORT_PTPGLOBAL 0xf 1790d632c3dSBrandon Streiff #define MV88E6390_G2_AVB_CMD_PORT_MASK 0x1f00 1800d632c3dSBrandon Streiff #define MV88E6390_G2_AVB_CMD_PORT_TAIGLOBAL 0x1e 1810d632c3dSBrandon Streiff #define MV88E6390_G2_AVB_CMD_PORT_PTPGLOBAL 0x1f 1820d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_BLOCK_PTP 0 1830d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_BLOCK_AVB 1 1840d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_BLOCK_QAV 2 1850d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_BLOCK_QVB 3 1860d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_BLOCK_MASK 0x00e0 1870d632c3dSBrandon Streiff #define MV88E6352_G2_AVB_CMD_ADDR_MASK 0x001f 1881d90016dSVivien Didelot 1891d90016dSVivien Didelot /* Offset 0x17: AVB Data Register */ 1901d90016dSVivien Didelot #define MV88E6352_G2_AVB_DATA 0x17 191d23a83f2SVivien Didelot 192e289ef0dSVivien Didelot /* Offset 0x18: SMI PHY Command Register */ 193e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD 0x18 194e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_BUSY 0x8000 195e289ef0dSVivien Didelot #define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK 0x6000 196e289ef0dSVivien Didelot #define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL 0x0000 197e289ef0dSVivien Didelot #define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL 0x2000 198e289ef0dSVivien Didelot #define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP 0x4000 199e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK 0x1000 200e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45 0x0000 201e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22 0x1000 202e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK 0x0c00 203e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA 0x0400 204e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA 0x0800 205e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR 0x0000 206e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA 0x0400 207e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC 0x0800 208e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA 0x0c00 209e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK 0x03e0 210e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK 0x001f 211e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK 0x03ff 212e289ef0dSVivien Didelot 213e289ef0dSVivien Didelot /* Offset 0x19: SMI PHY Data Register */ 214e289ef0dSVivien Didelot #define MV88E6XXX_G2_SMI_PHY_DATA 0x19 215e289ef0dSVivien Didelot 2161d90016dSVivien Didelot /* Offset 0x1A: Scratch and Misc. Register */ 2171d90016dSVivien Didelot #define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a 2181d90016dSVivien Didelot #define MV88E6XXX_G2_SCRATCH_MISC_UPDATE 0x8000 2191d90016dSVivien Didelot #define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK 0x7f00 2201d90016dSVivien Didelot #define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff 2213b19df73SVivien Didelot 2223b19df73SVivien Didelot /* Offset 0x1B: Watch Dog Control Register */ 223855cdfdeSRasmus Villemoes #define MV88E6250_G2_WDOG_CTL 0x1b 224855cdfdeSRasmus Villemoes #define MV88E6250_G2_WDOG_CTL_QC_HISTORY 0x0100 225855cdfdeSRasmus Villemoes #define MV88E6250_G2_WDOG_CTL_QC_EVENT 0x0080 226855cdfdeSRasmus Villemoes #define MV88E6250_G2_WDOG_CTL_QC_ENABLE 0x0040 227855cdfdeSRasmus Villemoes #define MV88E6250_G2_WDOG_CTL_EGRESS_HISTORY 0x0020 228855cdfdeSRasmus Villemoes #define MV88E6250_G2_WDOG_CTL_EGRESS_EVENT 0x0010 229855cdfdeSRasmus Villemoes #define MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE 0x0008 230855cdfdeSRasmus Villemoes #define MV88E6250_G2_WDOG_CTL_FORCE_IRQ 0x0004 231855cdfdeSRasmus Villemoes #define MV88E6250_G2_WDOG_CTL_HISTORY 0x0002 232855cdfdeSRasmus Villemoes #define MV88E6250_G2_WDOG_CTL_SWRESET 0x0001 233855cdfdeSRasmus Villemoes 234855cdfdeSRasmus Villemoes /* Offset 0x1B: Watch Dog Control Register */ 2353b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL 0x1b 2363b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT 0x0080 2373b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT 0x0040 2383b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_QC_ENABLE 0x0020 2393b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY 0x0010 2403b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE 0x0008 2413b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_FORCE_IRQ 0x0004 2423b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_HISTORY 0x0002 2433b19df73SVivien Didelot #define MV88E6352_G2_WDOG_CTL_SWRESET 0x0001 2443b19df73SVivien Didelot 2453b19df73SVivien Didelot /* Offset 0x1B: Watch Dog Control Register */ 2463b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL 0x1b 2473b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_UPDATE 0x8000 2483b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_MASK 0x7f00 2493b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE 0x0000 2503b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_INT_STS 0x1000 2513b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE 0x1100 2523b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_EVENT 0x1200 2533b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_PTR_HISTORY 0x1300 2543b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_DATA_MASK 0x00ff 2553b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_CUT_THROUGH 0x0008 2563b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER 0x0004 2573b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_EGRESS 0x0002 2583b19df73SVivien Didelot #define MV88E6390_G2_WDOG_CTL_FORCE_IRQ 0x0001 2593b19df73SVivien Didelot 2601d90016dSVivien Didelot /* Offset 0x1C: QoS Weights Register */ 2611d90016dSVivien Didelot #define MV88E6XXX_G2_QOS_WEIGHTS 0x1c 2621d90016dSVivien Didelot #define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE 0x8000 2631d90016dSVivien Didelot #define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK 0x3f00 2641d90016dSVivien Didelot #define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK 0x7f00 2651d90016dSVivien Didelot #define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK 0x00ff 2661d90016dSVivien Didelot 2671d90016dSVivien Didelot /* Offset 0x1D: Misc Register */ 2681d90016dSVivien Didelot #define MV88E6XXX_G2_MISC 0x1d 2691d90016dSVivien Didelot #define MV88E6XXX_G2_MISC_5_BIT_PORT 0x4000 2701d90016dSVivien Didelot #define MV88E6352_G2_NOEGR_POLICY 0x2000 2711d90016dSVivien Didelot #define MV88E6390_G2_LAG_ID_4 0x2000 272d23a83f2SVivien Didelot 273a73ccd61SBrandon Streiff /* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */ 274a73ccd61SBrandon Streiff /* Offset 0x02: Misc Configuration */ 275a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_MISC_CFG 0x02 276a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI 0x80 277a73ccd61SBrandon Streiff /* Offset 0x60-0x61: GPIO Configuration */ 278a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_CFG0 0x60 279a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_CFG1 0x61 280a73ccd61SBrandon Streiff /* Offset 0x62-0x63: GPIO Direction */ 281a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_DIR0 0x62 282a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_DIR1 0x63 283a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT 0 284a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_DIR_IN 1 285a73ccd61SBrandon Streiff /* Offset 0x64-0x65: GPIO Data */ 286a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_DATA0 0x64 287a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_DATA1 0x65 288a73ccd61SBrandon Streiff /* Offset 0x68-0x6F: GPIO Pin Control */ 289a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL0 0x68 290a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL1 0x69 291a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL2 0x6A 292a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL3 0x6B 293a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL4 0x6C 294a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL5 0x6D 295a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL6 0x6E 296a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL7 0x6F 2972510babcSAndrew Lunn #define MV88E6352_G2_SCRATCH_CONFIG_DATA0 0x70 2982510babcSAndrew Lunn #define MV88E6352_G2_SCRATCH_CONFIG_DATA1 0x71 2992510babcSAndrew Lunn #define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU BIT(2) 3002510babcSAndrew Lunn #define MV88E6352_G2_SCRATCH_CONFIG_DATA2 0x72 3018532c60eSMarcus Carlberg #define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK 0xf 30262001548SRussell King (Oracle) #define MV88E6352_G2_SCRATCH_CONFIG_DATA3 0x73 30362001548SRussell King (Oracle) #define MV88E6352_G2_SCRATCH_CONFIG_DATA3_S_SEL BIT(1) 304a73ccd61SBrandon Streiff 305a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO 0 306a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG 1 307a73ccd61SBrandon Streiff #define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ 2 308a73ccd61SBrandon Streiff 309b000be95SBrandon Streiff int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); 310b000be95SBrandon Streiff int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val); 31119fb7f69SVivien Didelot int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg, 31219fb7f69SVivien Didelot int bit, int val); 313b000be95SBrandon Streiff 314cd8da8bbSVivien Didelot int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 315cd8da8bbSVivien Didelot int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); 316cd8da8bbSVivien Didelot 317743a19e3SAndrew Lunn int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip, 318ee26a228SAndrew Lunn struct mii_bus *bus, 319ee26a228SAndrew Lunn int addr, int reg, u16 *val); 320743a19e3SAndrew Lunn int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip, 321ee26a228SAndrew Lunn struct mii_bus *bus, 322ee26a228SAndrew Lunn int addr, int reg, u16 val); 323743a19e3SAndrew Lunn int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip, 324743a19e3SAndrew Lunn struct mii_bus *bus, 325743a19e3SAndrew Lunn int addr, int devad, int reg, u16 *val); 326743a19e3SAndrew Lunn int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip, 327743a19e3SAndrew Lunn struct mii_bus *bus, 328743a19e3SAndrew Lunn int addr, int devad, int reg, u16 val); 329ec561276SVivien Didelot int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr); 33098fc3c6fSVivien Didelot 33198fc3c6fSVivien Didelot int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, 33298fc3c6fSVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 33398fc3c6fSVivien Didelot int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, 33498fc3c6fSVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 33598fc3c6fSVivien Didelot 336ec561276SVivien Didelot int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, 337ec561276SVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 338ec561276SVivien Didelot int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 339ec561276SVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 34098fc3c6fSVivien Didelot 341836021a2STobias Waldekranz int mv88e6xxx_g2_pvt_read(struct mv88e6xxx_chip *chip, int src_dev, 342836021a2STobias Waldekranz int src_port, u16 *data); 34317a1594eSVivien Didelot int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev, 34417a1594eSVivien Didelot int src_port, u16 data); 34581228996SVivien Didelot int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip); 34681228996SVivien Didelot 347dc30c35bSAndrew Lunn int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip); 348dc30c35bSAndrew Lunn void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip); 34951c901a7SVivien Didelot 3506f88284fSAndrew Lunn int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip, 3516f88284fSAndrew Lunn struct mii_bus *bus); 3526f88284fSAndrew Lunn void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip, 3536f88284fSAndrew Lunn struct mii_bus *bus); 3546f88284fSAndrew Lunn 35551c901a7SVivien Didelot int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 35651c901a7SVivien Didelot int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 357ec561276SVivien Didelot 3589e907d73SVivien Didelot int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip); 3599e907d73SVivien Didelot 36057e661aaSTobias Waldekranz int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num, 36157e661aaSTobias Waldekranz bool hash, u16 mask); 36257e661aaSTobias Waldekranz int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id, 36357e661aaSTobias Waldekranz u16 map); 364b28f872dSVivien Didelot int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip); 365b28f872dSVivien Didelot 366c7f047b6SVivien Didelot int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target, 367c7f047b6SVivien Didelot int port); 368*6ccf50d4SFabio Estevam int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip); 369c7f047b6SVivien Didelot 370fcd25166SAndrew Lunn extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops; 371855cdfdeSRasmus Villemoes extern const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops; 37261303736SAndrew Lunn extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops; 373089b91a0SGustav Ekelund extern const struct mv88e6xxx_irq_ops mv88e6393x_watchdog_ops; 374fcd25166SAndrew Lunn 375a469a612SAndrew Lunn extern const struct mv88e6xxx_avb_ops mv88e6165_avb_ops; 3760d632c3dSBrandon Streiff extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops; 3770d632c3dSBrandon Streiff extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops; 3780d632c3dSBrandon Streiff 379a73ccd61SBrandon Streiff extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops; 380a73ccd61SBrandon Streiff 3812510babcSAndrew Lunn int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, 3822510babcSAndrew Lunn bool external); 38362001548SRussell King (Oracle) int mv88e6352_g2_scratch_port_has_serdes(struct mv88e6xxx_chip *chip, int port); 3846239a386SAndrew Lunn int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin); 385c5f299d5SAndrew Lunn int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats); 3862510babcSAndrew Lunn 387ec561276SVivien Didelot #endif /* _MV88E6XXX_GLOBAL2_H */ 388