1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88E6xxx Switch Global 2 Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/interrupt.h> 13 #include <linux/irqdomain.h> 14 15 #include "chip.h" 16 #include "global1.h" /* for MV88E6XXX_G1_STS_IRQ_DEVICE */ 17 #include "global2.h" 18 19 int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 20 { 21 return mv88e6xxx_read(chip, chip->info->global2_addr, reg, val); 22 } 23 24 int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 25 { 26 return mv88e6xxx_write(chip, chip->info->global2_addr, reg, val); 27 } 28 29 int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update) 30 { 31 return mv88e6xxx_update(chip, chip->info->global2_addr, reg, update); 32 } 33 34 int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask) 35 { 36 return mv88e6xxx_wait(chip, chip->info->global2_addr, reg, mask); 37 } 38 39 /* Offset 0x00: Interrupt Source Register */ 40 41 static int mv88e6xxx_g2_int_source(struct mv88e6xxx_chip *chip, u16 *src) 42 { 43 /* Read (and clear most of) the Interrupt Source bits */ 44 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_INT_SRC, src); 45 } 46 47 /* Offset 0x01: Interrupt Mask Register */ 48 49 static int mv88e6xxx_g2_int_mask(struct mv88e6xxx_chip *chip, u16 mask) 50 { 51 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_INT_MASK, mask); 52 } 53 54 /* Offset 0x02: Management Enable 2x */ 55 56 static int mv88e6xxx_g2_mgmt_enable_2x(struct mv88e6xxx_chip *chip, u16 en2x) 57 { 58 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_2X, en2x); 59 } 60 61 /* Offset 0x03: Management Enable 0x */ 62 63 static int mv88e6xxx_g2_mgmt_enable_0x(struct mv88e6xxx_chip *chip, u16 en0x) 64 { 65 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_0X, en0x); 66 } 67 68 /* Offset 0x05: Switch Management Register */ 69 70 static int mv88e6xxx_g2_switch_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip, 71 bool enable) 72 { 73 u16 val; 74 int err; 75 76 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SWITCH_MGMT, &val); 77 if (err) 78 return err; 79 80 if (enable) 81 val |= MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU; 82 else 83 val &= ~MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU; 84 85 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MGMT, val); 86 } 87 88 int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 89 { 90 int err; 91 92 /* Consider the frames with reserved multicast destination 93 * addresses matching 01:80:c2:00:00:0x as MGMT. 94 */ 95 err = mv88e6xxx_g2_mgmt_enable_0x(chip, 0xffff); 96 if (err) 97 return err; 98 99 return mv88e6xxx_g2_switch_mgmt_rsvd2cpu(chip, true); 100 } 101 102 int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 103 { 104 int err; 105 106 /* Consider the frames with reserved multicast destination 107 * addresses matching 01:80:c2:00:00:2x as MGMT. 108 */ 109 err = mv88e6xxx_g2_mgmt_enable_2x(chip, 0xffff); 110 if (err) 111 return err; 112 113 return mv88e6185_g2_mgmt_rsvd2cpu(chip); 114 } 115 116 /* Offset 0x06: Device Mapping Table register */ 117 118 int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target, 119 int port) 120 { 121 u16 val = (target << 8) | (port & 0x1f); 122 /* Modern chips use 5 bits to define a device mapping port, 123 * but bit 4 is reserved on older chips, so it is safe to use. 124 */ 125 126 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_DEVICE_MAPPING, val); 127 } 128 129 /* Offset 0x07: Trunk Mask Table register */ 130 131 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num, 132 bool hash, u16 mask) 133 { 134 u16 val = (num << 12) | (mask & mv88e6xxx_port_mask(chip)); 135 136 if (hash) 137 val |= MV88E6XXX_G2_TRUNK_MASK_HASH; 138 139 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_TRUNK_MASK, val); 140 } 141 142 /* Offset 0x08: Trunk Mapping Table register */ 143 144 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id, 145 u16 map) 146 { 147 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1; 148 u16 val = (id << 11) | (map & port_mask); 149 150 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_TRUNK_MAPPING, val); 151 } 152 153 int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip) 154 { 155 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1; 156 int i, err; 157 158 /* Clear all eight possible Trunk Mask vectors */ 159 for (i = 0; i < 8; ++i) { 160 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask); 161 if (err) 162 return err; 163 } 164 165 /* Clear all sixteen possible Trunk ID routing vectors */ 166 for (i = 0; i < 16; ++i) { 167 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0); 168 if (err) 169 return err; 170 } 171 172 return 0; 173 } 174 175 /* Offset 0x09: Ingress Rate Command register 176 * Offset 0x0A: Ingress Rate Data register 177 */ 178 179 static int mv88e6xxx_g2_irl_wait(struct mv88e6xxx_chip *chip) 180 { 181 return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_IRL_CMD, 182 MV88E6XXX_G2_IRL_CMD_BUSY); 183 } 184 185 static int mv88e6xxx_g2_irl_op(struct mv88e6xxx_chip *chip, u16 op, int port, 186 int res, int reg) 187 { 188 int err; 189 190 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_IRL_CMD, 191 MV88E6XXX_G2_IRL_CMD_BUSY | op | (port << 8) | 192 (res << 5) | reg); 193 if (err) 194 return err; 195 196 return mv88e6xxx_g2_irl_wait(chip); 197 } 198 199 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port) 200 { 201 return mv88e6xxx_g2_irl_op(chip, MV88E6352_G2_IRL_CMD_OP_INIT_ALL, port, 202 0, 0); 203 } 204 205 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port) 206 { 207 return mv88e6xxx_g2_irl_op(chip, MV88E6390_G2_IRL_CMD_OP_INIT_ALL, port, 208 0, 0); 209 } 210 211 /* Offset 0x0B: Cross-chip Port VLAN (Addr) Register 212 * Offset 0x0C: Cross-chip Port VLAN Data Register 213 */ 214 215 static int mv88e6xxx_g2_pvt_op_wait(struct mv88e6xxx_chip *chip) 216 { 217 return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_PVT_ADDR, 218 MV88E6XXX_G2_PVT_ADDR_BUSY); 219 } 220 221 static int mv88e6xxx_g2_pvt_op(struct mv88e6xxx_chip *chip, int src_dev, 222 int src_port, u16 op) 223 { 224 int err; 225 226 /* 9-bit Cross-chip PVT pointer: with MV88E6XXX_G2_MISC_5_BIT_PORT 227 * cleared, source device is 5-bit, source port is 4-bit. 228 */ 229 op |= MV88E6XXX_G2_PVT_ADDR_BUSY; 230 op |= (src_dev & 0x1f) << 4; 231 op |= (src_port & 0xf); 232 233 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_ADDR, op); 234 if (err) 235 return err; 236 237 return mv88e6xxx_g2_pvt_op_wait(chip); 238 } 239 240 int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev, 241 int src_port, u16 data) 242 { 243 int err; 244 245 err = mv88e6xxx_g2_pvt_op_wait(chip); 246 if (err) 247 return err; 248 249 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_DATA, data); 250 if (err) 251 return err; 252 253 return mv88e6xxx_g2_pvt_op(chip, src_dev, src_port, 254 MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN); 255 } 256 257 /* Offset 0x0D: Switch MAC/WoL/WoF register */ 258 259 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip, 260 unsigned int pointer, u8 data) 261 { 262 u16 val = (pointer << 8) | data; 263 264 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_SWITCH_MAC, val); 265 } 266 267 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 268 { 269 int i, err; 270 271 for (i = 0; i < 6; i++) { 272 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]); 273 if (err) 274 break; 275 } 276 277 return err; 278 } 279 280 /* Offset 0x0F: Priority Override Table */ 281 282 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer, 283 u8 data) 284 { 285 u16 val = (pointer << 8) | (data & 0x7); 286 287 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_PRIO_OVERRIDE, val); 288 } 289 290 int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip) 291 { 292 int i, err; 293 294 /* Clear all sixteen possible Priority Override entries */ 295 for (i = 0; i < 16; i++) { 296 err = mv88e6xxx_g2_pot_write(chip, i, 0); 297 if (err) 298 break; 299 } 300 301 return err; 302 } 303 304 /* Offset 0x14: EEPROM Command 305 * Offset 0x15: EEPROM Data (for 16-bit data access) 306 * Offset 0x15: EEPROM Addr (for 8-bit data access) 307 */ 308 309 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip) 310 { 311 return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_EEPROM_CMD, 312 MV88E6XXX_G2_EEPROM_CMD_BUSY | 313 MV88E6XXX_G2_EEPROM_CMD_RUNNING); 314 } 315 316 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd) 317 { 318 int err; 319 320 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_EEPROM_CMD, 321 MV88E6XXX_G2_EEPROM_CMD_BUSY | cmd); 322 if (err) 323 return err; 324 325 return mv88e6xxx_g2_eeprom_wait(chip); 326 } 327 328 static int mv88e6xxx_g2_eeprom_read8(struct mv88e6xxx_chip *chip, 329 u16 addr, u8 *data) 330 { 331 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_READ; 332 int err; 333 334 err = mv88e6xxx_g2_eeprom_wait(chip); 335 if (err) 336 return err; 337 338 err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr); 339 if (err) 340 return err; 341 342 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd); 343 if (err) 344 return err; 345 346 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &cmd); 347 if (err) 348 return err; 349 350 *data = cmd & 0xff; 351 352 return 0; 353 } 354 355 static int mv88e6xxx_g2_eeprom_write8(struct mv88e6xxx_chip *chip, 356 u16 addr, u8 data) 357 { 358 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_WRITE | 359 MV88E6XXX_G2_EEPROM_CMD_WRITE_EN; 360 int err; 361 362 err = mv88e6xxx_g2_eeprom_wait(chip); 363 if (err) 364 return err; 365 366 err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr); 367 if (err) 368 return err; 369 370 return mv88e6xxx_g2_eeprom_cmd(chip, cmd | data); 371 } 372 373 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip, 374 u8 addr, u16 *data) 375 { 376 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_READ | addr; 377 int err; 378 379 err = mv88e6xxx_g2_eeprom_wait(chip); 380 if (err) 381 return err; 382 383 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd); 384 if (err) 385 return err; 386 387 return mv88e6xxx_g2_read(chip, MV88E6352_G2_EEPROM_DATA, data); 388 } 389 390 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip, 391 u8 addr, u16 data) 392 { 393 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_WRITE | addr; 394 int err; 395 396 err = mv88e6xxx_g2_eeprom_wait(chip); 397 if (err) 398 return err; 399 400 err = mv88e6xxx_g2_write(chip, MV88E6352_G2_EEPROM_DATA, data); 401 if (err) 402 return err; 403 404 return mv88e6xxx_g2_eeprom_cmd(chip, cmd); 405 } 406 407 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, 408 struct ethtool_eeprom *eeprom, u8 *data) 409 { 410 unsigned int offset = eeprom->offset; 411 unsigned int len = eeprom->len; 412 int err; 413 414 eeprom->len = 0; 415 416 while (len) { 417 err = mv88e6xxx_g2_eeprom_read8(chip, offset, data); 418 if (err) 419 return err; 420 421 eeprom->len++; 422 offset++; 423 data++; 424 len--; 425 } 426 427 return 0; 428 } 429 430 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, 431 struct ethtool_eeprom *eeprom, u8 *data) 432 { 433 unsigned int offset = eeprom->offset; 434 unsigned int len = eeprom->len; 435 int err; 436 437 eeprom->len = 0; 438 439 while (len) { 440 err = mv88e6xxx_g2_eeprom_write8(chip, offset, *data); 441 if (err) 442 return err; 443 444 eeprom->len++; 445 offset++; 446 data++; 447 len--; 448 } 449 450 return 0; 451 } 452 453 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, 454 struct ethtool_eeprom *eeprom, u8 *data) 455 { 456 unsigned int offset = eeprom->offset; 457 unsigned int len = eeprom->len; 458 u16 val; 459 int err; 460 461 eeprom->len = 0; 462 463 if (offset & 1) { 464 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 465 if (err) 466 return err; 467 468 *data++ = (val >> 8) & 0xff; 469 470 offset++; 471 len--; 472 eeprom->len++; 473 } 474 475 while (len >= 2) { 476 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 477 if (err) 478 return err; 479 480 *data++ = val & 0xff; 481 *data++ = (val >> 8) & 0xff; 482 483 offset += 2; 484 len -= 2; 485 eeprom->len += 2; 486 } 487 488 if (len) { 489 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 490 if (err) 491 return err; 492 493 *data++ = val & 0xff; 494 495 offset++; 496 len--; 497 eeprom->len++; 498 } 499 500 return 0; 501 } 502 503 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 504 struct ethtool_eeprom *eeprom, u8 *data) 505 { 506 unsigned int offset = eeprom->offset; 507 unsigned int len = eeprom->len; 508 u16 val; 509 int err; 510 511 /* Ensure the RO WriteEn bit is set */ 512 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &val); 513 if (err) 514 return err; 515 516 if (!(val & MV88E6XXX_G2_EEPROM_CMD_WRITE_EN)) 517 return -EROFS; 518 519 eeprom->len = 0; 520 521 if (offset & 1) { 522 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 523 if (err) 524 return err; 525 526 val = (*data++ << 8) | (val & 0xff); 527 528 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); 529 if (err) 530 return err; 531 532 offset++; 533 len--; 534 eeprom->len++; 535 } 536 537 while (len >= 2) { 538 val = *data++; 539 val |= *data++ << 8; 540 541 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); 542 if (err) 543 return err; 544 545 offset += 2; 546 len -= 2; 547 eeprom->len += 2; 548 } 549 550 if (len) { 551 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 552 if (err) 553 return err; 554 555 val = (val & 0xff00) | *data++; 556 557 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); 558 if (err) 559 return err; 560 561 offset++; 562 len--; 563 eeprom->len++; 564 } 565 566 return 0; 567 } 568 569 /* Offset 0x18: SMI PHY Command Register 570 * Offset 0x19: SMI PHY Data Register 571 */ 572 573 static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip) 574 { 575 return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_SMI_PHY_CMD, 576 MV88E6XXX_G2_SMI_PHY_CMD_BUSY); 577 } 578 579 static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd) 580 { 581 int err; 582 583 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_CMD, 584 MV88E6XXX_G2_SMI_PHY_CMD_BUSY | cmd); 585 if (err) 586 return err; 587 588 return mv88e6xxx_g2_smi_phy_wait(chip); 589 } 590 591 static int mv88e6xxx_g2_smi_phy_access(struct mv88e6xxx_chip *chip, 592 bool external, bool c45, u16 op, int dev, 593 int reg) 594 { 595 u16 cmd = op; 596 597 if (external) 598 cmd |= MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL; 599 else 600 cmd |= MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL; /* empty mask */ 601 602 if (c45) 603 cmd |= MV88E6XXX_G2_SMI_PHY_CMD_MODE_45; /* empty mask */ 604 else 605 cmd |= MV88E6XXX_G2_SMI_PHY_CMD_MODE_22; 606 607 dev <<= __bf_shf(MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK); 608 cmd |= dev & MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK; 609 cmd |= reg & MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK; 610 611 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd); 612 } 613 614 static int mv88e6xxx_g2_smi_phy_access_c22(struct mv88e6xxx_chip *chip, 615 bool external, u16 op, int dev, 616 int reg) 617 { 618 return mv88e6xxx_g2_smi_phy_access(chip, external, false, op, dev, reg); 619 } 620 621 /* IEEE 802.3 Clause 22 Read Data Register */ 622 static int mv88e6xxx_g2_smi_phy_read_data_c22(struct mv88e6xxx_chip *chip, 623 bool external, int dev, int reg, 624 u16 *data) 625 { 626 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA; 627 int err; 628 629 err = mv88e6xxx_g2_smi_phy_wait(chip); 630 if (err) 631 return err; 632 633 err = mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg); 634 if (err) 635 return err; 636 637 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data); 638 } 639 640 /* IEEE 802.3 Clause 22 Write Data Register */ 641 static int mv88e6xxx_g2_smi_phy_write_data_c22(struct mv88e6xxx_chip *chip, 642 bool external, int dev, int reg, 643 u16 data) 644 { 645 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA; 646 int err; 647 648 err = mv88e6xxx_g2_smi_phy_wait(chip); 649 if (err) 650 return err; 651 652 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data); 653 if (err) 654 return err; 655 656 return mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg); 657 } 658 659 static int mv88e6xxx_g2_smi_phy_access_c45(struct mv88e6xxx_chip *chip, 660 bool external, u16 op, int port, 661 int dev) 662 { 663 return mv88e6xxx_g2_smi_phy_access(chip, external, true, op, port, dev); 664 } 665 666 /* IEEE 802.3 Clause 45 Write Address Register */ 667 static int mv88e6xxx_g2_smi_phy_write_addr_c45(struct mv88e6xxx_chip *chip, 668 bool external, int port, int dev, 669 int addr) 670 { 671 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR; 672 int err; 673 674 err = mv88e6xxx_g2_smi_phy_wait(chip); 675 if (err) 676 return err; 677 678 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, addr); 679 if (err) 680 return err; 681 682 return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev); 683 } 684 685 /* IEEE 802.3 Clause 45 Read Data Register */ 686 static int mv88e6xxx_g2_smi_phy_read_data_c45(struct mv88e6xxx_chip *chip, 687 bool external, int port, int dev, 688 u16 *data) 689 { 690 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA; 691 int err; 692 693 err = mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev); 694 if (err) 695 return err; 696 697 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data); 698 } 699 700 static int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip, 701 bool external, int port, int reg, 702 u16 *data) 703 { 704 int dev = (reg >> 16) & 0x1f; 705 int addr = reg & 0xffff; 706 int err; 707 708 err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev, 709 addr); 710 if (err) 711 return err; 712 713 return mv88e6xxx_g2_smi_phy_read_data_c45(chip, external, port, dev, 714 data); 715 } 716 717 /* IEEE 802.3 Clause 45 Write Data Register */ 718 static int mv88e6xxx_g2_smi_phy_write_data_c45(struct mv88e6xxx_chip *chip, 719 bool external, int port, int dev, 720 u16 data) 721 { 722 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA; 723 int err; 724 725 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data); 726 if (err) 727 return err; 728 729 return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev); 730 } 731 732 static int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip, 733 bool external, int port, int reg, 734 u16 data) 735 { 736 int dev = (reg >> 16) & 0x1f; 737 int addr = reg & 0xffff; 738 int err; 739 740 err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev, 741 addr); 742 if (err) 743 return err; 744 745 return mv88e6xxx_g2_smi_phy_write_data_c45(chip, external, port, dev, 746 data); 747 } 748 749 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus, 750 int addr, int reg, u16 *val) 751 { 752 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 753 bool external = mdio_bus->external; 754 755 if (reg & MII_ADDR_C45) 756 return mv88e6xxx_g2_smi_phy_read_c45(chip, external, addr, reg, 757 val); 758 759 return mv88e6xxx_g2_smi_phy_read_data_c22(chip, external, addr, reg, 760 val); 761 } 762 763 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus, 764 int addr, int reg, u16 val) 765 { 766 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 767 bool external = mdio_bus->external; 768 769 if (reg & MII_ADDR_C45) 770 return mv88e6xxx_g2_smi_phy_write_c45(chip, external, addr, reg, 771 val); 772 773 return mv88e6xxx_g2_smi_phy_write_data_c22(chip, external, addr, reg, 774 val); 775 } 776 777 /* Offset 0x1B: Watchdog Control */ 778 static int mv88e6097_watchdog_action(struct mv88e6xxx_chip *chip, int irq) 779 { 780 u16 reg; 781 782 mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®); 783 784 dev_info(chip->dev, "Watchdog event: 0x%04x", reg); 785 786 return IRQ_HANDLED; 787 } 788 789 static void mv88e6097_watchdog_free(struct mv88e6xxx_chip *chip) 790 { 791 u16 reg; 792 793 mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®); 794 795 reg &= ~(MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE | 796 MV88E6352_G2_WDOG_CTL_QC_ENABLE); 797 798 mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL, reg); 799 } 800 801 static int mv88e6097_watchdog_setup(struct mv88e6xxx_chip *chip) 802 { 803 return mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL, 804 MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE | 805 MV88E6352_G2_WDOG_CTL_QC_ENABLE | 806 MV88E6352_G2_WDOG_CTL_SWRESET); 807 } 808 809 const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = { 810 .irq_action = mv88e6097_watchdog_action, 811 .irq_setup = mv88e6097_watchdog_setup, 812 .irq_free = mv88e6097_watchdog_free, 813 }; 814 815 static void mv88e6250_watchdog_free(struct mv88e6xxx_chip *chip) 816 { 817 u16 reg; 818 819 mv88e6xxx_g2_read(chip, MV88E6250_G2_WDOG_CTL, ®); 820 821 reg &= ~(MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE | 822 MV88E6250_G2_WDOG_CTL_QC_ENABLE); 823 824 mv88e6xxx_g2_write(chip, MV88E6250_G2_WDOG_CTL, reg); 825 } 826 827 static int mv88e6250_watchdog_setup(struct mv88e6xxx_chip *chip) 828 { 829 return mv88e6xxx_g2_write(chip, MV88E6250_G2_WDOG_CTL, 830 MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE | 831 MV88E6250_G2_WDOG_CTL_QC_ENABLE | 832 MV88E6250_G2_WDOG_CTL_SWRESET); 833 } 834 835 const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops = { 836 .irq_action = mv88e6097_watchdog_action, 837 .irq_setup = mv88e6250_watchdog_setup, 838 .irq_free = mv88e6250_watchdog_free, 839 }; 840 841 static int mv88e6390_watchdog_setup(struct mv88e6xxx_chip *chip) 842 { 843 return mv88e6xxx_g2_update(chip, MV88E6390_G2_WDOG_CTL, 844 MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE | 845 MV88E6390_G2_WDOG_CTL_CUT_THROUGH | 846 MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER | 847 MV88E6390_G2_WDOG_CTL_EGRESS | 848 MV88E6390_G2_WDOG_CTL_FORCE_IRQ); 849 } 850 851 static int mv88e6390_watchdog_action(struct mv88e6xxx_chip *chip, int irq) 852 { 853 int err; 854 u16 reg; 855 856 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL, 857 MV88E6390_G2_WDOG_CTL_PTR_EVENT); 858 err = mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®); 859 860 dev_info(chip->dev, "Watchdog event: 0x%04x", 861 reg & MV88E6390_G2_WDOG_CTL_DATA_MASK); 862 863 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL, 864 MV88E6390_G2_WDOG_CTL_PTR_HISTORY); 865 err = mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®); 866 867 dev_info(chip->dev, "Watchdog history: 0x%04x", 868 reg & MV88E6390_G2_WDOG_CTL_DATA_MASK); 869 870 /* Trigger a software reset to try to recover the switch */ 871 if (chip->info->ops->reset) 872 chip->info->ops->reset(chip); 873 874 mv88e6390_watchdog_setup(chip); 875 876 return IRQ_HANDLED; 877 } 878 879 static void mv88e6390_watchdog_free(struct mv88e6xxx_chip *chip) 880 { 881 mv88e6xxx_g2_update(chip, MV88E6390_G2_WDOG_CTL, 882 MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE); 883 } 884 885 const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = { 886 .irq_action = mv88e6390_watchdog_action, 887 .irq_setup = mv88e6390_watchdog_setup, 888 .irq_free = mv88e6390_watchdog_free, 889 }; 890 891 static irqreturn_t mv88e6xxx_g2_watchdog_thread_fn(int irq, void *dev_id) 892 { 893 struct mv88e6xxx_chip *chip = dev_id; 894 irqreturn_t ret = IRQ_NONE; 895 896 mv88e6xxx_reg_lock(chip); 897 if (chip->info->ops->watchdog_ops->irq_action) 898 ret = chip->info->ops->watchdog_ops->irq_action(chip, irq); 899 mv88e6xxx_reg_unlock(chip); 900 901 return ret; 902 } 903 904 static void mv88e6xxx_g2_watchdog_free(struct mv88e6xxx_chip *chip) 905 { 906 mv88e6xxx_reg_lock(chip); 907 if (chip->info->ops->watchdog_ops->irq_free) 908 chip->info->ops->watchdog_ops->irq_free(chip); 909 mv88e6xxx_reg_unlock(chip); 910 911 free_irq(chip->watchdog_irq, chip); 912 irq_dispose_mapping(chip->watchdog_irq); 913 } 914 915 static int mv88e6xxx_g2_watchdog_setup(struct mv88e6xxx_chip *chip) 916 { 917 int err; 918 919 chip->watchdog_irq = irq_find_mapping(chip->g2_irq.domain, 920 MV88E6XXX_G2_INT_SOURCE_WATCHDOG); 921 if (chip->watchdog_irq < 0) 922 return chip->watchdog_irq; 923 924 err = request_threaded_irq(chip->watchdog_irq, NULL, 925 mv88e6xxx_g2_watchdog_thread_fn, 926 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 927 "mv88e6xxx-watchdog", chip); 928 if (err) 929 return err; 930 931 mv88e6xxx_reg_lock(chip); 932 if (chip->info->ops->watchdog_ops->irq_setup) 933 err = chip->info->ops->watchdog_ops->irq_setup(chip); 934 mv88e6xxx_reg_unlock(chip); 935 936 return err; 937 } 938 939 /* Offset 0x1D: Misc Register */ 940 941 static int mv88e6xxx_g2_misc_5_bit_port(struct mv88e6xxx_chip *chip, 942 bool port_5_bit) 943 { 944 u16 val; 945 int err; 946 947 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_MISC, &val); 948 if (err) 949 return err; 950 951 if (port_5_bit) 952 val |= MV88E6XXX_G2_MISC_5_BIT_PORT; 953 else 954 val &= ~MV88E6XXX_G2_MISC_5_BIT_PORT; 955 956 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MISC, val); 957 } 958 959 int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip) 960 { 961 return mv88e6xxx_g2_misc_5_bit_port(chip, false); 962 } 963 964 static void mv88e6xxx_g2_irq_mask(struct irq_data *d) 965 { 966 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 967 unsigned int n = d->hwirq; 968 969 chip->g2_irq.masked |= (1 << n); 970 } 971 972 static void mv88e6xxx_g2_irq_unmask(struct irq_data *d) 973 { 974 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 975 unsigned int n = d->hwirq; 976 977 chip->g2_irq.masked &= ~(1 << n); 978 } 979 980 static irqreturn_t mv88e6xxx_g2_irq_thread_fn(int irq, void *dev_id) 981 { 982 struct mv88e6xxx_chip *chip = dev_id; 983 unsigned int nhandled = 0; 984 unsigned int sub_irq; 985 unsigned int n; 986 int err; 987 u16 reg; 988 989 mv88e6xxx_reg_lock(chip); 990 err = mv88e6xxx_g2_int_source(chip, ®); 991 mv88e6xxx_reg_unlock(chip); 992 if (err) 993 goto out; 994 995 for (n = 0; n < 16; ++n) { 996 if (reg & (1 << n)) { 997 sub_irq = irq_find_mapping(chip->g2_irq.domain, n); 998 handle_nested_irq(sub_irq); 999 ++nhandled; 1000 } 1001 } 1002 out: 1003 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 1004 } 1005 1006 static void mv88e6xxx_g2_irq_bus_lock(struct irq_data *d) 1007 { 1008 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 1009 1010 mv88e6xxx_reg_lock(chip); 1011 } 1012 1013 static void mv88e6xxx_g2_irq_bus_sync_unlock(struct irq_data *d) 1014 { 1015 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 1016 int err; 1017 1018 err = mv88e6xxx_g2_int_mask(chip, ~chip->g2_irq.masked); 1019 if (err) 1020 dev_err(chip->dev, "failed to mask interrupts\n"); 1021 1022 mv88e6xxx_reg_unlock(chip); 1023 } 1024 1025 static const struct irq_chip mv88e6xxx_g2_irq_chip = { 1026 .name = "mv88e6xxx-g2", 1027 .irq_mask = mv88e6xxx_g2_irq_mask, 1028 .irq_unmask = mv88e6xxx_g2_irq_unmask, 1029 .irq_bus_lock = mv88e6xxx_g2_irq_bus_lock, 1030 .irq_bus_sync_unlock = mv88e6xxx_g2_irq_bus_sync_unlock, 1031 }; 1032 1033 static int mv88e6xxx_g2_irq_domain_map(struct irq_domain *d, 1034 unsigned int irq, 1035 irq_hw_number_t hwirq) 1036 { 1037 struct mv88e6xxx_chip *chip = d->host_data; 1038 1039 irq_set_chip_data(irq, d->host_data); 1040 irq_set_chip_and_handler(irq, &chip->g2_irq.chip, handle_level_irq); 1041 irq_set_noprobe(irq); 1042 1043 return 0; 1044 } 1045 1046 static const struct irq_domain_ops mv88e6xxx_g2_irq_domain_ops = { 1047 .map = mv88e6xxx_g2_irq_domain_map, 1048 .xlate = irq_domain_xlate_twocell, 1049 }; 1050 1051 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip) 1052 { 1053 int irq, virq; 1054 1055 mv88e6xxx_g2_watchdog_free(chip); 1056 1057 free_irq(chip->device_irq, chip); 1058 irq_dispose_mapping(chip->device_irq); 1059 1060 for (irq = 0; irq < 16; irq++) { 1061 virq = irq_find_mapping(chip->g2_irq.domain, irq); 1062 irq_dispose_mapping(virq); 1063 } 1064 1065 irq_domain_remove(chip->g2_irq.domain); 1066 } 1067 1068 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip) 1069 { 1070 int err, irq, virq; 1071 1072 chip->g2_irq.domain = irq_domain_add_simple( 1073 chip->dev->of_node, 16, 0, &mv88e6xxx_g2_irq_domain_ops, chip); 1074 if (!chip->g2_irq.domain) 1075 return -ENOMEM; 1076 1077 for (irq = 0; irq < 16; irq++) 1078 irq_create_mapping(chip->g2_irq.domain, irq); 1079 1080 chip->g2_irq.chip = mv88e6xxx_g2_irq_chip; 1081 chip->g2_irq.masked = ~0; 1082 1083 chip->device_irq = irq_find_mapping(chip->g1_irq.domain, 1084 MV88E6XXX_G1_STS_IRQ_DEVICE); 1085 if (chip->device_irq < 0) { 1086 err = chip->device_irq; 1087 goto out; 1088 } 1089 1090 err = request_threaded_irq(chip->device_irq, NULL, 1091 mv88e6xxx_g2_irq_thread_fn, 1092 IRQF_ONESHOT, "mv88e6xxx-g2", chip); 1093 if (err) 1094 goto out; 1095 1096 return mv88e6xxx_g2_watchdog_setup(chip); 1097 1098 out: 1099 for (irq = 0; irq < 16; irq++) { 1100 virq = irq_find_mapping(chip->g2_irq.domain, irq); 1101 irq_dispose_mapping(virq); 1102 } 1103 1104 irq_domain_remove(chip->g2_irq.domain); 1105 1106 return err; 1107 } 1108 1109 int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip, 1110 struct mii_bus *bus) 1111 { 1112 int phy, irq, err, err_phy; 1113 1114 for (phy = 0; phy < chip->info->num_internal_phys; phy++) { 1115 irq = irq_find_mapping(chip->g2_irq.domain, phy); 1116 if (irq < 0) { 1117 err = irq; 1118 goto out; 1119 } 1120 bus->irq[chip->info->phy_base_addr + phy] = irq; 1121 } 1122 return 0; 1123 out: 1124 err_phy = phy; 1125 1126 for (phy = 0; phy < err_phy; phy++) 1127 irq_dispose_mapping(bus->irq[phy]); 1128 1129 return err; 1130 } 1131 1132 void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip, 1133 struct mii_bus *bus) 1134 { 1135 int phy; 1136 1137 for (phy = 0; phy < chip->info->num_internal_phys; phy++) 1138 irq_dispose_mapping(bus->irq[phy]); 1139 } 1140