1 /* 2 * Marvell 88E6xxx Switch Global 2 Registers support (device address 3 * 0x1C) 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #include <linux/irqdomain.h> 16 #include "mv88e6xxx.h" 17 #include "global2.h" 18 19 #define ADDR_GLOBAL2 0x1c 20 21 static int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 22 { 23 return mv88e6xxx_read(chip, ADDR_GLOBAL2, reg, val); 24 } 25 26 static int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 27 { 28 return mv88e6xxx_write(chip, ADDR_GLOBAL2, reg, val); 29 } 30 31 static int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update) 32 { 33 return mv88e6xxx_update(chip, ADDR_GLOBAL2, reg, update); 34 } 35 36 static int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask) 37 { 38 return mv88e6xxx_wait(chip, ADDR_GLOBAL2, reg, mask); 39 } 40 41 /* Offset 0x02: Management Enable 2x */ 42 /* Offset 0x03: Management Enable 0x */ 43 44 int mv88e6095_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 45 { 46 int err; 47 48 /* Consider the frames with reserved multicast destination 49 * addresses matching 01:80:c2:00:00:2x as MGMT. 50 */ 51 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) { 52 err = mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_2X, 0xffff); 53 if (err) 54 return err; 55 } 56 57 /* Consider the frames with reserved multicast destination 58 * addresses matching 01:80:c2:00:00:0x as MGMT. 59 */ 60 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) 61 return mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_0X, 0xffff); 62 63 return 0; 64 } 65 66 /* Offset 0x06: Device Mapping Table register */ 67 68 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, 69 int target, int port) 70 { 71 u16 val = (target << 8) | (port & 0xf); 72 73 return mv88e6xxx_g2_update(chip, GLOBAL2_DEVICE_MAPPING, val); 74 } 75 76 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip) 77 { 78 int target, port; 79 int err; 80 81 /* Initialize the routing port to the 32 possible target devices */ 82 for (target = 0; target < 32; ++target) { 83 port = 0xf; 84 85 if (target < DSA_MAX_SWITCHES) { 86 port = chip->ds->rtable[target]; 87 if (port == DSA_RTABLE_NONE) 88 port = 0xf; 89 } 90 91 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 92 if (err) 93 break; 94 } 95 96 return err; 97 } 98 99 /* Offset 0x07: Trunk Mask Table register */ 100 101 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num, 102 bool hask, u16 mask) 103 { 104 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1; 105 u16 val = (num << 12) | (mask & port_mask); 106 107 if (hask) 108 val |= GLOBAL2_TRUNK_MASK_HASK; 109 110 return mv88e6xxx_g2_update(chip, GLOBAL2_TRUNK_MASK, val); 111 } 112 113 /* Offset 0x08: Trunk Mapping Table register */ 114 115 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id, 116 u16 map) 117 { 118 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1; 119 u16 val = (id << 11) | (map & port_mask); 120 121 return mv88e6xxx_g2_update(chip, GLOBAL2_TRUNK_MAPPING, val); 122 } 123 124 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip) 125 { 126 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1; 127 int i, err; 128 129 /* Clear all eight possible Trunk Mask vectors */ 130 for (i = 0; i < 8; ++i) { 131 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask); 132 if (err) 133 return err; 134 } 135 136 /* Clear all sixteen possible Trunk ID routing vectors */ 137 for (i = 0; i < 16; ++i) { 138 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0); 139 if (err) 140 return err; 141 } 142 143 return 0; 144 } 145 146 /* Offset 0x09: Ingress Rate Command register 147 * Offset 0x0A: Ingress Rate Data register 148 */ 149 150 static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip) 151 { 152 int port, err; 153 154 /* Init all Ingress Rate Limit resources of all ports */ 155 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 156 /* XXX newer chips (like 88E6390) have different 2-bit ops */ 157 err = mv88e6xxx_g2_write(chip, GLOBAL2_IRL_CMD, 158 GLOBAL2_IRL_CMD_OP_INIT_ALL | 159 (port << 8)); 160 if (err) 161 break; 162 163 /* Wait for the operation to complete */ 164 err = mv88e6xxx_g2_wait(chip, GLOBAL2_IRL_CMD, 165 GLOBAL2_IRL_CMD_BUSY); 166 if (err) 167 break; 168 } 169 170 return err; 171 } 172 173 /* Offset 0x0D: Switch MAC/WoL/WoF register */ 174 175 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip, 176 unsigned int pointer, u8 data) 177 { 178 u16 val = (pointer << 8) | data; 179 180 return mv88e6xxx_g2_update(chip, GLOBAL2_SWITCH_MAC, val); 181 } 182 183 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 184 { 185 int i, err; 186 187 for (i = 0; i < 6; i++) { 188 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]); 189 if (err) 190 break; 191 } 192 193 return err; 194 } 195 196 /* Offset 0x0F: Priority Override Table */ 197 198 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer, 199 u8 data) 200 { 201 u16 val = (pointer << 8) | (data & 0x7); 202 203 return mv88e6xxx_g2_update(chip, GLOBAL2_PRIO_OVERRIDE, val); 204 } 205 206 static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip) 207 { 208 int i, err; 209 210 /* Clear all sixteen possible Priority Override entries */ 211 for (i = 0; i < 16; i++) { 212 err = mv88e6xxx_g2_pot_write(chip, i, 0); 213 if (err) 214 break; 215 } 216 217 return err; 218 } 219 220 /* Offset 0x14: EEPROM Command 221 * Offset 0x15: EEPROM Data (for 16-bit data access) 222 * Offset 0x15: EEPROM Addr (for 8-bit data access) 223 */ 224 225 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip) 226 { 227 return mv88e6xxx_g2_wait(chip, GLOBAL2_EEPROM_CMD, 228 GLOBAL2_EEPROM_CMD_BUSY | 229 GLOBAL2_EEPROM_CMD_RUNNING); 230 } 231 232 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd) 233 { 234 int err; 235 236 err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_CMD, cmd); 237 if (err) 238 return err; 239 240 return mv88e6xxx_g2_eeprom_wait(chip); 241 } 242 243 static int mv88e6xxx_g2_eeprom_read8(struct mv88e6xxx_chip *chip, 244 u16 addr, u8 *data) 245 { 246 u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ; 247 int err; 248 249 err = mv88e6xxx_g2_eeprom_wait(chip); 250 if (err) 251 return err; 252 253 err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_ADDR, addr); 254 if (err) 255 return err; 256 257 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd); 258 if (err) 259 return err; 260 261 err = mv88e6xxx_g2_read(chip, GLOBAL2_EEPROM_CMD, &cmd); 262 if (err) 263 return err; 264 265 *data = cmd & 0xff; 266 267 return 0; 268 } 269 270 static int mv88e6xxx_g2_eeprom_write8(struct mv88e6xxx_chip *chip, 271 u16 addr, u8 data) 272 { 273 u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | GLOBAL2_EEPROM_CMD_WRITE_EN; 274 int err; 275 276 err = mv88e6xxx_g2_eeprom_wait(chip); 277 if (err) 278 return err; 279 280 err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_ADDR, addr); 281 if (err) 282 return err; 283 284 return mv88e6xxx_g2_eeprom_cmd(chip, cmd | data); 285 } 286 287 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip, 288 u8 addr, u16 *data) 289 { 290 u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr; 291 int err; 292 293 err = mv88e6xxx_g2_eeprom_wait(chip); 294 if (err) 295 return err; 296 297 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd); 298 if (err) 299 return err; 300 301 return mv88e6xxx_g2_read(chip, GLOBAL2_EEPROM_DATA, data); 302 } 303 304 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip, 305 u8 addr, u16 data) 306 { 307 u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr; 308 int err; 309 310 err = mv88e6xxx_g2_eeprom_wait(chip); 311 if (err) 312 return err; 313 314 err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_DATA, data); 315 if (err) 316 return err; 317 318 return mv88e6xxx_g2_eeprom_cmd(chip, cmd); 319 } 320 321 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, 322 struct ethtool_eeprom *eeprom, u8 *data) 323 { 324 unsigned int offset = eeprom->offset; 325 unsigned int len = eeprom->len; 326 int err; 327 328 eeprom->len = 0; 329 330 while (len) { 331 err = mv88e6xxx_g2_eeprom_read8(chip, offset, data); 332 if (err) 333 return err; 334 335 eeprom->len++; 336 offset++; 337 data++; 338 len--; 339 } 340 341 return 0; 342 } 343 344 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, 345 struct ethtool_eeprom *eeprom, u8 *data) 346 { 347 unsigned int offset = eeprom->offset; 348 unsigned int len = eeprom->len; 349 int err; 350 351 eeprom->len = 0; 352 353 while (len) { 354 err = mv88e6xxx_g2_eeprom_write8(chip, offset, *data); 355 if (err) 356 return err; 357 358 eeprom->len++; 359 offset++; 360 data++; 361 len--; 362 } 363 364 return 0; 365 } 366 367 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, 368 struct ethtool_eeprom *eeprom, u8 *data) 369 { 370 unsigned int offset = eeprom->offset; 371 unsigned int len = eeprom->len; 372 u16 val; 373 int err; 374 375 eeprom->len = 0; 376 377 if (offset & 1) { 378 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 379 if (err) 380 return err; 381 382 *data++ = (val >> 8) & 0xff; 383 384 offset++; 385 len--; 386 eeprom->len++; 387 } 388 389 while (len >= 2) { 390 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 391 if (err) 392 return err; 393 394 *data++ = val & 0xff; 395 *data++ = (val >> 8) & 0xff; 396 397 offset += 2; 398 len -= 2; 399 eeprom->len += 2; 400 } 401 402 if (len) { 403 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 404 if (err) 405 return err; 406 407 *data++ = val & 0xff; 408 409 offset++; 410 len--; 411 eeprom->len++; 412 } 413 414 return 0; 415 } 416 417 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 418 struct ethtool_eeprom *eeprom, u8 *data) 419 { 420 unsigned int offset = eeprom->offset; 421 unsigned int len = eeprom->len; 422 u16 val; 423 int err; 424 425 /* Ensure the RO WriteEn bit is set */ 426 err = mv88e6xxx_g2_read(chip, GLOBAL2_EEPROM_CMD, &val); 427 if (err) 428 return err; 429 430 if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN)) 431 return -EROFS; 432 433 eeprom->len = 0; 434 435 if (offset & 1) { 436 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 437 if (err) 438 return err; 439 440 val = (*data++ << 8) | (val & 0xff); 441 442 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); 443 if (err) 444 return err; 445 446 offset++; 447 len--; 448 eeprom->len++; 449 } 450 451 while (len >= 2) { 452 val = *data++; 453 val |= *data++ << 8; 454 455 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); 456 if (err) 457 return err; 458 459 offset += 2; 460 len -= 2; 461 eeprom->len += 2; 462 } 463 464 if (len) { 465 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 466 if (err) 467 return err; 468 469 val = (val & 0xff00) | *data++; 470 471 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); 472 if (err) 473 return err; 474 475 offset++; 476 len--; 477 eeprom->len++; 478 } 479 480 return 0; 481 } 482 483 /* Offset 0x18: SMI PHY Command Register 484 * Offset 0x19: SMI PHY Data Register 485 */ 486 487 static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip) 488 { 489 return mv88e6xxx_g2_wait(chip, GLOBAL2_SMI_PHY_CMD, 490 GLOBAL2_SMI_PHY_CMD_BUSY); 491 } 492 493 static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd) 494 { 495 int err; 496 497 err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_CMD, cmd); 498 if (err) 499 return err; 500 501 return mv88e6xxx_g2_smi_phy_wait(chip); 502 } 503 504 static int mv88e6xxx_g2_smi_phy_write_addr(struct mv88e6xxx_chip *chip, 505 int addr, int device, int reg, 506 bool external) 507 { 508 int cmd = SMI_CMD_OP_45_WRITE_ADDR | (addr << 5) | device; 509 int err; 510 511 if (external) 512 cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL; 513 514 err = mv88e6xxx_g2_smi_phy_wait(chip); 515 if (err) 516 return err; 517 518 err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_DATA, reg); 519 if (err) 520 return err; 521 522 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd); 523 } 524 525 int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip, int addr, 526 int reg_c45, u16 *val, bool external) 527 { 528 int device = (reg_c45 >> 16) & 0x1f; 529 int reg = reg_c45 & 0xffff; 530 int err; 531 u16 cmd; 532 533 err = mv88e6xxx_g2_smi_phy_write_addr(chip, addr, device, reg, 534 external); 535 if (err) 536 return err; 537 538 cmd = GLOBAL2_SMI_PHY_CMD_OP_45_READ_DATA | (addr << 5) | device; 539 540 if (external) 541 cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL; 542 543 err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd); 544 if (err) 545 return err; 546 547 err = mv88e6xxx_g2_read(chip, GLOBAL2_SMI_PHY_DATA, val); 548 if (err) 549 return err; 550 551 err = *val; 552 553 return 0; 554 } 555 556 int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip, int addr, 557 int reg, u16 *val, bool external) 558 { 559 u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA | (addr << 5) | reg; 560 int err; 561 562 if (external) 563 cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL; 564 565 err = mv88e6xxx_g2_smi_phy_wait(chip); 566 if (err) 567 return err; 568 569 err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd); 570 if (err) 571 return err; 572 573 return mv88e6xxx_g2_read(chip, GLOBAL2_SMI_PHY_DATA, val); 574 } 575 576 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, 577 struct mii_bus *bus, 578 int addr, int reg, u16 *val) 579 { 580 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 581 bool external = mdio_bus->external; 582 583 if (reg & MII_ADDR_C45) 584 return mv88e6xxx_g2_smi_phy_read_c45(chip, addr, reg, val, 585 external); 586 return mv88e6xxx_g2_smi_phy_read_c22(chip, addr, reg, val, external); 587 } 588 589 int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip, int addr, 590 int reg_c45, u16 val, bool external) 591 { 592 int device = (reg_c45 >> 16) & 0x1f; 593 int reg = reg_c45 & 0xffff; 594 int err; 595 u16 cmd; 596 597 err = mv88e6xxx_g2_smi_phy_write_addr(chip, addr, device, reg, 598 external); 599 if (err) 600 return err; 601 602 cmd = GLOBAL2_SMI_PHY_CMD_OP_45_WRITE_DATA | (addr << 5) | device; 603 604 if (external) 605 cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL; 606 607 err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_DATA, val); 608 if (err) 609 return err; 610 611 err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd); 612 if (err) 613 return err; 614 615 return 0; 616 } 617 618 int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip, int addr, 619 int reg, u16 val, bool external) 620 { 621 u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA | (addr << 5) | reg; 622 int err; 623 624 if (external) 625 cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL; 626 627 err = mv88e6xxx_g2_smi_phy_wait(chip); 628 if (err) 629 return err; 630 631 err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_DATA, val); 632 if (err) 633 return err; 634 635 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd); 636 } 637 638 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, 639 struct mii_bus *bus, 640 int addr, int reg, u16 val) 641 { 642 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 643 bool external = mdio_bus->external; 644 645 if (reg & MII_ADDR_C45) 646 return mv88e6xxx_g2_smi_phy_write_c45(chip, addr, reg, val, 647 external); 648 649 return mv88e6xxx_g2_smi_phy_write_c22(chip, addr, reg, val, external); 650 } 651 652 static int mv88e6097_watchdog_action(struct mv88e6xxx_chip *chip, int irq) 653 { 654 u16 reg; 655 656 mv88e6xxx_g2_read(chip, GLOBAL2_WDOG_CONTROL, ®); 657 658 dev_info(chip->dev, "Watchdog event: 0x%04x", reg); 659 660 return IRQ_HANDLED; 661 } 662 663 static void mv88e6097_watchdog_free(struct mv88e6xxx_chip *chip) 664 { 665 u16 reg; 666 667 mv88e6xxx_g2_read(chip, GLOBAL2_WDOG_CONTROL, ®); 668 669 reg &= ~(GLOBAL2_WDOG_CONTROL_EGRESS_ENABLE | 670 GLOBAL2_WDOG_CONTROL_QC_ENABLE); 671 672 mv88e6xxx_g2_write(chip, GLOBAL2_WDOG_CONTROL, reg); 673 } 674 675 static int mv88e6097_watchdog_setup(struct mv88e6xxx_chip *chip) 676 { 677 return mv88e6xxx_g2_write(chip, GLOBAL2_WDOG_CONTROL, 678 GLOBAL2_WDOG_CONTROL_EGRESS_ENABLE | 679 GLOBAL2_WDOG_CONTROL_QC_ENABLE | 680 GLOBAL2_WDOG_CONTROL_SWRESET); 681 } 682 683 const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = { 684 .irq_action = mv88e6097_watchdog_action, 685 .irq_setup = mv88e6097_watchdog_setup, 686 .irq_free = mv88e6097_watchdog_free, 687 }; 688 689 static int mv88e6390_watchdog_setup(struct mv88e6xxx_chip *chip) 690 { 691 return mv88e6xxx_g2_update(chip, GLOBAL2_WDOG_CONTROL, 692 GLOBAL2_WDOG_INT_ENABLE | 693 GLOBAL2_WDOG_CUT_THROUGH | 694 GLOBAL2_WDOG_QUEUE_CONTROLLER | 695 GLOBAL2_WDOG_EGRESS | 696 GLOBAL2_WDOG_FORCE_IRQ); 697 } 698 699 static int mv88e6390_watchdog_action(struct mv88e6xxx_chip *chip, int irq) 700 { 701 int err; 702 u16 reg; 703 704 mv88e6xxx_g2_write(chip, GLOBAL2_WDOG_CONTROL, GLOBAL2_WDOG_EVENT); 705 err = mv88e6xxx_g2_read(chip, GLOBAL2_WDOG_CONTROL, ®); 706 707 dev_info(chip->dev, "Watchdog event: 0x%04x", 708 reg & GLOBAL2_WDOG_DATA_MASK); 709 710 mv88e6xxx_g2_write(chip, GLOBAL2_WDOG_CONTROL, GLOBAL2_WDOG_HISTORY); 711 err = mv88e6xxx_g2_read(chip, GLOBAL2_WDOG_CONTROL, ®); 712 713 dev_info(chip->dev, "Watchdog history: 0x%04x", 714 reg & GLOBAL2_WDOG_DATA_MASK); 715 716 /* Trigger a software reset to try to recover the switch */ 717 if (chip->info->ops->reset) 718 chip->info->ops->reset(chip); 719 720 mv88e6390_watchdog_setup(chip); 721 722 return IRQ_HANDLED; 723 } 724 725 static void mv88e6390_watchdog_free(struct mv88e6xxx_chip *chip) 726 { 727 mv88e6xxx_g2_update(chip, GLOBAL2_WDOG_CONTROL, 728 GLOBAL2_WDOG_INT_ENABLE); 729 } 730 731 const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = { 732 .irq_action = mv88e6390_watchdog_action, 733 .irq_setup = mv88e6390_watchdog_setup, 734 .irq_free = mv88e6390_watchdog_free, 735 }; 736 737 static irqreturn_t mv88e6xxx_g2_watchdog_thread_fn(int irq, void *dev_id) 738 { 739 struct mv88e6xxx_chip *chip = dev_id; 740 irqreturn_t ret = IRQ_NONE; 741 742 mutex_lock(&chip->reg_lock); 743 if (chip->info->ops->watchdog_ops->irq_action) 744 ret = chip->info->ops->watchdog_ops->irq_action(chip, irq); 745 mutex_unlock(&chip->reg_lock); 746 747 return ret; 748 } 749 750 static void mv88e6xxx_g2_watchdog_free(struct mv88e6xxx_chip *chip) 751 { 752 mutex_lock(&chip->reg_lock); 753 if (chip->info->ops->watchdog_ops->irq_free) 754 chip->info->ops->watchdog_ops->irq_free(chip); 755 mutex_unlock(&chip->reg_lock); 756 757 free_irq(chip->watchdog_irq, chip); 758 irq_dispose_mapping(chip->watchdog_irq); 759 } 760 761 static int mv88e6xxx_g2_watchdog_setup(struct mv88e6xxx_chip *chip) 762 { 763 int err; 764 765 chip->watchdog_irq = irq_find_mapping(chip->g2_irq.domain, 766 GLOBAL2_INT_SOURCE_WATCHDOG); 767 if (chip->watchdog_irq < 0) 768 return chip->watchdog_irq; 769 770 err = request_threaded_irq(chip->watchdog_irq, NULL, 771 mv88e6xxx_g2_watchdog_thread_fn, 772 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 773 "mv88e6xxx-watchdog", chip); 774 if (err) 775 return err; 776 777 mutex_lock(&chip->reg_lock); 778 if (chip->info->ops->watchdog_ops->irq_setup) 779 err = chip->info->ops->watchdog_ops->irq_setup(chip); 780 mutex_unlock(&chip->reg_lock); 781 782 return err; 783 } 784 785 static void mv88e6xxx_g2_irq_mask(struct irq_data *d) 786 { 787 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 788 unsigned int n = d->hwirq; 789 790 chip->g2_irq.masked |= (1 << n); 791 } 792 793 static void mv88e6xxx_g2_irq_unmask(struct irq_data *d) 794 { 795 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 796 unsigned int n = d->hwirq; 797 798 chip->g2_irq.masked &= ~(1 << n); 799 } 800 801 static irqreturn_t mv88e6xxx_g2_irq_thread_fn(int irq, void *dev_id) 802 { 803 struct mv88e6xxx_chip *chip = dev_id; 804 unsigned int nhandled = 0; 805 unsigned int sub_irq; 806 unsigned int n; 807 int err; 808 u16 reg; 809 810 mutex_lock(&chip->reg_lock); 811 err = mv88e6xxx_g2_read(chip, GLOBAL2_INT_SOURCE, ®); 812 mutex_unlock(&chip->reg_lock); 813 if (err) 814 goto out; 815 816 for (n = 0; n < 16; ++n) { 817 if (reg & (1 << n)) { 818 sub_irq = irq_find_mapping(chip->g2_irq.domain, n); 819 handle_nested_irq(sub_irq); 820 ++nhandled; 821 } 822 } 823 out: 824 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 825 } 826 827 static void mv88e6xxx_g2_irq_bus_lock(struct irq_data *d) 828 { 829 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 830 831 mutex_lock(&chip->reg_lock); 832 } 833 834 static void mv88e6xxx_g2_irq_bus_sync_unlock(struct irq_data *d) 835 { 836 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 837 838 mv88e6xxx_g2_write(chip, GLOBAL2_INT_MASK, ~chip->g2_irq.masked); 839 840 mutex_unlock(&chip->reg_lock); 841 } 842 843 static struct irq_chip mv88e6xxx_g2_irq_chip = { 844 .name = "mv88e6xxx-g2", 845 .irq_mask = mv88e6xxx_g2_irq_mask, 846 .irq_unmask = mv88e6xxx_g2_irq_unmask, 847 .irq_bus_lock = mv88e6xxx_g2_irq_bus_lock, 848 .irq_bus_sync_unlock = mv88e6xxx_g2_irq_bus_sync_unlock, 849 }; 850 851 static int mv88e6xxx_g2_irq_domain_map(struct irq_domain *d, 852 unsigned int irq, 853 irq_hw_number_t hwirq) 854 { 855 struct mv88e6xxx_chip *chip = d->host_data; 856 857 irq_set_chip_data(irq, d->host_data); 858 irq_set_chip_and_handler(irq, &chip->g2_irq.chip, handle_level_irq); 859 irq_set_noprobe(irq); 860 861 return 0; 862 } 863 864 static const struct irq_domain_ops mv88e6xxx_g2_irq_domain_ops = { 865 .map = mv88e6xxx_g2_irq_domain_map, 866 .xlate = irq_domain_xlate_twocell, 867 }; 868 869 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip) 870 { 871 int irq, virq; 872 873 mv88e6xxx_g2_watchdog_free(chip); 874 875 free_irq(chip->device_irq, chip); 876 irq_dispose_mapping(chip->device_irq); 877 878 for (irq = 0; irq < 16; irq++) { 879 virq = irq_find_mapping(chip->g2_irq.domain, irq); 880 irq_dispose_mapping(virq); 881 } 882 883 irq_domain_remove(chip->g2_irq.domain); 884 } 885 886 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip) 887 { 888 int err, irq, virq; 889 890 if (!chip->dev->of_node) 891 return -EINVAL; 892 893 chip->g2_irq.domain = irq_domain_add_simple( 894 chip->dev->of_node, 16, 0, &mv88e6xxx_g2_irq_domain_ops, chip); 895 if (!chip->g2_irq.domain) 896 return -ENOMEM; 897 898 for (irq = 0; irq < 16; irq++) 899 irq_create_mapping(chip->g2_irq.domain, irq); 900 901 chip->g2_irq.chip = mv88e6xxx_g2_irq_chip; 902 chip->g2_irq.masked = ~0; 903 904 chip->device_irq = irq_find_mapping(chip->g1_irq.domain, 905 GLOBAL_STATUS_IRQ_DEVICE); 906 if (chip->device_irq < 0) { 907 err = chip->device_irq; 908 goto out; 909 } 910 911 err = request_threaded_irq(chip->device_irq, NULL, 912 mv88e6xxx_g2_irq_thread_fn, 913 IRQF_ONESHOT, "mv88e6xxx-g1", chip); 914 if (err) 915 goto out; 916 917 return mv88e6xxx_g2_watchdog_setup(chip); 918 919 out: 920 for (irq = 0; irq < 16; irq++) { 921 virq = irq_find_mapping(chip->g2_irq.domain, irq); 922 irq_dispose_mapping(virq); 923 } 924 925 irq_domain_remove(chip->g2_irq.domain); 926 927 return err; 928 } 929 930 int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip) 931 { 932 u16 reg; 933 int err; 934 935 /* Ignore removed tag data on doubly tagged packets, disable 936 * flow control messages, force flow control priority to the 937 * highest, and send all special multicast frames to the CPU 938 * port at the highest priority. 939 */ 940 reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4); 941 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) || 942 mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) 943 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7; 944 err = mv88e6xxx_g2_write(chip, GLOBAL2_SWITCH_MGMT, reg); 945 if (err) 946 return err; 947 948 /* Program the DSA routing table. */ 949 err = mv88e6xxx_g2_set_device_mapping(chip); 950 if (err) 951 return err; 952 953 /* Clear all trunk masks and mapping. */ 954 err = mv88e6xxx_g2_clear_trunk(chip); 955 if (err) 956 return err; 957 958 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) { 959 /* Disable ingress rate limiting by resetting all per port 960 * ingress rate limit resources to their initial state. 961 */ 962 err = mv88e6xxx_g2_clear_irl(chip); 963 if (err) 964 return err; 965 } 966 967 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) { 968 /* Initialize Cross-chip Port VLAN Table to reset defaults */ 969 err = mv88e6xxx_g2_write(chip, GLOBAL2_PVT_ADDR, 970 GLOBAL2_PVT_ADDR_OP_INIT_ONES); 971 if (err) 972 return err; 973 } 974 975 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) { 976 /* Clear the priority override table. */ 977 err = mv88e6xxx_g2_clear_pot(chip); 978 if (err) 979 return err; 980 } 981 982 return 0; 983 } 984