12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2ec561276SVivien Didelot /* 31d90016dSVivien Didelot * Marvell 88E6xxx Switch Global 2 Registers support 4ec561276SVivien Didelot * 5ec561276SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 6ec561276SVivien Didelot * 74333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 84333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9ec561276SVivien Didelot */ 10ec561276SVivien Didelot 11e289ef0dSVivien Didelot #include <linux/bitfield.h> 12282ccf6eSFlorian Westphal #include <linux/interrupt.h> 13dc30c35bSAndrew Lunn #include <linux/irqdomain.h> 144d5f2ba7SVivien Didelot 154d5f2ba7SVivien Didelot #include "chip.h" 1682466921SVivien Didelot #include "global1.h" /* for MV88E6XXX_G1_STS_IRQ_DEVICE */ 17ec561276SVivien Didelot #include "global2.h" 18ec561276SVivien Didelot 19b000be95SBrandon Streiff int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 209fe850fbSVivien Didelot { 219069c13aSVivien Didelot return mv88e6xxx_read(chip, chip->info->global2_addr, reg, val); 229fe850fbSVivien Didelot } 239fe850fbSVivien Didelot 24b000be95SBrandon Streiff int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 259fe850fbSVivien Didelot { 269069c13aSVivien Didelot return mv88e6xxx_write(chip, chip->info->global2_addr, reg, val); 279fe850fbSVivien Didelot } 289fe850fbSVivien Didelot 2919fb7f69SVivien Didelot int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg, int 3019fb7f69SVivien Didelot bit, int val) 3119fb7f69SVivien Didelot { 3219fb7f69SVivien Didelot return mv88e6xxx_wait_bit(chip, chip->info->global2_addr, reg, 3319fb7f69SVivien Didelot bit, val); 3419fb7f69SVivien Didelot } 3519fb7f69SVivien Didelot 36d6c5e6afSVivien Didelot /* Offset 0x00: Interrupt Source Register */ 37d6c5e6afSVivien Didelot 38d6c5e6afSVivien Didelot static int mv88e6xxx_g2_int_source(struct mv88e6xxx_chip *chip, u16 *src) 39d6c5e6afSVivien Didelot { 40d6c5e6afSVivien Didelot /* Read (and clear most of) the Interrupt Source bits */ 41d6c5e6afSVivien Didelot return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_INT_SRC, src); 42d6c5e6afSVivien Didelot } 43d6c5e6afSVivien Didelot 44d6c5e6afSVivien Didelot /* Offset 0x01: Interrupt Mask Register */ 45d6c5e6afSVivien Didelot 46d6c5e6afSVivien Didelot static int mv88e6xxx_g2_int_mask(struct mv88e6xxx_chip *chip, u16 mask) 47d6c5e6afSVivien Didelot { 48d6c5e6afSVivien Didelot return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_INT_MASK, mask); 49d6c5e6afSVivien Didelot } 50d6c5e6afSVivien Didelot 516e55f698SAndrew Lunn /* Offset 0x02: Management Enable 2x */ 5251c901a7SVivien Didelot 5351c901a7SVivien Didelot static int mv88e6xxx_g2_mgmt_enable_2x(struct mv88e6xxx_chip *chip, u16 en2x) 5451c901a7SVivien Didelot { 5551c901a7SVivien Didelot return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_2X, en2x); 5651c901a7SVivien Didelot } 5751c901a7SVivien Didelot 586e55f698SAndrew Lunn /* Offset 0x03: Management Enable 0x */ 596e55f698SAndrew Lunn 6051c901a7SVivien Didelot static int mv88e6xxx_g2_mgmt_enable_0x(struct mv88e6xxx_chip *chip, u16 en0x) 6151c901a7SVivien Didelot { 6251c901a7SVivien Didelot return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_0X, en0x); 6351c901a7SVivien Didelot } 6451c901a7SVivien Didelot 6551c901a7SVivien Didelot /* Offset 0x05: Switch Management Register */ 6651c901a7SVivien Didelot 6751c901a7SVivien Didelot static int mv88e6xxx_g2_switch_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip, 6851c901a7SVivien Didelot bool enable) 6951c901a7SVivien Didelot { 7051c901a7SVivien Didelot u16 val; 7151c901a7SVivien Didelot int err; 7251c901a7SVivien Didelot 7351c901a7SVivien Didelot err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SWITCH_MGMT, &val); 7451c901a7SVivien Didelot if (err) 7551c901a7SVivien Didelot return err; 7651c901a7SVivien Didelot 7751c901a7SVivien Didelot if (enable) 7851c901a7SVivien Didelot val |= MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU; 7951c901a7SVivien Didelot else 8051c901a7SVivien Didelot val &= ~MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU; 8151c901a7SVivien Didelot 8251c901a7SVivien Didelot return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MGMT, val); 8351c901a7SVivien Didelot } 8451c901a7SVivien Didelot 8551c901a7SVivien Didelot int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 8651c901a7SVivien Didelot { 8751c901a7SVivien Didelot int err; 8851c901a7SVivien Didelot 8951c901a7SVivien Didelot /* Consider the frames with reserved multicast destination 9051c901a7SVivien Didelot * addresses matching 01:80:c2:00:00:0x as MGMT. 9151c901a7SVivien Didelot */ 9251c901a7SVivien Didelot err = mv88e6xxx_g2_mgmt_enable_0x(chip, 0xffff); 9351c901a7SVivien Didelot if (err) 9451c901a7SVivien Didelot return err; 9551c901a7SVivien Didelot 9651c901a7SVivien Didelot return mv88e6xxx_g2_switch_mgmt_rsvd2cpu(chip, true); 9751c901a7SVivien Didelot } 9851c901a7SVivien Didelot 9951c901a7SVivien Didelot int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 1006e55f698SAndrew Lunn { 1016e55f698SAndrew Lunn int err; 1026e55f698SAndrew Lunn 1036e55f698SAndrew Lunn /* Consider the frames with reserved multicast destination 1046e55f698SAndrew Lunn * addresses matching 01:80:c2:00:00:2x as MGMT. 1056e55f698SAndrew Lunn */ 10651c901a7SVivien Didelot err = mv88e6xxx_g2_mgmt_enable_2x(chip, 0xffff); 1076e55f698SAndrew Lunn if (err) 1086e55f698SAndrew Lunn return err; 1096e55f698SAndrew Lunn 11051c901a7SVivien Didelot return mv88e6185_g2_mgmt_rsvd2cpu(chip); 1116e55f698SAndrew Lunn } 1126e55f698SAndrew Lunn 113ec561276SVivien Didelot /* Offset 0x06: Device Mapping Table register */ 114ec561276SVivien Didelot 115c7f047b6SVivien Didelot int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target, 116c7f047b6SVivien Didelot int port) 117ec561276SVivien Didelot { 118c7f047b6SVivien Didelot u16 val = (target << 8) | (port & 0x1f); 119c7f047b6SVivien Didelot /* Modern chips use 5 bits to define a device mapping port, 120c7f047b6SVivien Didelot * but bit 4 is reserved on older chips, so it is safe to use. 121c7f047b6SVivien Didelot */ 122ec561276SVivien Didelot 1232ad4da77SVivien Didelot return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_DEVICE_MAPPING, 1242ad4da77SVivien Didelot MV88E6XXX_G2_DEVICE_MAPPING_UPDATE | val); 125ec561276SVivien Didelot } 126ec561276SVivien Didelot 127ec561276SVivien Didelot /* Offset 0x07: Trunk Mask Table register */ 128ec561276SVivien Didelot 129ec561276SVivien Didelot static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num, 13056dc7347SVivien Didelot bool hash, u16 mask) 131ec561276SVivien Didelot { 13256dc7347SVivien Didelot u16 val = (num << 12) | (mask & mv88e6xxx_port_mask(chip)); 133ec561276SVivien Didelot 13456dc7347SVivien Didelot if (hash) 13556dc7347SVivien Didelot val |= MV88E6XXX_G2_TRUNK_MASK_HASH; 136ec561276SVivien Didelot 1372ad4da77SVivien Didelot return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_TRUNK_MASK, 1382ad4da77SVivien Didelot MV88E6XXX_G2_TRUNK_MASK_UPDATE | val); 139ec561276SVivien Didelot } 140ec561276SVivien Didelot 141ec561276SVivien Didelot /* Offset 0x08: Trunk Mapping Table register */ 142ec561276SVivien Didelot 143ec561276SVivien Didelot static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id, 144ec561276SVivien Didelot u16 map) 145ec561276SVivien Didelot { 146370b4ffbSVivien Didelot const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1; 147ec561276SVivien Didelot u16 val = (id << 11) | (map & port_mask); 148ec561276SVivien Didelot 1492ad4da77SVivien Didelot return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_TRUNK_MAPPING, 1502ad4da77SVivien Didelot MV88E6XXX_G2_TRUNK_MAPPING_UPDATE | val); 151ec561276SVivien Didelot } 152ec561276SVivien Didelot 153b28f872dSVivien Didelot int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip) 154ec561276SVivien Didelot { 155370b4ffbSVivien Didelot const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1; 156ec561276SVivien Didelot int i, err; 157ec561276SVivien Didelot 158ec561276SVivien Didelot /* Clear all eight possible Trunk Mask vectors */ 159ec561276SVivien Didelot for (i = 0; i < 8; ++i) { 160ec561276SVivien Didelot err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask); 161ec561276SVivien Didelot if (err) 162ec561276SVivien Didelot return err; 163ec561276SVivien Didelot } 164ec561276SVivien Didelot 165ec561276SVivien Didelot /* Clear all sixteen possible Trunk ID routing vectors */ 166ec561276SVivien Didelot for (i = 0; i < 16; ++i) { 167ec561276SVivien Didelot err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0); 168ec561276SVivien Didelot if (err) 169ec561276SVivien Didelot return err; 170ec561276SVivien Didelot } 171ec561276SVivien Didelot 172ec561276SVivien Didelot return 0; 173ec561276SVivien Didelot } 174ec561276SVivien Didelot 175ec561276SVivien Didelot /* Offset 0x09: Ingress Rate Command register 176ec561276SVivien Didelot * Offset 0x0A: Ingress Rate Data register 177ec561276SVivien Didelot */ 178ec561276SVivien Didelot 179cd8da8bbSVivien Didelot static int mv88e6xxx_g2_irl_wait(struct mv88e6xxx_chip *chip) 180ec561276SVivien Didelot { 18119fb7f69SVivien Didelot int bit = __bf_shf(MV88E6XXX_G2_IRL_CMD_BUSY); 18219fb7f69SVivien Didelot 18319fb7f69SVivien Didelot return mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_IRL_CMD, bit, 0); 184ec561276SVivien Didelot } 185ec561276SVivien Didelot 186cd8da8bbSVivien Didelot static int mv88e6xxx_g2_irl_op(struct mv88e6xxx_chip *chip, u16 op, int port, 187cd8da8bbSVivien Didelot int res, int reg) 188cd8da8bbSVivien Didelot { 189cd8da8bbSVivien Didelot int err; 190cd8da8bbSVivien Didelot 191cd8da8bbSVivien Didelot err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_IRL_CMD, 192cd8da8bbSVivien Didelot MV88E6XXX_G2_IRL_CMD_BUSY | op | (port << 8) | 193cd8da8bbSVivien Didelot (res << 5) | reg); 194cd8da8bbSVivien Didelot if (err) 195ec561276SVivien Didelot return err; 196cd8da8bbSVivien Didelot 197cd8da8bbSVivien Didelot return mv88e6xxx_g2_irl_wait(chip); 198cd8da8bbSVivien Didelot } 199cd8da8bbSVivien Didelot 200cd8da8bbSVivien Didelot int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port) 201cd8da8bbSVivien Didelot { 202cd8da8bbSVivien Didelot return mv88e6xxx_g2_irl_op(chip, MV88E6352_G2_IRL_CMD_OP_INIT_ALL, port, 203cd8da8bbSVivien Didelot 0, 0); 204cd8da8bbSVivien Didelot } 205cd8da8bbSVivien Didelot 206cd8da8bbSVivien Didelot int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port) 207cd8da8bbSVivien Didelot { 208cd8da8bbSVivien Didelot return mv88e6xxx_g2_irl_op(chip, MV88E6390_G2_IRL_CMD_OP_INIT_ALL, port, 209cd8da8bbSVivien Didelot 0, 0); 210ec561276SVivien Didelot } 211ec561276SVivien Didelot 21217a1594eSVivien Didelot /* Offset 0x0B: Cross-chip Port VLAN (Addr) Register 21317a1594eSVivien Didelot * Offset 0x0C: Cross-chip Port VLAN Data Register 21417a1594eSVivien Didelot */ 21517a1594eSVivien Didelot 21617a1594eSVivien Didelot static int mv88e6xxx_g2_pvt_op_wait(struct mv88e6xxx_chip *chip) 21717a1594eSVivien Didelot { 21819fb7f69SVivien Didelot int bit = __bf_shf(MV88E6XXX_G2_PVT_ADDR_BUSY); 21919fb7f69SVivien Didelot 22019fb7f69SVivien Didelot return mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_PVT_ADDR, bit, 0); 22117a1594eSVivien Didelot } 22217a1594eSVivien Didelot 22317a1594eSVivien Didelot static int mv88e6xxx_g2_pvt_op(struct mv88e6xxx_chip *chip, int src_dev, 22417a1594eSVivien Didelot int src_port, u16 op) 22517a1594eSVivien Didelot { 22617a1594eSVivien Didelot int err; 22717a1594eSVivien Didelot 22867d1ea8eSVivien Didelot /* 9-bit Cross-chip PVT pointer: with MV88E6XXX_G2_MISC_5_BIT_PORT 22967d1ea8eSVivien Didelot * cleared, source device is 5-bit, source port is 4-bit. 23017a1594eSVivien Didelot */ 23167d1ea8eSVivien Didelot op |= MV88E6XXX_G2_PVT_ADDR_BUSY; 23217a1594eSVivien Didelot op |= (src_dev & 0x1f) << 4; 23317a1594eSVivien Didelot op |= (src_port & 0xf); 23417a1594eSVivien Didelot 23567d1ea8eSVivien Didelot err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_ADDR, op); 23617a1594eSVivien Didelot if (err) 23717a1594eSVivien Didelot return err; 23817a1594eSVivien Didelot 23917a1594eSVivien Didelot return mv88e6xxx_g2_pvt_op_wait(chip); 24017a1594eSVivien Didelot } 24117a1594eSVivien Didelot 24217a1594eSVivien Didelot int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev, 24317a1594eSVivien Didelot int src_port, u16 data) 24417a1594eSVivien Didelot { 24517a1594eSVivien Didelot int err; 24617a1594eSVivien Didelot 24717a1594eSVivien Didelot err = mv88e6xxx_g2_pvt_op_wait(chip); 24817a1594eSVivien Didelot if (err) 24917a1594eSVivien Didelot return err; 25017a1594eSVivien Didelot 25167d1ea8eSVivien Didelot err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_DATA, data); 25217a1594eSVivien Didelot if (err) 25317a1594eSVivien Didelot return err; 25417a1594eSVivien Didelot 25517a1594eSVivien Didelot return mv88e6xxx_g2_pvt_op(chip, src_dev, src_port, 25667d1ea8eSVivien Didelot MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN); 25717a1594eSVivien Didelot } 25817a1594eSVivien Didelot 259ec561276SVivien Didelot /* Offset 0x0D: Switch MAC/WoL/WoF register */ 260ec561276SVivien Didelot 261ec561276SVivien Didelot static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip, 262ec561276SVivien Didelot unsigned int pointer, u8 data) 263ec561276SVivien Didelot { 264ec561276SVivien Didelot u16 val = (pointer << 8) | data; 265ec561276SVivien Didelot 2662ad4da77SVivien Didelot return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MAC, 2672ad4da77SVivien Didelot MV88E6XXX_G2_SWITCH_MAC_UPDATE | val); 268ec561276SVivien Didelot } 269ec561276SVivien Didelot 270ec561276SVivien Didelot int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 271ec561276SVivien Didelot { 272ec561276SVivien Didelot int i, err; 273ec561276SVivien Didelot 274ec561276SVivien Didelot for (i = 0; i < 6; i++) { 275ec561276SVivien Didelot err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]); 276ec561276SVivien Didelot if (err) 277ec561276SVivien Didelot break; 278ec561276SVivien Didelot } 279ec561276SVivien Didelot 280ec561276SVivien Didelot return err; 281ec561276SVivien Didelot } 282ec561276SVivien Didelot 283ec561276SVivien Didelot /* Offset 0x0F: Priority Override Table */ 284ec561276SVivien Didelot 285ec561276SVivien Didelot static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer, 286ec561276SVivien Didelot u8 data) 287ec561276SVivien Didelot { 288ec561276SVivien Didelot u16 val = (pointer << 8) | (data & 0x7); 289ec561276SVivien Didelot 2902ad4da77SVivien Didelot return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PRIO_OVERRIDE, 2912ad4da77SVivien Didelot MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE | val); 292ec561276SVivien Didelot } 293ec561276SVivien Didelot 2949e907d73SVivien Didelot int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip) 295ec561276SVivien Didelot { 296ec561276SVivien Didelot int i, err; 297ec561276SVivien Didelot 298ec561276SVivien Didelot /* Clear all sixteen possible Priority Override entries */ 299ec561276SVivien Didelot for (i = 0; i < 16; i++) { 300ec561276SVivien Didelot err = mv88e6xxx_g2_pot_write(chip, i, 0); 301ec561276SVivien Didelot if (err) 302ec561276SVivien Didelot break; 303ec561276SVivien Didelot } 304ec561276SVivien Didelot 305ec561276SVivien Didelot return err; 306ec561276SVivien Didelot } 307ec561276SVivien Didelot 308ec561276SVivien Didelot /* Offset 0x14: EEPROM Command 30998fc3c6fSVivien Didelot * Offset 0x15: EEPROM Data (for 16-bit data access) 31098fc3c6fSVivien Didelot * Offset 0x15: EEPROM Addr (for 8-bit data access) 311ec561276SVivien Didelot */ 312ec561276SVivien Didelot 313ec561276SVivien Didelot static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip) 314ec561276SVivien Didelot { 31519fb7f69SVivien Didelot int bit = __bf_shf(MV88E6XXX_G2_EEPROM_CMD_BUSY); 31619fb7f69SVivien Didelot int err; 31719fb7f69SVivien Didelot 31819fb7f69SVivien Didelot err = mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_EEPROM_CMD, bit, 0); 31919fb7f69SVivien Didelot if (err) 32019fb7f69SVivien Didelot return err; 32119fb7f69SVivien Didelot 32219fb7f69SVivien Didelot bit = __bf_shf(MV88E6XXX_G2_EEPROM_CMD_RUNNING); 32319fb7f69SVivien Didelot 32419fb7f69SVivien Didelot return mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_EEPROM_CMD, bit, 0); 325ec561276SVivien Didelot } 326ec561276SVivien Didelot 327ec561276SVivien Didelot static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd) 328ec561276SVivien Didelot { 329ec561276SVivien Didelot int err; 330ec561276SVivien Didelot 3317fc8c9d5SVivien Didelot err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_EEPROM_CMD, 3327fc8c9d5SVivien Didelot MV88E6XXX_G2_EEPROM_CMD_BUSY | cmd); 333ec561276SVivien Didelot if (err) 334ec561276SVivien Didelot return err; 335ec561276SVivien Didelot 336ec561276SVivien Didelot return mv88e6xxx_g2_eeprom_wait(chip); 337ec561276SVivien Didelot } 338ec561276SVivien Didelot 33998fc3c6fSVivien Didelot static int mv88e6xxx_g2_eeprom_read8(struct mv88e6xxx_chip *chip, 34098fc3c6fSVivien Didelot u16 addr, u8 *data) 34198fc3c6fSVivien Didelot { 3427fc8c9d5SVivien Didelot u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_READ; 34398fc3c6fSVivien Didelot int err; 34498fc3c6fSVivien Didelot 34598fc3c6fSVivien Didelot err = mv88e6xxx_g2_eeprom_wait(chip); 34698fc3c6fSVivien Didelot if (err) 34798fc3c6fSVivien Didelot return err; 34898fc3c6fSVivien Didelot 3497fc8c9d5SVivien Didelot err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr); 35098fc3c6fSVivien Didelot if (err) 35198fc3c6fSVivien Didelot return err; 35298fc3c6fSVivien Didelot 35398fc3c6fSVivien Didelot err = mv88e6xxx_g2_eeprom_cmd(chip, cmd); 35498fc3c6fSVivien Didelot if (err) 35598fc3c6fSVivien Didelot return err; 35698fc3c6fSVivien Didelot 3577fc8c9d5SVivien Didelot err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &cmd); 35898fc3c6fSVivien Didelot if (err) 35998fc3c6fSVivien Didelot return err; 36098fc3c6fSVivien Didelot 36198fc3c6fSVivien Didelot *data = cmd & 0xff; 36298fc3c6fSVivien Didelot 36398fc3c6fSVivien Didelot return 0; 36498fc3c6fSVivien Didelot } 36598fc3c6fSVivien Didelot 36698fc3c6fSVivien Didelot static int mv88e6xxx_g2_eeprom_write8(struct mv88e6xxx_chip *chip, 36798fc3c6fSVivien Didelot u16 addr, u8 data) 36898fc3c6fSVivien Didelot { 3697fc8c9d5SVivien Didelot u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_WRITE | 3707fc8c9d5SVivien Didelot MV88E6XXX_G2_EEPROM_CMD_WRITE_EN; 37198fc3c6fSVivien Didelot int err; 37298fc3c6fSVivien Didelot 37398fc3c6fSVivien Didelot err = mv88e6xxx_g2_eeprom_wait(chip); 37498fc3c6fSVivien Didelot if (err) 37598fc3c6fSVivien Didelot return err; 37698fc3c6fSVivien Didelot 3777fc8c9d5SVivien Didelot err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr); 37898fc3c6fSVivien Didelot if (err) 37998fc3c6fSVivien Didelot return err; 38098fc3c6fSVivien Didelot 38198fc3c6fSVivien Didelot return mv88e6xxx_g2_eeprom_cmd(chip, cmd | data); 38298fc3c6fSVivien Didelot } 38398fc3c6fSVivien Didelot 384ec561276SVivien Didelot static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip, 385ec561276SVivien Didelot u8 addr, u16 *data) 386ec561276SVivien Didelot { 3877fc8c9d5SVivien Didelot u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_READ | addr; 388ec561276SVivien Didelot int err; 389ec561276SVivien Didelot 390ec561276SVivien Didelot err = mv88e6xxx_g2_eeprom_wait(chip); 391ec561276SVivien Didelot if (err) 392ec561276SVivien Didelot return err; 393ec561276SVivien Didelot 394ec561276SVivien Didelot err = mv88e6xxx_g2_eeprom_cmd(chip, cmd); 395ec561276SVivien Didelot if (err) 396ec561276SVivien Didelot return err; 397ec561276SVivien Didelot 3987fc8c9d5SVivien Didelot return mv88e6xxx_g2_read(chip, MV88E6352_G2_EEPROM_DATA, data); 399ec561276SVivien Didelot } 400ec561276SVivien Didelot 401ec561276SVivien Didelot static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip, 402ec561276SVivien Didelot u8 addr, u16 data) 403ec561276SVivien Didelot { 4047fc8c9d5SVivien Didelot u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_WRITE | addr; 405ec561276SVivien Didelot int err; 406ec561276SVivien Didelot 407ec561276SVivien Didelot err = mv88e6xxx_g2_eeprom_wait(chip); 408ec561276SVivien Didelot if (err) 409ec561276SVivien Didelot return err; 410ec561276SVivien Didelot 4117fc8c9d5SVivien Didelot err = mv88e6xxx_g2_write(chip, MV88E6352_G2_EEPROM_DATA, data); 412ec561276SVivien Didelot if (err) 413ec561276SVivien Didelot return err; 414ec561276SVivien Didelot 415ec561276SVivien Didelot return mv88e6xxx_g2_eeprom_cmd(chip, cmd); 416ec561276SVivien Didelot } 417ec561276SVivien Didelot 41898fc3c6fSVivien Didelot int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, 41998fc3c6fSVivien Didelot struct ethtool_eeprom *eeprom, u8 *data) 42098fc3c6fSVivien Didelot { 42198fc3c6fSVivien Didelot unsigned int offset = eeprom->offset; 42298fc3c6fSVivien Didelot unsigned int len = eeprom->len; 42398fc3c6fSVivien Didelot int err; 42498fc3c6fSVivien Didelot 42598fc3c6fSVivien Didelot eeprom->len = 0; 42698fc3c6fSVivien Didelot 42798fc3c6fSVivien Didelot while (len) { 42898fc3c6fSVivien Didelot err = mv88e6xxx_g2_eeprom_read8(chip, offset, data); 42998fc3c6fSVivien Didelot if (err) 43098fc3c6fSVivien Didelot return err; 43198fc3c6fSVivien Didelot 43298fc3c6fSVivien Didelot eeprom->len++; 43398fc3c6fSVivien Didelot offset++; 43498fc3c6fSVivien Didelot data++; 43598fc3c6fSVivien Didelot len--; 43698fc3c6fSVivien Didelot } 43798fc3c6fSVivien Didelot 43898fc3c6fSVivien Didelot return 0; 43998fc3c6fSVivien Didelot } 44098fc3c6fSVivien Didelot 44198fc3c6fSVivien Didelot int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, 44298fc3c6fSVivien Didelot struct ethtool_eeprom *eeprom, u8 *data) 44398fc3c6fSVivien Didelot { 44498fc3c6fSVivien Didelot unsigned int offset = eeprom->offset; 44598fc3c6fSVivien Didelot unsigned int len = eeprom->len; 44698fc3c6fSVivien Didelot int err; 44798fc3c6fSVivien Didelot 44898fc3c6fSVivien Didelot eeprom->len = 0; 44998fc3c6fSVivien Didelot 45098fc3c6fSVivien Didelot while (len) { 45198fc3c6fSVivien Didelot err = mv88e6xxx_g2_eeprom_write8(chip, offset, *data); 45298fc3c6fSVivien Didelot if (err) 45398fc3c6fSVivien Didelot return err; 45498fc3c6fSVivien Didelot 45598fc3c6fSVivien Didelot eeprom->len++; 45698fc3c6fSVivien Didelot offset++; 45798fc3c6fSVivien Didelot data++; 45898fc3c6fSVivien Didelot len--; 45998fc3c6fSVivien Didelot } 46098fc3c6fSVivien Didelot 46198fc3c6fSVivien Didelot return 0; 46298fc3c6fSVivien Didelot } 46398fc3c6fSVivien Didelot 464ec561276SVivien Didelot int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, 465ec561276SVivien Didelot struct ethtool_eeprom *eeprom, u8 *data) 466ec561276SVivien Didelot { 467ec561276SVivien Didelot unsigned int offset = eeprom->offset; 468ec561276SVivien Didelot unsigned int len = eeprom->len; 469ec561276SVivien Didelot u16 val; 470ec561276SVivien Didelot int err; 471ec561276SVivien Didelot 472ec561276SVivien Didelot eeprom->len = 0; 473ec561276SVivien Didelot 474ec561276SVivien Didelot if (offset & 1) { 475ec561276SVivien Didelot err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 476ec561276SVivien Didelot if (err) 477ec561276SVivien Didelot return err; 478ec561276SVivien Didelot 479ec561276SVivien Didelot *data++ = (val >> 8) & 0xff; 480ec561276SVivien Didelot 481ec561276SVivien Didelot offset++; 482ec561276SVivien Didelot len--; 483ec561276SVivien Didelot eeprom->len++; 484ec561276SVivien Didelot } 485ec561276SVivien Didelot 486ec561276SVivien Didelot while (len >= 2) { 487ec561276SVivien Didelot err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 488ec561276SVivien Didelot if (err) 489ec561276SVivien Didelot return err; 490ec561276SVivien Didelot 491ec561276SVivien Didelot *data++ = val & 0xff; 492ec561276SVivien Didelot *data++ = (val >> 8) & 0xff; 493ec561276SVivien Didelot 494ec561276SVivien Didelot offset += 2; 495ec561276SVivien Didelot len -= 2; 496ec561276SVivien Didelot eeprom->len += 2; 497ec561276SVivien Didelot } 498ec561276SVivien Didelot 499ec561276SVivien Didelot if (len) { 500ec561276SVivien Didelot err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 501ec561276SVivien Didelot if (err) 502ec561276SVivien Didelot return err; 503ec561276SVivien Didelot 504ec561276SVivien Didelot *data++ = val & 0xff; 505ec561276SVivien Didelot 506ec561276SVivien Didelot offset++; 507ec561276SVivien Didelot len--; 508ec561276SVivien Didelot eeprom->len++; 509ec561276SVivien Didelot } 510ec561276SVivien Didelot 511ec561276SVivien Didelot return 0; 512ec561276SVivien Didelot } 513ec561276SVivien Didelot 514ec561276SVivien Didelot int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, 515ec561276SVivien Didelot struct ethtool_eeprom *eeprom, u8 *data) 516ec561276SVivien Didelot { 517ec561276SVivien Didelot unsigned int offset = eeprom->offset; 518ec561276SVivien Didelot unsigned int len = eeprom->len; 519ec561276SVivien Didelot u16 val; 520ec561276SVivien Didelot int err; 521ec561276SVivien Didelot 522ec561276SVivien Didelot /* Ensure the RO WriteEn bit is set */ 5237fc8c9d5SVivien Didelot err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &val); 524ec561276SVivien Didelot if (err) 525ec561276SVivien Didelot return err; 526ec561276SVivien Didelot 5277fc8c9d5SVivien Didelot if (!(val & MV88E6XXX_G2_EEPROM_CMD_WRITE_EN)) 528ec561276SVivien Didelot return -EROFS; 529ec561276SVivien Didelot 530ec561276SVivien Didelot eeprom->len = 0; 531ec561276SVivien Didelot 532ec561276SVivien Didelot if (offset & 1) { 533ec561276SVivien Didelot err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 534ec561276SVivien Didelot if (err) 535ec561276SVivien Didelot return err; 536ec561276SVivien Didelot 537ec561276SVivien Didelot val = (*data++ << 8) | (val & 0xff); 538ec561276SVivien Didelot 539ec561276SVivien Didelot err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); 540ec561276SVivien Didelot if (err) 541ec561276SVivien Didelot return err; 542ec561276SVivien Didelot 543ec561276SVivien Didelot offset++; 544ec561276SVivien Didelot len--; 545ec561276SVivien Didelot eeprom->len++; 546ec561276SVivien Didelot } 547ec561276SVivien Didelot 548ec561276SVivien Didelot while (len >= 2) { 549ec561276SVivien Didelot val = *data++; 550ec561276SVivien Didelot val |= *data++ << 8; 551ec561276SVivien Didelot 552ec561276SVivien Didelot err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); 553ec561276SVivien Didelot if (err) 554ec561276SVivien Didelot return err; 555ec561276SVivien Didelot 556ec561276SVivien Didelot offset += 2; 557ec561276SVivien Didelot len -= 2; 558ec561276SVivien Didelot eeprom->len += 2; 559ec561276SVivien Didelot } 560ec561276SVivien Didelot 561ec561276SVivien Didelot if (len) { 562ec561276SVivien Didelot err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val); 563ec561276SVivien Didelot if (err) 564ec561276SVivien Didelot return err; 565ec561276SVivien Didelot 566ec561276SVivien Didelot val = (val & 0xff00) | *data++; 567ec561276SVivien Didelot 568ec561276SVivien Didelot err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val); 569ec561276SVivien Didelot if (err) 570ec561276SVivien Didelot return err; 571ec561276SVivien Didelot 572ec561276SVivien Didelot offset++; 573ec561276SVivien Didelot len--; 574ec561276SVivien Didelot eeprom->len++; 575ec561276SVivien Didelot } 576ec561276SVivien Didelot 577ec561276SVivien Didelot return 0; 578ec561276SVivien Didelot } 579ec561276SVivien Didelot 580ec561276SVivien Didelot /* Offset 0x18: SMI PHY Command Register 581ec561276SVivien Didelot * Offset 0x19: SMI PHY Data Register 582ec561276SVivien Didelot */ 583ec561276SVivien Didelot 584ec561276SVivien Didelot static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip) 585ec561276SVivien Didelot { 58619fb7f69SVivien Didelot int bit = __bf_shf(MV88E6XXX_G2_SMI_PHY_CMD_BUSY); 58719fb7f69SVivien Didelot 58819fb7f69SVivien Didelot return mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_SMI_PHY_CMD, bit, 0); 589ec561276SVivien Didelot } 590ec561276SVivien Didelot 591ec561276SVivien Didelot static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd) 592ec561276SVivien Didelot { 593ec561276SVivien Didelot int err; 594ec561276SVivien Didelot 595e289ef0dSVivien Didelot err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_CMD, 596e289ef0dSVivien Didelot MV88E6XXX_G2_SMI_PHY_CMD_BUSY | cmd); 597ec561276SVivien Didelot if (err) 598ec561276SVivien Didelot return err; 599ec561276SVivien Didelot 600ec561276SVivien Didelot return mv88e6xxx_g2_smi_phy_wait(chip); 601ec561276SVivien Didelot } 602ec561276SVivien Didelot 603e289ef0dSVivien Didelot static int mv88e6xxx_g2_smi_phy_access(struct mv88e6xxx_chip *chip, 604e289ef0dSVivien Didelot bool external, bool c45, u16 op, int dev, 605e289ef0dSVivien Didelot int reg) 606ec561276SVivien Didelot { 607e289ef0dSVivien Didelot u16 cmd = op; 608ec561276SVivien Didelot 609cf3e80dfSAndrew Lunn if (external) 610e289ef0dSVivien Didelot cmd |= MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL; 611e289ef0dSVivien Didelot else 612e289ef0dSVivien Didelot cmd |= MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL; /* empty mask */ 613cf3e80dfSAndrew Lunn 614e289ef0dSVivien Didelot if (c45) 615e289ef0dSVivien Didelot cmd |= MV88E6XXX_G2_SMI_PHY_CMD_MODE_45; /* empty mask */ 616e289ef0dSVivien Didelot else 617e289ef0dSVivien Didelot cmd |= MV88E6XXX_G2_SMI_PHY_CMD_MODE_22; 618cf3e80dfSAndrew Lunn 619e289ef0dSVivien Didelot dev <<= __bf_shf(MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK); 620e289ef0dSVivien Didelot cmd |= dev & MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK; 621e289ef0dSVivien Didelot cmd |= reg & MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK; 622cf3e80dfSAndrew Lunn 623cf3e80dfSAndrew Lunn return mv88e6xxx_g2_smi_phy_cmd(chip, cmd); 624cf3e80dfSAndrew Lunn } 625cf3e80dfSAndrew Lunn 626e289ef0dSVivien Didelot static int mv88e6xxx_g2_smi_phy_access_c22(struct mv88e6xxx_chip *chip, 627e289ef0dSVivien Didelot bool external, u16 op, int dev, 628e289ef0dSVivien Didelot int reg) 629cf3e80dfSAndrew Lunn { 630e289ef0dSVivien Didelot return mv88e6xxx_g2_smi_phy_access(chip, external, false, op, dev, reg); 631cf3e80dfSAndrew Lunn } 632cf3e80dfSAndrew Lunn 633e289ef0dSVivien Didelot /* IEEE 802.3 Clause 22 Read Data Register */ 634e289ef0dSVivien Didelot static int mv88e6xxx_g2_smi_phy_read_data_c22(struct mv88e6xxx_chip *chip, 635e289ef0dSVivien Didelot bool external, int dev, int reg, 636e289ef0dSVivien Didelot u16 *data) 637cf3e80dfSAndrew Lunn { 638e289ef0dSVivien Didelot u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA; 639cf3e80dfSAndrew Lunn int err; 640cf3e80dfSAndrew Lunn 641ec561276SVivien Didelot err = mv88e6xxx_g2_smi_phy_wait(chip); 642ec561276SVivien Didelot if (err) 643ec561276SVivien Didelot return err; 644ec561276SVivien Didelot 645e289ef0dSVivien Didelot err = mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg); 646ec561276SVivien Didelot if (err) 647ec561276SVivien Didelot return err; 648ec561276SVivien Didelot 649e289ef0dSVivien Didelot return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data); 650ec561276SVivien Didelot } 651ec561276SVivien Didelot 652e289ef0dSVivien Didelot /* IEEE 802.3 Clause 22 Write Data Register */ 653e289ef0dSVivien Didelot static int mv88e6xxx_g2_smi_phy_write_data_c22(struct mv88e6xxx_chip *chip, 654e289ef0dSVivien Didelot bool external, int dev, int reg, 655e289ef0dSVivien Didelot u16 data) 656e289ef0dSVivien Didelot { 657e289ef0dSVivien Didelot u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA; 658e289ef0dSVivien Didelot int err; 659e289ef0dSVivien Didelot 660e289ef0dSVivien Didelot err = mv88e6xxx_g2_smi_phy_wait(chip); 661e289ef0dSVivien Didelot if (err) 662e289ef0dSVivien Didelot return err; 663e289ef0dSVivien Didelot 664e289ef0dSVivien Didelot err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data); 665e289ef0dSVivien Didelot if (err) 666e289ef0dSVivien Didelot return err; 667e289ef0dSVivien Didelot 668e289ef0dSVivien Didelot return mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg); 669e289ef0dSVivien Didelot } 670e289ef0dSVivien Didelot 671e289ef0dSVivien Didelot static int mv88e6xxx_g2_smi_phy_access_c45(struct mv88e6xxx_chip *chip, 672e289ef0dSVivien Didelot bool external, u16 op, int port, 673e289ef0dSVivien Didelot int dev) 674e289ef0dSVivien Didelot { 675e289ef0dSVivien Didelot return mv88e6xxx_g2_smi_phy_access(chip, external, true, op, port, dev); 676e289ef0dSVivien Didelot } 677e289ef0dSVivien Didelot 678e289ef0dSVivien Didelot /* IEEE 802.3 Clause 45 Write Address Register */ 679e289ef0dSVivien Didelot static int mv88e6xxx_g2_smi_phy_write_addr_c45(struct mv88e6xxx_chip *chip, 680e289ef0dSVivien Didelot bool external, int port, int dev, 681e289ef0dSVivien Didelot int addr) 682e289ef0dSVivien Didelot { 683e289ef0dSVivien Didelot u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR; 684e289ef0dSVivien Didelot int err; 685e289ef0dSVivien Didelot 686e289ef0dSVivien Didelot err = mv88e6xxx_g2_smi_phy_wait(chip); 687e289ef0dSVivien Didelot if (err) 688e289ef0dSVivien Didelot return err; 689e289ef0dSVivien Didelot 690e289ef0dSVivien Didelot err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, addr); 691e289ef0dSVivien Didelot if (err) 692e289ef0dSVivien Didelot return err; 693e289ef0dSVivien Didelot 694e289ef0dSVivien Didelot return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev); 695e289ef0dSVivien Didelot } 696e289ef0dSVivien Didelot 697e289ef0dSVivien Didelot /* IEEE 802.3 Clause 45 Read Data Register */ 698e289ef0dSVivien Didelot static int mv88e6xxx_g2_smi_phy_read_data_c45(struct mv88e6xxx_chip *chip, 699e289ef0dSVivien Didelot bool external, int port, int dev, 700e289ef0dSVivien Didelot u16 *data) 701e289ef0dSVivien Didelot { 702e289ef0dSVivien Didelot u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA; 703e289ef0dSVivien Didelot int err; 704e289ef0dSVivien Didelot 705e289ef0dSVivien Didelot err = mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev); 706e289ef0dSVivien Didelot if (err) 707e289ef0dSVivien Didelot return err; 708e289ef0dSVivien Didelot 709e289ef0dSVivien Didelot return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data); 710e289ef0dSVivien Didelot } 711e289ef0dSVivien Didelot 712e289ef0dSVivien Didelot static int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip, 713e289ef0dSVivien Didelot bool external, int port, int reg, 714e289ef0dSVivien Didelot u16 *data) 715e289ef0dSVivien Didelot { 716e289ef0dSVivien Didelot int dev = (reg >> 16) & 0x1f; 717e289ef0dSVivien Didelot int addr = reg & 0xffff; 718e289ef0dSVivien Didelot int err; 719e289ef0dSVivien Didelot 720e289ef0dSVivien Didelot err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev, 721e289ef0dSVivien Didelot addr); 722e289ef0dSVivien Didelot if (err) 723e289ef0dSVivien Didelot return err; 724e289ef0dSVivien Didelot 725e289ef0dSVivien Didelot return mv88e6xxx_g2_smi_phy_read_data_c45(chip, external, port, dev, 726e289ef0dSVivien Didelot data); 727e289ef0dSVivien Didelot } 728e289ef0dSVivien Didelot 729e289ef0dSVivien Didelot /* IEEE 802.3 Clause 45 Write Data Register */ 730e289ef0dSVivien Didelot static int mv88e6xxx_g2_smi_phy_write_data_c45(struct mv88e6xxx_chip *chip, 731e289ef0dSVivien Didelot bool external, int port, int dev, 732e289ef0dSVivien Didelot u16 data) 733e289ef0dSVivien Didelot { 734e289ef0dSVivien Didelot u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA; 735e289ef0dSVivien Didelot int err; 736e289ef0dSVivien Didelot 737e289ef0dSVivien Didelot err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data); 738e289ef0dSVivien Didelot if (err) 739e289ef0dSVivien Didelot return err; 740e289ef0dSVivien Didelot 741e289ef0dSVivien Didelot return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev); 742e289ef0dSVivien Didelot } 743e289ef0dSVivien Didelot 744e289ef0dSVivien Didelot static int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip, 745e289ef0dSVivien Didelot bool external, int port, int reg, 746e289ef0dSVivien Didelot u16 data) 747e289ef0dSVivien Didelot { 748e289ef0dSVivien Didelot int dev = (reg >> 16) & 0x1f; 749e289ef0dSVivien Didelot int addr = reg & 0xffff; 750e289ef0dSVivien Didelot int err; 751e289ef0dSVivien Didelot 752e289ef0dSVivien Didelot err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev, 753e289ef0dSVivien Didelot addr); 754e289ef0dSVivien Didelot if (err) 755e289ef0dSVivien Didelot return err; 756e289ef0dSVivien Didelot 757e289ef0dSVivien Didelot return mv88e6xxx_g2_smi_phy_write_data_c45(chip, external, port, dev, 758e289ef0dSVivien Didelot data); 759e289ef0dSVivien Didelot } 760e289ef0dSVivien Didelot 761e289ef0dSVivien Didelot int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus, 762cf3e80dfSAndrew Lunn int addr, int reg, u16 *val) 763cf3e80dfSAndrew Lunn { 764cf3e80dfSAndrew Lunn struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 765cf3e80dfSAndrew Lunn bool external = mdio_bus->external; 766cf3e80dfSAndrew Lunn 767cf3e80dfSAndrew Lunn if (reg & MII_ADDR_C45) 768e289ef0dSVivien Didelot return mv88e6xxx_g2_smi_phy_read_c45(chip, external, addr, reg, 769e289ef0dSVivien Didelot val); 770e289ef0dSVivien Didelot 771e289ef0dSVivien Didelot return mv88e6xxx_g2_smi_phy_read_data_c22(chip, external, addr, reg, 772e289ef0dSVivien Didelot val); 773cf3e80dfSAndrew Lunn } 774cf3e80dfSAndrew Lunn 775e289ef0dSVivien Didelot int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus, 776cf3e80dfSAndrew Lunn int addr, int reg, u16 val) 777cf3e80dfSAndrew Lunn { 778cf3e80dfSAndrew Lunn struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 779cf3e80dfSAndrew Lunn bool external = mdio_bus->external; 780cf3e80dfSAndrew Lunn 781cf3e80dfSAndrew Lunn if (reg & MII_ADDR_C45) 782e289ef0dSVivien Didelot return mv88e6xxx_g2_smi_phy_write_c45(chip, external, addr, reg, 783e289ef0dSVivien Didelot val); 784cf3e80dfSAndrew Lunn 785e289ef0dSVivien Didelot return mv88e6xxx_g2_smi_phy_write_data_c22(chip, external, addr, reg, 786e289ef0dSVivien Didelot val); 787cf3e80dfSAndrew Lunn } 788cf3e80dfSAndrew Lunn 789a73ccd61SBrandon Streiff /* Offset 0x1B: Watchdog Control */ 790fcd25166SAndrew Lunn static int mv88e6097_watchdog_action(struct mv88e6xxx_chip *chip, int irq) 791fcd25166SAndrew Lunn { 792fcd25166SAndrew Lunn u16 reg; 793fcd25166SAndrew Lunn 7943b19df73SVivien Didelot mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®); 795fcd25166SAndrew Lunn 796fcd25166SAndrew Lunn dev_info(chip->dev, "Watchdog event: 0x%04x", reg); 797fcd25166SAndrew Lunn 798fcd25166SAndrew Lunn return IRQ_HANDLED; 799fcd25166SAndrew Lunn } 800fcd25166SAndrew Lunn 801fcd25166SAndrew Lunn static void mv88e6097_watchdog_free(struct mv88e6xxx_chip *chip) 802fcd25166SAndrew Lunn { 803fcd25166SAndrew Lunn u16 reg; 804fcd25166SAndrew Lunn 8053b19df73SVivien Didelot mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®); 806fcd25166SAndrew Lunn 8073b19df73SVivien Didelot reg &= ~(MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE | 8083b19df73SVivien Didelot MV88E6352_G2_WDOG_CTL_QC_ENABLE); 809fcd25166SAndrew Lunn 8103b19df73SVivien Didelot mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL, reg); 811fcd25166SAndrew Lunn } 812fcd25166SAndrew Lunn 813fcd25166SAndrew Lunn static int mv88e6097_watchdog_setup(struct mv88e6xxx_chip *chip) 814fcd25166SAndrew Lunn { 8153b19df73SVivien Didelot return mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL, 8163b19df73SVivien Didelot MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE | 8173b19df73SVivien Didelot MV88E6352_G2_WDOG_CTL_QC_ENABLE | 8183b19df73SVivien Didelot MV88E6352_G2_WDOG_CTL_SWRESET); 819fcd25166SAndrew Lunn } 820fcd25166SAndrew Lunn 821fcd25166SAndrew Lunn const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = { 822fcd25166SAndrew Lunn .irq_action = mv88e6097_watchdog_action, 823fcd25166SAndrew Lunn .irq_setup = mv88e6097_watchdog_setup, 824fcd25166SAndrew Lunn .irq_free = mv88e6097_watchdog_free, 825fcd25166SAndrew Lunn }; 826fcd25166SAndrew Lunn 827855cdfdeSRasmus Villemoes static void mv88e6250_watchdog_free(struct mv88e6xxx_chip *chip) 828855cdfdeSRasmus Villemoes { 829855cdfdeSRasmus Villemoes u16 reg; 830855cdfdeSRasmus Villemoes 831855cdfdeSRasmus Villemoes mv88e6xxx_g2_read(chip, MV88E6250_G2_WDOG_CTL, ®); 832855cdfdeSRasmus Villemoes 833855cdfdeSRasmus Villemoes reg &= ~(MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE | 834855cdfdeSRasmus Villemoes MV88E6250_G2_WDOG_CTL_QC_ENABLE); 835855cdfdeSRasmus Villemoes 836855cdfdeSRasmus Villemoes mv88e6xxx_g2_write(chip, MV88E6250_G2_WDOG_CTL, reg); 837855cdfdeSRasmus Villemoes } 838855cdfdeSRasmus Villemoes 839855cdfdeSRasmus Villemoes static int mv88e6250_watchdog_setup(struct mv88e6xxx_chip *chip) 840855cdfdeSRasmus Villemoes { 841855cdfdeSRasmus Villemoes return mv88e6xxx_g2_write(chip, MV88E6250_G2_WDOG_CTL, 842855cdfdeSRasmus Villemoes MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE | 843855cdfdeSRasmus Villemoes MV88E6250_G2_WDOG_CTL_QC_ENABLE | 844855cdfdeSRasmus Villemoes MV88E6250_G2_WDOG_CTL_SWRESET); 845855cdfdeSRasmus Villemoes } 846855cdfdeSRasmus Villemoes 847855cdfdeSRasmus Villemoes const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops = { 848855cdfdeSRasmus Villemoes .irq_action = mv88e6097_watchdog_action, 849855cdfdeSRasmus Villemoes .irq_setup = mv88e6250_watchdog_setup, 850855cdfdeSRasmus Villemoes .irq_free = mv88e6250_watchdog_free, 851855cdfdeSRasmus Villemoes }; 852855cdfdeSRasmus Villemoes 85361303736SAndrew Lunn static int mv88e6390_watchdog_setup(struct mv88e6xxx_chip *chip) 85461303736SAndrew Lunn { 8552ad4da77SVivien Didelot return mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL, 8562ad4da77SVivien Didelot MV88E6390_G2_WDOG_CTL_UPDATE | 8573b19df73SVivien Didelot MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE | 8583b19df73SVivien Didelot MV88E6390_G2_WDOG_CTL_CUT_THROUGH | 8593b19df73SVivien Didelot MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER | 8603b19df73SVivien Didelot MV88E6390_G2_WDOG_CTL_EGRESS | 8613b19df73SVivien Didelot MV88E6390_G2_WDOG_CTL_FORCE_IRQ); 86261303736SAndrew Lunn } 86361303736SAndrew Lunn 86461303736SAndrew Lunn static int mv88e6390_watchdog_action(struct mv88e6xxx_chip *chip, int irq) 86561303736SAndrew Lunn { 86661303736SAndrew Lunn int err; 86761303736SAndrew Lunn u16 reg; 86861303736SAndrew Lunn 8693b19df73SVivien Didelot mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL, 8703b19df73SVivien Didelot MV88E6390_G2_WDOG_CTL_PTR_EVENT); 8713b19df73SVivien Didelot err = mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®); 87261303736SAndrew Lunn 87361303736SAndrew Lunn dev_info(chip->dev, "Watchdog event: 0x%04x", 8743b19df73SVivien Didelot reg & MV88E6390_G2_WDOG_CTL_DATA_MASK); 87561303736SAndrew Lunn 8763b19df73SVivien Didelot mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL, 8773b19df73SVivien Didelot MV88E6390_G2_WDOG_CTL_PTR_HISTORY); 8783b19df73SVivien Didelot err = mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®); 87961303736SAndrew Lunn 88061303736SAndrew Lunn dev_info(chip->dev, "Watchdog history: 0x%04x", 8813b19df73SVivien Didelot reg & MV88E6390_G2_WDOG_CTL_DATA_MASK); 88261303736SAndrew Lunn 88361303736SAndrew Lunn /* Trigger a software reset to try to recover the switch */ 88461303736SAndrew Lunn if (chip->info->ops->reset) 88561303736SAndrew Lunn chip->info->ops->reset(chip); 88661303736SAndrew Lunn 88761303736SAndrew Lunn mv88e6390_watchdog_setup(chip); 88861303736SAndrew Lunn 88961303736SAndrew Lunn return IRQ_HANDLED; 89061303736SAndrew Lunn } 89161303736SAndrew Lunn 89261303736SAndrew Lunn static void mv88e6390_watchdog_free(struct mv88e6xxx_chip *chip) 89361303736SAndrew Lunn { 8942ad4da77SVivien Didelot mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL, 8952ad4da77SVivien Didelot MV88E6390_G2_WDOG_CTL_UPDATE | 8963b19df73SVivien Didelot MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE); 89761303736SAndrew Lunn } 89861303736SAndrew Lunn 89961303736SAndrew Lunn const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = { 90061303736SAndrew Lunn .irq_action = mv88e6390_watchdog_action, 90161303736SAndrew Lunn .irq_setup = mv88e6390_watchdog_setup, 90261303736SAndrew Lunn .irq_free = mv88e6390_watchdog_free, 90361303736SAndrew Lunn }; 90461303736SAndrew Lunn 905fcd25166SAndrew Lunn static irqreturn_t mv88e6xxx_g2_watchdog_thread_fn(int irq, void *dev_id) 906fcd25166SAndrew Lunn { 907fcd25166SAndrew Lunn struct mv88e6xxx_chip *chip = dev_id; 908fcd25166SAndrew Lunn irqreturn_t ret = IRQ_NONE; 909fcd25166SAndrew Lunn 910c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip); 911fcd25166SAndrew Lunn if (chip->info->ops->watchdog_ops->irq_action) 912fcd25166SAndrew Lunn ret = chip->info->ops->watchdog_ops->irq_action(chip, irq); 913c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip); 914fcd25166SAndrew Lunn 915fcd25166SAndrew Lunn return ret; 916fcd25166SAndrew Lunn } 917fcd25166SAndrew Lunn 918fcd25166SAndrew Lunn static void mv88e6xxx_g2_watchdog_free(struct mv88e6xxx_chip *chip) 919fcd25166SAndrew Lunn { 920c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip); 921fcd25166SAndrew Lunn if (chip->info->ops->watchdog_ops->irq_free) 922fcd25166SAndrew Lunn chip->info->ops->watchdog_ops->irq_free(chip); 923c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip); 924fcd25166SAndrew Lunn 925fcd25166SAndrew Lunn free_irq(chip->watchdog_irq, chip); 926fcd25166SAndrew Lunn irq_dispose_mapping(chip->watchdog_irq); 927fcd25166SAndrew Lunn } 928fcd25166SAndrew Lunn 929fcd25166SAndrew Lunn static int mv88e6xxx_g2_watchdog_setup(struct mv88e6xxx_chip *chip) 930fcd25166SAndrew Lunn { 931fcd25166SAndrew Lunn int err; 932fcd25166SAndrew Lunn 933fcd25166SAndrew Lunn chip->watchdog_irq = irq_find_mapping(chip->g2_irq.domain, 9341d90016dSVivien Didelot MV88E6XXX_G2_INT_SOURCE_WATCHDOG); 935fcd25166SAndrew Lunn if (chip->watchdog_irq < 0) 936fcd25166SAndrew Lunn return chip->watchdog_irq; 937fcd25166SAndrew Lunn 938fcd25166SAndrew Lunn err = request_threaded_irq(chip->watchdog_irq, NULL, 939fcd25166SAndrew Lunn mv88e6xxx_g2_watchdog_thread_fn, 940fcd25166SAndrew Lunn IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 941fcd25166SAndrew Lunn "mv88e6xxx-watchdog", chip); 942fcd25166SAndrew Lunn if (err) 943fcd25166SAndrew Lunn return err; 944fcd25166SAndrew Lunn 945c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip); 946fcd25166SAndrew Lunn if (chip->info->ops->watchdog_ops->irq_setup) 947fcd25166SAndrew Lunn err = chip->info->ops->watchdog_ops->irq_setup(chip); 948c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip); 949fcd25166SAndrew Lunn 950fcd25166SAndrew Lunn return err; 951fcd25166SAndrew Lunn } 952fcd25166SAndrew Lunn 95381228996SVivien Didelot /* Offset 0x1D: Misc Register */ 95481228996SVivien Didelot 95581228996SVivien Didelot static int mv88e6xxx_g2_misc_5_bit_port(struct mv88e6xxx_chip *chip, 95681228996SVivien Didelot bool port_5_bit) 95781228996SVivien Didelot { 95881228996SVivien Didelot u16 val; 95981228996SVivien Didelot int err; 96081228996SVivien Didelot 9611d90016dSVivien Didelot err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_MISC, &val); 96281228996SVivien Didelot if (err) 96381228996SVivien Didelot return err; 96481228996SVivien Didelot 96581228996SVivien Didelot if (port_5_bit) 9661d90016dSVivien Didelot val |= MV88E6XXX_G2_MISC_5_BIT_PORT; 96781228996SVivien Didelot else 9681d90016dSVivien Didelot val &= ~MV88E6XXX_G2_MISC_5_BIT_PORT; 96981228996SVivien Didelot 9701d90016dSVivien Didelot return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MISC, val); 97181228996SVivien Didelot } 97281228996SVivien Didelot 97381228996SVivien Didelot int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip) 97481228996SVivien Didelot { 97581228996SVivien Didelot return mv88e6xxx_g2_misc_5_bit_port(chip, false); 97681228996SVivien Didelot } 97781228996SVivien Didelot 978dc30c35bSAndrew Lunn static void mv88e6xxx_g2_irq_mask(struct irq_data *d) 979dc30c35bSAndrew Lunn { 980dc30c35bSAndrew Lunn struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 981dc30c35bSAndrew Lunn unsigned int n = d->hwirq; 982dc30c35bSAndrew Lunn 983dc30c35bSAndrew Lunn chip->g2_irq.masked |= (1 << n); 984dc30c35bSAndrew Lunn } 985dc30c35bSAndrew Lunn 986dc30c35bSAndrew Lunn static void mv88e6xxx_g2_irq_unmask(struct irq_data *d) 987dc30c35bSAndrew Lunn { 988dc30c35bSAndrew Lunn struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 989dc30c35bSAndrew Lunn unsigned int n = d->hwirq; 990dc30c35bSAndrew Lunn 991dc30c35bSAndrew Lunn chip->g2_irq.masked &= ~(1 << n); 992dc30c35bSAndrew Lunn } 993dc30c35bSAndrew Lunn 994dc30c35bSAndrew Lunn static irqreturn_t mv88e6xxx_g2_irq_thread_fn(int irq, void *dev_id) 995dc30c35bSAndrew Lunn { 996dc30c35bSAndrew Lunn struct mv88e6xxx_chip *chip = dev_id; 997dc30c35bSAndrew Lunn unsigned int nhandled = 0; 998dc30c35bSAndrew Lunn unsigned int sub_irq; 999dc30c35bSAndrew Lunn unsigned int n; 1000dc30c35bSAndrew Lunn int err; 1001dc30c35bSAndrew Lunn u16 reg; 1002dc30c35bSAndrew Lunn 1003c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip); 1004d6c5e6afSVivien Didelot err = mv88e6xxx_g2_int_source(chip, ®); 1005c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip); 1006dc30c35bSAndrew Lunn if (err) 1007dc30c35bSAndrew Lunn goto out; 1008dc30c35bSAndrew Lunn 1009dc30c35bSAndrew Lunn for (n = 0; n < 16; ++n) { 1010dc30c35bSAndrew Lunn if (reg & (1 << n)) { 1011dc30c35bSAndrew Lunn sub_irq = irq_find_mapping(chip->g2_irq.domain, n); 1012dc30c35bSAndrew Lunn handle_nested_irq(sub_irq); 1013dc30c35bSAndrew Lunn ++nhandled; 1014dc30c35bSAndrew Lunn } 1015dc30c35bSAndrew Lunn } 1016dc30c35bSAndrew Lunn out: 1017dc30c35bSAndrew Lunn return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 1018dc30c35bSAndrew Lunn } 1019dc30c35bSAndrew Lunn 1020dc30c35bSAndrew Lunn static void mv88e6xxx_g2_irq_bus_lock(struct irq_data *d) 1021dc30c35bSAndrew Lunn { 1022dc30c35bSAndrew Lunn struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 1023dc30c35bSAndrew Lunn 1024c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip); 1025dc30c35bSAndrew Lunn } 1026dc30c35bSAndrew Lunn 1027dc30c35bSAndrew Lunn static void mv88e6xxx_g2_irq_bus_sync_unlock(struct irq_data *d) 1028dc30c35bSAndrew Lunn { 1029dc30c35bSAndrew Lunn struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 1030d6c5e6afSVivien Didelot int err; 1031dc30c35bSAndrew Lunn 1032d6c5e6afSVivien Didelot err = mv88e6xxx_g2_int_mask(chip, ~chip->g2_irq.masked); 1033d6c5e6afSVivien Didelot if (err) 1034d6c5e6afSVivien Didelot dev_err(chip->dev, "failed to mask interrupts\n"); 1035dc30c35bSAndrew Lunn 1036c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip); 1037dc30c35bSAndrew Lunn } 1038dc30c35bSAndrew Lunn 10396eb15e21SBhumika Goyal static const struct irq_chip mv88e6xxx_g2_irq_chip = { 1040dc30c35bSAndrew Lunn .name = "mv88e6xxx-g2", 1041dc30c35bSAndrew Lunn .irq_mask = mv88e6xxx_g2_irq_mask, 1042dc30c35bSAndrew Lunn .irq_unmask = mv88e6xxx_g2_irq_unmask, 1043dc30c35bSAndrew Lunn .irq_bus_lock = mv88e6xxx_g2_irq_bus_lock, 1044dc30c35bSAndrew Lunn .irq_bus_sync_unlock = mv88e6xxx_g2_irq_bus_sync_unlock, 1045dc30c35bSAndrew Lunn }; 1046dc30c35bSAndrew Lunn 1047dc30c35bSAndrew Lunn static int mv88e6xxx_g2_irq_domain_map(struct irq_domain *d, 1048dc30c35bSAndrew Lunn unsigned int irq, 1049dc30c35bSAndrew Lunn irq_hw_number_t hwirq) 1050dc30c35bSAndrew Lunn { 1051dc30c35bSAndrew Lunn struct mv88e6xxx_chip *chip = d->host_data; 1052dc30c35bSAndrew Lunn 1053dc30c35bSAndrew Lunn irq_set_chip_data(irq, d->host_data); 1054dc30c35bSAndrew Lunn irq_set_chip_and_handler(irq, &chip->g2_irq.chip, handle_level_irq); 1055dc30c35bSAndrew Lunn irq_set_noprobe(irq); 1056dc30c35bSAndrew Lunn 1057dc30c35bSAndrew Lunn return 0; 1058dc30c35bSAndrew Lunn } 1059dc30c35bSAndrew Lunn 1060dc30c35bSAndrew Lunn static const struct irq_domain_ops mv88e6xxx_g2_irq_domain_ops = { 1061dc30c35bSAndrew Lunn .map = mv88e6xxx_g2_irq_domain_map, 1062dc30c35bSAndrew Lunn .xlate = irq_domain_xlate_twocell, 1063dc30c35bSAndrew Lunn }; 1064dc30c35bSAndrew Lunn 1065dc30c35bSAndrew Lunn void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip) 1066dc30c35bSAndrew Lunn { 1067dc30c35bSAndrew Lunn int irq, virq; 1068dc30c35bSAndrew Lunn 1069fcd25166SAndrew Lunn mv88e6xxx_g2_watchdog_free(chip); 1070fcd25166SAndrew Lunn 10718e757ebaSAndrew Lunn free_irq(chip->device_irq, chip); 10728e757ebaSAndrew Lunn irq_dispose_mapping(chip->device_irq); 10738e757ebaSAndrew Lunn 1074dc30c35bSAndrew Lunn for (irq = 0; irq < 16; irq++) { 1075dc30c35bSAndrew Lunn virq = irq_find_mapping(chip->g2_irq.domain, irq); 1076dc30c35bSAndrew Lunn irq_dispose_mapping(virq); 1077dc30c35bSAndrew Lunn } 1078dc30c35bSAndrew Lunn 1079dc30c35bSAndrew Lunn irq_domain_remove(chip->g2_irq.domain); 1080dc30c35bSAndrew Lunn } 1081dc30c35bSAndrew Lunn 1082dc30c35bSAndrew Lunn int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip) 1083dc30c35bSAndrew Lunn { 10848e757ebaSAndrew Lunn int err, irq, virq; 1085dc30c35bSAndrew Lunn 1086dc30c35bSAndrew Lunn chip->g2_irq.domain = irq_domain_add_simple( 1087dc30c35bSAndrew Lunn chip->dev->of_node, 16, 0, &mv88e6xxx_g2_irq_domain_ops, chip); 1088dc30c35bSAndrew Lunn if (!chip->g2_irq.domain) 1089dc30c35bSAndrew Lunn return -ENOMEM; 1090dc30c35bSAndrew Lunn 1091dc30c35bSAndrew Lunn for (irq = 0; irq < 16; irq++) 1092dc30c35bSAndrew Lunn irq_create_mapping(chip->g2_irq.domain, irq); 1093dc30c35bSAndrew Lunn 1094dc30c35bSAndrew Lunn chip->g2_irq.chip = mv88e6xxx_g2_irq_chip; 1095dc30c35bSAndrew Lunn chip->g2_irq.masked = ~0; 1096dc30c35bSAndrew Lunn 10978e757ebaSAndrew Lunn chip->device_irq = irq_find_mapping(chip->g1_irq.domain, 109882466921SVivien Didelot MV88E6XXX_G1_STS_IRQ_DEVICE); 10998e757ebaSAndrew Lunn if (chip->device_irq < 0) { 11008e757ebaSAndrew Lunn err = chip->device_irq; 1101dc30c35bSAndrew Lunn goto out; 1102dc30c35bSAndrew Lunn } 1103dc30c35bSAndrew Lunn 11048e757ebaSAndrew Lunn err = request_threaded_irq(chip->device_irq, NULL, 1105dc30c35bSAndrew Lunn mv88e6xxx_g2_irq_thread_fn, 110636d6ea94SUwe Kleine-König IRQF_ONESHOT, "mv88e6xxx-g2", chip); 1107dc30c35bSAndrew Lunn if (err) 1108dc30c35bSAndrew Lunn goto out; 1109dc30c35bSAndrew Lunn 1110fcd25166SAndrew Lunn return mv88e6xxx_g2_watchdog_setup(chip); 11118e757ebaSAndrew Lunn 1112dc30c35bSAndrew Lunn out: 11138e757ebaSAndrew Lunn for (irq = 0; irq < 16; irq++) { 11148e757ebaSAndrew Lunn virq = irq_find_mapping(chip->g2_irq.domain, irq); 11158e757ebaSAndrew Lunn irq_dispose_mapping(virq); 11168e757ebaSAndrew Lunn } 11178e757ebaSAndrew Lunn 11188e757ebaSAndrew Lunn irq_domain_remove(chip->g2_irq.domain); 1119dc30c35bSAndrew Lunn 1120dc30c35bSAndrew Lunn return err; 1121dc30c35bSAndrew Lunn } 1122dc30c35bSAndrew Lunn 11236f88284fSAndrew Lunn int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip, 11246f88284fSAndrew Lunn struct mii_bus *bus) 11256f88284fSAndrew Lunn { 11266f88284fSAndrew Lunn int phy, irq, err, err_phy; 11276f88284fSAndrew Lunn 11286f88284fSAndrew Lunn for (phy = 0; phy < chip->info->num_internal_phys; phy++) { 11296f88284fSAndrew Lunn irq = irq_find_mapping(chip->g2_irq.domain, phy); 11306f88284fSAndrew Lunn if (irq < 0) { 11316f88284fSAndrew Lunn err = irq; 11326f88284fSAndrew Lunn goto out; 11336f88284fSAndrew Lunn } 11349255bacdSAndrew Lunn bus->irq[chip->info->phy_base_addr + phy] = irq; 11356f88284fSAndrew Lunn } 11366f88284fSAndrew Lunn return 0; 11376f88284fSAndrew Lunn out: 11386f88284fSAndrew Lunn err_phy = phy; 11396f88284fSAndrew Lunn 11406f88284fSAndrew Lunn for (phy = 0; phy < err_phy; phy++) 11416f88284fSAndrew Lunn irq_dispose_mapping(bus->irq[phy]); 11426f88284fSAndrew Lunn 11436f88284fSAndrew Lunn return err; 11446f88284fSAndrew Lunn } 11456f88284fSAndrew Lunn 11466f88284fSAndrew Lunn void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip, 11476f88284fSAndrew Lunn struct mii_bus *bus) 11486f88284fSAndrew Lunn { 11496f88284fSAndrew Lunn int phy; 11506f88284fSAndrew Lunn 11516f88284fSAndrew Lunn for (phy = 0; phy < chip->info->num_internal_phys; phy++) 11526f88284fSAndrew Lunn irq_dispose_mapping(bus->irq[phy]); 11536f88284fSAndrew Lunn } 1154