1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Marvell 88E6xxx Address Translation Unit (ATU) support
4  *
5  * Copyright (c) 2008 Marvell Semiconductor
6  * Copyright (c) 2017 Savoir-faire Linux, Inc.
7  */
8 
9 #include <linux/bitfield.h>
10 #include <linux/interrupt.h>
11 #include <linux/irqdomain.h>
12 
13 #include "chip.h"
14 #include "global1.h"
15 #include "switchdev.h"
16 #include "trace.h"
17 
18 /* Offset 0x01: ATU FID Register */
19 
20 static int mv88e6xxx_g1_atu_fid_write(struct mv88e6xxx_chip *chip, u16 fid)
21 {
22 	return mv88e6xxx_g1_write(chip, MV88E6352_G1_ATU_FID, fid & 0xfff);
23 }
24 
25 /* Offset 0x0A: ATU Control Register */
26 
27 int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all)
28 {
29 	u16 val;
30 	int err;
31 
32 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
33 	if (err)
34 		return err;
35 
36 	if (learn2all)
37 		val |= MV88E6XXX_G1_ATU_CTL_LEARN2ALL;
38 	else
39 		val &= ~MV88E6XXX_G1_ATU_CTL_LEARN2ALL;
40 
41 	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val);
42 }
43 
44 int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
45 				  unsigned int msecs)
46 {
47 	const unsigned int coeff = chip->info->age_time_coeff;
48 	const unsigned int min = 0x01 * coeff;
49 	const unsigned int max = 0xff * coeff;
50 	u8 age_time;
51 	u16 val;
52 	int err;
53 
54 	if (msecs < min || msecs > max)
55 		return -ERANGE;
56 
57 	/* Round to nearest multiple of coeff */
58 	age_time = (msecs + coeff / 2) / coeff;
59 
60 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
61 	if (err)
62 		return err;
63 
64 	/* AgeTime is 11:4 bits */
65 	val &= ~0xff0;
66 	val |= age_time << 4;
67 
68 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val);
69 	if (err)
70 		return err;
71 
72 	dev_dbg(chip->dev, "AgeTime set to 0x%02x (%d ms)\n", age_time,
73 		age_time * coeff);
74 
75 	return 0;
76 }
77 
78 int mv88e6165_g1_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash)
79 {
80 	int err;
81 	u16 val;
82 
83 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
84 	if (err)
85 		return err;
86 
87 	*hash = val & MV88E6161_G1_ATU_CTL_HASH_MASK;
88 
89 	return 0;
90 }
91 
92 int mv88e6165_g1_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash)
93 {
94 	int err;
95 	u16 val;
96 
97 	if (hash & ~MV88E6161_G1_ATU_CTL_HASH_MASK)
98 		return -EINVAL;
99 
100 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
101 	if (err)
102 		return err;
103 
104 	val &= ~MV88E6161_G1_ATU_CTL_HASH_MASK;
105 	val |= hash;
106 
107 	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val);
108 }
109 
110 /* Offset 0x0B: ATU Operation Register */
111 
112 static int mv88e6xxx_g1_atu_op_wait(struct mv88e6xxx_chip *chip)
113 {
114 	int bit = __bf_shf(MV88E6XXX_G1_ATU_OP_BUSY);
115 
116 	return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_ATU_OP, bit, 0);
117 }
118 
119 static int mv88e6xxx_g1_read_atu_violation(struct mv88e6xxx_chip *chip)
120 {
121 	int err;
122 
123 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_OP,
124 				 MV88E6XXX_G1_ATU_OP_BUSY |
125 				 MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION);
126 	if (err)
127 		return err;
128 
129 	return mv88e6xxx_g1_atu_op_wait(chip);
130 }
131 
132 static int mv88e6xxx_g1_atu_op(struct mv88e6xxx_chip *chip, u16 fid, u16 op)
133 {
134 	u16 val;
135 	int err;
136 
137 	/* FID bits are dispatched all around gradually as more are supported */
138 	if (mv88e6xxx_num_databases(chip) > 256) {
139 		err = mv88e6xxx_g1_atu_fid_write(chip, fid);
140 		if (err)
141 			return err;
142 	} else {
143 		if (mv88e6xxx_num_databases(chip) > 64) {
144 			/* ATU DBNum[7:4] are located in ATU Control 15:12 */
145 			err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL,
146 						&val);
147 			if (err)
148 				return err;
149 
150 			val = (val & 0x0fff) | ((fid << 8) & 0xf000);
151 			err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL,
152 						 val);
153 			if (err)
154 				return err;
155 		} else if (mv88e6xxx_num_databases(chip) > 16) {
156 			/* ATU DBNum[5:4] are located in ATU Operation 9:8 */
157 			op |= (fid & 0x30) << 4;
158 		}
159 
160 		/* ATU DBNum[3:0] are located in ATU Operation 3:0 */
161 		op |= fid & 0xf;
162 	}
163 
164 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_OP,
165 				 MV88E6XXX_G1_ATU_OP_BUSY | op);
166 	if (err)
167 		return err;
168 
169 	return mv88e6xxx_g1_atu_op_wait(chip);
170 }
171 
172 int mv88e6xxx_g1_atu_get_next(struct mv88e6xxx_chip *chip, u16 fid)
173 {
174 	return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB);
175 }
176 
177 static int mv88e6xxx_g1_atu_fid_read(struct mv88e6xxx_chip *chip, u16 *fid)
178 {
179 	u16 val = 0, upper = 0, op = 0;
180 	int err = -EOPNOTSUPP;
181 
182 	if (mv88e6xxx_num_databases(chip) > 256) {
183 		err = mv88e6xxx_g1_read(chip, MV88E6352_G1_ATU_FID, &val);
184 		val &= 0xfff;
185 		if (err)
186 			return err;
187 	} else {
188 		err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_OP, &op);
189 		if (err)
190 			return err;
191 		if (mv88e6xxx_num_databases(chip) > 64) {
192 			/* ATU DBNum[7:4] are located in ATU Control 15:12 */
193 			err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL,
194 						&upper);
195 			if (err)
196 				return err;
197 
198 			upper = (upper >> 8) & 0x00f0;
199 		} else if (mv88e6xxx_num_databases(chip) > 16) {
200 			/* ATU DBNum[5:4] are located in ATU Operation 9:8 */
201 			upper = (op >> 4) & 0x30;
202 		}
203 
204 		/* ATU DBNum[3:0] are located in ATU Operation 3:0 */
205 		val = (op & 0xf) | upper;
206 	}
207 	*fid = val;
208 
209 	return err;
210 }
211 
212 /* Offset 0x0C: ATU Data Register */
213 
214 static int mv88e6xxx_g1_atu_data_read(struct mv88e6xxx_chip *chip,
215 				      struct mv88e6xxx_atu_entry *entry)
216 {
217 	u16 val;
218 	int err;
219 
220 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_DATA, &val);
221 	if (err)
222 		return err;
223 
224 	entry->state = val & 0xf;
225 	if (entry->state) {
226 		entry->trunk = !!(val & MV88E6XXX_G1_ATU_DATA_TRUNK);
227 		entry->portvec = (val >> 4) & mv88e6xxx_port_mask(chip);
228 	}
229 
230 	return 0;
231 }
232 
233 static int mv88e6xxx_g1_atu_data_write(struct mv88e6xxx_chip *chip,
234 				       struct mv88e6xxx_atu_entry *entry)
235 {
236 	u16 data = entry->state & 0xf;
237 
238 	if (entry->state) {
239 		if (entry->trunk)
240 			data |= MV88E6XXX_G1_ATU_DATA_TRUNK;
241 
242 		data |= (entry->portvec & mv88e6xxx_port_mask(chip)) << 4;
243 	}
244 
245 	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_DATA, data);
246 }
247 
248 /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
249  * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
250  * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
251  */
252 
253 static int mv88e6xxx_g1_atu_mac_read(struct mv88e6xxx_chip *chip,
254 				     struct mv88e6xxx_atu_entry *entry)
255 {
256 	u16 val;
257 	int i, err;
258 
259 	for (i = 0; i < 3; i++) {
260 		err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_MAC01 + i, &val);
261 		if (err)
262 			return err;
263 
264 		entry->mac[i * 2] = val >> 8;
265 		entry->mac[i * 2 + 1] = val & 0xff;
266 	}
267 
268 	return 0;
269 }
270 
271 static int mv88e6xxx_g1_atu_mac_write(struct mv88e6xxx_chip *chip,
272 				      struct mv88e6xxx_atu_entry *entry)
273 {
274 	u16 val;
275 	int i, err;
276 
277 	for (i = 0; i < 3; i++) {
278 		val = (entry->mac[i * 2] << 8) | entry->mac[i * 2 + 1];
279 		err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_MAC01 + i, val);
280 		if (err)
281 			return err;
282 	}
283 
284 	return 0;
285 }
286 
287 /* Address Translation Unit operations */
288 
289 int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
290 			     struct mv88e6xxx_atu_entry *entry)
291 {
292 	int err;
293 
294 	err = mv88e6xxx_g1_atu_op_wait(chip);
295 	if (err)
296 		return err;
297 
298 	/* Write the MAC address to iterate from only once */
299 	if (!entry->state) {
300 		err = mv88e6xxx_g1_atu_mac_write(chip, entry);
301 		if (err)
302 			return err;
303 	}
304 
305 	err = mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB);
306 	if (err)
307 		return err;
308 
309 	err = mv88e6xxx_g1_atu_data_read(chip, entry);
310 	if (err)
311 		return err;
312 
313 	return mv88e6xxx_g1_atu_mac_read(chip, entry);
314 }
315 
316 int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
317 			       struct mv88e6xxx_atu_entry *entry)
318 {
319 	int err;
320 
321 	err = mv88e6xxx_g1_atu_op_wait(chip);
322 	if (err)
323 		return err;
324 
325 	err = mv88e6xxx_g1_atu_mac_write(chip, entry);
326 	if (err)
327 		return err;
328 
329 	err = mv88e6xxx_g1_atu_data_write(chip, entry);
330 	if (err)
331 		return err;
332 
333 	return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_LOAD_DB);
334 }
335 
336 static int mv88e6xxx_g1_atu_flushmove(struct mv88e6xxx_chip *chip, u16 fid,
337 				      struct mv88e6xxx_atu_entry *entry,
338 				      bool all)
339 {
340 	u16 op;
341 	int err;
342 
343 	err = mv88e6xxx_g1_atu_op_wait(chip);
344 	if (err)
345 		return err;
346 
347 	err = mv88e6xxx_g1_atu_data_write(chip, entry);
348 	if (err)
349 		return err;
350 
351 	/* Flush/Move all or non-static entries from all or a given database */
352 	if (all && fid)
353 		op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB;
354 	else if (fid)
355 		op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
356 	else if (all)
357 		op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL;
358 	else
359 		op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC;
360 
361 	return mv88e6xxx_g1_atu_op(chip, fid, op);
362 }
363 
364 int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all)
365 {
366 	struct mv88e6xxx_atu_entry entry = {
367 		.state = 0, /* Null EntryState means Flush */
368 	};
369 
370 	return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all);
371 }
372 
373 static int mv88e6xxx_g1_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
374 				 int from_port, int to_port, bool all)
375 {
376 	struct mv88e6xxx_atu_entry entry = { 0 };
377 	unsigned long mask;
378 	int shift;
379 
380 	if (!chip->info->atu_move_port_mask)
381 		return -EOPNOTSUPP;
382 
383 	mask = chip->info->atu_move_port_mask;
384 	shift = bitmap_weight(&mask, 16);
385 
386 	entry.state = 0xf; /* Full EntryState means Move */
387 	entry.portvec = from_port & mask;
388 	entry.portvec |= (to_port & mask) << shift;
389 
390 	return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all);
391 }
392 
393 int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port,
394 			    bool all)
395 {
396 	int from_port = port;
397 	int to_port = chip->info->atu_move_port_mask;
398 
399 	return mv88e6xxx_g1_atu_move(chip, fid, from_port, to_port, all);
400 }
401 
402 static irqreturn_t mv88e6xxx_g1_atu_prob_irq_thread_fn(int irq, void *dev_id)
403 {
404 	struct mv88e6xxx_chip *chip = dev_id;
405 	struct mv88e6xxx_atu_entry entry;
406 	int err, spid;
407 	u16 val, fid;
408 
409 	mv88e6xxx_reg_lock(chip);
410 
411 	err = mv88e6xxx_g1_read_atu_violation(chip);
412 	if (err)
413 		goto out_unlock;
414 
415 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_OP, &val);
416 	if (err)
417 		goto out_unlock;
418 
419 	err = mv88e6xxx_g1_atu_fid_read(chip, &fid);
420 	if (err)
421 		goto out_unlock;
422 
423 	err = mv88e6xxx_g1_atu_data_read(chip, &entry);
424 	if (err)
425 		goto out_unlock;
426 
427 	err = mv88e6xxx_g1_atu_mac_read(chip, &entry);
428 	if (err)
429 		goto out_unlock;
430 
431 	mv88e6xxx_reg_unlock(chip);
432 
433 	spid = entry.state;
434 
435 	if (val & MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION) {
436 		trace_mv88e6xxx_atu_member_violation(chip->dev, spid,
437 						     entry.portvec, entry.mac,
438 						     fid);
439 		chip->ports[spid].atu_member_violation++;
440 	}
441 
442 	if (val & MV88E6XXX_G1_ATU_OP_MISS_VIOLATION) {
443 		trace_mv88e6xxx_atu_miss_violation(chip->dev, spid,
444 						   entry.portvec, entry.mac,
445 						   fid);
446 		chip->ports[spid].atu_miss_violation++;
447 
448 		if (fid != MV88E6XXX_FID_STANDALONE && chip->ports[spid].mab) {
449 			err = mv88e6xxx_handle_miss_violation(chip, spid,
450 							      &entry, fid);
451 			if (err)
452 				goto out;
453 		}
454 	}
455 
456 	if (val & MV88E6XXX_G1_ATU_OP_FULL_VIOLATION) {
457 		trace_mv88e6xxx_atu_full_violation(chip->dev, spid,
458 						   entry.portvec, entry.mac,
459 						   fid);
460 		chip->ports[spid].atu_full_violation++;
461 	}
462 
463 	return IRQ_HANDLED;
464 
465 out_unlock:
466 	mv88e6xxx_reg_unlock(chip);
467 
468 out:
469 	dev_err(chip->dev, "ATU problem: error %d while handling interrupt\n",
470 		err);
471 	return IRQ_HANDLED;
472 }
473 
474 int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip)
475 {
476 	int err;
477 
478 	chip->atu_prob_irq = irq_find_mapping(chip->g1_irq.domain,
479 					      MV88E6XXX_G1_STS_IRQ_ATU_PROB);
480 	if (chip->atu_prob_irq < 0)
481 		return chip->atu_prob_irq;
482 
483 	snprintf(chip->atu_prob_irq_name, sizeof(chip->atu_prob_irq_name),
484 		 "mv88e6xxx-%s-g1-atu-prob", dev_name(chip->dev));
485 
486 	err = request_threaded_irq(chip->atu_prob_irq, NULL,
487 				   mv88e6xxx_g1_atu_prob_irq_thread_fn,
488 				   IRQF_ONESHOT, chip->atu_prob_irq_name,
489 				   chip);
490 	if (err)
491 		irq_dispose_mapping(chip->atu_prob_irq);
492 
493 	return err;
494 }
495 
496 void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip)
497 {
498 	free_irq(chip->atu_prob_irq, chip);
499 	irq_dispose_mapping(chip->atu_prob_irq);
500 }
501