12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2720c6343SVivien Didelot /* 3720c6343SVivien Didelot * Marvell 88E6xxx Address Translation Unit (ATU) support 4720c6343SVivien Didelot * 5720c6343SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 6720c6343SVivien Didelot * Copyright (c) 2017 Savoir-faire Linux, Inc. 7720c6343SVivien Didelot */ 819fb7f69SVivien Didelot 919fb7f69SVivien Didelot #include <linux/bitfield.h> 100977644cSAndrew Lunn #include <linux/interrupt.h> 110977644cSAndrew Lunn #include <linux/irqdomain.h> 12720c6343SVivien Didelot 134d5f2ba7SVivien Didelot #include "chip.h" 14720c6343SVivien Didelot #include "global1.h" 15720c6343SVivien Didelot 169c13c026SVivien Didelot /* Offset 0x01: ATU FID Register */ 179c13c026SVivien Didelot 189c13c026SVivien Didelot static int mv88e6xxx_g1_atu_fid_write(struct mv88e6xxx_chip *chip, u16 fid) 199c13c026SVivien Didelot { 2027c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6352_G1_ATU_FID, fid & 0xfff); 219c13c026SVivien Didelot } 229c13c026SVivien Didelot 23720c6343SVivien Didelot /* Offset 0x0A: ATU Control Register */ 24720c6343SVivien Didelot 25c3a7d4adSVivien Didelot int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all) 26c3a7d4adSVivien Didelot { 27c3a7d4adSVivien Didelot u16 val; 28c3a7d4adSVivien Didelot int err; 29c3a7d4adSVivien Didelot 3027c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 31c3a7d4adSVivien Didelot if (err) 32c3a7d4adSVivien Didelot return err; 33c3a7d4adSVivien Didelot 34c3a7d4adSVivien Didelot if (learn2all) 3527c0e600SVivien Didelot val |= MV88E6XXX_G1_ATU_CTL_LEARN2ALL; 36c3a7d4adSVivien Didelot else 3727c0e600SVivien Didelot val &= ~MV88E6XXX_G1_ATU_CTL_LEARN2ALL; 38c3a7d4adSVivien Didelot 3927c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); 40c3a7d4adSVivien Didelot } 41c3a7d4adSVivien Didelot 42720c6343SVivien Didelot int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip, 43720c6343SVivien Didelot unsigned int msecs) 44720c6343SVivien Didelot { 45720c6343SVivien Didelot const unsigned int coeff = chip->info->age_time_coeff; 46720c6343SVivien Didelot const unsigned int min = 0x01 * coeff; 47720c6343SVivien Didelot const unsigned int max = 0xff * coeff; 48720c6343SVivien Didelot u8 age_time; 49720c6343SVivien Didelot u16 val; 50720c6343SVivien Didelot int err; 51720c6343SVivien Didelot 52720c6343SVivien Didelot if (msecs < min || msecs > max) 53720c6343SVivien Didelot return -ERANGE; 54720c6343SVivien Didelot 55720c6343SVivien Didelot /* Round to nearest multiple of coeff */ 56720c6343SVivien Didelot age_time = (msecs + coeff / 2) / coeff; 57720c6343SVivien Didelot 5827c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 59720c6343SVivien Didelot if (err) 60720c6343SVivien Didelot return err; 61720c6343SVivien Didelot 62720c6343SVivien Didelot /* AgeTime is 11:4 bits */ 63720c6343SVivien Didelot val &= ~0xff0; 64720c6343SVivien Didelot val |= age_time << 4; 65720c6343SVivien Didelot 6627c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); 67bae76dd9SVivien Didelot if (err) 68bae76dd9SVivien Didelot return err; 69bae76dd9SVivien Didelot 70bae76dd9SVivien Didelot dev_dbg(chip->dev, "AgeTime set to 0x%02x (%d ms)\n", age_time, 71bae76dd9SVivien Didelot age_time * coeff); 72bae76dd9SVivien Didelot 73bae76dd9SVivien Didelot return 0; 74720c6343SVivien Didelot } 759c13c026SVivien Didelot 769c13c026SVivien Didelot /* Offset 0x0B: ATU Operation Register */ 779c13c026SVivien Didelot 789c13c026SVivien Didelot static int mv88e6xxx_g1_atu_op_wait(struct mv88e6xxx_chip *chip) 799c13c026SVivien Didelot { 8019fb7f69SVivien Didelot int bit = __bf_shf(MV88E6XXX_G1_ATU_OP_BUSY); 8119fb7f69SVivien Didelot 8219fb7f69SVivien Didelot return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_ATU_OP, bit, 0); 839c13c026SVivien Didelot } 849c13c026SVivien Didelot 859c13c026SVivien Didelot static int mv88e6xxx_g1_atu_op(struct mv88e6xxx_chip *chip, u16 fid, u16 op) 869c13c026SVivien Didelot { 879c13c026SVivien Didelot u16 val; 889c13c026SVivien Didelot int err; 899c13c026SVivien Didelot 909c13c026SVivien Didelot /* FID bits are dispatched all around gradually as more are supported */ 919c13c026SVivien Didelot if (mv88e6xxx_num_databases(chip) > 256) { 929c13c026SVivien Didelot err = mv88e6xxx_g1_atu_fid_write(chip, fid); 939c13c026SVivien Didelot if (err) 949c13c026SVivien Didelot return err; 959c13c026SVivien Didelot } else { 967b83df0dSRasmus Villemoes if (mv88e6xxx_num_databases(chip) > 64) { 979c13c026SVivien Didelot /* ATU DBNum[7:4] are located in ATU Control 15:12 */ 9827c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, 9927c0e600SVivien Didelot &val); 1009c13c026SVivien Didelot if (err) 1019c13c026SVivien Didelot return err; 1029c13c026SVivien Didelot 1039c13c026SVivien Didelot val = (val & 0x0fff) | ((fid << 8) & 0xf000); 10427c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, 10527c0e600SVivien Didelot val); 1069c13c026SVivien Didelot if (err) 1079c13c026SVivien Didelot return err; 1087b83df0dSRasmus Villemoes } else if (mv88e6xxx_num_databases(chip) > 16) { 1097b83df0dSRasmus Villemoes /* ATU DBNum[5:4] are located in ATU Operation 9:8 */ 1107b83df0dSRasmus Villemoes op |= (fid & 0x30) << 4; 1119c13c026SVivien Didelot } 1129c13c026SVivien Didelot 1139c13c026SVivien Didelot /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ 1149c13c026SVivien Didelot op |= fid & 0xf; 1159c13c026SVivien Didelot } 1169c13c026SVivien Didelot 11727c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_OP, 11827c0e600SVivien Didelot MV88E6XXX_G1_ATU_OP_BUSY | op); 1199c13c026SVivien Didelot if (err) 1209c13c026SVivien Didelot return err; 1219c13c026SVivien Didelot 1229c13c026SVivien Didelot return mv88e6xxx_g1_atu_op_wait(chip); 1239c13c026SVivien Didelot } 1249c13c026SVivien Didelot 1259c13c026SVivien Didelot /* Offset 0x0C: ATU Data Register */ 1269c13c026SVivien Didelot 127dabc1a96SVivien Didelot static int mv88e6xxx_g1_atu_data_read(struct mv88e6xxx_chip *chip, 128dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 129dabc1a96SVivien Didelot { 130dabc1a96SVivien Didelot u16 val; 131dabc1a96SVivien Didelot int err; 132dabc1a96SVivien Didelot 13327c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_DATA, &val); 134dabc1a96SVivien Didelot if (err) 135dabc1a96SVivien Didelot return err; 136dabc1a96SVivien Didelot 137dabc1a96SVivien Didelot entry->state = val & 0xf; 138d8291a95SVivien Didelot if (entry->state) { 13927c0e600SVivien Didelot entry->trunk = !!(val & MV88E6XXX_G1_ATU_DATA_TRUNK); 14001bd96c8SVivien Didelot entry->portvec = (val >> 4) & mv88e6xxx_port_mask(chip); 141dabc1a96SVivien Didelot } 142dabc1a96SVivien Didelot 143dabc1a96SVivien Didelot return 0; 144dabc1a96SVivien Didelot } 145dabc1a96SVivien Didelot 1469c13c026SVivien Didelot static int mv88e6xxx_g1_atu_data_write(struct mv88e6xxx_chip *chip, 1479c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 1489c13c026SVivien Didelot { 1499c13c026SVivien Didelot u16 data = entry->state & 0xf; 1509c13c026SVivien Didelot 151d8291a95SVivien Didelot if (entry->state) { 1529c13c026SVivien Didelot if (entry->trunk) 15327c0e600SVivien Didelot data |= MV88E6XXX_G1_ATU_DATA_TRUNK; 1549c13c026SVivien Didelot 15501bd96c8SVivien Didelot data |= (entry->portvec & mv88e6xxx_port_mask(chip)) << 4; 1569c13c026SVivien Didelot } 1579c13c026SVivien Didelot 15827c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_DATA, data); 1599c13c026SVivien Didelot } 1609c13c026SVivien Didelot 1619c13c026SVivien Didelot /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1 1629c13c026SVivien Didelot * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3 1639c13c026SVivien Didelot * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5 1649c13c026SVivien Didelot */ 1659c13c026SVivien Didelot 166dabc1a96SVivien Didelot static int mv88e6xxx_g1_atu_mac_read(struct mv88e6xxx_chip *chip, 167dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 168dabc1a96SVivien Didelot { 169dabc1a96SVivien Didelot u16 val; 170dabc1a96SVivien Didelot int i, err; 171dabc1a96SVivien Didelot 172dabc1a96SVivien Didelot for (i = 0; i < 3; i++) { 17327c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_MAC01 + i, &val); 174dabc1a96SVivien Didelot if (err) 175dabc1a96SVivien Didelot return err; 176dabc1a96SVivien Didelot 177dabc1a96SVivien Didelot entry->mac[i * 2] = val >> 8; 178dabc1a96SVivien Didelot entry->mac[i * 2 + 1] = val & 0xff; 179dabc1a96SVivien Didelot } 180dabc1a96SVivien Didelot 181dabc1a96SVivien Didelot return 0; 182dabc1a96SVivien Didelot } 183dabc1a96SVivien Didelot 1849c13c026SVivien Didelot static int mv88e6xxx_g1_atu_mac_write(struct mv88e6xxx_chip *chip, 1859c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 1869c13c026SVivien Didelot { 1879c13c026SVivien Didelot u16 val; 1889c13c026SVivien Didelot int i, err; 1899c13c026SVivien Didelot 1909c13c026SVivien Didelot for (i = 0; i < 3; i++) { 1919c13c026SVivien Didelot val = (entry->mac[i * 2] << 8) | entry->mac[i * 2 + 1]; 19227c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_MAC01 + i, val); 1939c13c026SVivien Didelot if (err) 1949c13c026SVivien Didelot return err; 1959c13c026SVivien Didelot } 1969c13c026SVivien Didelot 1979c13c026SVivien Didelot return 0; 1989c13c026SVivien Didelot } 1999c13c026SVivien Didelot 2009c13c026SVivien Didelot /* Address Translation Unit operations */ 2019c13c026SVivien Didelot 202dabc1a96SVivien Didelot int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 203dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 204dabc1a96SVivien Didelot { 205dabc1a96SVivien Didelot int err; 206dabc1a96SVivien Didelot 207dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 208dabc1a96SVivien Didelot if (err) 209dabc1a96SVivien Didelot return err; 210dabc1a96SVivien Didelot 211dabc1a96SVivien Didelot /* Write the MAC address to iterate from only once */ 212d8291a95SVivien Didelot if (!entry->state) { 213dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_mac_write(chip, entry); 214dabc1a96SVivien Didelot if (err) 215dabc1a96SVivien Didelot return err; 216dabc1a96SVivien Didelot } 217dabc1a96SVivien Didelot 21827c0e600SVivien Didelot err = mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB); 219dabc1a96SVivien Didelot if (err) 220dabc1a96SVivien Didelot return err; 221dabc1a96SVivien Didelot 222dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_data_read(chip, entry); 223dabc1a96SVivien Didelot if (err) 224dabc1a96SVivien Didelot return err; 225dabc1a96SVivien Didelot 226dabc1a96SVivien Didelot return mv88e6xxx_g1_atu_mac_read(chip, entry); 227dabc1a96SVivien Didelot } 228dabc1a96SVivien Didelot 2299c13c026SVivien Didelot int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid, 2309c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 2319c13c026SVivien Didelot { 2329c13c026SVivien Didelot int err; 2339c13c026SVivien Didelot 2349c13c026SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 2359c13c026SVivien Didelot if (err) 2369c13c026SVivien Didelot return err; 2379c13c026SVivien Didelot 2389c13c026SVivien Didelot err = mv88e6xxx_g1_atu_mac_write(chip, entry); 2399c13c026SVivien Didelot if (err) 2409c13c026SVivien Didelot return err; 2419c13c026SVivien Didelot 2429c13c026SVivien Didelot err = mv88e6xxx_g1_atu_data_write(chip, entry); 2439c13c026SVivien Didelot if (err) 2449c13c026SVivien Didelot return err; 2459c13c026SVivien Didelot 24627c0e600SVivien Didelot return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_LOAD_DB); 2479c13c026SVivien Didelot } 248daefc943SVivien Didelot 249daefc943SVivien Didelot static int mv88e6xxx_g1_atu_flushmove(struct mv88e6xxx_chip *chip, u16 fid, 250daefc943SVivien Didelot struct mv88e6xxx_atu_entry *entry, 251daefc943SVivien Didelot bool all) 252daefc943SVivien Didelot { 253daefc943SVivien Didelot u16 op; 254daefc943SVivien Didelot int err; 255daefc943SVivien Didelot 256daefc943SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 257daefc943SVivien Didelot if (err) 258daefc943SVivien Didelot return err; 259daefc943SVivien Didelot 260daefc943SVivien Didelot err = mv88e6xxx_g1_atu_data_write(chip, entry); 261daefc943SVivien Didelot if (err) 262daefc943SVivien Didelot return err; 263daefc943SVivien Didelot 264daefc943SVivien Didelot /* Flush/Move all or non-static entries from all or a given database */ 265daefc943SVivien Didelot if (all && fid) 26627c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB; 267daefc943SVivien Didelot else if (fid) 26827c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; 269daefc943SVivien Didelot else if (all) 27027c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL; 271daefc943SVivien Didelot else 27227c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC; 273daefc943SVivien Didelot 274daefc943SVivien Didelot return mv88e6xxx_g1_atu_op(chip, fid, op); 275daefc943SVivien Didelot } 276daefc943SVivien Didelot 277daefc943SVivien Didelot int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all) 278daefc943SVivien Didelot { 279daefc943SVivien Didelot struct mv88e6xxx_atu_entry entry = { 280daefc943SVivien Didelot .state = 0, /* Null EntryState means Flush */ 281daefc943SVivien Didelot }; 282daefc943SVivien Didelot 283daefc943SVivien Didelot return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all); 284daefc943SVivien Didelot } 285e606ca36SVivien Didelot 286e606ca36SVivien Didelot static int mv88e6xxx_g1_atu_move(struct mv88e6xxx_chip *chip, u16 fid, 287e606ca36SVivien Didelot int from_port, int to_port, bool all) 288e606ca36SVivien Didelot { 289e606ca36SVivien Didelot struct mv88e6xxx_atu_entry entry = { 0 }; 290e606ca36SVivien Didelot unsigned long mask; 291e606ca36SVivien Didelot int shift; 292e606ca36SVivien Didelot 293e606ca36SVivien Didelot if (!chip->info->atu_move_port_mask) 294e606ca36SVivien Didelot return -EOPNOTSUPP; 295e606ca36SVivien Didelot 296e606ca36SVivien Didelot mask = chip->info->atu_move_port_mask; 297e606ca36SVivien Didelot shift = bitmap_weight(&mask, 16); 298e606ca36SVivien Didelot 299e606ca36SVivien Didelot entry.state = 0xf, /* Full EntryState means Move */ 30001bd96c8SVivien Didelot entry.portvec = from_port & mask; 30101bd96c8SVivien Didelot entry.portvec |= (to_port & mask) << shift; 302e606ca36SVivien Didelot 303e606ca36SVivien Didelot return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all); 304e606ca36SVivien Didelot } 305e606ca36SVivien Didelot 306e606ca36SVivien Didelot int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port, 307e606ca36SVivien Didelot bool all) 308e606ca36SVivien Didelot { 309e606ca36SVivien Didelot int from_port = port; 310e606ca36SVivien Didelot int to_port = chip->info->atu_move_port_mask; 311e606ca36SVivien Didelot 312e606ca36SVivien Didelot return mv88e6xxx_g1_atu_move(chip, fid, from_port, to_port, all); 313e606ca36SVivien Didelot } 3140977644cSAndrew Lunn 3150977644cSAndrew Lunn static irqreturn_t mv88e6xxx_g1_atu_prob_irq_thread_fn(int irq, void *dev_id) 3160977644cSAndrew Lunn { 3170977644cSAndrew Lunn struct mv88e6xxx_chip *chip = dev_id; 3180977644cSAndrew Lunn struct mv88e6xxx_atu_entry entry; 31975c05a74SAndrew Lunn int spid; 3200977644cSAndrew Lunn int err; 3210977644cSAndrew Lunn u16 val; 3220977644cSAndrew Lunn 323c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip); 3240977644cSAndrew Lunn 3250977644cSAndrew Lunn err = mv88e6xxx_g1_atu_op(chip, 0, 3260977644cSAndrew Lunn MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION); 3270977644cSAndrew Lunn if (err) 3280977644cSAndrew Lunn goto out; 3290977644cSAndrew Lunn 3300977644cSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_OP, &val); 3310977644cSAndrew Lunn if (err) 3320977644cSAndrew Lunn goto out; 3330977644cSAndrew Lunn 3340977644cSAndrew Lunn err = mv88e6xxx_g1_atu_data_read(chip, &entry); 3350977644cSAndrew Lunn if (err) 3360977644cSAndrew Lunn goto out; 3370977644cSAndrew Lunn 3380977644cSAndrew Lunn err = mv88e6xxx_g1_atu_mac_read(chip, &entry); 3390977644cSAndrew Lunn if (err) 3400977644cSAndrew Lunn goto out; 3410977644cSAndrew Lunn 34275c05a74SAndrew Lunn spid = entry.state; 34375c05a74SAndrew Lunn 3440977644cSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION) { 3450977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 3460977644cSAndrew Lunn "ATU age out violation for %pM\n", 3470977644cSAndrew Lunn entry.mac); 3480977644cSAndrew Lunn } 3490977644cSAndrew Lunn 3500977644cSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION) { 3510977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 35275c05a74SAndrew Lunn "ATU member violation for %pM portvec %x spid %d\n", 35375c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 35475c05a74SAndrew Lunn chip->ports[spid].atu_member_violation++; 3550977644cSAndrew Lunn } 3560977644cSAndrew Lunn 357ddca24dfSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_MISS_VIOLATION) { 3580977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 35975c05a74SAndrew Lunn "ATU miss violation for %pM portvec %x spid %d\n", 36075c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 36175c05a74SAndrew Lunn chip->ports[spid].atu_miss_violation++; 36265f60e45SAndrew Lunn } 3630977644cSAndrew Lunn 36465f60e45SAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_FULL_VIOLATION) { 3650977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 36675c05a74SAndrew Lunn "ATU full violation for %pM portvec %x spid %d\n", 36775c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 36875c05a74SAndrew Lunn chip->ports[spid].atu_full_violation++; 36965f60e45SAndrew Lunn } 370c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip); 3710977644cSAndrew Lunn 3720977644cSAndrew Lunn return IRQ_HANDLED; 3730977644cSAndrew Lunn 3740977644cSAndrew Lunn out: 375c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip); 3760977644cSAndrew Lunn 3770977644cSAndrew Lunn dev_err(chip->dev, "ATU problem: error %d while handling interrupt\n", 3780977644cSAndrew Lunn err); 3790977644cSAndrew Lunn return IRQ_HANDLED; 3800977644cSAndrew Lunn } 3810977644cSAndrew Lunn 3820977644cSAndrew Lunn int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip) 3830977644cSAndrew Lunn { 3840977644cSAndrew Lunn int err; 3850977644cSAndrew Lunn 3860977644cSAndrew Lunn chip->atu_prob_irq = irq_find_mapping(chip->g1_irq.domain, 3870977644cSAndrew Lunn MV88E6XXX_G1_STS_IRQ_ATU_PROB); 3880977644cSAndrew Lunn if (chip->atu_prob_irq < 0) 3899b662a3eSAndrew Lunn return chip->atu_prob_irq; 3900977644cSAndrew Lunn 3910977644cSAndrew Lunn err = request_threaded_irq(chip->atu_prob_irq, NULL, 3920977644cSAndrew Lunn mv88e6xxx_g1_atu_prob_irq_thread_fn, 3930977644cSAndrew Lunn IRQF_ONESHOT, "mv88e6xxx-g1-atu-prob", 3940977644cSAndrew Lunn chip); 3950977644cSAndrew Lunn if (err) 3960977644cSAndrew Lunn irq_dispose_mapping(chip->atu_prob_irq); 3970977644cSAndrew Lunn 3980977644cSAndrew Lunn return err; 3990977644cSAndrew Lunn } 4000977644cSAndrew Lunn 4010977644cSAndrew Lunn void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip) 4020977644cSAndrew Lunn { 4030977644cSAndrew Lunn free_irq(chip->atu_prob_irq, chip); 4040977644cSAndrew Lunn irq_dispose_mapping(chip->atu_prob_irq); 4050977644cSAndrew Lunn } 406