12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2720c6343SVivien Didelot /* 3720c6343SVivien Didelot * Marvell 88E6xxx Address Translation Unit (ATU) support 4720c6343SVivien Didelot * 5720c6343SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 6720c6343SVivien Didelot * Copyright (c) 2017 Savoir-faire Linux, Inc. 7720c6343SVivien Didelot */ 80977644cSAndrew Lunn #include <linux/interrupt.h> 90977644cSAndrew Lunn #include <linux/irqdomain.h> 10720c6343SVivien Didelot 114d5f2ba7SVivien Didelot #include "chip.h" 12720c6343SVivien Didelot #include "global1.h" 13720c6343SVivien Didelot 149c13c026SVivien Didelot /* Offset 0x01: ATU FID Register */ 159c13c026SVivien Didelot 169c13c026SVivien Didelot static int mv88e6xxx_g1_atu_fid_write(struct mv88e6xxx_chip *chip, u16 fid) 179c13c026SVivien Didelot { 1827c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6352_G1_ATU_FID, fid & 0xfff); 199c13c026SVivien Didelot } 209c13c026SVivien Didelot 21720c6343SVivien Didelot /* Offset 0x0A: ATU Control Register */ 22720c6343SVivien Didelot 23c3a7d4adSVivien Didelot int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all) 24c3a7d4adSVivien Didelot { 25c3a7d4adSVivien Didelot u16 val; 26c3a7d4adSVivien Didelot int err; 27c3a7d4adSVivien Didelot 2827c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 29c3a7d4adSVivien Didelot if (err) 30c3a7d4adSVivien Didelot return err; 31c3a7d4adSVivien Didelot 32c3a7d4adSVivien Didelot if (learn2all) 3327c0e600SVivien Didelot val |= MV88E6XXX_G1_ATU_CTL_LEARN2ALL; 34c3a7d4adSVivien Didelot else 3527c0e600SVivien Didelot val &= ~MV88E6XXX_G1_ATU_CTL_LEARN2ALL; 36c3a7d4adSVivien Didelot 3727c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); 38c3a7d4adSVivien Didelot } 39c3a7d4adSVivien Didelot 40720c6343SVivien Didelot int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip, 41720c6343SVivien Didelot unsigned int msecs) 42720c6343SVivien Didelot { 43720c6343SVivien Didelot const unsigned int coeff = chip->info->age_time_coeff; 44720c6343SVivien Didelot const unsigned int min = 0x01 * coeff; 45720c6343SVivien Didelot const unsigned int max = 0xff * coeff; 46720c6343SVivien Didelot u8 age_time; 47720c6343SVivien Didelot u16 val; 48720c6343SVivien Didelot int err; 49720c6343SVivien Didelot 50720c6343SVivien Didelot if (msecs < min || msecs > max) 51720c6343SVivien Didelot return -ERANGE; 52720c6343SVivien Didelot 53720c6343SVivien Didelot /* Round to nearest multiple of coeff */ 54720c6343SVivien Didelot age_time = (msecs + coeff / 2) / coeff; 55720c6343SVivien Didelot 5627c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 57720c6343SVivien Didelot if (err) 58720c6343SVivien Didelot return err; 59720c6343SVivien Didelot 60720c6343SVivien Didelot /* AgeTime is 11:4 bits */ 61720c6343SVivien Didelot val &= ~0xff0; 62720c6343SVivien Didelot val |= age_time << 4; 63720c6343SVivien Didelot 6427c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); 65bae76dd9SVivien Didelot if (err) 66bae76dd9SVivien Didelot return err; 67bae76dd9SVivien Didelot 68bae76dd9SVivien Didelot dev_dbg(chip->dev, "AgeTime set to 0x%02x (%d ms)\n", age_time, 69bae76dd9SVivien Didelot age_time * coeff); 70bae76dd9SVivien Didelot 71bae76dd9SVivien Didelot return 0; 72720c6343SVivien Didelot } 739c13c026SVivien Didelot 749c13c026SVivien Didelot /* Offset 0x0B: ATU Operation Register */ 759c13c026SVivien Didelot 769c13c026SVivien Didelot static int mv88e6xxx_g1_atu_op_wait(struct mv88e6xxx_chip *chip) 779c13c026SVivien Didelot { 7827c0e600SVivien Didelot return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_ATU_OP, 7927c0e600SVivien Didelot MV88E6XXX_G1_ATU_OP_BUSY); 809c13c026SVivien Didelot } 819c13c026SVivien Didelot 829c13c026SVivien Didelot static int mv88e6xxx_g1_atu_op(struct mv88e6xxx_chip *chip, u16 fid, u16 op) 839c13c026SVivien Didelot { 849c13c026SVivien Didelot u16 val; 859c13c026SVivien Didelot int err; 869c13c026SVivien Didelot 879c13c026SVivien Didelot /* FID bits are dispatched all around gradually as more are supported */ 889c13c026SVivien Didelot if (mv88e6xxx_num_databases(chip) > 256) { 899c13c026SVivien Didelot err = mv88e6xxx_g1_atu_fid_write(chip, fid); 909c13c026SVivien Didelot if (err) 919c13c026SVivien Didelot return err; 929c13c026SVivien Didelot } else { 937b83df0dSRasmus Villemoes if (mv88e6xxx_num_databases(chip) > 64) { 949c13c026SVivien Didelot /* ATU DBNum[7:4] are located in ATU Control 15:12 */ 9527c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, 9627c0e600SVivien Didelot &val); 979c13c026SVivien Didelot if (err) 989c13c026SVivien Didelot return err; 999c13c026SVivien Didelot 1009c13c026SVivien Didelot val = (val & 0x0fff) | ((fid << 8) & 0xf000); 10127c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, 10227c0e600SVivien Didelot val); 1039c13c026SVivien Didelot if (err) 1049c13c026SVivien Didelot return err; 1057b83df0dSRasmus Villemoes } else if (mv88e6xxx_num_databases(chip) > 16) { 1067b83df0dSRasmus Villemoes /* ATU DBNum[5:4] are located in ATU Operation 9:8 */ 1077b83df0dSRasmus Villemoes op |= (fid & 0x30) << 4; 1089c13c026SVivien Didelot } 1099c13c026SVivien Didelot 1109c13c026SVivien Didelot /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ 1119c13c026SVivien Didelot op |= fid & 0xf; 1129c13c026SVivien Didelot } 1139c13c026SVivien Didelot 11427c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_OP, 11527c0e600SVivien Didelot MV88E6XXX_G1_ATU_OP_BUSY | op); 1169c13c026SVivien Didelot if (err) 1179c13c026SVivien Didelot return err; 1189c13c026SVivien Didelot 1199c13c026SVivien Didelot return mv88e6xxx_g1_atu_op_wait(chip); 1209c13c026SVivien Didelot } 1219c13c026SVivien Didelot 1229c13c026SVivien Didelot /* Offset 0x0C: ATU Data Register */ 1239c13c026SVivien Didelot 124dabc1a96SVivien Didelot static int mv88e6xxx_g1_atu_data_read(struct mv88e6xxx_chip *chip, 125dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 126dabc1a96SVivien Didelot { 127dabc1a96SVivien Didelot u16 val; 128dabc1a96SVivien Didelot int err; 129dabc1a96SVivien Didelot 13027c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_DATA, &val); 131dabc1a96SVivien Didelot if (err) 132dabc1a96SVivien Didelot return err; 133dabc1a96SVivien Didelot 134dabc1a96SVivien Didelot entry->state = val & 0xf; 13527c0e600SVivien Didelot if (entry->state != MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 13627c0e600SVivien Didelot entry->trunk = !!(val & MV88E6XXX_G1_ATU_DATA_TRUNK); 13701bd96c8SVivien Didelot entry->portvec = (val >> 4) & mv88e6xxx_port_mask(chip); 138dabc1a96SVivien Didelot } 139dabc1a96SVivien Didelot 140dabc1a96SVivien Didelot return 0; 141dabc1a96SVivien Didelot } 142dabc1a96SVivien Didelot 1439c13c026SVivien Didelot static int mv88e6xxx_g1_atu_data_write(struct mv88e6xxx_chip *chip, 1449c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 1459c13c026SVivien Didelot { 1469c13c026SVivien Didelot u16 data = entry->state & 0xf; 1479c13c026SVivien Didelot 14827c0e600SVivien Didelot if (entry->state != MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1499c13c026SVivien Didelot if (entry->trunk) 15027c0e600SVivien Didelot data |= MV88E6XXX_G1_ATU_DATA_TRUNK; 1519c13c026SVivien Didelot 15201bd96c8SVivien Didelot data |= (entry->portvec & mv88e6xxx_port_mask(chip)) << 4; 1539c13c026SVivien Didelot } 1549c13c026SVivien Didelot 15527c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_DATA, data); 1569c13c026SVivien Didelot } 1579c13c026SVivien Didelot 1589c13c026SVivien Didelot /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1 1599c13c026SVivien Didelot * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3 1609c13c026SVivien Didelot * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5 1619c13c026SVivien Didelot */ 1629c13c026SVivien Didelot 163dabc1a96SVivien Didelot static int mv88e6xxx_g1_atu_mac_read(struct mv88e6xxx_chip *chip, 164dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 165dabc1a96SVivien Didelot { 166dabc1a96SVivien Didelot u16 val; 167dabc1a96SVivien Didelot int i, err; 168dabc1a96SVivien Didelot 169dabc1a96SVivien Didelot for (i = 0; i < 3; i++) { 17027c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_MAC01 + i, &val); 171dabc1a96SVivien Didelot if (err) 172dabc1a96SVivien Didelot return err; 173dabc1a96SVivien Didelot 174dabc1a96SVivien Didelot entry->mac[i * 2] = val >> 8; 175dabc1a96SVivien Didelot entry->mac[i * 2 + 1] = val & 0xff; 176dabc1a96SVivien Didelot } 177dabc1a96SVivien Didelot 178dabc1a96SVivien Didelot return 0; 179dabc1a96SVivien Didelot } 180dabc1a96SVivien Didelot 1819c13c026SVivien Didelot static int mv88e6xxx_g1_atu_mac_write(struct mv88e6xxx_chip *chip, 1829c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 1839c13c026SVivien Didelot { 1849c13c026SVivien Didelot u16 val; 1859c13c026SVivien Didelot int i, err; 1869c13c026SVivien Didelot 1879c13c026SVivien Didelot for (i = 0; i < 3; i++) { 1889c13c026SVivien Didelot val = (entry->mac[i * 2] << 8) | entry->mac[i * 2 + 1]; 18927c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_MAC01 + i, val); 1909c13c026SVivien Didelot if (err) 1919c13c026SVivien Didelot return err; 1929c13c026SVivien Didelot } 1939c13c026SVivien Didelot 1949c13c026SVivien Didelot return 0; 1959c13c026SVivien Didelot } 1969c13c026SVivien Didelot 1979c13c026SVivien Didelot /* Address Translation Unit operations */ 1989c13c026SVivien Didelot 199dabc1a96SVivien Didelot int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 200dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 201dabc1a96SVivien Didelot { 202dabc1a96SVivien Didelot int err; 203dabc1a96SVivien Didelot 204dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 205dabc1a96SVivien Didelot if (err) 206dabc1a96SVivien Didelot return err; 207dabc1a96SVivien Didelot 208dabc1a96SVivien Didelot /* Write the MAC address to iterate from only once */ 20927c0e600SVivien Didelot if (entry->state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 210dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_mac_write(chip, entry); 211dabc1a96SVivien Didelot if (err) 212dabc1a96SVivien Didelot return err; 213dabc1a96SVivien Didelot } 214dabc1a96SVivien Didelot 21527c0e600SVivien Didelot err = mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB); 216dabc1a96SVivien Didelot if (err) 217dabc1a96SVivien Didelot return err; 218dabc1a96SVivien Didelot 219dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_data_read(chip, entry); 220dabc1a96SVivien Didelot if (err) 221dabc1a96SVivien Didelot return err; 222dabc1a96SVivien Didelot 223dabc1a96SVivien Didelot return mv88e6xxx_g1_atu_mac_read(chip, entry); 224dabc1a96SVivien Didelot } 225dabc1a96SVivien Didelot 2269c13c026SVivien Didelot int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid, 2279c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 2289c13c026SVivien Didelot { 2299c13c026SVivien Didelot int err; 2309c13c026SVivien Didelot 2319c13c026SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 2329c13c026SVivien Didelot if (err) 2339c13c026SVivien Didelot return err; 2349c13c026SVivien Didelot 2359c13c026SVivien Didelot err = mv88e6xxx_g1_atu_mac_write(chip, entry); 2369c13c026SVivien Didelot if (err) 2379c13c026SVivien Didelot return err; 2389c13c026SVivien Didelot 2399c13c026SVivien Didelot err = mv88e6xxx_g1_atu_data_write(chip, entry); 2409c13c026SVivien Didelot if (err) 2419c13c026SVivien Didelot return err; 2429c13c026SVivien Didelot 24327c0e600SVivien Didelot return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_LOAD_DB); 2449c13c026SVivien Didelot } 245daefc943SVivien Didelot 246daefc943SVivien Didelot static int mv88e6xxx_g1_atu_flushmove(struct mv88e6xxx_chip *chip, u16 fid, 247daefc943SVivien Didelot struct mv88e6xxx_atu_entry *entry, 248daefc943SVivien Didelot bool all) 249daefc943SVivien Didelot { 250daefc943SVivien Didelot u16 op; 251daefc943SVivien Didelot int err; 252daefc943SVivien Didelot 253daefc943SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 254daefc943SVivien Didelot if (err) 255daefc943SVivien Didelot return err; 256daefc943SVivien Didelot 257daefc943SVivien Didelot err = mv88e6xxx_g1_atu_data_write(chip, entry); 258daefc943SVivien Didelot if (err) 259daefc943SVivien Didelot return err; 260daefc943SVivien Didelot 261daefc943SVivien Didelot /* Flush/Move all or non-static entries from all or a given database */ 262daefc943SVivien Didelot if (all && fid) 26327c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB; 264daefc943SVivien Didelot else if (fid) 26527c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; 266daefc943SVivien Didelot else if (all) 26727c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL; 268daefc943SVivien Didelot else 26927c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC; 270daefc943SVivien Didelot 271daefc943SVivien Didelot return mv88e6xxx_g1_atu_op(chip, fid, op); 272daefc943SVivien Didelot } 273daefc943SVivien Didelot 274daefc943SVivien Didelot int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all) 275daefc943SVivien Didelot { 276daefc943SVivien Didelot struct mv88e6xxx_atu_entry entry = { 277daefc943SVivien Didelot .state = 0, /* Null EntryState means Flush */ 278daefc943SVivien Didelot }; 279daefc943SVivien Didelot 280daefc943SVivien Didelot return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all); 281daefc943SVivien Didelot } 282e606ca36SVivien Didelot 283e606ca36SVivien Didelot static int mv88e6xxx_g1_atu_move(struct mv88e6xxx_chip *chip, u16 fid, 284e606ca36SVivien Didelot int from_port, int to_port, bool all) 285e606ca36SVivien Didelot { 286e606ca36SVivien Didelot struct mv88e6xxx_atu_entry entry = { 0 }; 287e606ca36SVivien Didelot unsigned long mask; 288e606ca36SVivien Didelot int shift; 289e606ca36SVivien Didelot 290e606ca36SVivien Didelot if (!chip->info->atu_move_port_mask) 291e606ca36SVivien Didelot return -EOPNOTSUPP; 292e606ca36SVivien Didelot 293e606ca36SVivien Didelot mask = chip->info->atu_move_port_mask; 294e606ca36SVivien Didelot shift = bitmap_weight(&mask, 16); 295e606ca36SVivien Didelot 296e606ca36SVivien Didelot entry.state = 0xf, /* Full EntryState means Move */ 29701bd96c8SVivien Didelot entry.portvec = from_port & mask; 29801bd96c8SVivien Didelot entry.portvec |= (to_port & mask) << shift; 299e606ca36SVivien Didelot 300e606ca36SVivien Didelot return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all); 301e606ca36SVivien Didelot } 302e606ca36SVivien Didelot 303e606ca36SVivien Didelot int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port, 304e606ca36SVivien Didelot bool all) 305e606ca36SVivien Didelot { 306e606ca36SVivien Didelot int from_port = port; 307e606ca36SVivien Didelot int to_port = chip->info->atu_move_port_mask; 308e606ca36SVivien Didelot 309e606ca36SVivien Didelot return mv88e6xxx_g1_atu_move(chip, fid, from_port, to_port, all); 310e606ca36SVivien Didelot } 3110977644cSAndrew Lunn 3120977644cSAndrew Lunn static irqreturn_t mv88e6xxx_g1_atu_prob_irq_thread_fn(int irq, void *dev_id) 3130977644cSAndrew Lunn { 3140977644cSAndrew Lunn struct mv88e6xxx_chip *chip = dev_id; 3150977644cSAndrew Lunn struct mv88e6xxx_atu_entry entry; 31675c05a74SAndrew Lunn int spid; 3170977644cSAndrew Lunn int err; 3180977644cSAndrew Lunn u16 val; 3190977644cSAndrew Lunn 320c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip); 3210977644cSAndrew Lunn 3220977644cSAndrew Lunn err = mv88e6xxx_g1_atu_op(chip, 0, 3230977644cSAndrew Lunn MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION); 3240977644cSAndrew Lunn if (err) 3250977644cSAndrew Lunn goto out; 3260977644cSAndrew Lunn 3270977644cSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_OP, &val); 3280977644cSAndrew Lunn if (err) 3290977644cSAndrew Lunn goto out; 3300977644cSAndrew Lunn 3310977644cSAndrew Lunn err = mv88e6xxx_g1_atu_data_read(chip, &entry); 3320977644cSAndrew Lunn if (err) 3330977644cSAndrew Lunn goto out; 3340977644cSAndrew Lunn 3350977644cSAndrew Lunn err = mv88e6xxx_g1_atu_mac_read(chip, &entry); 3360977644cSAndrew Lunn if (err) 3370977644cSAndrew Lunn goto out; 3380977644cSAndrew Lunn 33975c05a74SAndrew Lunn spid = entry.state; 34075c05a74SAndrew Lunn 3410977644cSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION) { 3420977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 3430977644cSAndrew Lunn "ATU age out violation for %pM\n", 3440977644cSAndrew Lunn entry.mac); 3450977644cSAndrew Lunn } 3460977644cSAndrew Lunn 3470977644cSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION) { 3480977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 34975c05a74SAndrew Lunn "ATU member violation for %pM portvec %x spid %d\n", 35075c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 35175c05a74SAndrew Lunn chip->ports[spid].atu_member_violation++; 3520977644cSAndrew Lunn } 3530977644cSAndrew Lunn 354ddca24dfSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_MISS_VIOLATION) { 3550977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 35675c05a74SAndrew Lunn "ATU miss violation for %pM portvec %x spid %d\n", 35775c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 35875c05a74SAndrew Lunn chip->ports[spid].atu_miss_violation++; 35965f60e45SAndrew Lunn } 3600977644cSAndrew Lunn 36165f60e45SAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_FULL_VIOLATION) { 3620977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 36375c05a74SAndrew Lunn "ATU full violation for %pM portvec %x spid %d\n", 36475c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 36575c05a74SAndrew Lunn chip->ports[spid].atu_full_violation++; 36665f60e45SAndrew Lunn } 367c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip); 3680977644cSAndrew Lunn 3690977644cSAndrew Lunn return IRQ_HANDLED; 3700977644cSAndrew Lunn 3710977644cSAndrew Lunn out: 372c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip); 3730977644cSAndrew Lunn 3740977644cSAndrew Lunn dev_err(chip->dev, "ATU problem: error %d while handling interrupt\n", 3750977644cSAndrew Lunn err); 3760977644cSAndrew Lunn return IRQ_HANDLED; 3770977644cSAndrew Lunn } 3780977644cSAndrew Lunn 3790977644cSAndrew Lunn int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip) 3800977644cSAndrew Lunn { 3810977644cSAndrew Lunn int err; 3820977644cSAndrew Lunn 3830977644cSAndrew Lunn chip->atu_prob_irq = irq_find_mapping(chip->g1_irq.domain, 3840977644cSAndrew Lunn MV88E6XXX_G1_STS_IRQ_ATU_PROB); 3850977644cSAndrew Lunn if (chip->atu_prob_irq < 0) 3869b662a3eSAndrew Lunn return chip->atu_prob_irq; 3870977644cSAndrew Lunn 3880977644cSAndrew Lunn err = request_threaded_irq(chip->atu_prob_irq, NULL, 3890977644cSAndrew Lunn mv88e6xxx_g1_atu_prob_irq_thread_fn, 3900977644cSAndrew Lunn IRQF_ONESHOT, "mv88e6xxx-g1-atu-prob", 3910977644cSAndrew Lunn chip); 3920977644cSAndrew Lunn if (err) 3930977644cSAndrew Lunn irq_dispose_mapping(chip->atu_prob_irq); 3940977644cSAndrew Lunn 3950977644cSAndrew Lunn return err; 3960977644cSAndrew Lunn } 3970977644cSAndrew Lunn 3980977644cSAndrew Lunn void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip) 3990977644cSAndrew Lunn { 4000977644cSAndrew Lunn free_irq(chip->atu_prob_irq, chip); 4010977644cSAndrew Lunn irq_dispose_mapping(chip->atu_prob_irq); 4020977644cSAndrew Lunn } 403