1720c6343SVivien Didelot /* 2720c6343SVivien Didelot * Marvell 88E6xxx Address Translation Unit (ATU) support 3720c6343SVivien Didelot * 4720c6343SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 5720c6343SVivien Didelot * Copyright (c) 2017 Savoir-faire Linux, Inc. 6720c6343SVivien Didelot * 7720c6343SVivien Didelot * This program is free software; you can redistribute it and/or modify 8720c6343SVivien Didelot * it under the terms of the GNU General Public License as published by 9720c6343SVivien Didelot * the Free Software Foundation; either version 2 of the License, or 10720c6343SVivien Didelot * (at your option) any later version. 11720c6343SVivien Didelot */ 120977644cSAndrew Lunn #include <linux/interrupt.h> 130977644cSAndrew Lunn #include <linux/irqdomain.h> 14720c6343SVivien Didelot 154d5f2ba7SVivien Didelot #include "chip.h" 16720c6343SVivien Didelot #include "global1.h" 17720c6343SVivien Didelot 189c13c026SVivien Didelot /* Offset 0x01: ATU FID Register */ 199c13c026SVivien Didelot 209c13c026SVivien Didelot static int mv88e6xxx_g1_atu_fid_write(struct mv88e6xxx_chip *chip, u16 fid) 219c13c026SVivien Didelot { 2227c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6352_G1_ATU_FID, fid & 0xfff); 239c13c026SVivien Didelot } 249c13c026SVivien Didelot 25720c6343SVivien Didelot /* Offset 0x0A: ATU Control Register */ 26720c6343SVivien Didelot 27c3a7d4adSVivien Didelot int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all) 28c3a7d4adSVivien Didelot { 29c3a7d4adSVivien Didelot u16 val; 30c3a7d4adSVivien Didelot int err; 31c3a7d4adSVivien Didelot 3227c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 33c3a7d4adSVivien Didelot if (err) 34c3a7d4adSVivien Didelot return err; 35c3a7d4adSVivien Didelot 36c3a7d4adSVivien Didelot if (learn2all) 3727c0e600SVivien Didelot val |= MV88E6XXX_G1_ATU_CTL_LEARN2ALL; 38c3a7d4adSVivien Didelot else 3927c0e600SVivien Didelot val &= ~MV88E6XXX_G1_ATU_CTL_LEARN2ALL; 40c3a7d4adSVivien Didelot 4127c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); 42c3a7d4adSVivien Didelot } 43c3a7d4adSVivien Didelot 44720c6343SVivien Didelot int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip, 45720c6343SVivien Didelot unsigned int msecs) 46720c6343SVivien Didelot { 47720c6343SVivien Didelot const unsigned int coeff = chip->info->age_time_coeff; 48720c6343SVivien Didelot const unsigned int min = 0x01 * coeff; 49720c6343SVivien Didelot const unsigned int max = 0xff * coeff; 50720c6343SVivien Didelot u8 age_time; 51720c6343SVivien Didelot u16 val; 52720c6343SVivien Didelot int err; 53720c6343SVivien Didelot 54720c6343SVivien Didelot if (msecs < min || msecs > max) 55720c6343SVivien Didelot return -ERANGE; 56720c6343SVivien Didelot 57720c6343SVivien Didelot /* Round to nearest multiple of coeff */ 58720c6343SVivien Didelot age_time = (msecs + coeff / 2) / coeff; 59720c6343SVivien Didelot 6027c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 61720c6343SVivien Didelot if (err) 62720c6343SVivien Didelot return err; 63720c6343SVivien Didelot 64720c6343SVivien Didelot /* AgeTime is 11:4 bits */ 65720c6343SVivien Didelot val &= ~0xff0; 66720c6343SVivien Didelot val |= age_time << 4; 67720c6343SVivien Didelot 6827c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); 69bae76dd9SVivien Didelot if (err) 70bae76dd9SVivien Didelot return err; 71bae76dd9SVivien Didelot 72bae76dd9SVivien Didelot dev_dbg(chip->dev, "AgeTime set to 0x%02x (%d ms)\n", age_time, 73bae76dd9SVivien Didelot age_time * coeff); 74bae76dd9SVivien Didelot 75bae76dd9SVivien Didelot return 0; 76720c6343SVivien Didelot } 779c13c026SVivien Didelot 789c13c026SVivien Didelot /* Offset 0x0B: ATU Operation Register */ 799c13c026SVivien Didelot 809c13c026SVivien Didelot static int mv88e6xxx_g1_atu_op_wait(struct mv88e6xxx_chip *chip) 819c13c026SVivien Didelot { 8227c0e600SVivien Didelot return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_ATU_OP, 8327c0e600SVivien Didelot MV88E6XXX_G1_ATU_OP_BUSY); 849c13c026SVivien Didelot } 859c13c026SVivien Didelot 869c13c026SVivien Didelot static int mv88e6xxx_g1_atu_op(struct mv88e6xxx_chip *chip, u16 fid, u16 op) 879c13c026SVivien Didelot { 889c13c026SVivien Didelot u16 val; 899c13c026SVivien Didelot int err; 909c13c026SVivien Didelot 919c13c026SVivien Didelot /* FID bits are dispatched all around gradually as more are supported */ 929c13c026SVivien Didelot if (mv88e6xxx_num_databases(chip) > 256) { 939c13c026SVivien Didelot err = mv88e6xxx_g1_atu_fid_write(chip, fid); 949c13c026SVivien Didelot if (err) 959c13c026SVivien Didelot return err; 969c13c026SVivien Didelot } else { 977b83df0dSRasmus Villemoes if (mv88e6xxx_num_databases(chip) > 64) { 989c13c026SVivien Didelot /* ATU DBNum[7:4] are located in ATU Control 15:12 */ 9927c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, 10027c0e600SVivien Didelot &val); 1019c13c026SVivien Didelot if (err) 1029c13c026SVivien Didelot return err; 1039c13c026SVivien Didelot 1049c13c026SVivien Didelot val = (val & 0x0fff) | ((fid << 8) & 0xf000); 10527c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, 10627c0e600SVivien Didelot val); 1079c13c026SVivien Didelot if (err) 1089c13c026SVivien Didelot return err; 1097b83df0dSRasmus Villemoes } else if (mv88e6xxx_num_databases(chip) > 16) { 1107b83df0dSRasmus Villemoes /* ATU DBNum[5:4] are located in ATU Operation 9:8 */ 1117b83df0dSRasmus Villemoes op |= (fid & 0x30) << 4; 1129c13c026SVivien Didelot } 1139c13c026SVivien Didelot 1149c13c026SVivien Didelot /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ 1159c13c026SVivien Didelot op |= fid & 0xf; 1169c13c026SVivien Didelot } 1179c13c026SVivien Didelot 11827c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_OP, 11927c0e600SVivien Didelot MV88E6XXX_G1_ATU_OP_BUSY | op); 1209c13c026SVivien Didelot if (err) 1219c13c026SVivien Didelot return err; 1229c13c026SVivien Didelot 1239c13c026SVivien Didelot return mv88e6xxx_g1_atu_op_wait(chip); 1249c13c026SVivien Didelot } 1259c13c026SVivien Didelot 1269c13c026SVivien Didelot /* Offset 0x0C: ATU Data Register */ 1279c13c026SVivien Didelot 128dabc1a96SVivien Didelot static int mv88e6xxx_g1_atu_data_read(struct mv88e6xxx_chip *chip, 129dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 130dabc1a96SVivien Didelot { 131dabc1a96SVivien Didelot u16 val; 132dabc1a96SVivien Didelot int err; 133dabc1a96SVivien Didelot 13427c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_DATA, &val); 135dabc1a96SVivien Didelot if (err) 136dabc1a96SVivien Didelot return err; 137dabc1a96SVivien Didelot 138dabc1a96SVivien Didelot entry->state = val & 0xf; 13927c0e600SVivien Didelot if (entry->state != MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 14027c0e600SVivien Didelot entry->trunk = !!(val & MV88E6XXX_G1_ATU_DATA_TRUNK); 14101bd96c8SVivien Didelot entry->portvec = (val >> 4) & mv88e6xxx_port_mask(chip); 142dabc1a96SVivien Didelot } 143dabc1a96SVivien Didelot 144dabc1a96SVivien Didelot return 0; 145dabc1a96SVivien Didelot } 146dabc1a96SVivien Didelot 1479c13c026SVivien Didelot static int mv88e6xxx_g1_atu_data_write(struct mv88e6xxx_chip *chip, 1489c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 1499c13c026SVivien Didelot { 1509c13c026SVivien Didelot u16 data = entry->state & 0xf; 1519c13c026SVivien Didelot 15227c0e600SVivien Didelot if (entry->state != MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1539c13c026SVivien Didelot if (entry->trunk) 15427c0e600SVivien Didelot data |= MV88E6XXX_G1_ATU_DATA_TRUNK; 1559c13c026SVivien Didelot 15601bd96c8SVivien Didelot data |= (entry->portvec & mv88e6xxx_port_mask(chip)) << 4; 1579c13c026SVivien Didelot } 1589c13c026SVivien Didelot 15927c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_DATA, data); 1609c13c026SVivien Didelot } 1619c13c026SVivien Didelot 1629c13c026SVivien Didelot /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1 1639c13c026SVivien Didelot * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3 1649c13c026SVivien Didelot * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5 1659c13c026SVivien Didelot */ 1669c13c026SVivien Didelot 167dabc1a96SVivien Didelot static int mv88e6xxx_g1_atu_mac_read(struct mv88e6xxx_chip *chip, 168dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 169dabc1a96SVivien Didelot { 170dabc1a96SVivien Didelot u16 val; 171dabc1a96SVivien Didelot int i, err; 172dabc1a96SVivien Didelot 173dabc1a96SVivien Didelot for (i = 0; i < 3; i++) { 17427c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_MAC01 + i, &val); 175dabc1a96SVivien Didelot if (err) 176dabc1a96SVivien Didelot return err; 177dabc1a96SVivien Didelot 178dabc1a96SVivien Didelot entry->mac[i * 2] = val >> 8; 179dabc1a96SVivien Didelot entry->mac[i * 2 + 1] = val & 0xff; 180dabc1a96SVivien Didelot } 181dabc1a96SVivien Didelot 182dabc1a96SVivien Didelot return 0; 183dabc1a96SVivien Didelot } 184dabc1a96SVivien Didelot 1859c13c026SVivien Didelot static int mv88e6xxx_g1_atu_mac_write(struct mv88e6xxx_chip *chip, 1869c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 1879c13c026SVivien Didelot { 1889c13c026SVivien Didelot u16 val; 1899c13c026SVivien Didelot int i, err; 1909c13c026SVivien Didelot 1919c13c026SVivien Didelot for (i = 0; i < 3; i++) { 1929c13c026SVivien Didelot val = (entry->mac[i * 2] << 8) | entry->mac[i * 2 + 1]; 19327c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_MAC01 + i, val); 1949c13c026SVivien Didelot if (err) 1959c13c026SVivien Didelot return err; 1969c13c026SVivien Didelot } 1979c13c026SVivien Didelot 1989c13c026SVivien Didelot return 0; 1999c13c026SVivien Didelot } 2009c13c026SVivien Didelot 2019c13c026SVivien Didelot /* Address Translation Unit operations */ 2029c13c026SVivien Didelot 203dabc1a96SVivien Didelot int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 204dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 205dabc1a96SVivien Didelot { 206dabc1a96SVivien Didelot int err; 207dabc1a96SVivien Didelot 208dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 209dabc1a96SVivien Didelot if (err) 210dabc1a96SVivien Didelot return err; 211dabc1a96SVivien Didelot 212dabc1a96SVivien Didelot /* Write the MAC address to iterate from only once */ 21327c0e600SVivien Didelot if (entry->state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 214dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_mac_write(chip, entry); 215dabc1a96SVivien Didelot if (err) 216dabc1a96SVivien Didelot return err; 217dabc1a96SVivien Didelot } 218dabc1a96SVivien Didelot 21927c0e600SVivien Didelot err = mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB); 220dabc1a96SVivien Didelot if (err) 221dabc1a96SVivien Didelot return err; 222dabc1a96SVivien Didelot 223dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_data_read(chip, entry); 224dabc1a96SVivien Didelot if (err) 225dabc1a96SVivien Didelot return err; 226dabc1a96SVivien Didelot 227dabc1a96SVivien Didelot return mv88e6xxx_g1_atu_mac_read(chip, entry); 228dabc1a96SVivien Didelot } 229dabc1a96SVivien Didelot 2309c13c026SVivien Didelot int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid, 2319c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 2329c13c026SVivien Didelot { 2339c13c026SVivien Didelot int err; 2349c13c026SVivien Didelot 2359c13c026SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 2369c13c026SVivien Didelot if (err) 2379c13c026SVivien Didelot return err; 2389c13c026SVivien Didelot 2399c13c026SVivien Didelot err = mv88e6xxx_g1_atu_mac_write(chip, entry); 2409c13c026SVivien Didelot if (err) 2419c13c026SVivien Didelot return err; 2429c13c026SVivien Didelot 2439c13c026SVivien Didelot err = mv88e6xxx_g1_atu_data_write(chip, entry); 2449c13c026SVivien Didelot if (err) 2459c13c026SVivien Didelot return err; 2469c13c026SVivien Didelot 24727c0e600SVivien Didelot return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_LOAD_DB); 2489c13c026SVivien Didelot } 249daefc943SVivien Didelot 250daefc943SVivien Didelot static int mv88e6xxx_g1_atu_flushmove(struct mv88e6xxx_chip *chip, u16 fid, 251daefc943SVivien Didelot struct mv88e6xxx_atu_entry *entry, 252daefc943SVivien Didelot bool all) 253daefc943SVivien Didelot { 254daefc943SVivien Didelot u16 op; 255daefc943SVivien Didelot int err; 256daefc943SVivien Didelot 257daefc943SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 258daefc943SVivien Didelot if (err) 259daefc943SVivien Didelot return err; 260daefc943SVivien Didelot 261daefc943SVivien Didelot err = mv88e6xxx_g1_atu_data_write(chip, entry); 262daefc943SVivien Didelot if (err) 263daefc943SVivien Didelot return err; 264daefc943SVivien Didelot 265daefc943SVivien Didelot /* Flush/Move all or non-static entries from all or a given database */ 266daefc943SVivien Didelot if (all && fid) 26727c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB; 268daefc943SVivien Didelot else if (fid) 26927c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; 270daefc943SVivien Didelot else if (all) 27127c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL; 272daefc943SVivien Didelot else 27327c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC; 274daefc943SVivien Didelot 275daefc943SVivien Didelot return mv88e6xxx_g1_atu_op(chip, fid, op); 276daefc943SVivien Didelot } 277daefc943SVivien Didelot 278daefc943SVivien Didelot int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all) 279daefc943SVivien Didelot { 280daefc943SVivien Didelot struct mv88e6xxx_atu_entry entry = { 281daefc943SVivien Didelot .state = 0, /* Null EntryState means Flush */ 282daefc943SVivien Didelot }; 283daefc943SVivien Didelot 284daefc943SVivien Didelot return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all); 285daefc943SVivien Didelot } 286e606ca36SVivien Didelot 287e606ca36SVivien Didelot static int mv88e6xxx_g1_atu_move(struct mv88e6xxx_chip *chip, u16 fid, 288e606ca36SVivien Didelot int from_port, int to_port, bool all) 289e606ca36SVivien Didelot { 290e606ca36SVivien Didelot struct mv88e6xxx_atu_entry entry = { 0 }; 291e606ca36SVivien Didelot unsigned long mask; 292e606ca36SVivien Didelot int shift; 293e606ca36SVivien Didelot 294e606ca36SVivien Didelot if (!chip->info->atu_move_port_mask) 295e606ca36SVivien Didelot return -EOPNOTSUPP; 296e606ca36SVivien Didelot 297e606ca36SVivien Didelot mask = chip->info->atu_move_port_mask; 298e606ca36SVivien Didelot shift = bitmap_weight(&mask, 16); 299e606ca36SVivien Didelot 300e606ca36SVivien Didelot entry.state = 0xf, /* Full EntryState means Move */ 30101bd96c8SVivien Didelot entry.portvec = from_port & mask; 30201bd96c8SVivien Didelot entry.portvec |= (to_port & mask) << shift; 303e606ca36SVivien Didelot 304e606ca36SVivien Didelot return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all); 305e606ca36SVivien Didelot } 306e606ca36SVivien Didelot 307e606ca36SVivien Didelot int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port, 308e606ca36SVivien Didelot bool all) 309e606ca36SVivien Didelot { 310e606ca36SVivien Didelot int from_port = port; 311e606ca36SVivien Didelot int to_port = chip->info->atu_move_port_mask; 312e606ca36SVivien Didelot 313e606ca36SVivien Didelot return mv88e6xxx_g1_atu_move(chip, fid, from_port, to_port, all); 314e606ca36SVivien Didelot } 3150977644cSAndrew Lunn 3160977644cSAndrew Lunn static irqreturn_t mv88e6xxx_g1_atu_prob_irq_thread_fn(int irq, void *dev_id) 3170977644cSAndrew Lunn { 3180977644cSAndrew Lunn struct mv88e6xxx_chip *chip = dev_id; 3190977644cSAndrew Lunn struct mv88e6xxx_atu_entry entry; 32075c05a74SAndrew Lunn int spid; 3210977644cSAndrew Lunn int err; 3220977644cSAndrew Lunn u16 val; 3230977644cSAndrew Lunn 3240977644cSAndrew Lunn mutex_lock(&chip->reg_lock); 3250977644cSAndrew Lunn 3260977644cSAndrew Lunn err = mv88e6xxx_g1_atu_op(chip, 0, 3270977644cSAndrew Lunn MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION); 3280977644cSAndrew Lunn if (err) 3290977644cSAndrew Lunn goto out; 3300977644cSAndrew Lunn 3310977644cSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_OP, &val); 3320977644cSAndrew Lunn if (err) 3330977644cSAndrew Lunn goto out; 3340977644cSAndrew Lunn 3350977644cSAndrew Lunn err = mv88e6xxx_g1_atu_data_read(chip, &entry); 3360977644cSAndrew Lunn if (err) 3370977644cSAndrew Lunn goto out; 3380977644cSAndrew Lunn 3390977644cSAndrew Lunn err = mv88e6xxx_g1_atu_mac_read(chip, &entry); 3400977644cSAndrew Lunn if (err) 3410977644cSAndrew Lunn goto out; 3420977644cSAndrew Lunn 34375c05a74SAndrew Lunn spid = entry.state; 34475c05a74SAndrew Lunn 3450977644cSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION) { 3460977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 3470977644cSAndrew Lunn "ATU age out violation for %pM\n", 3480977644cSAndrew Lunn entry.mac); 3490977644cSAndrew Lunn } 3500977644cSAndrew Lunn 3510977644cSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION) { 3520977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 35375c05a74SAndrew Lunn "ATU member violation for %pM portvec %x spid %d\n", 35475c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 35575c05a74SAndrew Lunn chip->ports[spid].atu_member_violation++; 3560977644cSAndrew Lunn } 3570977644cSAndrew Lunn 358ddca24dfSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_MISS_VIOLATION) { 3590977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 36075c05a74SAndrew Lunn "ATU miss violation for %pM portvec %x spid %d\n", 36175c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 36275c05a74SAndrew Lunn chip->ports[spid].atu_miss_violation++; 36365f60e45SAndrew Lunn } 3640977644cSAndrew Lunn 36565f60e45SAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_FULL_VIOLATION) { 3660977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 36775c05a74SAndrew Lunn "ATU full violation for %pM portvec %x spid %d\n", 36875c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 36975c05a74SAndrew Lunn chip->ports[spid].atu_full_violation++; 37065f60e45SAndrew Lunn } 37165f60e45SAndrew Lunn mutex_unlock(&chip->reg_lock); 3720977644cSAndrew Lunn 3730977644cSAndrew Lunn return IRQ_HANDLED; 3740977644cSAndrew Lunn 3750977644cSAndrew Lunn out: 3760977644cSAndrew Lunn mutex_unlock(&chip->reg_lock); 3770977644cSAndrew Lunn 3780977644cSAndrew Lunn dev_err(chip->dev, "ATU problem: error %d while handling interrupt\n", 3790977644cSAndrew Lunn err); 3800977644cSAndrew Lunn return IRQ_HANDLED; 3810977644cSAndrew Lunn } 3820977644cSAndrew Lunn 3830977644cSAndrew Lunn int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip) 3840977644cSAndrew Lunn { 3850977644cSAndrew Lunn int err; 3860977644cSAndrew Lunn 3870977644cSAndrew Lunn chip->atu_prob_irq = irq_find_mapping(chip->g1_irq.domain, 3880977644cSAndrew Lunn MV88E6XXX_G1_STS_IRQ_ATU_PROB); 3890977644cSAndrew Lunn if (chip->atu_prob_irq < 0) 3909b662a3eSAndrew Lunn return chip->atu_prob_irq; 3910977644cSAndrew Lunn 3920977644cSAndrew Lunn err = request_threaded_irq(chip->atu_prob_irq, NULL, 3930977644cSAndrew Lunn mv88e6xxx_g1_atu_prob_irq_thread_fn, 3940977644cSAndrew Lunn IRQF_ONESHOT, "mv88e6xxx-g1-atu-prob", 3950977644cSAndrew Lunn chip); 3960977644cSAndrew Lunn if (err) 3970977644cSAndrew Lunn irq_dispose_mapping(chip->atu_prob_irq); 3980977644cSAndrew Lunn 3990977644cSAndrew Lunn return err; 4000977644cSAndrew Lunn } 4010977644cSAndrew Lunn 4020977644cSAndrew Lunn void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip) 4030977644cSAndrew Lunn { 4040977644cSAndrew Lunn free_irq(chip->atu_prob_irq, chip); 4050977644cSAndrew Lunn irq_dispose_mapping(chip->atu_prob_irq); 4060977644cSAndrew Lunn } 407