12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2720c6343SVivien Didelot /* 3720c6343SVivien Didelot * Marvell 88E6xxx Address Translation Unit (ATU) support 4720c6343SVivien Didelot * 5720c6343SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 6720c6343SVivien Didelot * Copyright (c) 2017 Savoir-faire Linux, Inc. 7720c6343SVivien Didelot */ 819fb7f69SVivien Didelot 919fb7f69SVivien Didelot #include <linux/bitfield.h> 100977644cSAndrew Lunn #include <linux/interrupt.h> 110977644cSAndrew Lunn #include <linux/irqdomain.h> 12720c6343SVivien Didelot 134d5f2ba7SVivien Didelot #include "chip.h" 14720c6343SVivien Didelot #include "global1.h" 15720c6343SVivien Didelot 169c13c026SVivien Didelot /* Offset 0x01: ATU FID Register */ 179c13c026SVivien Didelot 189c13c026SVivien Didelot static int mv88e6xxx_g1_atu_fid_write(struct mv88e6xxx_chip *chip, u16 fid) 199c13c026SVivien Didelot { 2027c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6352_G1_ATU_FID, fid & 0xfff); 219c13c026SVivien Didelot } 229c13c026SVivien Didelot 23720c6343SVivien Didelot /* Offset 0x0A: ATU Control Register */ 24720c6343SVivien Didelot 25c3a7d4adSVivien Didelot int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all) 26c3a7d4adSVivien Didelot { 27c3a7d4adSVivien Didelot u16 val; 28c3a7d4adSVivien Didelot int err; 29c3a7d4adSVivien Didelot 3027c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 31c3a7d4adSVivien Didelot if (err) 32c3a7d4adSVivien Didelot return err; 33c3a7d4adSVivien Didelot 34c3a7d4adSVivien Didelot if (learn2all) 3527c0e600SVivien Didelot val |= MV88E6XXX_G1_ATU_CTL_LEARN2ALL; 36c3a7d4adSVivien Didelot else 3727c0e600SVivien Didelot val &= ~MV88E6XXX_G1_ATU_CTL_LEARN2ALL; 38c3a7d4adSVivien Didelot 3927c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); 40c3a7d4adSVivien Didelot } 41c3a7d4adSVivien Didelot 42720c6343SVivien Didelot int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip, 43720c6343SVivien Didelot unsigned int msecs) 44720c6343SVivien Didelot { 45720c6343SVivien Didelot const unsigned int coeff = chip->info->age_time_coeff; 46720c6343SVivien Didelot const unsigned int min = 0x01 * coeff; 47720c6343SVivien Didelot const unsigned int max = 0xff * coeff; 48720c6343SVivien Didelot u8 age_time; 49720c6343SVivien Didelot u16 val; 50720c6343SVivien Didelot int err; 51720c6343SVivien Didelot 52720c6343SVivien Didelot if (msecs < min || msecs > max) 53720c6343SVivien Didelot return -ERANGE; 54720c6343SVivien Didelot 55720c6343SVivien Didelot /* Round to nearest multiple of coeff */ 56720c6343SVivien Didelot age_time = (msecs + coeff / 2) / coeff; 57720c6343SVivien Didelot 5827c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 59720c6343SVivien Didelot if (err) 60720c6343SVivien Didelot return err; 61720c6343SVivien Didelot 62720c6343SVivien Didelot /* AgeTime is 11:4 bits */ 63720c6343SVivien Didelot val &= ~0xff0; 64720c6343SVivien Didelot val |= age_time << 4; 65720c6343SVivien Didelot 6627c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); 67bae76dd9SVivien Didelot if (err) 68bae76dd9SVivien Didelot return err; 69bae76dd9SVivien Didelot 70bae76dd9SVivien Didelot dev_dbg(chip->dev, "AgeTime set to 0x%02x (%d ms)\n", age_time, 71bae76dd9SVivien Didelot age_time * coeff); 72bae76dd9SVivien Didelot 73bae76dd9SVivien Didelot return 0; 74720c6343SVivien Didelot } 759c13c026SVivien Didelot 7623e8b470SAndrew Lunn int mv88e6165_g1_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash) 7723e8b470SAndrew Lunn { 7823e8b470SAndrew Lunn int err; 7923e8b470SAndrew Lunn u16 val; 8023e8b470SAndrew Lunn 8123e8b470SAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 8223e8b470SAndrew Lunn if (err) 8323e8b470SAndrew Lunn return err; 8423e8b470SAndrew Lunn 8523e8b470SAndrew Lunn *hash = val & MV88E6161_G1_ATU_CTL_HASH_MASK; 8623e8b470SAndrew Lunn 8723e8b470SAndrew Lunn return 0; 8823e8b470SAndrew Lunn } 8923e8b470SAndrew Lunn 9023e8b470SAndrew Lunn int mv88e6165_g1_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash) 9123e8b470SAndrew Lunn { 9223e8b470SAndrew Lunn int err; 9323e8b470SAndrew Lunn u16 val; 9423e8b470SAndrew Lunn 9523e8b470SAndrew Lunn if (hash & ~MV88E6161_G1_ATU_CTL_HASH_MASK) 9623e8b470SAndrew Lunn return -EINVAL; 9723e8b470SAndrew Lunn 9823e8b470SAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 9923e8b470SAndrew Lunn if (err) 10023e8b470SAndrew Lunn return err; 10123e8b470SAndrew Lunn 10223e8b470SAndrew Lunn val &= ~MV88E6161_G1_ATU_CTL_HASH_MASK; 10323e8b470SAndrew Lunn val |= hash; 10423e8b470SAndrew Lunn 10523e8b470SAndrew Lunn return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); 10623e8b470SAndrew Lunn } 10723e8b470SAndrew Lunn 1089c13c026SVivien Didelot /* Offset 0x0B: ATU Operation Register */ 1099c13c026SVivien Didelot 1109c13c026SVivien Didelot static int mv88e6xxx_g1_atu_op_wait(struct mv88e6xxx_chip *chip) 1119c13c026SVivien Didelot { 11219fb7f69SVivien Didelot int bit = __bf_shf(MV88E6XXX_G1_ATU_OP_BUSY); 11319fb7f69SVivien Didelot 11419fb7f69SVivien Didelot return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_ATU_OP, bit, 0); 1159c13c026SVivien Didelot } 1169c13c026SVivien Didelot 1179c13c026SVivien Didelot static int mv88e6xxx_g1_atu_op(struct mv88e6xxx_chip *chip, u16 fid, u16 op) 1189c13c026SVivien Didelot { 1199c13c026SVivien Didelot u16 val; 1209c13c026SVivien Didelot int err; 1219c13c026SVivien Didelot 1229c13c026SVivien Didelot /* FID bits are dispatched all around gradually as more are supported */ 1239c13c026SVivien Didelot if (mv88e6xxx_num_databases(chip) > 256) { 1249c13c026SVivien Didelot err = mv88e6xxx_g1_atu_fid_write(chip, fid); 1259c13c026SVivien Didelot if (err) 1269c13c026SVivien Didelot return err; 1279c13c026SVivien Didelot } else { 1287b83df0dSRasmus Villemoes if (mv88e6xxx_num_databases(chip) > 64) { 1299c13c026SVivien Didelot /* ATU DBNum[7:4] are located in ATU Control 15:12 */ 13027c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, 13127c0e600SVivien Didelot &val); 1329c13c026SVivien Didelot if (err) 1339c13c026SVivien Didelot return err; 1349c13c026SVivien Didelot 1359c13c026SVivien Didelot val = (val & 0x0fff) | ((fid << 8) & 0xf000); 13627c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, 13727c0e600SVivien Didelot val); 1389c13c026SVivien Didelot if (err) 1399c13c026SVivien Didelot return err; 1407b83df0dSRasmus Villemoes } else if (mv88e6xxx_num_databases(chip) > 16) { 1417b83df0dSRasmus Villemoes /* ATU DBNum[5:4] are located in ATU Operation 9:8 */ 1427b83df0dSRasmus Villemoes op |= (fid & 0x30) << 4; 1439c13c026SVivien Didelot } 1449c13c026SVivien Didelot 1459c13c026SVivien Didelot /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ 1469c13c026SVivien Didelot op |= fid & 0xf; 1479c13c026SVivien Didelot } 1489c13c026SVivien Didelot 14927c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_OP, 15027c0e600SVivien Didelot MV88E6XXX_G1_ATU_OP_BUSY | op); 1519c13c026SVivien Didelot if (err) 1529c13c026SVivien Didelot return err; 1539c13c026SVivien Didelot 1549c13c026SVivien Didelot return mv88e6xxx_g1_atu_op_wait(chip); 1559c13c026SVivien Didelot } 1569c13c026SVivien Didelot 157c5f299d5SAndrew Lunn int mv88e6xxx_g1_atu_get_next(struct mv88e6xxx_chip *chip, u16 fid) 158c5f299d5SAndrew Lunn { 159c5f299d5SAndrew Lunn return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB); 160c5f299d5SAndrew Lunn } 161c5f299d5SAndrew Lunn 1629c13c026SVivien Didelot /* Offset 0x0C: ATU Data Register */ 1639c13c026SVivien Didelot 164dabc1a96SVivien Didelot static int mv88e6xxx_g1_atu_data_read(struct mv88e6xxx_chip *chip, 165dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 166dabc1a96SVivien Didelot { 167dabc1a96SVivien Didelot u16 val; 168dabc1a96SVivien Didelot int err; 169dabc1a96SVivien Didelot 17027c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_DATA, &val); 171dabc1a96SVivien Didelot if (err) 172dabc1a96SVivien Didelot return err; 173dabc1a96SVivien Didelot 174dabc1a96SVivien Didelot entry->state = val & 0xf; 175d8291a95SVivien Didelot if (entry->state) { 17627c0e600SVivien Didelot entry->trunk = !!(val & MV88E6XXX_G1_ATU_DATA_TRUNK); 17701bd96c8SVivien Didelot entry->portvec = (val >> 4) & mv88e6xxx_port_mask(chip); 178dabc1a96SVivien Didelot } 179dabc1a96SVivien Didelot 180dabc1a96SVivien Didelot return 0; 181dabc1a96SVivien Didelot } 182dabc1a96SVivien Didelot 1839c13c026SVivien Didelot static int mv88e6xxx_g1_atu_data_write(struct mv88e6xxx_chip *chip, 1849c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 1859c13c026SVivien Didelot { 1869c13c026SVivien Didelot u16 data = entry->state & 0xf; 1879c13c026SVivien Didelot 188d8291a95SVivien Didelot if (entry->state) { 1899c13c026SVivien Didelot if (entry->trunk) 19027c0e600SVivien Didelot data |= MV88E6XXX_G1_ATU_DATA_TRUNK; 1919c13c026SVivien Didelot 19201bd96c8SVivien Didelot data |= (entry->portvec & mv88e6xxx_port_mask(chip)) << 4; 1939c13c026SVivien Didelot } 1949c13c026SVivien Didelot 19527c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_DATA, data); 1969c13c026SVivien Didelot } 1979c13c026SVivien Didelot 1989c13c026SVivien Didelot /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1 1999c13c026SVivien Didelot * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3 2009c13c026SVivien Didelot * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5 2019c13c026SVivien Didelot */ 2029c13c026SVivien Didelot 203dabc1a96SVivien Didelot static int mv88e6xxx_g1_atu_mac_read(struct mv88e6xxx_chip *chip, 204dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 205dabc1a96SVivien Didelot { 206dabc1a96SVivien Didelot u16 val; 207dabc1a96SVivien Didelot int i, err; 208dabc1a96SVivien Didelot 209dabc1a96SVivien Didelot for (i = 0; i < 3; i++) { 21027c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_MAC01 + i, &val); 211dabc1a96SVivien Didelot if (err) 212dabc1a96SVivien Didelot return err; 213dabc1a96SVivien Didelot 214dabc1a96SVivien Didelot entry->mac[i * 2] = val >> 8; 215dabc1a96SVivien Didelot entry->mac[i * 2 + 1] = val & 0xff; 216dabc1a96SVivien Didelot } 217dabc1a96SVivien Didelot 218dabc1a96SVivien Didelot return 0; 219dabc1a96SVivien Didelot } 220dabc1a96SVivien Didelot 2219c13c026SVivien Didelot static int mv88e6xxx_g1_atu_mac_write(struct mv88e6xxx_chip *chip, 2229c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 2239c13c026SVivien Didelot { 2249c13c026SVivien Didelot u16 val; 2259c13c026SVivien Didelot int i, err; 2269c13c026SVivien Didelot 2279c13c026SVivien Didelot for (i = 0; i < 3; i++) { 2289c13c026SVivien Didelot val = (entry->mac[i * 2] << 8) | entry->mac[i * 2 + 1]; 22927c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_MAC01 + i, val); 2309c13c026SVivien Didelot if (err) 2319c13c026SVivien Didelot return err; 2329c13c026SVivien Didelot } 2339c13c026SVivien Didelot 2349c13c026SVivien Didelot return 0; 2359c13c026SVivien Didelot } 2369c13c026SVivien Didelot 2379c13c026SVivien Didelot /* Address Translation Unit operations */ 2389c13c026SVivien Didelot 239dabc1a96SVivien Didelot int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 240dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 241dabc1a96SVivien Didelot { 242dabc1a96SVivien Didelot int err; 243dabc1a96SVivien Didelot 244dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 245dabc1a96SVivien Didelot if (err) 246dabc1a96SVivien Didelot return err; 247dabc1a96SVivien Didelot 248dabc1a96SVivien Didelot /* Write the MAC address to iterate from only once */ 249d8291a95SVivien Didelot if (!entry->state) { 250dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_mac_write(chip, entry); 251dabc1a96SVivien Didelot if (err) 252dabc1a96SVivien Didelot return err; 253dabc1a96SVivien Didelot } 254dabc1a96SVivien Didelot 25527c0e600SVivien Didelot err = mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB); 256dabc1a96SVivien Didelot if (err) 257dabc1a96SVivien Didelot return err; 258dabc1a96SVivien Didelot 259dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_data_read(chip, entry); 260dabc1a96SVivien Didelot if (err) 261dabc1a96SVivien Didelot return err; 262dabc1a96SVivien Didelot 263dabc1a96SVivien Didelot return mv88e6xxx_g1_atu_mac_read(chip, entry); 264dabc1a96SVivien Didelot } 265dabc1a96SVivien Didelot 2669c13c026SVivien Didelot int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid, 2679c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 2689c13c026SVivien Didelot { 2699c13c026SVivien Didelot int err; 2709c13c026SVivien Didelot 2719c13c026SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 2729c13c026SVivien Didelot if (err) 2739c13c026SVivien Didelot return err; 2749c13c026SVivien Didelot 2759c13c026SVivien Didelot err = mv88e6xxx_g1_atu_mac_write(chip, entry); 2769c13c026SVivien Didelot if (err) 2779c13c026SVivien Didelot return err; 2789c13c026SVivien Didelot 2799c13c026SVivien Didelot err = mv88e6xxx_g1_atu_data_write(chip, entry); 2809c13c026SVivien Didelot if (err) 2819c13c026SVivien Didelot return err; 2829c13c026SVivien Didelot 28327c0e600SVivien Didelot return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_LOAD_DB); 2849c13c026SVivien Didelot } 285daefc943SVivien Didelot 286daefc943SVivien Didelot static int mv88e6xxx_g1_atu_flushmove(struct mv88e6xxx_chip *chip, u16 fid, 287daefc943SVivien Didelot struct mv88e6xxx_atu_entry *entry, 288daefc943SVivien Didelot bool all) 289daefc943SVivien Didelot { 290daefc943SVivien Didelot u16 op; 291daefc943SVivien Didelot int err; 292daefc943SVivien Didelot 293daefc943SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 294daefc943SVivien Didelot if (err) 295daefc943SVivien Didelot return err; 296daefc943SVivien Didelot 297daefc943SVivien Didelot err = mv88e6xxx_g1_atu_data_write(chip, entry); 298daefc943SVivien Didelot if (err) 299daefc943SVivien Didelot return err; 300daefc943SVivien Didelot 301daefc943SVivien Didelot /* Flush/Move all or non-static entries from all or a given database */ 302daefc943SVivien Didelot if (all && fid) 30327c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB; 304daefc943SVivien Didelot else if (fid) 30527c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; 306daefc943SVivien Didelot else if (all) 30727c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL; 308daefc943SVivien Didelot else 30927c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC; 310daefc943SVivien Didelot 311daefc943SVivien Didelot return mv88e6xxx_g1_atu_op(chip, fid, op); 312daefc943SVivien Didelot } 313daefc943SVivien Didelot 314daefc943SVivien Didelot int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all) 315daefc943SVivien Didelot { 316daefc943SVivien Didelot struct mv88e6xxx_atu_entry entry = { 317daefc943SVivien Didelot .state = 0, /* Null EntryState means Flush */ 318daefc943SVivien Didelot }; 319daefc943SVivien Didelot 320daefc943SVivien Didelot return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all); 321daefc943SVivien Didelot } 322e606ca36SVivien Didelot 323e606ca36SVivien Didelot static int mv88e6xxx_g1_atu_move(struct mv88e6xxx_chip *chip, u16 fid, 324e606ca36SVivien Didelot int from_port, int to_port, bool all) 325e606ca36SVivien Didelot { 326e606ca36SVivien Didelot struct mv88e6xxx_atu_entry entry = { 0 }; 327e606ca36SVivien Didelot unsigned long mask; 328e606ca36SVivien Didelot int shift; 329e606ca36SVivien Didelot 330e606ca36SVivien Didelot if (!chip->info->atu_move_port_mask) 331e606ca36SVivien Didelot return -EOPNOTSUPP; 332e606ca36SVivien Didelot 333e606ca36SVivien Didelot mask = chip->info->atu_move_port_mask; 334e606ca36SVivien Didelot shift = bitmap_weight(&mask, 16); 335e606ca36SVivien Didelot 336*59d4c93dSZheng Yongjun entry.state = 0xf; /* Full EntryState means Move */ 33701bd96c8SVivien Didelot entry.portvec = from_port & mask; 33801bd96c8SVivien Didelot entry.portvec |= (to_port & mask) << shift; 339e606ca36SVivien Didelot 340e606ca36SVivien Didelot return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all); 341e606ca36SVivien Didelot } 342e606ca36SVivien Didelot 343e606ca36SVivien Didelot int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port, 344e606ca36SVivien Didelot bool all) 345e606ca36SVivien Didelot { 346e606ca36SVivien Didelot int from_port = port; 347e606ca36SVivien Didelot int to_port = chip->info->atu_move_port_mask; 348e606ca36SVivien Didelot 349e606ca36SVivien Didelot return mv88e6xxx_g1_atu_move(chip, fid, from_port, to_port, all); 350e606ca36SVivien Didelot } 3510977644cSAndrew Lunn 3520977644cSAndrew Lunn static irqreturn_t mv88e6xxx_g1_atu_prob_irq_thread_fn(int irq, void *dev_id) 3530977644cSAndrew Lunn { 3540977644cSAndrew Lunn struct mv88e6xxx_chip *chip = dev_id; 3550977644cSAndrew Lunn struct mv88e6xxx_atu_entry entry; 35675c05a74SAndrew Lunn int spid; 3570977644cSAndrew Lunn int err; 3580977644cSAndrew Lunn u16 val; 3590977644cSAndrew Lunn 360c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip); 3610977644cSAndrew Lunn 3620977644cSAndrew Lunn err = mv88e6xxx_g1_atu_op(chip, 0, 3630977644cSAndrew Lunn MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION); 3640977644cSAndrew Lunn if (err) 3650977644cSAndrew Lunn goto out; 3660977644cSAndrew Lunn 3670977644cSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_OP, &val); 3680977644cSAndrew Lunn if (err) 3690977644cSAndrew Lunn goto out; 3700977644cSAndrew Lunn 3710977644cSAndrew Lunn err = mv88e6xxx_g1_atu_data_read(chip, &entry); 3720977644cSAndrew Lunn if (err) 3730977644cSAndrew Lunn goto out; 3740977644cSAndrew Lunn 3750977644cSAndrew Lunn err = mv88e6xxx_g1_atu_mac_read(chip, &entry); 3760977644cSAndrew Lunn if (err) 3770977644cSAndrew Lunn goto out; 3780977644cSAndrew Lunn 37975c05a74SAndrew Lunn spid = entry.state; 38075c05a74SAndrew Lunn 3810977644cSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION) { 3820977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 3830977644cSAndrew Lunn "ATU age out violation for %pM\n", 3840977644cSAndrew Lunn entry.mac); 3850977644cSAndrew Lunn } 3860977644cSAndrew Lunn 3870977644cSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION) { 3880977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 38975c05a74SAndrew Lunn "ATU member violation for %pM portvec %x spid %d\n", 39075c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 39175c05a74SAndrew Lunn chip->ports[spid].atu_member_violation++; 3920977644cSAndrew Lunn } 3930977644cSAndrew Lunn 394ddca24dfSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_MISS_VIOLATION) { 3950977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 39675c05a74SAndrew Lunn "ATU miss violation for %pM portvec %x spid %d\n", 39775c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 39875c05a74SAndrew Lunn chip->ports[spid].atu_miss_violation++; 39965f60e45SAndrew Lunn } 4000977644cSAndrew Lunn 40165f60e45SAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_FULL_VIOLATION) { 4020977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 40375c05a74SAndrew Lunn "ATU full violation for %pM portvec %x spid %d\n", 40475c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 40575c05a74SAndrew Lunn chip->ports[spid].atu_full_violation++; 40665f60e45SAndrew Lunn } 407c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip); 4080977644cSAndrew Lunn 4090977644cSAndrew Lunn return IRQ_HANDLED; 4100977644cSAndrew Lunn 4110977644cSAndrew Lunn out: 412c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip); 4130977644cSAndrew Lunn 4140977644cSAndrew Lunn dev_err(chip->dev, "ATU problem: error %d while handling interrupt\n", 4150977644cSAndrew Lunn err); 4160977644cSAndrew Lunn return IRQ_HANDLED; 4170977644cSAndrew Lunn } 4180977644cSAndrew Lunn 4190977644cSAndrew Lunn int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip) 4200977644cSAndrew Lunn { 4210977644cSAndrew Lunn int err; 4220977644cSAndrew Lunn 4230977644cSAndrew Lunn chip->atu_prob_irq = irq_find_mapping(chip->g1_irq.domain, 4240977644cSAndrew Lunn MV88E6XXX_G1_STS_IRQ_ATU_PROB); 4250977644cSAndrew Lunn if (chip->atu_prob_irq < 0) 4269b662a3eSAndrew Lunn return chip->atu_prob_irq; 4270977644cSAndrew Lunn 4288ddf0b56SAndrew Lunn snprintf(chip->atu_prob_irq_name, sizeof(chip->atu_prob_irq_name), 4298ddf0b56SAndrew Lunn "mv88e6xxx-%s-g1-atu-prob", dev_name(chip->dev)); 4308ddf0b56SAndrew Lunn 4310977644cSAndrew Lunn err = request_threaded_irq(chip->atu_prob_irq, NULL, 4320977644cSAndrew Lunn mv88e6xxx_g1_atu_prob_irq_thread_fn, 4338ddf0b56SAndrew Lunn IRQF_ONESHOT, chip->atu_prob_irq_name, 4340977644cSAndrew Lunn chip); 4350977644cSAndrew Lunn if (err) 4360977644cSAndrew Lunn irq_dispose_mapping(chip->atu_prob_irq); 4370977644cSAndrew Lunn 4380977644cSAndrew Lunn return err; 4390977644cSAndrew Lunn } 4400977644cSAndrew Lunn 4410977644cSAndrew Lunn void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip) 4420977644cSAndrew Lunn { 4430977644cSAndrew Lunn free_irq(chip->atu_prob_irq, chip); 4440977644cSAndrew Lunn irq_dispose_mapping(chip->atu_prob_irq); 4450977644cSAndrew Lunn } 446