12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2720c6343SVivien Didelot /* 3720c6343SVivien Didelot * Marvell 88E6xxx Address Translation Unit (ATU) support 4720c6343SVivien Didelot * 5720c6343SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 6720c6343SVivien Didelot * Copyright (c) 2017 Savoir-faire Linux, Inc. 7720c6343SVivien Didelot */ 819fb7f69SVivien Didelot 919fb7f69SVivien Didelot #include <linux/bitfield.h> 100977644cSAndrew Lunn #include <linux/interrupt.h> 110977644cSAndrew Lunn #include <linux/irqdomain.h> 12720c6343SVivien Didelot 134d5f2ba7SVivien Didelot #include "chip.h" 14720c6343SVivien Didelot #include "global1.h" 15720c6343SVivien Didelot 169c13c026SVivien Didelot /* Offset 0x01: ATU FID Register */ 179c13c026SVivien Didelot 189c13c026SVivien Didelot static int mv88e6xxx_g1_atu_fid_write(struct mv88e6xxx_chip *chip, u16 fid) 199c13c026SVivien Didelot { 2027c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6352_G1_ATU_FID, fid & 0xfff); 219c13c026SVivien Didelot } 229c13c026SVivien Didelot 23720c6343SVivien Didelot /* Offset 0x0A: ATU Control Register */ 24720c6343SVivien Didelot 25c3a7d4adSVivien Didelot int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all) 26c3a7d4adSVivien Didelot { 27c3a7d4adSVivien Didelot u16 val; 28c3a7d4adSVivien Didelot int err; 29c3a7d4adSVivien Didelot 3027c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 31c3a7d4adSVivien Didelot if (err) 32c3a7d4adSVivien Didelot return err; 33c3a7d4adSVivien Didelot 34c3a7d4adSVivien Didelot if (learn2all) 3527c0e600SVivien Didelot val |= MV88E6XXX_G1_ATU_CTL_LEARN2ALL; 36c3a7d4adSVivien Didelot else 3727c0e600SVivien Didelot val &= ~MV88E6XXX_G1_ATU_CTL_LEARN2ALL; 38c3a7d4adSVivien Didelot 3927c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); 40c3a7d4adSVivien Didelot } 41c3a7d4adSVivien Didelot 42720c6343SVivien Didelot int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip, 43720c6343SVivien Didelot unsigned int msecs) 44720c6343SVivien Didelot { 45720c6343SVivien Didelot const unsigned int coeff = chip->info->age_time_coeff; 46720c6343SVivien Didelot const unsigned int min = 0x01 * coeff; 47720c6343SVivien Didelot const unsigned int max = 0xff * coeff; 48720c6343SVivien Didelot u8 age_time; 49720c6343SVivien Didelot u16 val; 50720c6343SVivien Didelot int err; 51720c6343SVivien Didelot 52720c6343SVivien Didelot if (msecs < min || msecs > max) 53720c6343SVivien Didelot return -ERANGE; 54720c6343SVivien Didelot 55720c6343SVivien Didelot /* Round to nearest multiple of coeff */ 56720c6343SVivien Didelot age_time = (msecs + coeff / 2) / coeff; 57720c6343SVivien Didelot 5827c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 59720c6343SVivien Didelot if (err) 60720c6343SVivien Didelot return err; 61720c6343SVivien Didelot 62720c6343SVivien Didelot /* AgeTime is 11:4 bits */ 63720c6343SVivien Didelot val &= ~0xff0; 64720c6343SVivien Didelot val |= age_time << 4; 65720c6343SVivien Didelot 6627c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); 67bae76dd9SVivien Didelot if (err) 68bae76dd9SVivien Didelot return err; 69bae76dd9SVivien Didelot 70bae76dd9SVivien Didelot dev_dbg(chip->dev, "AgeTime set to 0x%02x (%d ms)\n", age_time, 71bae76dd9SVivien Didelot age_time * coeff); 72bae76dd9SVivien Didelot 73bae76dd9SVivien Didelot return 0; 74720c6343SVivien Didelot } 759c13c026SVivien Didelot 7623e8b470SAndrew Lunn int mv88e6165_g1_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash) 7723e8b470SAndrew Lunn { 7823e8b470SAndrew Lunn int err; 7923e8b470SAndrew Lunn u16 val; 8023e8b470SAndrew Lunn 8123e8b470SAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 8223e8b470SAndrew Lunn if (err) 8323e8b470SAndrew Lunn return err; 8423e8b470SAndrew Lunn 8523e8b470SAndrew Lunn *hash = val & MV88E6161_G1_ATU_CTL_HASH_MASK; 8623e8b470SAndrew Lunn 8723e8b470SAndrew Lunn return 0; 8823e8b470SAndrew Lunn } 8923e8b470SAndrew Lunn 9023e8b470SAndrew Lunn int mv88e6165_g1_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash) 9123e8b470SAndrew Lunn { 9223e8b470SAndrew Lunn int err; 9323e8b470SAndrew Lunn u16 val; 9423e8b470SAndrew Lunn 9523e8b470SAndrew Lunn if (hash & ~MV88E6161_G1_ATU_CTL_HASH_MASK) 9623e8b470SAndrew Lunn return -EINVAL; 9723e8b470SAndrew Lunn 9823e8b470SAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 9923e8b470SAndrew Lunn if (err) 10023e8b470SAndrew Lunn return err; 10123e8b470SAndrew Lunn 10223e8b470SAndrew Lunn val &= ~MV88E6161_G1_ATU_CTL_HASH_MASK; 10323e8b470SAndrew Lunn val |= hash; 10423e8b470SAndrew Lunn 10523e8b470SAndrew Lunn return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); 10623e8b470SAndrew Lunn } 10723e8b470SAndrew Lunn 1089c13c026SVivien Didelot /* Offset 0x0B: ATU Operation Register */ 1099c13c026SVivien Didelot 1109c13c026SVivien Didelot static int mv88e6xxx_g1_atu_op_wait(struct mv88e6xxx_chip *chip) 1119c13c026SVivien Didelot { 11219fb7f69SVivien Didelot int bit = __bf_shf(MV88E6XXX_G1_ATU_OP_BUSY); 11319fb7f69SVivien Didelot 11419fb7f69SVivien Didelot return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_ATU_OP, bit, 0); 1159c13c026SVivien Didelot } 1169c13c026SVivien Didelot 117*4bf24ad0SHans J. Schultz static int mv88e6xxx_g1_read_atu_violation(struct mv88e6xxx_chip *chip) 118*4bf24ad0SHans J. Schultz { 119*4bf24ad0SHans J. Schultz int err; 120*4bf24ad0SHans J. Schultz 121*4bf24ad0SHans J. Schultz err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_OP, 122*4bf24ad0SHans J. Schultz MV88E6XXX_G1_ATU_OP_BUSY | 123*4bf24ad0SHans J. Schultz MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION); 124*4bf24ad0SHans J. Schultz if (err) 125*4bf24ad0SHans J. Schultz return err; 126*4bf24ad0SHans J. Schultz 127*4bf24ad0SHans J. Schultz return mv88e6xxx_g1_atu_op_wait(chip); 128*4bf24ad0SHans J. Schultz } 129*4bf24ad0SHans J. Schultz 1309c13c026SVivien Didelot static int mv88e6xxx_g1_atu_op(struct mv88e6xxx_chip *chip, u16 fid, u16 op) 1319c13c026SVivien Didelot { 1329c13c026SVivien Didelot u16 val; 1339c13c026SVivien Didelot int err; 1349c13c026SVivien Didelot 1359c13c026SVivien Didelot /* FID bits are dispatched all around gradually as more are supported */ 1369c13c026SVivien Didelot if (mv88e6xxx_num_databases(chip) > 256) { 1379c13c026SVivien Didelot err = mv88e6xxx_g1_atu_fid_write(chip, fid); 1389c13c026SVivien Didelot if (err) 1399c13c026SVivien Didelot return err; 1409c13c026SVivien Didelot } else { 1417b83df0dSRasmus Villemoes if (mv88e6xxx_num_databases(chip) > 64) { 1429c13c026SVivien Didelot /* ATU DBNum[7:4] are located in ATU Control 15:12 */ 14327c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, 14427c0e600SVivien Didelot &val); 1459c13c026SVivien Didelot if (err) 1469c13c026SVivien Didelot return err; 1479c13c026SVivien Didelot 1489c13c026SVivien Didelot val = (val & 0x0fff) | ((fid << 8) & 0xf000); 14927c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, 15027c0e600SVivien Didelot val); 1519c13c026SVivien Didelot if (err) 1529c13c026SVivien Didelot return err; 1537b83df0dSRasmus Villemoes } else if (mv88e6xxx_num_databases(chip) > 16) { 1547b83df0dSRasmus Villemoes /* ATU DBNum[5:4] are located in ATU Operation 9:8 */ 1557b83df0dSRasmus Villemoes op |= (fid & 0x30) << 4; 1569c13c026SVivien Didelot } 1579c13c026SVivien Didelot 1589c13c026SVivien Didelot /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ 1599c13c026SVivien Didelot op |= fid & 0xf; 1609c13c026SVivien Didelot } 1619c13c026SVivien Didelot 16227c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_OP, 16327c0e600SVivien Didelot MV88E6XXX_G1_ATU_OP_BUSY | op); 1649c13c026SVivien Didelot if (err) 1659c13c026SVivien Didelot return err; 1669c13c026SVivien Didelot 1679c13c026SVivien Didelot return mv88e6xxx_g1_atu_op_wait(chip); 1689c13c026SVivien Didelot } 1699c13c026SVivien Didelot 170c5f299d5SAndrew Lunn int mv88e6xxx_g1_atu_get_next(struct mv88e6xxx_chip *chip, u16 fid) 171c5f299d5SAndrew Lunn { 172c5f299d5SAndrew Lunn return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB); 173c5f299d5SAndrew Lunn } 174c5f299d5SAndrew Lunn 175*4bf24ad0SHans J. Schultz static int mv88e6xxx_g1_atu_fid_read(struct mv88e6xxx_chip *chip, u16 *fid) 176*4bf24ad0SHans J. Schultz { 177*4bf24ad0SHans J. Schultz u16 val = 0, upper = 0, op = 0; 178*4bf24ad0SHans J. Schultz int err = -EOPNOTSUPP; 179*4bf24ad0SHans J. Schultz 180*4bf24ad0SHans J. Schultz if (mv88e6xxx_num_databases(chip) > 256) { 181*4bf24ad0SHans J. Schultz err = mv88e6xxx_g1_read(chip, MV88E6352_G1_ATU_FID, &val); 182*4bf24ad0SHans J. Schultz val &= 0xfff; 183*4bf24ad0SHans J. Schultz if (err) 184*4bf24ad0SHans J. Schultz return err; 185*4bf24ad0SHans J. Schultz } else { 186*4bf24ad0SHans J. Schultz err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_OP, &op); 187*4bf24ad0SHans J. Schultz if (err) 188*4bf24ad0SHans J. Schultz return err; 189*4bf24ad0SHans J. Schultz if (mv88e6xxx_num_databases(chip) > 64) { 190*4bf24ad0SHans J. Schultz /* ATU DBNum[7:4] are located in ATU Control 15:12 */ 191*4bf24ad0SHans J. Schultz err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, 192*4bf24ad0SHans J. Schultz &upper); 193*4bf24ad0SHans J. Schultz if (err) 194*4bf24ad0SHans J. Schultz return err; 195*4bf24ad0SHans J. Schultz 196*4bf24ad0SHans J. Schultz upper = (upper >> 8) & 0x00f0; 197*4bf24ad0SHans J. Schultz } else if (mv88e6xxx_num_databases(chip) > 16) { 198*4bf24ad0SHans J. Schultz /* ATU DBNum[5:4] are located in ATU Operation 9:8 */ 199*4bf24ad0SHans J. Schultz upper = (op >> 4) & 0x30; 200*4bf24ad0SHans J. Schultz } 201*4bf24ad0SHans J. Schultz 202*4bf24ad0SHans J. Schultz /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ 203*4bf24ad0SHans J. Schultz val = (op & 0xf) | upper; 204*4bf24ad0SHans J. Schultz } 205*4bf24ad0SHans J. Schultz *fid = val; 206*4bf24ad0SHans J. Schultz 207*4bf24ad0SHans J. Schultz return err; 208*4bf24ad0SHans J. Schultz } 209*4bf24ad0SHans J. Schultz 2109c13c026SVivien Didelot /* Offset 0x0C: ATU Data Register */ 2119c13c026SVivien Didelot 212dabc1a96SVivien Didelot static int mv88e6xxx_g1_atu_data_read(struct mv88e6xxx_chip *chip, 213dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 214dabc1a96SVivien Didelot { 215dabc1a96SVivien Didelot u16 val; 216dabc1a96SVivien Didelot int err; 217dabc1a96SVivien Didelot 21827c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_DATA, &val); 219dabc1a96SVivien Didelot if (err) 220dabc1a96SVivien Didelot return err; 221dabc1a96SVivien Didelot 222dabc1a96SVivien Didelot entry->state = val & 0xf; 223d8291a95SVivien Didelot if (entry->state) { 22427c0e600SVivien Didelot entry->trunk = !!(val & MV88E6XXX_G1_ATU_DATA_TRUNK); 22501bd96c8SVivien Didelot entry->portvec = (val >> 4) & mv88e6xxx_port_mask(chip); 226dabc1a96SVivien Didelot } 227dabc1a96SVivien Didelot 228dabc1a96SVivien Didelot return 0; 229dabc1a96SVivien Didelot } 230dabc1a96SVivien Didelot 2319c13c026SVivien Didelot static int mv88e6xxx_g1_atu_data_write(struct mv88e6xxx_chip *chip, 2329c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 2339c13c026SVivien Didelot { 2349c13c026SVivien Didelot u16 data = entry->state & 0xf; 2359c13c026SVivien Didelot 236d8291a95SVivien Didelot if (entry->state) { 2379c13c026SVivien Didelot if (entry->trunk) 23827c0e600SVivien Didelot data |= MV88E6XXX_G1_ATU_DATA_TRUNK; 2399c13c026SVivien Didelot 24001bd96c8SVivien Didelot data |= (entry->portvec & mv88e6xxx_port_mask(chip)) << 4; 2419c13c026SVivien Didelot } 2429c13c026SVivien Didelot 24327c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_DATA, data); 2449c13c026SVivien Didelot } 2459c13c026SVivien Didelot 2469c13c026SVivien Didelot /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1 2479c13c026SVivien Didelot * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3 2489c13c026SVivien Didelot * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5 2499c13c026SVivien Didelot */ 2509c13c026SVivien Didelot 251dabc1a96SVivien Didelot static int mv88e6xxx_g1_atu_mac_read(struct mv88e6xxx_chip *chip, 252dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 253dabc1a96SVivien Didelot { 254dabc1a96SVivien Didelot u16 val; 255dabc1a96SVivien Didelot int i, err; 256dabc1a96SVivien Didelot 257dabc1a96SVivien Didelot for (i = 0; i < 3; i++) { 25827c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_MAC01 + i, &val); 259dabc1a96SVivien Didelot if (err) 260dabc1a96SVivien Didelot return err; 261dabc1a96SVivien Didelot 262dabc1a96SVivien Didelot entry->mac[i * 2] = val >> 8; 263dabc1a96SVivien Didelot entry->mac[i * 2 + 1] = val & 0xff; 264dabc1a96SVivien Didelot } 265dabc1a96SVivien Didelot 266dabc1a96SVivien Didelot return 0; 267dabc1a96SVivien Didelot } 268dabc1a96SVivien Didelot 2699c13c026SVivien Didelot static int mv88e6xxx_g1_atu_mac_write(struct mv88e6xxx_chip *chip, 2709c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 2719c13c026SVivien Didelot { 2729c13c026SVivien Didelot u16 val; 2739c13c026SVivien Didelot int i, err; 2749c13c026SVivien Didelot 2759c13c026SVivien Didelot for (i = 0; i < 3; i++) { 2769c13c026SVivien Didelot val = (entry->mac[i * 2] << 8) | entry->mac[i * 2 + 1]; 27727c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_MAC01 + i, val); 2789c13c026SVivien Didelot if (err) 2799c13c026SVivien Didelot return err; 2809c13c026SVivien Didelot } 2819c13c026SVivien Didelot 2829c13c026SVivien Didelot return 0; 2839c13c026SVivien Didelot } 2849c13c026SVivien Didelot 2859c13c026SVivien Didelot /* Address Translation Unit operations */ 2869c13c026SVivien Didelot 287dabc1a96SVivien Didelot int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 288dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 289dabc1a96SVivien Didelot { 290dabc1a96SVivien Didelot int err; 291dabc1a96SVivien Didelot 292dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 293dabc1a96SVivien Didelot if (err) 294dabc1a96SVivien Didelot return err; 295dabc1a96SVivien Didelot 296dabc1a96SVivien Didelot /* Write the MAC address to iterate from only once */ 297d8291a95SVivien Didelot if (!entry->state) { 298dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_mac_write(chip, entry); 299dabc1a96SVivien Didelot if (err) 300dabc1a96SVivien Didelot return err; 301dabc1a96SVivien Didelot } 302dabc1a96SVivien Didelot 30327c0e600SVivien Didelot err = mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB); 304dabc1a96SVivien Didelot if (err) 305dabc1a96SVivien Didelot return err; 306dabc1a96SVivien Didelot 307dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_data_read(chip, entry); 308dabc1a96SVivien Didelot if (err) 309dabc1a96SVivien Didelot return err; 310dabc1a96SVivien Didelot 311dabc1a96SVivien Didelot return mv88e6xxx_g1_atu_mac_read(chip, entry); 312dabc1a96SVivien Didelot } 313dabc1a96SVivien Didelot 3149c13c026SVivien Didelot int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid, 3159c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 3169c13c026SVivien Didelot { 3179c13c026SVivien Didelot int err; 3189c13c026SVivien Didelot 3199c13c026SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 3209c13c026SVivien Didelot if (err) 3219c13c026SVivien Didelot return err; 3229c13c026SVivien Didelot 3239c13c026SVivien Didelot err = mv88e6xxx_g1_atu_mac_write(chip, entry); 3249c13c026SVivien Didelot if (err) 3259c13c026SVivien Didelot return err; 3269c13c026SVivien Didelot 3279c13c026SVivien Didelot err = mv88e6xxx_g1_atu_data_write(chip, entry); 3289c13c026SVivien Didelot if (err) 3299c13c026SVivien Didelot return err; 3309c13c026SVivien Didelot 33127c0e600SVivien Didelot return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_LOAD_DB); 3329c13c026SVivien Didelot } 333daefc943SVivien Didelot 334daefc943SVivien Didelot static int mv88e6xxx_g1_atu_flushmove(struct mv88e6xxx_chip *chip, u16 fid, 335daefc943SVivien Didelot struct mv88e6xxx_atu_entry *entry, 336daefc943SVivien Didelot bool all) 337daefc943SVivien Didelot { 338daefc943SVivien Didelot u16 op; 339daefc943SVivien Didelot int err; 340daefc943SVivien Didelot 341daefc943SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 342daefc943SVivien Didelot if (err) 343daefc943SVivien Didelot return err; 344daefc943SVivien Didelot 345daefc943SVivien Didelot err = mv88e6xxx_g1_atu_data_write(chip, entry); 346daefc943SVivien Didelot if (err) 347daefc943SVivien Didelot return err; 348daefc943SVivien Didelot 349daefc943SVivien Didelot /* Flush/Move all or non-static entries from all or a given database */ 350daefc943SVivien Didelot if (all && fid) 35127c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB; 352daefc943SVivien Didelot else if (fid) 35327c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; 354daefc943SVivien Didelot else if (all) 35527c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL; 356daefc943SVivien Didelot else 35727c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC; 358daefc943SVivien Didelot 359daefc943SVivien Didelot return mv88e6xxx_g1_atu_op(chip, fid, op); 360daefc943SVivien Didelot } 361daefc943SVivien Didelot 362daefc943SVivien Didelot int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all) 363daefc943SVivien Didelot { 364daefc943SVivien Didelot struct mv88e6xxx_atu_entry entry = { 365daefc943SVivien Didelot .state = 0, /* Null EntryState means Flush */ 366daefc943SVivien Didelot }; 367daefc943SVivien Didelot 368daefc943SVivien Didelot return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all); 369daefc943SVivien Didelot } 370e606ca36SVivien Didelot 371e606ca36SVivien Didelot static int mv88e6xxx_g1_atu_move(struct mv88e6xxx_chip *chip, u16 fid, 372e606ca36SVivien Didelot int from_port, int to_port, bool all) 373e606ca36SVivien Didelot { 374e606ca36SVivien Didelot struct mv88e6xxx_atu_entry entry = { 0 }; 375e606ca36SVivien Didelot unsigned long mask; 376e606ca36SVivien Didelot int shift; 377e606ca36SVivien Didelot 378e606ca36SVivien Didelot if (!chip->info->atu_move_port_mask) 379e606ca36SVivien Didelot return -EOPNOTSUPP; 380e606ca36SVivien Didelot 381e606ca36SVivien Didelot mask = chip->info->atu_move_port_mask; 382e606ca36SVivien Didelot shift = bitmap_weight(&mask, 16); 383e606ca36SVivien Didelot 38459d4c93dSZheng Yongjun entry.state = 0xf; /* Full EntryState means Move */ 38501bd96c8SVivien Didelot entry.portvec = from_port & mask; 38601bd96c8SVivien Didelot entry.portvec |= (to_port & mask) << shift; 387e606ca36SVivien Didelot 388e606ca36SVivien Didelot return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all); 389e606ca36SVivien Didelot } 390e606ca36SVivien Didelot 391e606ca36SVivien Didelot int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port, 392e606ca36SVivien Didelot bool all) 393e606ca36SVivien Didelot { 394e606ca36SVivien Didelot int from_port = port; 395e606ca36SVivien Didelot int to_port = chip->info->atu_move_port_mask; 396e606ca36SVivien Didelot 397e606ca36SVivien Didelot return mv88e6xxx_g1_atu_move(chip, fid, from_port, to_port, all); 398e606ca36SVivien Didelot } 3990977644cSAndrew Lunn 4000977644cSAndrew Lunn static irqreturn_t mv88e6xxx_g1_atu_prob_irq_thread_fn(int irq, void *dev_id) 4010977644cSAndrew Lunn { 4020977644cSAndrew Lunn struct mv88e6xxx_chip *chip = dev_id; 4030977644cSAndrew Lunn struct mv88e6xxx_atu_entry entry; 404*4bf24ad0SHans J. Schultz int err, spid; 405*4bf24ad0SHans J. Schultz u16 val, fid; 4060977644cSAndrew Lunn 407c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip); 4080977644cSAndrew Lunn 409*4bf24ad0SHans J. Schultz err = mv88e6xxx_g1_read_atu_violation(chip); 4100977644cSAndrew Lunn if (err) 4110977644cSAndrew Lunn goto out; 4120977644cSAndrew Lunn 4130977644cSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_OP, &val); 4140977644cSAndrew Lunn if (err) 4150977644cSAndrew Lunn goto out; 4160977644cSAndrew Lunn 417*4bf24ad0SHans J. Schultz err = mv88e6xxx_g1_atu_fid_read(chip, &fid); 418*4bf24ad0SHans J. Schultz if (err) 419*4bf24ad0SHans J. Schultz goto out; 420*4bf24ad0SHans J. Schultz 4210977644cSAndrew Lunn err = mv88e6xxx_g1_atu_data_read(chip, &entry); 4220977644cSAndrew Lunn if (err) 4230977644cSAndrew Lunn goto out; 4240977644cSAndrew Lunn 4250977644cSAndrew Lunn err = mv88e6xxx_g1_atu_mac_read(chip, &entry); 4260977644cSAndrew Lunn if (err) 4270977644cSAndrew Lunn goto out; 4280977644cSAndrew Lunn 42975c05a74SAndrew Lunn spid = entry.state; 43075c05a74SAndrew Lunn 4310977644cSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION) { 4320977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 433*4bf24ad0SHans J. Schultz "ATU member violation for %pM fid %u portvec %x spid %d\n", 434*4bf24ad0SHans J. Schultz entry.mac, fid, entry.portvec, spid); 43575c05a74SAndrew Lunn chip->ports[spid].atu_member_violation++; 4360977644cSAndrew Lunn } 4370977644cSAndrew Lunn 438ddca24dfSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_MISS_VIOLATION) { 4390977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 440*4bf24ad0SHans J. Schultz "ATU miss violation for %pM fid %u portvec %x spid %d\n", 441*4bf24ad0SHans J. Schultz entry.mac, fid, entry.portvec, spid); 44275c05a74SAndrew Lunn chip->ports[spid].atu_miss_violation++; 44365f60e45SAndrew Lunn } 4440977644cSAndrew Lunn 44565f60e45SAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_FULL_VIOLATION) { 4460977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 447*4bf24ad0SHans J. Schultz "ATU full violation for %pM fid %u portvec %x spid %d\n", 448*4bf24ad0SHans J. Schultz entry.mac, fid, entry.portvec, spid); 44975c05a74SAndrew Lunn chip->ports[spid].atu_full_violation++; 45065f60e45SAndrew Lunn } 451c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip); 4520977644cSAndrew Lunn 4530977644cSAndrew Lunn return IRQ_HANDLED; 4540977644cSAndrew Lunn 4550977644cSAndrew Lunn out: 456c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip); 4570977644cSAndrew Lunn 4580977644cSAndrew Lunn dev_err(chip->dev, "ATU problem: error %d while handling interrupt\n", 4590977644cSAndrew Lunn err); 4600977644cSAndrew Lunn return IRQ_HANDLED; 4610977644cSAndrew Lunn } 4620977644cSAndrew Lunn 4630977644cSAndrew Lunn int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip) 4640977644cSAndrew Lunn { 4650977644cSAndrew Lunn int err; 4660977644cSAndrew Lunn 4670977644cSAndrew Lunn chip->atu_prob_irq = irq_find_mapping(chip->g1_irq.domain, 4680977644cSAndrew Lunn MV88E6XXX_G1_STS_IRQ_ATU_PROB); 4690977644cSAndrew Lunn if (chip->atu_prob_irq < 0) 4709b662a3eSAndrew Lunn return chip->atu_prob_irq; 4710977644cSAndrew Lunn 4728ddf0b56SAndrew Lunn snprintf(chip->atu_prob_irq_name, sizeof(chip->atu_prob_irq_name), 4738ddf0b56SAndrew Lunn "mv88e6xxx-%s-g1-atu-prob", dev_name(chip->dev)); 4748ddf0b56SAndrew Lunn 4750977644cSAndrew Lunn err = request_threaded_irq(chip->atu_prob_irq, NULL, 4760977644cSAndrew Lunn mv88e6xxx_g1_atu_prob_irq_thread_fn, 4778ddf0b56SAndrew Lunn IRQF_ONESHOT, chip->atu_prob_irq_name, 4780977644cSAndrew Lunn chip); 4790977644cSAndrew Lunn if (err) 4800977644cSAndrew Lunn irq_dispose_mapping(chip->atu_prob_irq); 4810977644cSAndrew Lunn 4820977644cSAndrew Lunn return err; 4830977644cSAndrew Lunn } 4840977644cSAndrew Lunn 4850977644cSAndrew Lunn void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip) 4860977644cSAndrew Lunn { 4870977644cSAndrew Lunn free_irq(chip->atu_prob_irq, chip); 4880977644cSAndrew Lunn irq_dispose_mapping(chip->atu_prob_irq); 4890977644cSAndrew Lunn } 490