12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2720c6343SVivien Didelot /* 3720c6343SVivien Didelot * Marvell 88E6xxx Address Translation Unit (ATU) support 4720c6343SVivien Didelot * 5720c6343SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 6720c6343SVivien Didelot * Copyright (c) 2017 Savoir-faire Linux, Inc. 7720c6343SVivien Didelot */ 80977644cSAndrew Lunn #include <linux/interrupt.h> 90977644cSAndrew Lunn #include <linux/irqdomain.h> 10720c6343SVivien Didelot 114d5f2ba7SVivien Didelot #include "chip.h" 12720c6343SVivien Didelot #include "global1.h" 13720c6343SVivien Didelot 149c13c026SVivien Didelot /* Offset 0x01: ATU FID Register */ 159c13c026SVivien Didelot 169c13c026SVivien Didelot static int mv88e6xxx_g1_atu_fid_write(struct mv88e6xxx_chip *chip, u16 fid) 179c13c026SVivien Didelot { 1827c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6352_G1_ATU_FID, fid & 0xfff); 199c13c026SVivien Didelot } 209c13c026SVivien Didelot 21720c6343SVivien Didelot /* Offset 0x0A: ATU Control Register */ 22720c6343SVivien Didelot 23c3a7d4adSVivien Didelot int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all) 24c3a7d4adSVivien Didelot { 25c3a7d4adSVivien Didelot u16 val; 26c3a7d4adSVivien Didelot int err; 27c3a7d4adSVivien Didelot 2827c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 29c3a7d4adSVivien Didelot if (err) 30c3a7d4adSVivien Didelot return err; 31c3a7d4adSVivien Didelot 32c3a7d4adSVivien Didelot if (learn2all) 3327c0e600SVivien Didelot val |= MV88E6XXX_G1_ATU_CTL_LEARN2ALL; 34c3a7d4adSVivien Didelot else 3527c0e600SVivien Didelot val &= ~MV88E6XXX_G1_ATU_CTL_LEARN2ALL; 36c3a7d4adSVivien Didelot 3727c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); 38c3a7d4adSVivien Didelot } 39c3a7d4adSVivien Didelot 40720c6343SVivien Didelot int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip, 41720c6343SVivien Didelot unsigned int msecs) 42720c6343SVivien Didelot { 43720c6343SVivien Didelot const unsigned int coeff = chip->info->age_time_coeff; 44720c6343SVivien Didelot const unsigned int min = 0x01 * coeff; 45720c6343SVivien Didelot const unsigned int max = 0xff * coeff; 46720c6343SVivien Didelot u8 age_time; 47720c6343SVivien Didelot u16 val; 48720c6343SVivien Didelot int err; 49720c6343SVivien Didelot 50720c6343SVivien Didelot if (msecs < min || msecs > max) 51720c6343SVivien Didelot return -ERANGE; 52720c6343SVivien Didelot 53720c6343SVivien Didelot /* Round to nearest multiple of coeff */ 54720c6343SVivien Didelot age_time = (msecs + coeff / 2) / coeff; 55720c6343SVivien Didelot 5627c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 57720c6343SVivien Didelot if (err) 58720c6343SVivien Didelot return err; 59720c6343SVivien Didelot 60720c6343SVivien Didelot /* AgeTime is 11:4 bits */ 61720c6343SVivien Didelot val &= ~0xff0; 62720c6343SVivien Didelot val |= age_time << 4; 63720c6343SVivien Didelot 6427c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); 65bae76dd9SVivien Didelot if (err) 66bae76dd9SVivien Didelot return err; 67bae76dd9SVivien Didelot 68bae76dd9SVivien Didelot dev_dbg(chip->dev, "AgeTime set to 0x%02x (%d ms)\n", age_time, 69bae76dd9SVivien Didelot age_time * coeff); 70bae76dd9SVivien Didelot 71bae76dd9SVivien Didelot return 0; 72720c6343SVivien Didelot } 739c13c026SVivien Didelot 749c13c026SVivien Didelot /* Offset 0x0B: ATU Operation Register */ 759c13c026SVivien Didelot 769c13c026SVivien Didelot static int mv88e6xxx_g1_atu_op_wait(struct mv88e6xxx_chip *chip) 779c13c026SVivien Didelot { 7827c0e600SVivien Didelot return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_ATU_OP, 7927c0e600SVivien Didelot MV88E6XXX_G1_ATU_OP_BUSY); 809c13c026SVivien Didelot } 819c13c026SVivien Didelot 829c13c026SVivien Didelot static int mv88e6xxx_g1_atu_op(struct mv88e6xxx_chip *chip, u16 fid, u16 op) 839c13c026SVivien Didelot { 849c13c026SVivien Didelot u16 val; 859c13c026SVivien Didelot int err; 869c13c026SVivien Didelot 879c13c026SVivien Didelot /* FID bits are dispatched all around gradually as more are supported */ 889c13c026SVivien Didelot if (mv88e6xxx_num_databases(chip) > 256) { 899c13c026SVivien Didelot err = mv88e6xxx_g1_atu_fid_write(chip, fid); 909c13c026SVivien Didelot if (err) 919c13c026SVivien Didelot return err; 929c13c026SVivien Didelot } else { 939c13c026SVivien Didelot if (mv88e6xxx_num_databases(chip) > 16) { 949c13c026SVivien Didelot /* ATU DBNum[7:4] are located in ATU Control 15:12 */ 9527c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, 9627c0e600SVivien Didelot &val); 979c13c026SVivien Didelot if (err) 989c13c026SVivien Didelot return err; 999c13c026SVivien Didelot 1009c13c026SVivien Didelot val = (val & 0x0fff) | ((fid << 8) & 0xf000); 10127c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, 10227c0e600SVivien Didelot val); 1039c13c026SVivien Didelot if (err) 1049c13c026SVivien Didelot return err; 1059c13c026SVivien Didelot } 1069c13c026SVivien Didelot 1079c13c026SVivien Didelot /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ 1089c13c026SVivien Didelot op |= fid & 0xf; 1099c13c026SVivien Didelot } 1109c13c026SVivien Didelot 11127c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_OP, 11227c0e600SVivien Didelot MV88E6XXX_G1_ATU_OP_BUSY | op); 1139c13c026SVivien Didelot if (err) 1149c13c026SVivien Didelot return err; 1159c13c026SVivien Didelot 1169c13c026SVivien Didelot return mv88e6xxx_g1_atu_op_wait(chip); 1179c13c026SVivien Didelot } 1189c13c026SVivien Didelot 1199c13c026SVivien Didelot /* Offset 0x0C: ATU Data Register */ 1209c13c026SVivien Didelot 121dabc1a96SVivien Didelot static int mv88e6xxx_g1_atu_data_read(struct mv88e6xxx_chip *chip, 122dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 123dabc1a96SVivien Didelot { 124dabc1a96SVivien Didelot u16 val; 125dabc1a96SVivien Didelot int err; 126dabc1a96SVivien Didelot 12727c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_DATA, &val); 128dabc1a96SVivien Didelot if (err) 129dabc1a96SVivien Didelot return err; 130dabc1a96SVivien Didelot 131dabc1a96SVivien Didelot entry->state = val & 0xf; 13227c0e600SVivien Didelot if (entry->state != MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 13327c0e600SVivien Didelot entry->trunk = !!(val & MV88E6XXX_G1_ATU_DATA_TRUNK); 13401bd96c8SVivien Didelot entry->portvec = (val >> 4) & mv88e6xxx_port_mask(chip); 135dabc1a96SVivien Didelot } 136dabc1a96SVivien Didelot 137dabc1a96SVivien Didelot return 0; 138dabc1a96SVivien Didelot } 139dabc1a96SVivien Didelot 1409c13c026SVivien Didelot static int mv88e6xxx_g1_atu_data_write(struct mv88e6xxx_chip *chip, 1419c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 1429c13c026SVivien Didelot { 1439c13c026SVivien Didelot u16 data = entry->state & 0xf; 1449c13c026SVivien Didelot 14527c0e600SVivien Didelot if (entry->state != MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1469c13c026SVivien Didelot if (entry->trunk) 14727c0e600SVivien Didelot data |= MV88E6XXX_G1_ATU_DATA_TRUNK; 1489c13c026SVivien Didelot 14901bd96c8SVivien Didelot data |= (entry->portvec & mv88e6xxx_port_mask(chip)) << 4; 1509c13c026SVivien Didelot } 1519c13c026SVivien Didelot 15227c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_DATA, data); 1539c13c026SVivien Didelot } 1549c13c026SVivien Didelot 1559c13c026SVivien Didelot /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1 1569c13c026SVivien Didelot * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3 1579c13c026SVivien Didelot * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5 1589c13c026SVivien Didelot */ 1599c13c026SVivien Didelot 160dabc1a96SVivien Didelot static int mv88e6xxx_g1_atu_mac_read(struct mv88e6xxx_chip *chip, 161dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 162dabc1a96SVivien Didelot { 163dabc1a96SVivien Didelot u16 val; 164dabc1a96SVivien Didelot int i, err; 165dabc1a96SVivien Didelot 166dabc1a96SVivien Didelot for (i = 0; i < 3; i++) { 16727c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_MAC01 + i, &val); 168dabc1a96SVivien Didelot if (err) 169dabc1a96SVivien Didelot return err; 170dabc1a96SVivien Didelot 171dabc1a96SVivien Didelot entry->mac[i * 2] = val >> 8; 172dabc1a96SVivien Didelot entry->mac[i * 2 + 1] = val & 0xff; 173dabc1a96SVivien Didelot } 174dabc1a96SVivien Didelot 175dabc1a96SVivien Didelot return 0; 176dabc1a96SVivien Didelot } 177dabc1a96SVivien Didelot 1789c13c026SVivien Didelot static int mv88e6xxx_g1_atu_mac_write(struct mv88e6xxx_chip *chip, 1799c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 1809c13c026SVivien Didelot { 1819c13c026SVivien Didelot u16 val; 1829c13c026SVivien Didelot int i, err; 1839c13c026SVivien Didelot 1849c13c026SVivien Didelot for (i = 0; i < 3; i++) { 1859c13c026SVivien Didelot val = (entry->mac[i * 2] << 8) | entry->mac[i * 2 + 1]; 18627c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_MAC01 + i, val); 1879c13c026SVivien Didelot if (err) 1889c13c026SVivien Didelot return err; 1899c13c026SVivien Didelot } 1909c13c026SVivien Didelot 1919c13c026SVivien Didelot return 0; 1929c13c026SVivien Didelot } 1939c13c026SVivien Didelot 1949c13c026SVivien Didelot /* Address Translation Unit operations */ 1959c13c026SVivien Didelot 196dabc1a96SVivien Didelot int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 197dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 198dabc1a96SVivien Didelot { 199dabc1a96SVivien Didelot int err; 200dabc1a96SVivien Didelot 201dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 202dabc1a96SVivien Didelot if (err) 203dabc1a96SVivien Didelot return err; 204dabc1a96SVivien Didelot 205dabc1a96SVivien Didelot /* Write the MAC address to iterate from only once */ 20627c0e600SVivien Didelot if (entry->state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 207dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_mac_write(chip, entry); 208dabc1a96SVivien Didelot if (err) 209dabc1a96SVivien Didelot return err; 210dabc1a96SVivien Didelot } 211dabc1a96SVivien Didelot 21227c0e600SVivien Didelot err = mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB); 213dabc1a96SVivien Didelot if (err) 214dabc1a96SVivien Didelot return err; 215dabc1a96SVivien Didelot 216dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_data_read(chip, entry); 217dabc1a96SVivien Didelot if (err) 218dabc1a96SVivien Didelot return err; 219dabc1a96SVivien Didelot 220dabc1a96SVivien Didelot return mv88e6xxx_g1_atu_mac_read(chip, entry); 221dabc1a96SVivien Didelot } 222dabc1a96SVivien Didelot 2239c13c026SVivien Didelot int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid, 2249c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 2259c13c026SVivien Didelot { 2269c13c026SVivien Didelot int err; 2279c13c026SVivien Didelot 2289c13c026SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 2299c13c026SVivien Didelot if (err) 2309c13c026SVivien Didelot return err; 2319c13c026SVivien Didelot 2329c13c026SVivien Didelot err = mv88e6xxx_g1_atu_mac_write(chip, entry); 2339c13c026SVivien Didelot if (err) 2349c13c026SVivien Didelot return err; 2359c13c026SVivien Didelot 2369c13c026SVivien Didelot err = mv88e6xxx_g1_atu_data_write(chip, entry); 2379c13c026SVivien Didelot if (err) 2389c13c026SVivien Didelot return err; 2399c13c026SVivien Didelot 24027c0e600SVivien Didelot return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_LOAD_DB); 2419c13c026SVivien Didelot } 242daefc943SVivien Didelot 243daefc943SVivien Didelot static int mv88e6xxx_g1_atu_flushmove(struct mv88e6xxx_chip *chip, u16 fid, 244daefc943SVivien Didelot struct mv88e6xxx_atu_entry *entry, 245daefc943SVivien Didelot bool all) 246daefc943SVivien Didelot { 247daefc943SVivien Didelot u16 op; 248daefc943SVivien Didelot int err; 249daefc943SVivien Didelot 250daefc943SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 251daefc943SVivien Didelot if (err) 252daefc943SVivien Didelot return err; 253daefc943SVivien Didelot 254daefc943SVivien Didelot err = mv88e6xxx_g1_atu_data_write(chip, entry); 255daefc943SVivien Didelot if (err) 256daefc943SVivien Didelot return err; 257daefc943SVivien Didelot 258daefc943SVivien Didelot /* Flush/Move all or non-static entries from all or a given database */ 259daefc943SVivien Didelot if (all && fid) 26027c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB; 261daefc943SVivien Didelot else if (fid) 26227c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; 263daefc943SVivien Didelot else if (all) 26427c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL; 265daefc943SVivien Didelot else 26627c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC; 267daefc943SVivien Didelot 268daefc943SVivien Didelot return mv88e6xxx_g1_atu_op(chip, fid, op); 269daefc943SVivien Didelot } 270daefc943SVivien Didelot 271daefc943SVivien Didelot int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all) 272daefc943SVivien Didelot { 273daefc943SVivien Didelot struct mv88e6xxx_atu_entry entry = { 274daefc943SVivien Didelot .state = 0, /* Null EntryState means Flush */ 275daefc943SVivien Didelot }; 276daefc943SVivien Didelot 277daefc943SVivien Didelot return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all); 278daefc943SVivien Didelot } 279e606ca36SVivien Didelot 280e606ca36SVivien Didelot static int mv88e6xxx_g1_atu_move(struct mv88e6xxx_chip *chip, u16 fid, 281e606ca36SVivien Didelot int from_port, int to_port, bool all) 282e606ca36SVivien Didelot { 283e606ca36SVivien Didelot struct mv88e6xxx_atu_entry entry = { 0 }; 284e606ca36SVivien Didelot unsigned long mask; 285e606ca36SVivien Didelot int shift; 286e606ca36SVivien Didelot 287e606ca36SVivien Didelot if (!chip->info->atu_move_port_mask) 288e606ca36SVivien Didelot return -EOPNOTSUPP; 289e606ca36SVivien Didelot 290e606ca36SVivien Didelot mask = chip->info->atu_move_port_mask; 291e606ca36SVivien Didelot shift = bitmap_weight(&mask, 16); 292e606ca36SVivien Didelot 293e606ca36SVivien Didelot entry.state = 0xf, /* Full EntryState means Move */ 29401bd96c8SVivien Didelot entry.portvec = from_port & mask; 29501bd96c8SVivien Didelot entry.portvec |= (to_port & mask) << shift; 296e606ca36SVivien Didelot 297e606ca36SVivien Didelot return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all); 298e606ca36SVivien Didelot } 299e606ca36SVivien Didelot 300e606ca36SVivien Didelot int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port, 301e606ca36SVivien Didelot bool all) 302e606ca36SVivien Didelot { 303e606ca36SVivien Didelot int from_port = port; 304e606ca36SVivien Didelot int to_port = chip->info->atu_move_port_mask; 305e606ca36SVivien Didelot 306e606ca36SVivien Didelot return mv88e6xxx_g1_atu_move(chip, fid, from_port, to_port, all); 307e606ca36SVivien Didelot } 3080977644cSAndrew Lunn 3090977644cSAndrew Lunn static irqreturn_t mv88e6xxx_g1_atu_prob_irq_thread_fn(int irq, void *dev_id) 3100977644cSAndrew Lunn { 3110977644cSAndrew Lunn struct mv88e6xxx_chip *chip = dev_id; 3120977644cSAndrew Lunn struct mv88e6xxx_atu_entry entry; 31375c05a74SAndrew Lunn int spid; 3140977644cSAndrew Lunn int err; 3150977644cSAndrew Lunn u16 val; 3160977644cSAndrew Lunn 3170977644cSAndrew Lunn mutex_lock(&chip->reg_lock); 3180977644cSAndrew Lunn 3190977644cSAndrew Lunn err = mv88e6xxx_g1_atu_op(chip, 0, 3200977644cSAndrew Lunn MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION); 3210977644cSAndrew Lunn if (err) 3220977644cSAndrew Lunn goto out; 3230977644cSAndrew Lunn 3240977644cSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_OP, &val); 3250977644cSAndrew Lunn if (err) 3260977644cSAndrew Lunn goto out; 3270977644cSAndrew Lunn 3280977644cSAndrew Lunn err = mv88e6xxx_g1_atu_data_read(chip, &entry); 3290977644cSAndrew Lunn if (err) 3300977644cSAndrew Lunn goto out; 3310977644cSAndrew Lunn 3320977644cSAndrew Lunn err = mv88e6xxx_g1_atu_mac_read(chip, &entry); 3330977644cSAndrew Lunn if (err) 3340977644cSAndrew Lunn goto out; 3350977644cSAndrew Lunn 33675c05a74SAndrew Lunn spid = entry.state; 33775c05a74SAndrew Lunn 3380977644cSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION) { 3390977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 3400977644cSAndrew Lunn "ATU age out violation for %pM\n", 3410977644cSAndrew Lunn entry.mac); 3420977644cSAndrew Lunn } 3430977644cSAndrew Lunn 3440977644cSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION) { 3450977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 34675c05a74SAndrew Lunn "ATU member violation for %pM portvec %x spid %d\n", 34775c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 34875c05a74SAndrew Lunn chip->ports[spid].atu_member_violation++; 3490977644cSAndrew Lunn } 3500977644cSAndrew Lunn 351ddca24dfSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_MISS_VIOLATION) { 3520977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 35375c05a74SAndrew Lunn "ATU miss violation for %pM portvec %x spid %d\n", 35475c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 35575c05a74SAndrew Lunn chip->ports[spid].atu_miss_violation++; 35665f60e45SAndrew Lunn } 3570977644cSAndrew Lunn 35865f60e45SAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_FULL_VIOLATION) { 3590977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 36075c05a74SAndrew Lunn "ATU full violation for %pM portvec %x spid %d\n", 36175c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 36275c05a74SAndrew Lunn chip->ports[spid].atu_full_violation++; 36365f60e45SAndrew Lunn } 36465f60e45SAndrew Lunn mutex_unlock(&chip->reg_lock); 3650977644cSAndrew Lunn 3660977644cSAndrew Lunn return IRQ_HANDLED; 3670977644cSAndrew Lunn 3680977644cSAndrew Lunn out: 3690977644cSAndrew Lunn mutex_unlock(&chip->reg_lock); 3700977644cSAndrew Lunn 3710977644cSAndrew Lunn dev_err(chip->dev, "ATU problem: error %d while handling interrupt\n", 3720977644cSAndrew Lunn err); 3730977644cSAndrew Lunn return IRQ_HANDLED; 3740977644cSAndrew Lunn } 3750977644cSAndrew Lunn 3760977644cSAndrew Lunn int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip) 3770977644cSAndrew Lunn { 3780977644cSAndrew Lunn int err; 3790977644cSAndrew Lunn 3800977644cSAndrew Lunn chip->atu_prob_irq = irq_find_mapping(chip->g1_irq.domain, 3810977644cSAndrew Lunn MV88E6XXX_G1_STS_IRQ_ATU_PROB); 3820977644cSAndrew Lunn if (chip->atu_prob_irq < 0) 3839b662a3eSAndrew Lunn return chip->atu_prob_irq; 3840977644cSAndrew Lunn 3850977644cSAndrew Lunn err = request_threaded_irq(chip->atu_prob_irq, NULL, 3860977644cSAndrew Lunn mv88e6xxx_g1_atu_prob_irq_thread_fn, 3870977644cSAndrew Lunn IRQF_ONESHOT, "mv88e6xxx-g1-atu-prob", 3880977644cSAndrew Lunn chip); 3890977644cSAndrew Lunn if (err) 3900977644cSAndrew Lunn irq_dispose_mapping(chip->atu_prob_irq); 3910977644cSAndrew Lunn 3920977644cSAndrew Lunn return err; 3930977644cSAndrew Lunn } 3940977644cSAndrew Lunn 3950977644cSAndrew Lunn void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip) 3960977644cSAndrew Lunn { 3970977644cSAndrew Lunn free_irq(chip->atu_prob_irq, chip); 3980977644cSAndrew Lunn irq_dispose_mapping(chip->atu_prob_irq); 3990977644cSAndrew Lunn } 400