12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2720c6343SVivien Didelot /* 3720c6343SVivien Didelot * Marvell 88E6xxx Address Translation Unit (ATU) support 4720c6343SVivien Didelot * 5720c6343SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 6720c6343SVivien Didelot * Copyright (c) 2017 Savoir-faire Linux, Inc. 7720c6343SVivien Didelot */ 819fb7f69SVivien Didelot 919fb7f69SVivien Didelot #include <linux/bitfield.h> 100977644cSAndrew Lunn #include <linux/interrupt.h> 110977644cSAndrew Lunn #include <linux/irqdomain.h> 12720c6343SVivien Didelot 134d5f2ba7SVivien Didelot #include "chip.h" 14720c6343SVivien Didelot #include "global1.h" 15720c6343SVivien Didelot 169c13c026SVivien Didelot /* Offset 0x01: ATU FID Register */ 179c13c026SVivien Didelot 189c13c026SVivien Didelot static int mv88e6xxx_g1_atu_fid_write(struct mv88e6xxx_chip *chip, u16 fid) 199c13c026SVivien Didelot { 2027c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6352_G1_ATU_FID, fid & 0xfff); 219c13c026SVivien Didelot } 229c13c026SVivien Didelot 23720c6343SVivien Didelot /* Offset 0x0A: ATU Control Register */ 24720c6343SVivien Didelot 25c3a7d4adSVivien Didelot int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all) 26c3a7d4adSVivien Didelot { 27c3a7d4adSVivien Didelot u16 val; 28c3a7d4adSVivien Didelot int err; 29c3a7d4adSVivien Didelot 3027c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 31c3a7d4adSVivien Didelot if (err) 32c3a7d4adSVivien Didelot return err; 33c3a7d4adSVivien Didelot 34c3a7d4adSVivien Didelot if (learn2all) 3527c0e600SVivien Didelot val |= MV88E6XXX_G1_ATU_CTL_LEARN2ALL; 36c3a7d4adSVivien Didelot else 3727c0e600SVivien Didelot val &= ~MV88E6XXX_G1_ATU_CTL_LEARN2ALL; 38c3a7d4adSVivien Didelot 3927c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); 40c3a7d4adSVivien Didelot } 41c3a7d4adSVivien Didelot 42720c6343SVivien Didelot int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip, 43720c6343SVivien Didelot unsigned int msecs) 44720c6343SVivien Didelot { 45720c6343SVivien Didelot const unsigned int coeff = chip->info->age_time_coeff; 46720c6343SVivien Didelot const unsigned int min = 0x01 * coeff; 47720c6343SVivien Didelot const unsigned int max = 0xff * coeff; 48720c6343SVivien Didelot u8 age_time; 49720c6343SVivien Didelot u16 val; 50720c6343SVivien Didelot int err; 51720c6343SVivien Didelot 52720c6343SVivien Didelot if (msecs < min || msecs > max) 53720c6343SVivien Didelot return -ERANGE; 54720c6343SVivien Didelot 55720c6343SVivien Didelot /* Round to nearest multiple of coeff */ 56720c6343SVivien Didelot age_time = (msecs + coeff / 2) / coeff; 57720c6343SVivien Didelot 5827c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 59720c6343SVivien Didelot if (err) 60720c6343SVivien Didelot return err; 61720c6343SVivien Didelot 62720c6343SVivien Didelot /* AgeTime is 11:4 bits */ 63720c6343SVivien Didelot val &= ~0xff0; 64720c6343SVivien Didelot val |= age_time << 4; 65720c6343SVivien Didelot 6627c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); 67bae76dd9SVivien Didelot if (err) 68bae76dd9SVivien Didelot return err; 69bae76dd9SVivien Didelot 70bae76dd9SVivien Didelot dev_dbg(chip->dev, "AgeTime set to 0x%02x (%d ms)\n", age_time, 71bae76dd9SVivien Didelot age_time * coeff); 72bae76dd9SVivien Didelot 73bae76dd9SVivien Didelot return 0; 74720c6343SVivien Didelot } 759c13c026SVivien Didelot 76*23e8b470SAndrew Lunn int mv88e6165_g1_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash) 77*23e8b470SAndrew Lunn { 78*23e8b470SAndrew Lunn int err; 79*23e8b470SAndrew Lunn u16 val; 80*23e8b470SAndrew Lunn 81*23e8b470SAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 82*23e8b470SAndrew Lunn if (err) 83*23e8b470SAndrew Lunn return err; 84*23e8b470SAndrew Lunn 85*23e8b470SAndrew Lunn *hash = val & MV88E6161_G1_ATU_CTL_HASH_MASK; 86*23e8b470SAndrew Lunn 87*23e8b470SAndrew Lunn return 0; 88*23e8b470SAndrew Lunn } 89*23e8b470SAndrew Lunn 90*23e8b470SAndrew Lunn int mv88e6165_g1_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash) 91*23e8b470SAndrew Lunn { 92*23e8b470SAndrew Lunn int err; 93*23e8b470SAndrew Lunn u16 val; 94*23e8b470SAndrew Lunn 95*23e8b470SAndrew Lunn if (hash & ~MV88E6161_G1_ATU_CTL_HASH_MASK) 96*23e8b470SAndrew Lunn return -EINVAL; 97*23e8b470SAndrew Lunn 98*23e8b470SAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val); 99*23e8b470SAndrew Lunn if (err) 100*23e8b470SAndrew Lunn return err; 101*23e8b470SAndrew Lunn 102*23e8b470SAndrew Lunn val &= ~MV88E6161_G1_ATU_CTL_HASH_MASK; 103*23e8b470SAndrew Lunn val |= hash; 104*23e8b470SAndrew Lunn 105*23e8b470SAndrew Lunn return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val); 106*23e8b470SAndrew Lunn } 107*23e8b470SAndrew Lunn 1089c13c026SVivien Didelot /* Offset 0x0B: ATU Operation Register */ 1099c13c026SVivien Didelot 1109c13c026SVivien Didelot static int mv88e6xxx_g1_atu_op_wait(struct mv88e6xxx_chip *chip) 1119c13c026SVivien Didelot { 11219fb7f69SVivien Didelot int bit = __bf_shf(MV88E6XXX_G1_ATU_OP_BUSY); 11319fb7f69SVivien Didelot 11419fb7f69SVivien Didelot return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_ATU_OP, bit, 0); 1159c13c026SVivien Didelot } 1169c13c026SVivien Didelot 1179c13c026SVivien Didelot static int mv88e6xxx_g1_atu_op(struct mv88e6xxx_chip *chip, u16 fid, u16 op) 1189c13c026SVivien Didelot { 1199c13c026SVivien Didelot u16 val; 1209c13c026SVivien Didelot int err; 1219c13c026SVivien Didelot 1229c13c026SVivien Didelot /* FID bits are dispatched all around gradually as more are supported */ 1239c13c026SVivien Didelot if (mv88e6xxx_num_databases(chip) > 256) { 1249c13c026SVivien Didelot err = mv88e6xxx_g1_atu_fid_write(chip, fid); 1259c13c026SVivien Didelot if (err) 1269c13c026SVivien Didelot return err; 1279c13c026SVivien Didelot } else { 1287b83df0dSRasmus Villemoes if (mv88e6xxx_num_databases(chip) > 64) { 1299c13c026SVivien Didelot /* ATU DBNum[7:4] are located in ATU Control 15:12 */ 13027c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, 13127c0e600SVivien Didelot &val); 1329c13c026SVivien Didelot if (err) 1339c13c026SVivien Didelot return err; 1349c13c026SVivien Didelot 1359c13c026SVivien Didelot val = (val & 0x0fff) | ((fid << 8) & 0xf000); 13627c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, 13727c0e600SVivien Didelot val); 1389c13c026SVivien Didelot if (err) 1399c13c026SVivien Didelot return err; 1407b83df0dSRasmus Villemoes } else if (mv88e6xxx_num_databases(chip) > 16) { 1417b83df0dSRasmus Villemoes /* ATU DBNum[5:4] are located in ATU Operation 9:8 */ 1427b83df0dSRasmus Villemoes op |= (fid & 0x30) << 4; 1439c13c026SVivien Didelot } 1449c13c026SVivien Didelot 1459c13c026SVivien Didelot /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ 1469c13c026SVivien Didelot op |= fid & 0xf; 1479c13c026SVivien Didelot } 1489c13c026SVivien Didelot 14927c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_OP, 15027c0e600SVivien Didelot MV88E6XXX_G1_ATU_OP_BUSY | op); 1519c13c026SVivien Didelot if (err) 1529c13c026SVivien Didelot return err; 1539c13c026SVivien Didelot 1549c13c026SVivien Didelot return mv88e6xxx_g1_atu_op_wait(chip); 1559c13c026SVivien Didelot } 1569c13c026SVivien Didelot 1579c13c026SVivien Didelot /* Offset 0x0C: ATU Data Register */ 1589c13c026SVivien Didelot 159dabc1a96SVivien Didelot static int mv88e6xxx_g1_atu_data_read(struct mv88e6xxx_chip *chip, 160dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 161dabc1a96SVivien Didelot { 162dabc1a96SVivien Didelot u16 val; 163dabc1a96SVivien Didelot int err; 164dabc1a96SVivien Didelot 16527c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_DATA, &val); 166dabc1a96SVivien Didelot if (err) 167dabc1a96SVivien Didelot return err; 168dabc1a96SVivien Didelot 169dabc1a96SVivien Didelot entry->state = val & 0xf; 170d8291a95SVivien Didelot if (entry->state) { 17127c0e600SVivien Didelot entry->trunk = !!(val & MV88E6XXX_G1_ATU_DATA_TRUNK); 17201bd96c8SVivien Didelot entry->portvec = (val >> 4) & mv88e6xxx_port_mask(chip); 173dabc1a96SVivien Didelot } 174dabc1a96SVivien Didelot 175dabc1a96SVivien Didelot return 0; 176dabc1a96SVivien Didelot } 177dabc1a96SVivien Didelot 1789c13c026SVivien Didelot static int mv88e6xxx_g1_atu_data_write(struct mv88e6xxx_chip *chip, 1799c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 1809c13c026SVivien Didelot { 1819c13c026SVivien Didelot u16 data = entry->state & 0xf; 1829c13c026SVivien Didelot 183d8291a95SVivien Didelot if (entry->state) { 1849c13c026SVivien Didelot if (entry->trunk) 18527c0e600SVivien Didelot data |= MV88E6XXX_G1_ATU_DATA_TRUNK; 1869c13c026SVivien Didelot 18701bd96c8SVivien Didelot data |= (entry->portvec & mv88e6xxx_port_mask(chip)) << 4; 1889c13c026SVivien Didelot } 1899c13c026SVivien Didelot 19027c0e600SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_DATA, data); 1919c13c026SVivien Didelot } 1929c13c026SVivien Didelot 1939c13c026SVivien Didelot /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1 1949c13c026SVivien Didelot * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3 1959c13c026SVivien Didelot * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5 1969c13c026SVivien Didelot */ 1979c13c026SVivien Didelot 198dabc1a96SVivien Didelot static int mv88e6xxx_g1_atu_mac_read(struct mv88e6xxx_chip *chip, 199dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 200dabc1a96SVivien Didelot { 201dabc1a96SVivien Didelot u16 val; 202dabc1a96SVivien Didelot int i, err; 203dabc1a96SVivien Didelot 204dabc1a96SVivien Didelot for (i = 0; i < 3; i++) { 20527c0e600SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_MAC01 + i, &val); 206dabc1a96SVivien Didelot if (err) 207dabc1a96SVivien Didelot return err; 208dabc1a96SVivien Didelot 209dabc1a96SVivien Didelot entry->mac[i * 2] = val >> 8; 210dabc1a96SVivien Didelot entry->mac[i * 2 + 1] = val & 0xff; 211dabc1a96SVivien Didelot } 212dabc1a96SVivien Didelot 213dabc1a96SVivien Didelot return 0; 214dabc1a96SVivien Didelot } 215dabc1a96SVivien Didelot 2169c13c026SVivien Didelot static int mv88e6xxx_g1_atu_mac_write(struct mv88e6xxx_chip *chip, 2179c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 2189c13c026SVivien Didelot { 2199c13c026SVivien Didelot u16 val; 2209c13c026SVivien Didelot int i, err; 2219c13c026SVivien Didelot 2229c13c026SVivien Didelot for (i = 0; i < 3; i++) { 2239c13c026SVivien Didelot val = (entry->mac[i * 2] << 8) | entry->mac[i * 2 + 1]; 22427c0e600SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_MAC01 + i, val); 2259c13c026SVivien Didelot if (err) 2269c13c026SVivien Didelot return err; 2279c13c026SVivien Didelot } 2289c13c026SVivien Didelot 2299c13c026SVivien Didelot return 0; 2309c13c026SVivien Didelot } 2319c13c026SVivien Didelot 2329c13c026SVivien Didelot /* Address Translation Unit operations */ 2339c13c026SVivien Didelot 234dabc1a96SVivien Didelot int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 235dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry) 236dabc1a96SVivien Didelot { 237dabc1a96SVivien Didelot int err; 238dabc1a96SVivien Didelot 239dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 240dabc1a96SVivien Didelot if (err) 241dabc1a96SVivien Didelot return err; 242dabc1a96SVivien Didelot 243dabc1a96SVivien Didelot /* Write the MAC address to iterate from only once */ 244d8291a95SVivien Didelot if (!entry->state) { 245dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_mac_write(chip, entry); 246dabc1a96SVivien Didelot if (err) 247dabc1a96SVivien Didelot return err; 248dabc1a96SVivien Didelot } 249dabc1a96SVivien Didelot 25027c0e600SVivien Didelot err = mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB); 251dabc1a96SVivien Didelot if (err) 252dabc1a96SVivien Didelot return err; 253dabc1a96SVivien Didelot 254dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_data_read(chip, entry); 255dabc1a96SVivien Didelot if (err) 256dabc1a96SVivien Didelot return err; 257dabc1a96SVivien Didelot 258dabc1a96SVivien Didelot return mv88e6xxx_g1_atu_mac_read(chip, entry); 259dabc1a96SVivien Didelot } 260dabc1a96SVivien Didelot 2619c13c026SVivien Didelot int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid, 2629c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry) 2639c13c026SVivien Didelot { 2649c13c026SVivien Didelot int err; 2659c13c026SVivien Didelot 2669c13c026SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 2679c13c026SVivien Didelot if (err) 2689c13c026SVivien Didelot return err; 2699c13c026SVivien Didelot 2709c13c026SVivien Didelot err = mv88e6xxx_g1_atu_mac_write(chip, entry); 2719c13c026SVivien Didelot if (err) 2729c13c026SVivien Didelot return err; 2739c13c026SVivien Didelot 2749c13c026SVivien Didelot err = mv88e6xxx_g1_atu_data_write(chip, entry); 2759c13c026SVivien Didelot if (err) 2769c13c026SVivien Didelot return err; 2779c13c026SVivien Didelot 27827c0e600SVivien Didelot return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_LOAD_DB); 2799c13c026SVivien Didelot } 280daefc943SVivien Didelot 281daefc943SVivien Didelot static int mv88e6xxx_g1_atu_flushmove(struct mv88e6xxx_chip *chip, u16 fid, 282daefc943SVivien Didelot struct mv88e6xxx_atu_entry *entry, 283daefc943SVivien Didelot bool all) 284daefc943SVivien Didelot { 285daefc943SVivien Didelot u16 op; 286daefc943SVivien Didelot int err; 287daefc943SVivien Didelot 288daefc943SVivien Didelot err = mv88e6xxx_g1_atu_op_wait(chip); 289daefc943SVivien Didelot if (err) 290daefc943SVivien Didelot return err; 291daefc943SVivien Didelot 292daefc943SVivien Didelot err = mv88e6xxx_g1_atu_data_write(chip, entry); 293daefc943SVivien Didelot if (err) 294daefc943SVivien Didelot return err; 295daefc943SVivien Didelot 296daefc943SVivien Didelot /* Flush/Move all or non-static entries from all or a given database */ 297daefc943SVivien Didelot if (all && fid) 29827c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB; 299daefc943SVivien Didelot else if (fid) 30027c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; 301daefc943SVivien Didelot else if (all) 30227c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL; 303daefc943SVivien Didelot else 30427c0e600SVivien Didelot op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC; 305daefc943SVivien Didelot 306daefc943SVivien Didelot return mv88e6xxx_g1_atu_op(chip, fid, op); 307daefc943SVivien Didelot } 308daefc943SVivien Didelot 309daefc943SVivien Didelot int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all) 310daefc943SVivien Didelot { 311daefc943SVivien Didelot struct mv88e6xxx_atu_entry entry = { 312daefc943SVivien Didelot .state = 0, /* Null EntryState means Flush */ 313daefc943SVivien Didelot }; 314daefc943SVivien Didelot 315daefc943SVivien Didelot return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all); 316daefc943SVivien Didelot } 317e606ca36SVivien Didelot 318e606ca36SVivien Didelot static int mv88e6xxx_g1_atu_move(struct mv88e6xxx_chip *chip, u16 fid, 319e606ca36SVivien Didelot int from_port, int to_port, bool all) 320e606ca36SVivien Didelot { 321e606ca36SVivien Didelot struct mv88e6xxx_atu_entry entry = { 0 }; 322e606ca36SVivien Didelot unsigned long mask; 323e606ca36SVivien Didelot int shift; 324e606ca36SVivien Didelot 325e606ca36SVivien Didelot if (!chip->info->atu_move_port_mask) 326e606ca36SVivien Didelot return -EOPNOTSUPP; 327e606ca36SVivien Didelot 328e606ca36SVivien Didelot mask = chip->info->atu_move_port_mask; 329e606ca36SVivien Didelot shift = bitmap_weight(&mask, 16); 330e606ca36SVivien Didelot 331e606ca36SVivien Didelot entry.state = 0xf, /* Full EntryState means Move */ 33201bd96c8SVivien Didelot entry.portvec = from_port & mask; 33301bd96c8SVivien Didelot entry.portvec |= (to_port & mask) << shift; 334e606ca36SVivien Didelot 335e606ca36SVivien Didelot return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all); 336e606ca36SVivien Didelot } 337e606ca36SVivien Didelot 338e606ca36SVivien Didelot int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port, 339e606ca36SVivien Didelot bool all) 340e606ca36SVivien Didelot { 341e606ca36SVivien Didelot int from_port = port; 342e606ca36SVivien Didelot int to_port = chip->info->atu_move_port_mask; 343e606ca36SVivien Didelot 344e606ca36SVivien Didelot return mv88e6xxx_g1_atu_move(chip, fid, from_port, to_port, all); 345e606ca36SVivien Didelot } 3460977644cSAndrew Lunn 3470977644cSAndrew Lunn static irqreturn_t mv88e6xxx_g1_atu_prob_irq_thread_fn(int irq, void *dev_id) 3480977644cSAndrew Lunn { 3490977644cSAndrew Lunn struct mv88e6xxx_chip *chip = dev_id; 3500977644cSAndrew Lunn struct mv88e6xxx_atu_entry entry; 35175c05a74SAndrew Lunn int spid; 3520977644cSAndrew Lunn int err; 3530977644cSAndrew Lunn u16 val; 3540977644cSAndrew Lunn 355c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip); 3560977644cSAndrew Lunn 3570977644cSAndrew Lunn err = mv88e6xxx_g1_atu_op(chip, 0, 3580977644cSAndrew Lunn MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION); 3590977644cSAndrew Lunn if (err) 3600977644cSAndrew Lunn goto out; 3610977644cSAndrew Lunn 3620977644cSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_OP, &val); 3630977644cSAndrew Lunn if (err) 3640977644cSAndrew Lunn goto out; 3650977644cSAndrew Lunn 3660977644cSAndrew Lunn err = mv88e6xxx_g1_atu_data_read(chip, &entry); 3670977644cSAndrew Lunn if (err) 3680977644cSAndrew Lunn goto out; 3690977644cSAndrew Lunn 3700977644cSAndrew Lunn err = mv88e6xxx_g1_atu_mac_read(chip, &entry); 3710977644cSAndrew Lunn if (err) 3720977644cSAndrew Lunn goto out; 3730977644cSAndrew Lunn 37475c05a74SAndrew Lunn spid = entry.state; 37575c05a74SAndrew Lunn 3760977644cSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION) { 3770977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 3780977644cSAndrew Lunn "ATU age out violation for %pM\n", 3790977644cSAndrew Lunn entry.mac); 3800977644cSAndrew Lunn } 3810977644cSAndrew Lunn 3820977644cSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION) { 3830977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 38475c05a74SAndrew Lunn "ATU member violation for %pM portvec %x spid %d\n", 38575c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 38675c05a74SAndrew Lunn chip->ports[spid].atu_member_violation++; 3870977644cSAndrew Lunn } 3880977644cSAndrew Lunn 389ddca24dfSAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_MISS_VIOLATION) { 3900977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 39175c05a74SAndrew Lunn "ATU miss violation for %pM portvec %x spid %d\n", 39275c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 39375c05a74SAndrew Lunn chip->ports[spid].atu_miss_violation++; 39465f60e45SAndrew Lunn } 3950977644cSAndrew Lunn 39665f60e45SAndrew Lunn if (val & MV88E6XXX_G1_ATU_OP_FULL_VIOLATION) { 3970977644cSAndrew Lunn dev_err_ratelimited(chip->dev, 39875c05a74SAndrew Lunn "ATU full violation for %pM portvec %x spid %d\n", 39975c05a74SAndrew Lunn entry.mac, entry.portvec, spid); 40075c05a74SAndrew Lunn chip->ports[spid].atu_full_violation++; 40165f60e45SAndrew Lunn } 402c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip); 4030977644cSAndrew Lunn 4040977644cSAndrew Lunn return IRQ_HANDLED; 4050977644cSAndrew Lunn 4060977644cSAndrew Lunn out: 407c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip); 4080977644cSAndrew Lunn 4090977644cSAndrew Lunn dev_err(chip->dev, "ATU problem: error %d while handling interrupt\n", 4100977644cSAndrew Lunn err); 4110977644cSAndrew Lunn return IRQ_HANDLED; 4120977644cSAndrew Lunn } 4130977644cSAndrew Lunn 4140977644cSAndrew Lunn int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip) 4150977644cSAndrew Lunn { 4160977644cSAndrew Lunn int err; 4170977644cSAndrew Lunn 4180977644cSAndrew Lunn chip->atu_prob_irq = irq_find_mapping(chip->g1_irq.domain, 4190977644cSAndrew Lunn MV88E6XXX_G1_STS_IRQ_ATU_PROB); 4200977644cSAndrew Lunn if (chip->atu_prob_irq < 0) 4219b662a3eSAndrew Lunn return chip->atu_prob_irq; 4220977644cSAndrew Lunn 4230977644cSAndrew Lunn err = request_threaded_irq(chip->atu_prob_irq, NULL, 4240977644cSAndrew Lunn mv88e6xxx_g1_atu_prob_irq_thread_fn, 4250977644cSAndrew Lunn IRQF_ONESHOT, "mv88e6xxx-g1-atu-prob", 4260977644cSAndrew Lunn chip); 4270977644cSAndrew Lunn if (err) 4280977644cSAndrew Lunn irq_dispose_mapping(chip->atu_prob_irq); 4290977644cSAndrew Lunn 4300977644cSAndrew Lunn return err; 4310977644cSAndrew Lunn } 4320977644cSAndrew Lunn 4330977644cSAndrew Lunn void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip) 4340977644cSAndrew Lunn { 4350977644cSAndrew Lunn free_irq(chip->atu_prob_irq, chip); 4360977644cSAndrew Lunn irq_dispose_mapping(chip->atu_prob_irq); 4370977644cSAndrew Lunn } 438