1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Marvell 88E6xxx Switch Global (1) Registers support
4  *
5  * Copyright (c) 2008 Marvell Semiconductor
6  *
7  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9  */
10 
11 #ifndef _MV88E6XXX_GLOBAL1_H
12 #define _MV88E6XXX_GLOBAL1_H
13 
14 #include "chip.h"
15 
16 /* Offset 0x00: Switch Global Status Register */
17 #define MV88E6XXX_G1_STS				0x00
18 #define MV88E6352_G1_STS_PPU_STATE			0x8000
19 #define MV88E6185_G1_STS_PPU_STATE_MASK			0xc000
20 #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST		0x0000
21 #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING		0x4000
22 #define MV88E6185_G1_STS_PPU_STATE_DISABLED		0x8000
23 #define MV88E6185_G1_STS_PPU_STATE_POLLING		0xc000
24 #define MV88E6XXX_G1_STS_INIT_READY			0x0800
25 #define MV88E6XXX_G1_STS_IRQ_AVB			8
26 #define MV88E6XXX_G1_STS_IRQ_DEVICE			7
27 #define MV88E6XXX_G1_STS_IRQ_STATS			6
28 #define MV88E6XXX_G1_STS_IRQ_VTU_PROB			5
29 #define MV88E6XXX_G1_STS_IRQ_VTU_DONE			4
30 #define MV88E6XXX_G1_STS_IRQ_ATU_PROB			3
31 #define MV88E6XXX_G1_STS_IRQ_ATU_DONE			2
32 #define MV88E6XXX_G1_STS_IRQ_TCAM_DONE			1
33 #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE		0
34 
35 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
36  * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
37  * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
38  */
39 #define MV88E6XXX_G1_MAC_01		0x01
40 #define MV88E6XXX_G1_MAC_23		0x02
41 #define MV88E6XXX_G1_MAC_45		0x03
42 
43 /* Offset 0x01: ATU FID Register */
44 #define MV88E6352_G1_ATU_FID		0x01
45 
46 /* Offset 0x02: VTU FID Register */
47 #define MV88E6352_G1_VTU_FID		0x02
48 #define MV88E6352_G1_VTU_FID_MASK	0x0fff
49 
50 /* Offset 0x03: VTU SID Register */
51 #define MV88E6352_G1_VTU_SID		0x03
52 #define MV88E6352_G1_VTU_SID_MASK	0x3f
53 
54 /* Offset 0x04: Switch Global Control Register */
55 #define MV88E6XXX_G1_CTL1			0x04
56 #define MV88E6XXX_G1_CTL1_SW_RESET		0x8000
57 #define MV88E6XXX_G1_CTL1_PPU_ENABLE		0x4000
58 #define MV88E6352_G1_CTL1_DISCARD_EXCESS	0x2000
59 #define MV88E6185_G1_CTL1_SCHED_PRIO		0x0800
60 #define MV88E6185_G1_CTL1_MAX_FRAME_1632	0x0400
61 #define MV88E6185_G1_CTL1_RELOAD_EEPROM		0x0200
62 #define MV88E6XXX_G1_CTL1_DEVICE_EN		0x0080
63 #define MV88E6XXX_G1_CTL1_STATS_DONE_EN		0x0040
64 #define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN	0x0020
65 #define MV88E6XXX_G1_CTL1_VTU_DONE_EN		0x0010
66 #define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN	0x0008
67 #define MV88E6XXX_G1_CTL1_ATU_DONE_EN		0x0004
68 #define MV88E6XXX_G1_CTL1_TCAM_EN		0x0002
69 #define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN	0x0001
70 
71 /* Offset 0x05: VTU Operation Register */
72 #define MV88E6XXX_G1_VTU_OP			0x05
73 #define MV88E6XXX_G1_VTU_OP_BUSY		0x8000
74 #define MV88E6XXX_G1_VTU_OP_MASK		0x7000
75 #define MV88E6XXX_G1_VTU_OP_FLUSH_ALL		0x1000
76 #define MV88E6XXX_G1_VTU_OP_NOOP		0x2000
77 #define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE	0x3000
78 #define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT	0x4000
79 #define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE	0x5000
80 #define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT	0x6000
81 #define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION	0x7000
82 #define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION	BIT(6)
83 #define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION	BIT(5)
84 #define MV88E6XXX_G1_VTU_OP_SPID_MASK		0xf
85 
86 /* Offset 0x06: VTU VID Register */
87 #define MV88E6XXX_G1_VTU_VID		0x06
88 #define MV88E6XXX_G1_VTU_VID_MASK	0x0fff
89 #define MV88E6390_G1_VTU_VID_PAGE	0x2000
90 #define MV88E6XXX_G1_VTU_VID_VALID	0x1000
91 
92 /* Offset 0x07: VTU/STU Data Register 1
93  * Offset 0x08: VTU/STU Data Register 2
94  * Offset 0x09: VTU/STU Data Register 3
95  */
96 #define MV88E6XXX_G1_VTU_DATA1				0x07
97 #define MV88E6XXX_G1_VTU_DATA2				0x08
98 #define MV88E6XXX_G1_VTU_DATA3				0x09
99 #define MV88E6XXX_G1_VTU_STU_DATA_MASK			0x0003
100 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED	0x0000
101 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED	0x0001
102 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED		0x0002
103 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER	0x0003
104 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED	0x0000
105 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING	0x0001
106 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING	0x0002
107 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING	0x0003
108 
109 /* Offset 0x0A: ATU Control Register */
110 #define MV88E6XXX_G1_ATU_CTL		0x0a
111 #define MV88E6XXX_G1_ATU_CTL_LEARN2ALL	0x0008
112 
113 /* Offset 0x0B: ATU Operation Register */
114 #define MV88E6XXX_G1_ATU_OP				0x0b
115 #define MV88E6XXX_G1_ATU_OP_BUSY			0x8000
116 #define MV88E6XXX_G1_ATU_OP_MASK			0x7000
117 #define MV88E6XXX_G1_ATU_OP_NOOP			0x0000
118 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL		0x1000
119 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC	0x2000
120 #define MV88E6XXX_G1_ATU_OP_LOAD_DB			0x3000
121 #define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB			0x4000
122 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB		0x5000
123 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB	0x6000
124 #define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION		0x7000
125 #define MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION		BIT(7)
126 #define MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION		BIT(6)
127 #define MV88E6XXX_G1_ATU_OP_MISS_VIOLATION		BIT(5)
128 #define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION		BIT(4)
129 
130 /* Offset 0x0C: ATU Data Register */
131 #define MV88E6XXX_G1_ATU_DATA					0x0c
132 #define MV88E6XXX_G1_ATU_DATA_TRUNK				0x8000
133 #define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK			0x00f0
134 #define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK			0x3ff0
135 #define MV88E6XXX_G1_ATU_DATA_STATE_MASK			0x000f
136 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_UNUSED			0x0000
137 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_1_OLDEST		0x0001
138 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_2			0x0002
139 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_3			0x0003
140 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_4			0x0004
141 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_5			0x0005
142 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_6			0x0006
143 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_7_NEWEST		0x0007
144 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY		0x0008
145 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY_PO		0x0009
146 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL		0x000a
147 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL_PO	0x000b
148 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT		0x000c
149 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT_PO	0x000d
150 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC			0x000e
151 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_PO		0x000f
152 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED			0x0000
153 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY		0x0004
154 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL		0x0005
155 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT		0x0006
156 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC			0x0007
157 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY_PO		0x000c
158 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL_PO	0x000d
159 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT_PO	0x000e
160 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_PO		0x000f
161 
162 /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
163  * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
164  * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
165  */
166 #define MV88E6XXX_G1_ATU_MAC01		0x0d
167 #define MV88E6XXX_G1_ATU_MAC23		0x0e
168 #define MV88E6XXX_G1_ATU_MAC45		0x0f
169 
170 /* Offset 0x10: IP-PRI Mapping Register 0
171  * Offset 0x11: IP-PRI Mapping Register 1
172  * Offset 0x12: IP-PRI Mapping Register 2
173  * Offset 0x13: IP-PRI Mapping Register 3
174  * Offset 0x14: IP-PRI Mapping Register 4
175  * Offset 0x15: IP-PRI Mapping Register 5
176  * Offset 0x16: IP-PRI Mapping Register 6
177  * Offset 0x17: IP-PRI Mapping Register 7
178  */
179 #define MV88E6XXX_G1_IP_PRI_0	0x10
180 #define MV88E6XXX_G1_IP_PRI_1	0x11
181 #define MV88E6XXX_G1_IP_PRI_2	0x12
182 #define MV88E6XXX_G1_IP_PRI_3	0x13
183 #define MV88E6XXX_G1_IP_PRI_4	0x14
184 #define MV88E6XXX_G1_IP_PRI_5	0x15
185 #define MV88E6XXX_G1_IP_PRI_6	0x16
186 #define MV88E6XXX_G1_IP_PRI_7	0x17
187 
188 /* Offset 0x18: IEEE-PRI Register */
189 #define MV88E6XXX_G1_IEEE_PRI	0x18
190 
191 /* Offset 0x19: Core Tag Type */
192 #define MV88E6185_G1_CORE_TAG_TYPE	0x19
193 
194 /* Offset 0x1A: Monitor Control */
195 #define MV88E6185_G1_MONITOR_CTL			0x1a
196 #define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK	0xf000
197 #define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK	0x0f00
198 #define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK	        0x00f0
199 #define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK	        0x00f0
200 #define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK	0x000f
201 
202 /* Offset 0x1A: Monitor & MGMT Control Register */
203 #define MV88E6390_G1_MONITOR_MGMT_CTL				0x1a
204 #define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE			0x8000
205 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK			0x3f00
206 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO	0x0000
207 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI	0x0100
208 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO	0x0200
209 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI	0x0300
210 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST		0x2000
211 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST		0x2100
212 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST		0x3000
213 #define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK			0x00ff
214 
215 /* Offset 0x1C: Global Control 2 */
216 #define MV88E6XXX_G1_CTL2			0x1c
217 #define MV88E6185_G1_CTL2_CASCADE_PORT_MASK	0xf000
218 #define MV88E6185_G1_CTL2_CASCADE_PORT_NONE	0xe000
219 #define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI	0xf000
220 #define MV88E6352_G1_CTL2_HEADER_TYPE_MASK	0xc000
221 #define MV88E6352_G1_CTL2_HEADER_TYPE_ORIG	0x0000
222 #define MV88E6352_G1_CTL2_HEADER_TYPE_MGMT	0x4000
223 #define MV88E6390_G1_CTL2_HEADER_TYPE_LAG	0x8000
224 #define MV88E6352_G1_CTL2_RMU_MODE_MASK		0x3000
225 #define MV88E6352_G1_CTL2_RMU_MODE_DISABLED	0x0000
226 #define MV88E6352_G1_CTL2_RMU_MODE_PORT_4	0x1000
227 #define MV88E6352_G1_CTL2_RMU_MODE_PORT_5	0x2000
228 #define MV88E6352_G1_CTL2_RMU_MODE_PORT_6	0x3000
229 #define MV88E6085_G1_CTL2_DA_CHECK		0x4000
230 #define MV88E6085_G1_CTL2_P10RM			0x2000
231 #define MV88E6085_G1_CTL2_RM_ENABLE		0x1000
232 #define MV88E6352_G1_CTL2_DA_CHECK		0x0800
233 #define MV88E6390_G1_CTL2_RMU_MODE_MASK		0x0700
234 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_0	0x0000
235 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_1	0x0100
236 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_9	0x0200
237 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_10	0x0300
238 #define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA	0x0600
239 #define MV88E6390_G1_CTL2_RMU_MODE_DISABLED	0x0700
240 #define MV88E6390_G1_CTL2_HIST_MODE_MASK	0x00c0
241 #define MV88E6390_G1_CTL2_HIST_MODE_RX		0x0040
242 #define MV88E6390_G1_CTL2_HIST_MODE_TX		0x0080
243 #define MV88E6352_G1_CTL2_CTR_MODE_MASK		0x0060
244 #define MV88E6390_G1_CTL2_CTR_MODE		0x0020
245 #define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK	0x001f
246 
247 /* Offset 0x1D: Stats Operation Register */
248 #define MV88E6XXX_G1_STATS_OP			0x1d
249 #define MV88E6XXX_G1_STATS_OP_BUSY		0x8000
250 #define MV88E6XXX_G1_STATS_OP_NOP		0x0000
251 #define MV88E6XXX_G1_STATS_OP_FLUSH_ALL		0x1000
252 #define MV88E6XXX_G1_STATS_OP_FLUSH_PORT	0x2000
253 #define MV88E6XXX_G1_STATS_OP_READ_CAPTURED	0x4000
254 #define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT	0x5000
255 #define MV88E6XXX_G1_STATS_OP_HIST_RX		0x0400
256 #define MV88E6XXX_G1_STATS_OP_HIST_TX		0x0800
257 #define MV88E6XXX_G1_STATS_OP_HIST_RX_TX	0x0c00
258 #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9	0x0200
259 #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10	0x0400
260 
261 /* Offset 0x1E: Stats Counter Register Bytes 3 & 2
262  * Offset 0x1F: Stats Counter Register Bytes 1 & 0
263  */
264 #define MV88E6XXX_G1_STATS_COUNTER_32	0x1e
265 #define MV88E6XXX_G1_STATS_COUNTER_01	0x1f
266 
267 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
268 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
269 int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
270 			  bit, int val);
271 int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
272 			   u16 mask, u16 val);
273 
274 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
275 
276 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip);
277 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip);
278 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip);
279 
280 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip);
281 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip);
282 
283 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
284 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
285 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
286 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
287 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
288 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val);
289 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip);
290 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port);
291 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port);
292 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
293 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
294 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
295 
296 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip);
297 
298 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
299 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
300 
301 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);
302 
303 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip);
304 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip);
305 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip);
306 
307 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index);
308 
309 int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);
310 int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
311 				  unsigned int msecs);
312 int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
313 			     struct mv88e6xxx_atu_entry *entry);
314 int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
315 			       struct mv88e6xxx_atu_entry *entry);
316 int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all);
317 int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port,
318 			    bool all);
319 int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip);
320 void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip);
321 
322 int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
323 			     struct mv88e6xxx_vtu_entry *entry);
324 int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
325 			       struct mv88e6xxx_vtu_entry *entry);
326 int mv88e6250_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
327 			     struct mv88e6xxx_vtu_entry *entry);
328 int mv88e6250_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
329 			       struct mv88e6xxx_vtu_entry *entry);
330 int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
331 			     struct mv88e6xxx_vtu_entry *entry);
332 int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
333 			       struct mv88e6xxx_vtu_entry *entry);
334 int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
335 			     struct mv88e6xxx_vtu_entry *entry);
336 int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
337 			       struct mv88e6xxx_vtu_entry *entry);
338 int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip);
339 int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip *chip);
340 void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip *chip);
341 
342 #endif /* _MV88E6XXX_GLOBAL1_H */
343