1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Marvell 88E6xxx Switch Global (1) Registers support
4  *
5  * Copyright (c) 2008 Marvell Semiconductor
6  *
7  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9  */
10 
11 #ifndef _MV88E6XXX_GLOBAL1_H
12 #define _MV88E6XXX_GLOBAL1_H
13 
14 #include "chip.h"
15 
16 /* Offset 0x00: Switch Global Status Register */
17 #define MV88E6XXX_G1_STS				0x00
18 #define MV88E6352_G1_STS_PPU_STATE			0x8000
19 #define MV88E6185_G1_STS_PPU_STATE_MASK			0xc000
20 #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST		0x0000
21 #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING		0x4000
22 #define MV88E6185_G1_STS_PPU_STATE_DISABLED		0x8000
23 #define MV88E6185_G1_STS_PPU_STATE_POLLING		0xc000
24 #define MV88E6XXX_G1_STS_INIT_READY			0x0800
25 #define MV88E6393X_G1_STS_IRQ_DEVICE_2			9
26 #define MV88E6XXX_G1_STS_IRQ_AVB			8
27 #define MV88E6XXX_G1_STS_IRQ_DEVICE			7
28 #define MV88E6XXX_G1_STS_IRQ_STATS			6
29 #define MV88E6XXX_G1_STS_IRQ_VTU_PROB			5
30 #define MV88E6XXX_G1_STS_IRQ_VTU_DONE			4
31 #define MV88E6XXX_G1_STS_IRQ_ATU_PROB			3
32 #define MV88E6XXX_G1_STS_IRQ_ATU_DONE			2
33 #define MV88E6XXX_G1_STS_IRQ_TCAM_DONE			1
34 #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE		0
35 
36 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
37  * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
38  * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
39  */
40 #define MV88E6XXX_G1_MAC_01		0x01
41 #define MV88E6XXX_G1_MAC_23		0x02
42 #define MV88E6XXX_G1_MAC_45		0x03
43 
44 /* Offset 0x01: ATU FID Register */
45 #define MV88E6352_G1_ATU_FID		0x01
46 
47 /* Offset 0x02: VTU FID Register */
48 #define MV88E6352_G1_VTU_FID		0x02
49 #define MV88E6352_G1_VTU_FID_VID_POLICY	0x1000
50 #define MV88E6352_G1_VTU_FID_MASK	0x0fff
51 
52 /* Offset 0x03: VTU SID Register */
53 #define MV88E6352_G1_VTU_SID		0x03
54 #define MV88E6352_G1_VTU_SID_MASK	0x3f
55 
56 /* Offset 0x04: Switch Global Control Register */
57 #define MV88E6XXX_G1_CTL1			0x04
58 #define MV88E6XXX_G1_CTL1_SW_RESET		0x8000
59 #define MV88E6XXX_G1_CTL1_PPU_ENABLE		0x4000
60 #define MV88E6352_G1_CTL1_DISCARD_EXCESS	0x2000
61 #define MV88E6185_G1_CTL1_SCHED_PRIO		0x0800
62 #define MV88E6185_G1_CTL1_MAX_FRAME_1632	0x0400
63 #define MV88E6185_G1_CTL1_RELOAD_EEPROM		0x0200
64 #define MV88E6393X_G1_CTL1_DEVICE2_EN		0x0200
65 #define MV88E6XXX_G1_CTL1_DEVICE_EN		0x0080
66 #define MV88E6XXX_G1_CTL1_STATS_DONE_EN		0x0040
67 #define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN	0x0020
68 #define MV88E6XXX_G1_CTL1_VTU_DONE_EN		0x0010
69 #define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN	0x0008
70 #define MV88E6XXX_G1_CTL1_ATU_DONE_EN		0x0004
71 #define MV88E6XXX_G1_CTL1_TCAM_EN		0x0002
72 #define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN	0x0001
73 
74 /* Offset 0x05: VTU Operation Register */
75 #define MV88E6XXX_G1_VTU_OP			0x05
76 #define MV88E6XXX_G1_VTU_OP_BUSY		0x8000
77 #define MV88E6XXX_G1_VTU_OP_MASK		0x7000
78 #define MV88E6XXX_G1_VTU_OP_FLUSH_ALL		0x1000
79 #define MV88E6XXX_G1_VTU_OP_NOOP		0x2000
80 #define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE	0x3000
81 #define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT	0x4000
82 #define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE	0x5000
83 #define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT	0x6000
84 #define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION	0x7000
85 #define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION	BIT(6)
86 #define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION	BIT(5)
87 #define MV88E6XXX_G1_VTU_OP_SPID_MASK		0xf
88 
89 /* Offset 0x06: VTU VID Register */
90 #define MV88E6XXX_G1_VTU_VID		0x06
91 #define MV88E6XXX_G1_VTU_VID_MASK	0x0fff
92 #define MV88E6390_G1_VTU_VID_PAGE	0x2000
93 #define MV88E6XXX_G1_VTU_VID_VALID	0x1000
94 
95 /* Offset 0x07: VTU/STU Data Register 1
96  * Offset 0x08: VTU/STU Data Register 2
97  * Offset 0x09: VTU/STU Data Register 3
98  */
99 #define MV88E6XXX_G1_VTU_DATA1				0x07
100 #define MV88E6XXX_G1_VTU_DATA2				0x08
101 #define MV88E6XXX_G1_VTU_DATA3				0x09
102 #define MV88E6XXX_G1_VTU_STU_DATA_MASK			0x0003
103 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED	0x0000
104 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED	0x0001
105 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED		0x0002
106 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER	0x0003
107 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED	0x0000
108 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING	0x0001
109 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING	0x0002
110 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING	0x0003
111 
112 /* Offset 0x0A: ATU Control Register */
113 #define MV88E6XXX_G1_ATU_CTL		0x0a
114 #define MV88E6XXX_G1_ATU_CTL_LEARN2ALL	0x0008
115 #define MV88E6161_G1_ATU_CTL_HASH_MASK	0x0003
116 
117 /* Offset 0x0B: ATU Operation Register */
118 #define MV88E6XXX_G1_ATU_OP				0x0b
119 #define MV88E6XXX_G1_ATU_OP_BUSY			0x8000
120 #define MV88E6XXX_G1_ATU_OP_MASK			0x7000
121 #define MV88E6XXX_G1_ATU_OP_NOOP			0x0000
122 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL		0x1000
123 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC	0x2000
124 #define MV88E6XXX_G1_ATU_OP_LOAD_DB			0x3000
125 #define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB			0x4000
126 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB		0x5000
127 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB	0x6000
128 #define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION		0x7000
129 #define MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION		BIT(7)
130 #define MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION		BIT(6)
131 #define MV88E6XXX_G1_ATU_OP_MISS_VIOLATION		BIT(5)
132 #define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION		BIT(4)
133 
134 /* Offset 0x0C: ATU Data Register */
135 #define MV88E6XXX_G1_ATU_DATA					0x0c
136 #define MV88E6XXX_G1_ATU_DATA_TRUNK				0x8000
137 #define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK			0x00f0
138 #define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK			0x3ff0
139 #define MV88E6XXX_G1_ATU_DATA_STATE_MASK			0x000f
140 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_UNUSED			0x0000
141 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_1_OLDEST		0x0001
142 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_2			0x0002
143 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_3			0x0003
144 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_4			0x0004
145 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_5			0x0005
146 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_6			0x0006
147 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_7_NEWEST		0x0007
148 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY		0x0008
149 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY_PO		0x0009
150 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL		0x000a
151 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL_PO	0x000b
152 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT		0x000c
153 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT_PO	0x000d
154 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC			0x000e
155 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_PO		0x000f
156 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED			0x0000
157 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY		0x0004
158 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL		0x0005
159 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT		0x0006
160 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC			0x0007
161 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY_PO		0x000c
162 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL_PO	0x000d
163 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT_PO	0x000e
164 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_PO		0x000f
165 
166 /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
167  * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
168  * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
169  */
170 #define MV88E6XXX_G1_ATU_MAC01		0x0d
171 #define MV88E6XXX_G1_ATU_MAC23		0x0e
172 #define MV88E6XXX_G1_ATU_MAC45		0x0f
173 
174 /* Offset 0x10: IP-PRI Mapping Register 0
175  * Offset 0x11: IP-PRI Mapping Register 1
176  * Offset 0x12: IP-PRI Mapping Register 2
177  * Offset 0x13: IP-PRI Mapping Register 3
178  * Offset 0x14: IP-PRI Mapping Register 4
179  * Offset 0x15: IP-PRI Mapping Register 5
180  * Offset 0x16: IP-PRI Mapping Register 6
181  * Offset 0x17: IP-PRI Mapping Register 7
182  */
183 #define MV88E6XXX_G1_IP_PRI_0	0x10
184 #define MV88E6XXX_G1_IP_PRI_1	0x11
185 #define MV88E6XXX_G1_IP_PRI_2	0x12
186 #define MV88E6XXX_G1_IP_PRI_3	0x13
187 #define MV88E6XXX_G1_IP_PRI_4	0x14
188 #define MV88E6XXX_G1_IP_PRI_5	0x15
189 #define MV88E6XXX_G1_IP_PRI_6	0x16
190 #define MV88E6XXX_G1_IP_PRI_7	0x17
191 
192 /* Offset 0x18: IEEE-PRI Register */
193 #define MV88E6XXX_G1_IEEE_PRI	0x18
194 
195 /* Offset 0x19: Core Tag Type */
196 #define MV88E6185_G1_CORE_TAG_TYPE	0x19
197 
198 /* Offset 0x1A: Monitor Control */
199 #define MV88E6185_G1_MONITOR_CTL			0x1a
200 #define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK	0xf000
201 #define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK	0x0f00
202 #define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK	        0x00f0
203 #define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK	        0x00f0
204 #define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK	0x000f
205 
206 /* Offset 0x1A: Monitor & MGMT Control Register */
207 #define MV88E6390_G1_MONITOR_MGMT_CTL				0x1a
208 #define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE			0x8000
209 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK			0x3f00
210 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO	0x0000
211 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI	0x0100
212 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO	0x0200
213 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI	0x0300
214 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST		0x2000
215 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST		0x2100
216 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST		0x3000
217 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_PTP_CPU_DEST		0x3200
218 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI	0x00e0
219 #define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK			0x00ff
220 
221 /* Offset 0x1C: Global Control 2 */
222 #define MV88E6XXX_G1_CTL2			0x1c
223 #define MV88E6185_G1_CTL2_CASCADE_PORT_MASK	0xf000
224 #define MV88E6185_G1_CTL2_CASCADE_PORT_NONE	0xe000
225 #define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI	0xf000
226 #define MV88E6352_G1_CTL2_HEADER_TYPE_MASK	0xc000
227 #define MV88E6352_G1_CTL2_HEADER_TYPE_ORIG	0x0000
228 #define MV88E6352_G1_CTL2_HEADER_TYPE_MGMT	0x4000
229 #define MV88E6390_G1_CTL2_HEADER_TYPE_LAG	0x8000
230 #define MV88E6352_G1_CTL2_RMU_MODE_MASK		0x3000
231 #define MV88E6352_G1_CTL2_RMU_MODE_DISABLED	0x0000
232 #define MV88E6352_G1_CTL2_RMU_MODE_PORT_4	0x1000
233 #define MV88E6352_G1_CTL2_RMU_MODE_PORT_5	0x2000
234 #define MV88E6352_G1_CTL2_RMU_MODE_PORT_6	0x3000
235 #define MV88E6085_G1_CTL2_DA_CHECK		0x4000
236 #define MV88E6085_G1_CTL2_P10RM			0x2000
237 #define MV88E6085_G1_CTL2_RM_ENABLE		0x1000
238 #define MV88E6352_G1_CTL2_DA_CHECK		0x0800
239 #define MV88E6390_G1_CTL2_RMU_MODE_MASK		0x0700
240 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_0	0x0000
241 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_1	0x0100
242 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_9	0x0200
243 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_10	0x0300
244 #define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA	0x0600
245 #define MV88E6390_G1_CTL2_RMU_MODE_DISABLED	0x0700
246 #define MV88E6390_G1_CTL2_HIST_MODE_MASK	0x00c0
247 #define MV88E6390_G1_CTL2_HIST_MODE_RX		0x0040
248 #define MV88E6390_G1_CTL2_HIST_MODE_TX		0x0080
249 #define MV88E6352_G1_CTL2_CTR_MODE_MASK		0x0060
250 #define MV88E6390_G1_CTL2_CTR_MODE		0x0020
251 #define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK	0x001f
252 
253 /* Offset 0x1D: Stats Operation Register */
254 #define MV88E6XXX_G1_STATS_OP			0x1d
255 #define MV88E6XXX_G1_STATS_OP_BUSY		0x8000
256 #define MV88E6XXX_G1_STATS_OP_NOP		0x0000
257 #define MV88E6XXX_G1_STATS_OP_FLUSH_ALL		0x1000
258 #define MV88E6XXX_G1_STATS_OP_FLUSH_PORT	0x2000
259 #define MV88E6XXX_G1_STATS_OP_READ_CAPTURED	0x4000
260 #define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT	0x5000
261 #define MV88E6XXX_G1_STATS_OP_HIST_RX		0x0400
262 #define MV88E6XXX_G1_STATS_OP_HIST_TX		0x0800
263 #define MV88E6XXX_G1_STATS_OP_HIST_RX_TX	0x0c00
264 #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9	0x0200
265 #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10	0x0400
266 
267 /* Offset 0x1E: Stats Counter Register Bytes 3 & 2
268  * Offset 0x1F: Stats Counter Register Bytes 1 & 0
269  */
270 #define MV88E6XXX_G1_STATS_COUNTER_32	0x1e
271 #define MV88E6XXX_G1_STATS_COUNTER_01	0x1f
272 
273 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
274 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
275 int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
276 			  bit, int val);
277 int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
278 			   u16 mask, u16 val);
279 
280 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
281 
282 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip);
283 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip);
284 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip);
285 
286 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip);
287 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip);
288 
289 int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu);
290 
291 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
292 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
293 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
294 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
295 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
296 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val);
297 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip);
298 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
299 				 enum mv88e6xxx_egress_direction direction,
300 				 int port);
301 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
302 				 enum mv88e6xxx_egress_direction direction,
303 				 int port);
304 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
305 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
306 int mv88e6390_g1_set_ptp_cpu_port(struct mv88e6xxx_chip *chip, int port);
307 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
308 
309 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip);
310 
311 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
312 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
313 
314 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);
315 
316 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip);
317 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip);
318 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip);
319 
320 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index);
321 
322 int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);
323 int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
324 				  unsigned int msecs);
325 int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
326 			     struct mv88e6xxx_atu_entry *entry);
327 int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
328 			       struct mv88e6xxx_atu_entry *entry);
329 int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all);
330 int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port,
331 			    bool all);
332 int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip);
333 void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip);
334 int mv88e6165_g1_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash);
335 int mv88e6165_g1_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash);
336 
337 int mv88e6xxx_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
338 			     struct mv88e6xxx_vtu_entry *entry);
339 int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
340 			     struct mv88e6xxx_vtu_entry *entry);
341 int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
342 			       struct mv88e6xxx_vtu_entry *entry);
343 int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
344 			     struct mv88e6xxx_vtu_entry *entry);
345 int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
346 			       struct mv88e6xxx_vtu_entry *entry);
347 int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
348 			     struct mv88e6xxx_vtu_entry *entry);
349 int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
350 			       struct mv88e6xxx_vtu_entry *entry);
351 int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip);
352 int mv88e6xxx_g1_stu_getnext(struct mv88e6xxx_chip *chip,
353 			     struct mv88e6xxx_stu_entry *entry);
354 int mv88e6352_g1_stu_getnext(struct mv88e6xxx_chip *chip,
355 			     struct mv88e6xxx_stu_entry *entry);
356 int mv88e6352_g1_stu_loadpurge(struct mv88e6xxx_chip *chip,
357 			       struct mv88e6xxx_stu_entry *entry);
358 int mv88e6390_g1_stu_getnext(struct mv88e6xxx_chip *chip,
359 			     struct mv88e6xxx_stu_entry *entry);
360 int mv88e6390_g1_stu_loadpurge(struct mv88e6xxx_chip *chip,
361 			       struct mv88e6xxx_stu_entry *entry);
362 int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip *chip);
363 void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip *chip);
364 int mv88e6xxx_g1_atu_get_next(struct mv88e6xxx_chip *chip, u16 fid);
365 
366 #endif /* _MV88E6XXX_GLOBAL1_H */
367