1a935c052SVivien Didelot /* 2a935c052SVivien Didelot * Marvell 88E6xxx Switch Global (1) Registers support 3a935c052SVivien Didelot * 4a935c052SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 5a935c052SVivien Didelot * 64333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 74333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8a935c052SVivien Didelot * 9a935c052SVivien Didelot * This program is free software; you can redistribute it and/or modify 10a935c052SVivien Didelot * it under the terms of the GNU General Public License as published by 11a935c052SVivien Didelot * the Free Software Foundation; either version 2 of the License, or 12a935c052SVivien Didelot * (at your option) any later version. 13a935c052SVivien Didelot */ 14a935c052SVivien Didelot 15a935c052SVivien Didelot #ifndef _MV88E6XXX_GLOBAL1_H 16a935c052SVivien Didelot #define _MV88E6XXX_GLOBAL1_H 17a935c052SVivien Didelot 184d5f2ba7SVivien Didelot #include "chip.h" 19a935c052SVivien Didelot 20e097097bSVivien Didelot #define GLOBAL_STATUS 0x00 21e097097bSVivien Didelot #define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */ 22e097097bSVivien Didelot #define GLOBAL_STATUS_PPU_STATE_MASK (0x3 << 14) /* 6165 6185 */ 23e097097bSVivien Didelot #define GLOBAL_STATUS_PPU_STATE_DISABLED_RST (0x0 << 14) 24e097097bSVivien Didelot #define GLOBAL_STATUS_PPU_STATE_INITIALIZING (0x1 << 14) 25e097097bSVivien Didelot #define GLOBAL_STATUS_PPU_STATE_DISABLED (0x2 << 14) 26e097097bSVivien Didelot #define GLOBAL_STATUS_PPU_STATE_POLLING (0x3 << 14) 27e097097bSVivien Didelot #define GLOBAL_STATUS_INIT_READY BIT(11) 28e097097bSVivien Didelot #define GLOBAL_STATUS_IRQ_AVB 8 29e097097bSVivien Didelot #define GLOBAL_STATUS_IRQ_DEVICE 7 30e097097bSVivien Didelot #define GLOBAL_STATUS_IRQ_STATS 6 31e097097bSVivien Didelot #define GLOBAL_STATUS_IRQ_VTU_PROBLEM 5 32e097097bSVivien Didelot #define GLOBAL_STATUS_IRQ_VTU_DONE 4 33e097097bSVivien Didelot #define GLOBAL_STATUS_IRQ_ATU_PROBLEM 3 34e097097bSVivien Didelot #define GLOBAL_STATUS_IRQ_ATU_DONE 2 35e097097bSVivien Didelot #define GLOBAL_STATUS_IRQ_TCAM_DONE 1 36e097097bSVivien Didelot #define GLOBAL_STATUS_IRQ_EEPROM_DONE 0 37e097097bSVivien Didelot #define GLOBAL_MAC_01 0x01 38e097097bSVivien Didelot #define GLOBAL_MAC_23 0x02 39e097097bSVivien Didelot #define GLOBAL_MAC_45 0x03 40e097097bSVivien Didelot #define GLOBAL_ATU_FID 0x01 41e097097bSVivien Didelot #define GLOBAL_VTU_FID 0x02 42e097097bSVivien Didelot #define GLOBAL_VTU_FID_MASK 0xfff 43e097097bSVivien Didelot #define GLOBAL_VTU_SID 0x03 /* 6097 6165 6351 6352 */ 44e097097bSVivien Didelot #define GLOBAL_VTU_SID_MASK 0x3f 45e097097bSVivien Didelot #define GLOBAL_CONTROL 0x04 46e097097bSVivien Didelot #define GLOBAL_CONTROL_SW_RESET BIT(15) 47e097097bSVivien Didelot #define GLOBAL_CONTROL_PPU_ENABLE BIT(14) 48e097097bSVivien Didelot #define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */ 49e097097bSVivien Didelot #define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */ 50e097097bSVivien Didelot #define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */ 51e097097bSVivien Didelot #define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */ 52e097097bSVivien Didelot #define GLOBAL_CONTROL_DEVICE_EN BIT(7) 53e097097bSVivien Didelot #define GLOBAL_CONTROL_STATS_DONE_EN BIT(6) 54e097097bSVivien Didelot #define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5) 55e097097bSVivien Didelot #define GLOBAL_CONTROL_VTU_DONE_EN BIT(4) 56e097097bSVivien Didelot #define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3) 57e097097bSVivien Didelot #define GLOBAL_CONTROL_ATU_DONE_EN BIT(2) 58e097097bSVivien Didelot #define GLOBAL_CONTROL_TCAM_EN BIT(1) 59e097097bSVivien Didelot #define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0) 60e097097bSVivien Didelot #define GLOBAL_VTU_OP 0x05 61e097097bSVivien Didelot #define GLOBAL_VTU_OP_BUSY BIT(15) 62e097097bSVivien Didelot #define GLOBAL_VTU_OP_FLUSH_ALL ((0x01 << 12) | GLOBAL_VTU_OP_BUSY) 63e097097bSVivien Didelot #define GLOBAL_VTU_OP_VTU_LOAD_PURGE ((0x03 << 12) | GLOBAL_VTU_OP_BUSY) 64e097097bSVivien Didelot #define GLOBAL_VTU_OP_VTU_GET_NEXT ((0x04 << 12) | GLOBAL_VTU_OP_BUSY) 65e097097bSVivien Didelot #define GLOBAL_VTU_OP_STU_LOAD_PURGE ((0x05 << 12) | GLOBAL_VTU_OP_BUSY) 66e097097bSVivien Didelot #define GLOBAL_VTU_OP_STU_GET_NEXT ((0x06 << 12) | GLOBAL_VTU_OP_BUSY) 67e097097bSVivien Didelot #define GLOBAL_VTU_VID 0x06 68e097097bSVivien Didelot #define GLOBAL_VTU_VID_MASK 0xfff 69e097097bSVivien Didelot #define GLOBAL_VTU_VID_PAGE BIT(13) 70e097097bSVivien Didelot #define GLOBAL_VTU_VID_VALID BIT(12) 71e097097bSVivien Didelot #define GLOBAL_VTU_DATA_0_3 0x07 72e097097bSVivien Didelot #define GLOBAL_VTU_DATA_4_7 0x08 73e097097bSVivien Didelot #define GLOBAL_VTU_DATA_8_11 0x09 74e097097bSVivien Didelot #define GLOBAL_VTU_STU_DATA_MASK 0x03 75e097097bSVivien Didelot #define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x00 76e097097bSVivien Didelot #define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED 0x01 77e097097bSVivien Didelot #define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED 0x02 78e097097bSVivien Didelot #define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x03 79e097097bSVivien Didelot #define GLOBAL_STU_DATA_PORT_STATE_DISABLED 0x00 80e097097bSVivien Didelot #define GLOBAL_STU_DATA_PORT_STATE_BLOCKING 0x01 81e097097bSVivien Didelot #define GLOBAL_STU_DATA_PORT_STATE_LEARNING 0x02 82e097097bSVivien Didelot #define GLOBAL_STU_DATA_PORT_STATE_FORWARDING 0x03 83e097097bSVivien Didelot #define GLOBAL_ATU_CONTROL 0x0a 84e097097bSVivien Didelot #define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3) 85e097097bSVivien Didelot #define GLOBAL_ATU_OP 0x0b 86e097097bSVivien Didelot #define GLOBAL_ATU_OP_BUSY BIT(15) 87e097097bSVivien Didelot #define GLOBAL_ATU_OP_NOP (0 << 12) 88e097097bSVivien Didelot #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY) 89e097097bSVivien Didelot #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY) 90e097097bSVivien Didelot #define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY) 91e097097bSVivien Didelot #define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY) 92e097097bSVivien Didelot #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY) 93e097097bSVivien Didelot #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY) 94e097097bSVivien Didelot #define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY) 95e097097bSVivien Didelot #define GLOBAL_ATU_DATA 0x0c 96e097097bSVivien Didelot #define GLOBAL_ATU_DATA_TRUNK BIT(15) 97e097097bSVivien Didelot #define GLOBAL_ATU_DATA_TRUNK_ID_MASK 0x00f0 98e097097bSVivien Didelot #define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT 4 99e097097bSVivien Didelot #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0 100e097097bSVivien Didelot #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4 101e097097bSVivien Didelot #define GLOBAL_ATU_DATA_STATE_MASK 0x0f 102e097097bSVivien Didelot #define GLOBAL_ATU_DATA_STATE_UNUSED 0x00 103e097097bSVivien Didelot #define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d 104e097097bSVivien Didelot #define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e 105e097097bSVivien Didelot #define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f 106e097097bSVivien Didelot #define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05 107e097097bSVivien Didelot #define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07 108e097097bSVivien Didelot #define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e 109e097097bSVivien Didelot #define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f 110e097097bSVivien Didelot #define GLOBAL_ATU_MAC_01 0x0d 111e097097bSVivien Didelot #define GLOBAL_ATU_MAC_23 0x0e 112e097097bSVivien Didelot #define GLOBAL_ATU_MAC_45 0x0f 113e097097bSVivien Didelot #define GLOBAL_IP_PRI_0 0x10 114e097097bSVivien Didelot #define GLOBAL_IP_PRI_1 0x11 115e097097bSVivien Didelot #define GLOBAL_IP_PRI_2 0x12 116e097097bSVivien Didelot #define GLOBAL_IP_PRI_3 0x13 117e097097bSVivien Didelot #define GLOBAL_IP_PRI_4 0x14 118e097097bSVivien Didelot #define GLOBAL_IP_PRI_5 0x15 119e097097bSVivien Didelot #define GLOBAL_IP_PRI_6 0x16 120e097097bSVivien Didelot #define GLOBAL_IP_PRI_7 0x17 121e097097bSVivien Didelot #define GLOBAL_IEEE_PRI 0x18 122e097097bSVivien Didelot #define GLOBAL_CORE_TAG_TYPE 0x19 123e097097bSVivien Didelot #define GLOBAL_MONITOR_CONTROL 0x1a 124e097097bSVivien Didelot #define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12 125e097097bSVivien Didelot #define GLOBAL_MONITOR_CONTROL_INGRESS_MASK (0xf << 12) 126e097097bSVivien Didelot #define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8 127e097097bSVivien Didelot #define GLOBAL_MONITOR_CONTROL_EGRESS_MASK (0xf << 8) 128e097097bSVivien Didelot #define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4 129e097097bSVivien Didelot #define GLOBAL_MONITOR_CONTROL_ARP_MASK (0xf << 4) 130e097097bSVivien Didelot #define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0 131e097097bSVivien Didelot #define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0) 132e097097bSVivien Didelot #define GLOBAL_MONITOR_CONTROL_UPDATE BIT(15) 133e097097bSVivien Didelot #define GLOBAL_MONITOR_CONTROL_0180C280000000XLO (0x00 << 8) 134e097097bSVivien Didelot #define GLOBAL_MONITOR_CONTROL_0180C280000000XHI (0x01 << 8) 135e097097bSVivien Didelot #define GLOBAL_MONITOR_CONTROL_0180C280000002XLO (0x02 << 8) 136e097097bSVivien Didelot #define GLOBAL_MONITOR_CONTROL_0180C280000002XHI (0x03 << 8) 137e097097bSVivien Didelot #define GLOBAL_MONITOR_CONTROL_INGRESS (0x20 << 8) 138e097097bSVivien Didelot #define GLOBAL_MONITOR_CONTROL_EGRESS (0x21 << 8) 139e097097bSVivien Didelot #define GLOBAL_MONITOR_CONTROL_CPU_DEST (0x30 << 8) 140e097097bSVivien Didelot #define GLOBAL_CONTROL_2 0x1c 141e097097bSVivien Didelot #define GLOBAL_CONTROL_2_NO_CASCADE 0xe000 142e097097bSVivien Didelot #define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000 143e097097bSVivien Didelot #define GLOBAL_CONTROL_2_HIST_RX (0x1 << 6) 144e097097bSVivien Didelot #define GLOBAL_CONTROL_2_HIST_TX (0x2 << 6) 145e097097bSVivien Didelot #define GLOBAL_CONTROL_2_HIST_RX_TX (0x3 << 6) 146e097097bSVivien Didelot #define GLOBAL_STATS_OP 0x1d 147e097097bSVivien Didelot #define GLOBAL_STATS_OP_BUSY BIT(15) 148e097097bSVivien Didelot #define GLOBAL_STATS_OP_NOP (0 << 12) 149e097097bSVivien Didelot #define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY) 150e097097bSVivien Didelot #define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY) 151e097097bSVivien Didelot #define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY) 152e097097bSVivien Didelot #define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY) 153e097097bSVivien Didelot #define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY) 154e097097bSVivien Didelot #define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY) 155e097097bSVivien Didelot #define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY) 156e097097bSVivien Didelot #define GLOBAL_STATS_OP_BANK_1_BIT_9 BIT(9) 157e097097bSVivien Didelot #define GLOBAL_STATS_OP_BANK_1_BIT_10 BIT(10) 158e097097bSVivien Didelot #define GLOBAL_STATS_COUNTER_32 0x1e 159e097097bSVivien Didelot #define GLOBAL_STATS_COUNTER_01 0x1f 160e097097bSVivien Didelot 161a935c052SVivien Didelot int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); 162a935c052SVivien Didelot int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val); 163a935c052SVivien Didelot int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask); 16417e708baSVivien Didelot 16517e708baSVivien Didelot int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip); 16617e708baSVivien Didelot int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip); 16717e708baSVivien Didelot 168a199d8b6SVivien Didelot int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip); 169a199d8b6SVivien Didelot int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip); 170a199d8b6SVivien Didelot 1717f9ef3afSAndrew Lunn int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip); 172a605a0feSAndrew Lunn int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); 173a605a0feSAndrew Lunn int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); 17479523473SAndrew Lunn int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); 175de227387SAndrew Lunn int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip); 1767f9ef3afSAndrew Lunn void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val); 17733641994SAndrew Lunn int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port); 17833641994SAndrew Lunn int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port); 17933641994SAndrew Lunn int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port); 18033641994SAndrew Lunn int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port); 1816e55f698SAndrew Lunn int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 182a935c052SVivien Didelot 183c3a7d4adSVivien Didelot int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all); 184720c6343SVivien Didelot int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip, 185720c6343SVivien Didelot unsigned int msecs); 186dabc1a96SVivien Didelot int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 187dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry); 1889c13c026SVivien Didelot int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid, 1899c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry); 190daefc943SVivien Didelot int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all); 191e606ca36SVivien Didelot int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port, 192e606ca36SVivien Didelot bool all); 193720c6343SVivien Didelot 194f1394b78SVivien Didelot int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 195f1394b78SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 1960ad5daf6SVivien Didelot int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1970ad5daf6SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 198f1394b78SVivien Didelot int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 199f1394b78SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 2000ad5daf6SVivien Didelot int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, 2010ad5daf6SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 202931d1822SVivien Didelot int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 203931d1822SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 204931d1822SVivien Didelot int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, 205931d1822SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 206b486d7c9SVivien Didelot int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip); 207332aa5ccSVivien Didelot 208a935c052SVivien Didelot #endif /* _MV88E6XXX_GLOBAL1_H */ 209