12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2a935c052SVivien Didelot /* 3a935c052SVivien Didelot * Marvell 88E6xxx Switch Global (1) Registers support 4a935c052SVivien Didelot * 5a935c052SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 6a935c052SVivien Didelot * 74333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 84333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9a935c052SVivien Didelot */ 10a935c052SVivien Didelot 11a935c052SVivien Didelot #ifndef _MV88E6XXX_GLOBAL1_H 12a935c052SVivien Didelot #define _MV88E6XXX_GLOBAL1_H 13a935c052SVivien Didelot 144d5f2ba7SVivien Didelot #include "chip.h" 15a935c052SVivien Didelot 1682466921SVivien Didelot /* Offset 0x00: Switch Global Status Register */ 1782466921SVivien Didelot #define MV88E6XXX_G1_STS 0x00 1882466921SVivien Didelot #define MV88E6352_G1_STS_PPU_STATE 0x8000 1982466921SVivien Didelot #define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000 2082466921SVivien Didelot #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000 2182466921SVivien Didelot #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000 2282466921SVivien Didelot #define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000 2382466921SVivien Didelot #define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000 2482466921SVivien Didelot #define MV88E6XXX_G1_STS_INIT_READY 0x0800 2582466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_AVB 8 2682466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_DEVICE 7 2782466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_STATS 6 2862eb1162SAndrew Lunn #define MV88E6XXX_G1_STS_IRQ_VTU_PROB 5 2982466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_VTU_DONE 4 300977644cSAndrew Lunn #define MV88E6XXX_G1_STS_IRQ_ATU_PROB 3 3182466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_ATU_DONE 2 3282466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_TCAM_DONE 1 3382466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0 3482466921SVivien Didelot 354b0c4817SVivien Didelot /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 364b0c4817SVivien Didelot * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 374b0c4817SVivien Didelot * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 384b0c4817SVivien Didelot */ 394b0c4817SVivien Didelot #define MV88E6XXX_G1_MAC_01 0x01 404b0c4817SVivien Didelot #define MV88E6XXX_G1_MAC_23 0x02 414b0c4817SVivien Didelot #define MV88E6XXX_G1_MAC_45 0x03 424b0c4817SVivien Didelot 4327c0e600SVivien Didelot /* Offset 0x01: ATU FID Register */ 4427c0e600SVivien Didelot #define MV88E6352_G1_ATU_FID 0x01 4527c0e600SVivien Didelot 467ec60d6eSVivien Didelot /* Offset 0x02: VTU FID Register */ 477ec60d6eSVivien Didelot #define MV88E6352_G1_VTU_FID 0x02 487ec60d6eSVivien Didelot #define MV88E6352_G1_VTU_FID_MASK 0x0fff 497ec60d6eSVivien Didelot 507ec60d6eSVivien Didelot /* Offset 0x03: VTU SID Register */ 517ec60d6eSVivien Didelot #define MV88E6352_G1_VTU_SID 0x03 527ec60d6eSVivien Didelot #define MV88E6352_G1_VTU_SID_MASK 0x3f 537ec60d6eSVivien Didelot 54d77f4321SVivien Didelot /* Offset 0x04: Switch Global Control Register */ 55d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1 0x04 56d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_SW_RESET 0x8000 57d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_PPU_ENABLE 0x4000 58d77f4321SVivien Didelot #define MV88E6352_G1_CTL1_DISCARD_EXCESS 0x2000 59d77f4321SVivien Didelot #define MV88E6185_G1_CTL1_SCHED_PRIO 0x0800 60d77f4321SVivien Didelot #define MV88E6185_G1_CTL1_MAX_FRAME_1632 0x0400 61d77f4321SVivien Didelot #define MV88E6185_G1_CTL1_RELOAD_EEPROM 0x0200 62d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_DEVICE_EN 0x0080 63d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_STATS_DONE_EN 0x0040 64d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN 0x0020 65d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_VTU_DONE_EN 0x0010 66d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN 0x0008 67d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_ATU_DONE_EN 0x0004 68d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_TCAM_EN 0x0002 69d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN 0x0001 707ec60d6eSVivien Didelot 717ec60d6eSVivien Didelot /* Offset 0x05: VTU Operation Register */ 727ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP 0x05 737ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_BUSY 0x8000 747ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_MASK 0x7000 757ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_FLUSH_ALL 0x1000 767ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_NOOP 0x2000 777ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE 0x3000 787ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT 0x4000 797ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE 0x5000 807ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT 0x6000 8162eb1162SAndrew Lunn #define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION 0x7000 8262eb1162SAndrew Lunn #define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION BIT(6) 8362eb1162SAndrew Lunn #define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION BIT(5) 8462eb1162SAndrew Lunn #define MV88E6XXX_G1_VTU_OP_SPID_MASK 0xf 857ec60d6eSVivien Didelot 867ec60d6eSVivien Didelot /* Offset 0x06: VTU VID Register */ 877ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_VID 0x06 887ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_VID_MASK 0x0fff 897ec60d6eSVivien Didelot #define MV88E6390_G1_VTU_VID_PAGE 0x2000 907ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_VID_VALID 0x1000 917ec60d6eSVivien Didelot 927ec60d6eSVivien Didelot /* Offset 0x07: VTU/STU Data Register 1 937ec60d6eSVivien Didelot * Offset 0x08: VTU/STU Data Register 2 947ec60d6eSVivien Didelot * Offset 0x09: VTU/STU Data Register 3 957ec60d6eSVivien Didelot */ 967ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA1 0x07 977ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA2 0x08 987ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA3 0x09 997ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_STU_DATA_MASK 0x0003 1007ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x0000 1017ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED 0x0001 1027ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED 0x0002 1037ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x0003 1047ec60d6eSVivien Didelot #define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED 0x0000 1057ec60d6eSVivien Didelot #define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING 0x0001 1067ec60d6eSVivien Didelot #define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING 0x0002 1077ec60d6eSVivien Didelot #define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING 0x0003 10827c0e600SVivien Didelot 10927c0e600SVivien Didelot /* Offset 0x0A: ATU Control Register */ 11027c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_CTL 0x0a 11127c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_CTL_LEARN2ALL 0x0008 11227c0e600SVivien Didelot 11327c0e600SVivien Didelot /* Offset 0x0B: ATU Operation Register */ 11427c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP 0x0b 11527c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_BUSY 0x8000 11627c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_MASK 0x7000 11727c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_NOOP 0x0000 11827c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL 0x1000 11927c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC 0x2000 12027c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_LOAD_DB 0x3000 12127c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB 0x4000 12227c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB 0x5000 12327c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB 0x6000 12427c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION 0x7000 1250977644cSAndrew Lunn #define MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION BIT(7) 1260977644cSAndrew Lunn #define MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION BIT(6) 127ddca24dfSAndrew Lunn #define MV88E6XXX_G1_ATU_OP_MISS_VIOLATION BIT(5) 1280977644cSAndrew Lunn #define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION BIT(4) 12927c0e600SVivien Didelot 13027c0e600SVivien Didelot /* Offset 0x0C: ATU Data Register */ 13127c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA 0x0c 13227c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_TRUNK 0x8000 13327c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK 0x00f0 13427c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK 0x3ff0 13527c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MASK 0x000f 136d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_UNUSED 0x0000 137d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_1_OLDEST 0x0001 138d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_2 0x0002 139d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_3 0x0003 140d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_4 0x0004 141d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_5 0x0005 142d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_6 0x0006 143d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_7_NEWEST 0x0007 144d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY 0x0008 145d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY_PO 0x0009 146d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL 0x000a 147d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL_PO 0x000b 148d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT 0x000c 149d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT_PO 0x000d 15027c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC 0x000e 151d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_PO 0x000f 152d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED 0x0000 153d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY 0x0004 154d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL 0x0005 155d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT 0x0006 15627c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC 0x0007 157d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY_PO 0x000c 158d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL_PO 0x000d 159d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT_PO 0x000e 160d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_PO 0x000f 16127c0e600SVivien Didelot 16227c0e600SVivien Didelot /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1 16327c0e600SVivien Didelot * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3 16427c0e600SVivien Didelot * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5 16527c0e600SVivien Didelot */ 16627c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_MAC01 0x0d 16727c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_MAC23 0x0e 16827c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_MAC45 0x0f 16927c0e600SVivien Didelot 170ccba8f3aSVivien Didelot /* Offset 0x10: IP-PRI Mapping Register 0 171ccba8f3aSVivien Didelot * Offset 0x11: IP-PRI Mapping Register 1 172ccba8f3aSVivien Didelot * Offset 0x12: IP-PRI Mapping Register 2 173ccba8f3aSVivien Didelot * Offset 0x13: IP-PRI Mapping Register 3 174ccba8f3aSVivien Didelot * Offset 0x14: IP-PRI Mapping Register 4 175ccba8f3aSVivien Didelot * Offset 0x15: IP-PRI Mapping Register 5 176ccba8f3aSVivien Didelot * Offset 0x16: IP-PRI Mapping Register 6 177ccba8f3aSVivien Didelot * Offset 0x17: IP-PRI Mapping Register 7 178ccba8f3aSVivien Didelot */ 179ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_0 0x10 180ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_1 0x11 181ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_2 0x12 182ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_3 0x13 183ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_4 0x14 184ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_5 0x15 185ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_6 0x16 186ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_7 0x17 187ccba8f3aSVivien Didelot 188ccba8f3aSVivien Didelot /* Offset 0x18: IEEE-PRI Register */ 189ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IEEE_PRI 0x18 190ccba8f3aSVivien Didelot 191ccba8f3aSVivien Didelot /* Offset 0x19: Core Tag Type */ 192ccba8f3aSVivien Didelot #define MV88E6185_G1_CORE_TAG_TYPE 0x19 193101515c8SVivien Didelot 194101515c8SVivien Didelot /* Offset 0x1A: Monitor Control */ 195101515c8SVivien Didelot #define MV88E6185_G1_MONITOR_CTL 0x1a 196101515c8SVivien Didelot #define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK 0xf000 197101515c8SVivien Didelot #define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK 0x0f00 198101515c8SVivien Didelot #define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK 0x00f0 199101515c8SVivien Didelot #define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK 0x00f0 200101515c8SVivien Didelot #define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK 0x000f 201101515c8SVivien Didelot 202101515c8SVivien Didelot /* Offset 0x1A: Monitor & MGMT Control Register */ 203101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL 0x1a 204101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE 0x8000 205101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK 0x3f00 206989f405aSRasmus Villemoes #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO 0x0000 207989f405aSRasmus Villemoes #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI 0x0100 208989f405aSRasmus Villemoes #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO 0x0200 209989f405aSRasmus Villemoes #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI 0x0300 210101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST 0x2000 211101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST 0x2100 212101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST 0x3000 213101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK 0x00ff 214d77f4321SVivien Didelot 215d77f4321SVivien Didelot /* Offset 0x1C: Global Control 2 */ 216d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL2 0x1c 21702317e68SVivien Didelot #define MV88E6185_G1_CTL2_CASCADE_PORT_MASK 0xf000 21802317e68SVivien Didelot #define MV88E6185_G1_CTL2_CASCADE_PORT_NONE 0xe000 21902317e68SVivien Didelot #define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI 0xf000 220408d2debSVivien Didelot #define MV88E6352_G1_CTL2_HEADER_TYPE_MASK 0xc000 221408d2debSVivien Didelot #define MV88E6352_G1_CTL2_HEADER_TYPE_ORIG 0x0000 222408d2debSVivien Didelot #define MV88E6352_G1_CTL2_HEADER_TYPE_MGMT 0x4000 223408d2debSVivien Didelot #define MV88E6390_G1_CTL2_HEADER_TYPE_LAG 0x8000 2249e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_RMU_MODE_MASK 0x3000 2259e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_RMU_MODE_DISABLED 0x0000 2269e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_RMU_MODE_PORT_4 0x1000 2279e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_RMU_MODE_PORT_5 0x2000 2289e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_RMU_MODE_PORT_6 0x3000 2299e5baf9bSVivien Didelot #define MV88E6085_G1_CTL2_DA_CHECK 0x4000 2309e5baf9bSVivien Didelot #define MV88E6085_G1_CTL2_P10RM 0x2000 2319e5baf9bSVivien Didelot #define MV88E6085_G1_CTL2_RM_ENABLE 0x1000 2329e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_DA_CHECK 0x0800 2339e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_MASK 0x0700 2349e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_PORT_0 0x0000 2359e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_PORT_1 0x0100 2369e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_PORT_9 0x0200 2379e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_PORT_10 0x0300 2389e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA 0x0600 2399e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_DISABLED 0x0700 240408d2debSVivien Didelot #define MV88E6390_G1_CTL2_HIST_MODE_MASK 0x00c0 241408d2debSVivien Didelot #define MV88E6390_G1_CTL2_HIST_MODE_RX 0x0040 242408d2debSVivien Didelot #define MV88E6390_G1_CTL2_HIST_MODE_TX 0x0080 243408d2debSVivien Didelot #define MV88E6352_G1_CTL2_CTR_MODE_MASK 0x0060 244408d2debSVivien Didelot #define MV88E6390_G1_CTL2_CTR_MODE 0x0020 24523c98919SVivien Didelot #define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK 0x001f 246d77f4321SVivien Didelot 24757d1ef38SVivien Didelot /* Offset 0x1D: Stats Operation Register */ 24857d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP 0x1d 24957d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_BUSY 0x8000 25057d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_NOP 0x0000 25157d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_FLUSH_ALL 0x1000 25257d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_FLUSH_PORT 0x2000 25357d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_READ_CAPTURED 0x4000 25457d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT 0x5000 25557d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_HIST_RX 0x0400 25657d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_HIST_TX 0x0800 25757d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_HIST_RX_TX 0x0c00 25857d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9 0x0200 25957d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10 0x0400 26057d1ef38SVivien Didelot 26157d1ef38SVivien Didelot /* Offset 0x1E: Stats Counter Register Bytes 3 & 2 26257d1ef38SVivien Didelot * Offset 0x1F: Stats Counter Register Bytes 1 & 0 26357d1ef38SVivien Didelot */ 26457d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_COUNTER_32 0x1e 26557d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_COUNTER_01 0x1f 266e097097bSVivien Didelot 267a935c052SVivien Didelot int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); 268a935c052SVivien Didelot int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val); 26919fb7f69SVivien Didelot int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int 27019fb7f69SVivien Didelot bit, int val); 271683f2244SVivien Didelot int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, 272683f2244SVivien Didelot u16 mask, u16 val); 27317e708baSVivien Didelot 2744b0c4817SVivien Didelot int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr); 2754b0c4817SVivien Didelot 27617e708baSVivien Didelot int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip); 27717e708baSVivien Didelot int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip); 2781f71836fSRasmus Villemoes int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip); 27917e708baSVivien Didelot 280a199d8b6SVivien Didelot int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip); 281a199d8b6SVivien Didelot int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip); 282a199d8b6SVivien Didelot 283a605a0feSAndrew Lunn int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); 284a605a0feSAndrew Lunn int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); 28579523473SAndrew Lunn int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); 28640cff8fcSAndrew Lunn int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip); 287de227387SAndrew Lunn int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip); 2887f9ef3afSAndrew Lunn void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val); 28940cff8fcSAndrew Lunn int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip); 29033641994SAndrew Lunn int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port); 29133641994SAndrew Lunn int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port); 29233641994SAndrew Lunn int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port); 29333641994SAndrew Lunn int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port); 2946e55f698SAndrew Lunn int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 295a935c052SVivien Didelot 29693e18d61SVivien Didelot int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip); 297df63b0d9SRasmus Villemoes 29893e18d61SVivien Didelot int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip); 299df63b0d9SRasmus Villemoes int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip); 30093e18d61SVivien Didelot 30102317e68SVivien Didelot int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port); 30202317e68SVivien Didelot 3039e5baf9bSVivien Didelot int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip); 3049e5baf9bSVivien Didelot int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip); 3059e5baf9bSVivien Didelot int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip); 3069e5baf9bSVivien Didelot 30723c98919SVivien Didelot int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index); 30823c98919SVivien Didelot 309c3a7d4adSVivien Didelot int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all); 310720c6343SVivien Didelot int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip, 311720c6343SVivien Didelot unsigned int msecs); 312dabc1a96SVivien Didelot int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 313dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry); 3149c13c026SVivien Didelot int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid, 3159c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry); 316daefc943SVivien Didelot int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all); 317e606ca36SVivien Didelot int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port, 318e606ca36SVivien Didelot bool all); 3190977644cSAndrew Lunn int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip); 3200977644cSAndrew Lunn void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip); 321720c6343SVivien Didelot 322f1394b78SVivien Didelot int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 323f1394b78SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 3240ad5daf6SVivien Didelot int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, 3250ad5daf6SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 326bec8e572SRasmus Villemoes int mv88e6250_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 327bec8e572SRasmus Villemoes struct mv88e6xxx_vtu_entry *entry); 328bec8e572SRasmus Villemoes int mv88e6250_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, 329bec8e572SRasmus Villemoes struct mv88e6xxx_vtu_entry *entry); 330f1394b78SVivien Didelot int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 331f1394b78SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 3320ad5daf6SVivien Didelot int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, 3330ad5daf6SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 334931d1822SVivien Didelot int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 335931d1822SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 336931d1822SVivien Didelot int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, 337931d1822SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 338b486d7c9SVivien Didelot int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip); 33962eb1162SAndrew Lunn int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip *chip); 34062eb1162SAndrew Lunn void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip *chip); 341332aa5ccSVivien Didelot 342a935c052SVivien Didelot #endif /* _MV88E6XXX_GLOBAL1_H */ 343