1a935c052SVivien Didelot /* 2a935c052SVivien Didelot * Marvell 88E6xxx Switch Global (1) Registers support 3a935c052SVivien Didelot * 4a935c052SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 5a935c052SVivien Didelot * 64333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 74333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8a935c052SVivien Didelot * 9a935c052SVivien Didelot * This program is free software; you can redistribute it and/or modify 10a935c052SVivien Didelot * it under the terms of the GNU General Public License as published by 11a935c052SVivien Didelot * the Free Software Foundation; either version 2 of the License, or 12a935c052SVivien Didelot * (at your option) any later version. 13a935c052SVivien Didelot */ 14a935c052SVivien Didelot 15a935c052SVivien Didelot #ifndef _MV88E6XXX_GLOBAL1_H 16a935c052SVivien Didelot #define _MV88E6XXX_GLOBAL1_H 17a935c052SVivien Didelot 184d5f2ba7SVivien Didelot #include "chip.h" 19a935c052SVivien Didelot 2082466921SVivien Didelot /* Offset 0x00: Switch Global Status Register */ 2182466921SVivien Didelot #define MV88E6XXX_G1_STS 0x00 2282466921SVivien Didelot #define MV88E6352_G1_STS_PPU_STATE 0x8000 2382466921SVivien Didelot #define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000 2482466921SVivien Didelot #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000 2582466921SVivien Didelot #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000 2682466921SVivien Didelot #define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000 2782466921SVivien Didelot #define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000 2882466921SVivien Didelot #define MV88E6XXX_G1_STS_INIT_READY 0x0800 2982466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_AVB 8 3082466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_DEVICE 7 3182466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_STATS 6 3262eb1162SAndrew Lunn #define MV88E6XXX_G1_STS_IRQ_VTU_PROB 5 3382466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_VTU_DONE 4 340977644cSAndrew Lunn #define MV88E6XXX_G1_STS_IRQ_ATU_PROB 3 3582466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_ATU_DONE 2 3682466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_TCAM_DONE 1 3782466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0 3882466921SVivien Didelot 394b0c4817SVivien Didelot /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 404b0c4817SVivien Didelot * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 414b0c4817SVivien Didelot * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 424b0c4817SVivien Didelot */ 434b0c4817SVivien Didelot #define MV88E6XXX_G1_MAC_01 0x01 444b0c4817SVivien Didelot #define MV88E6XXX_G1_MAC_23 0x02 454b0c4817SVivien Didelot #define MV88E6XXX_G1_MAC_45 0x03 464b0c4817SVivien Didelot 4727c0e600SVivien Didelot /* Offset 0x01: ATU FID Register */ 4827c0e600SVivien Didelot #define MV88E6352_G1_ATU_FID 0x01 4927c0e600SVivien Didelot 507ec60d6eSVivien Didelot /* Offset 0x02: VTU FID Register */ 517ec60d6eSVivien Didelot #define MV88E6352_G1_VTU_FID 0x02 527ec60d6eSVivien Didelot #define MV88E6352_G1_VTU_FID_MASK 0x0fff 537ec60d6eSVivien Didelot 547ec60d6eSVivien Didelot /* Offset 0x03: VTU SID Register */ 557ec60d6eSVivien Didelot #define MV88E6352_G1_VTU_SID 0x03 567ec60d6eSVivien Didelot #define MV88E6352_G1_VTU_SID_MASK 0x3f 577ec60d6eSVivien Didelot 58d77f4321SVivien Didelot /* Offset 0x04: Switch Global Control Register */ 59d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1 0x04 60d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_SW_RESET 0x8000 61d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_PPU_ENABLE 0x4000 62d77f4321SVivien Didelot #define MV88E6352_G1_CTL1_DISCARD_EXCESS 0x2000 63d77f4321SVivien Didelot #define MV88E6185_G1_CTL1_SCHED_PRIO 0x0800 64d77f4321SVivien Didelot #define MV88E6185_G1_CTL1_MAX_FRAME_1632 0x0400 65d77f4321SVivien Didelot #define MV88E6185_G1_CTL1_RELOAD_EEPROM 0x0200 66d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_DEVICE_EN 0x0080 67d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_STATS_DONE_EN 0x0040 68d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN 0x0020 69d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_VTU_DONE_EN 0x0010 70d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN 0x0008 71d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_ATU_DONE_EN 0x0004 72d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_TCAM_EN 0x0002 73d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN 0x0001 747ec60d6eSVivien Didelot 757ec60d6eSVivien Didelot /* Offset 0x05: VTU Operation Register */ 767ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP 0x05 777ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_BUSY 0x8000 787ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_MASK 0x7000 797ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_FLUSH_ALL 0x1000 807ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_NOOP 0x2000 817ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE 0x3000 827ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT 0x4000 837ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE 0x5000 847ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT 0x6000 8562eb1162SAndrew Lunn #define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION 0x7000 8662eb1162SAndrew Lunn #define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION BIT(6) 8762eb1162SAndrew Lunn #define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION BIT(5) 8862eb1162SAndrew Lunn #define MV88E6XXX_G1_VTU_OP_SPID_MASK 0xf 897ec60d6eSVivien Didelot 907ec60d6eSVivien Didelot /* Offset 0x06: VTU VID Register */ 917ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_VID 0x06 927ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_VID_MASK 0x0fff 937ec60d6eSVivien Didelot #define MV88E6390_G1_VTU_VID_PAGE 0x2000 947ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_VID_VALID 0x1000 957ec60d6eSVivien Didelot 967ec60d6eSVivien Didelot /* Offset 0x07: VTU/STU Data Register 1 977ec60d6eSVivien Didelot * Offset 0x08: VTU/STU Data Register 2 987ec60d6eSVivien Didelot * Offset 0x09: VTU/STU Data Register 3 997ec60d6eSVivien Didelot */ 1007ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA1 0x07 1017ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA2 0x08 1027ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA3 0x09 1037ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_STU_DATA_MASK 0x0003 1047ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x0000 1057ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED 0x0001 1067ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED 0x0002 1077ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x0003 1087ec60d6eSVivien Didelot #define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED 0x0000 1097ec60d6eSVivien Didelot #define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING 0x0001 1107ec60d6eSVivien Didelot #define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING 0x0002 1117ec60d6eSVivien Didelot #define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING 0x0003 11227c0e600SVivien Didelot 11327c0e600SVivien Didelot /* Offset 0x0A: ATU Control Register */ 11427c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_CTL 0x0a 11527c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_CTL_LEARN2ALL 0x0008 11627c0e600SVivien Didelot 11727c0e600SVivien Didelot /* Offset 0x0B: ATU Operation Register */ 11827c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP 0x0b 11927c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_BUSY 0x8000 12027c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_MASK 0x7000 12127c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_NOOP 0x0000 12227c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL 0x1000 12327c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC 0x2000 12427c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_LOAD_DB 0x3000 12527c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB 0x4000 12627c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB 0x5000 12727c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB 0x6000 12827c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION 0x7000 1290977644cSAndrew Lunn #define MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION BIT(7) 1300977644cSAndrew Lunn #define MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION BIT(6) 131ddca24dfSAndrew Lunn #define MV88E6XXX_G1_ATU_OP_MISS_VIOLATION BIT(5) 1320977644cSAndrew Lunn #define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION BIT(4) 13327c0e600SVivien Didelot 13427c0e600SVivien Didelot /* Offset 0x0C: ATU Data Register */ 13527c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA 0x0c 13627c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_TRUNK 0x8000 13727c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK 0x00f0 13827c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK 0x3ff0 13927c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MASK 0x000f 14027c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UNUSED 0x0000 14127c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_MGMT 0x000d 14227c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC 0x000e 14327c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_PRIO_OVER 0x000f 14427c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_NONE_RATE 0x0005 14527c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC 0x0007 14627c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_MGMT 0x000e 14727c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_PRIO_OVER 0x000f 14827c0e600SVivien Didelot 14927c0e600SVivien Didelot /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1 15027c0e600SVivien Didelot * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3 15127c0e600SVivien Didelot * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5 15227c0e600SVivien Didelot */ 15327c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_MAC01 0x0d 15427c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_MAC23 0x0e 15527c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_MAC45 0x0f 15627c0e600SVivien Didelot 157ccba8f3aSVivien Didelot /* Offset 0x10: IP-PRI Mapping Register 0 158ccba8f3aSVivien Didelot * Offset 0x11: IP-PRI Mapping Register 1 159ccba8f3aSVivien Didelot * Offset 0x12: IP-PRI Mapping Register 2 160ccba8f3aSVivien Didelot * Offset 0x13: IP-PRI Mapping Register 3 161ccba8f3aSVivien Didelot * Offset 0x14: IP-PRI Mapping Register 4 162ccba8f3aSVivien Didelot * Offset 0x15: IP-PRI Mapping Register 5 163ccba8f3aSVivien Didelot * Offset 0x16: IP-PRI Mapping Register 6 164ccba8f3aSVivien Didelot * Offset 0x17: IP-PRI Mapping Register 7 165ccba8f3aSVivien Didelot */ 166ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_0 0x10 167ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_1 0x11 168ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_2 0x12 169ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_3 0x13 170ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_4 0x14 171ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_5 0x15 172ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_6 0x16 173ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_7 0x17 174ccba8f3aSVivien Didelot 175ccba8f3aSVivien Didelot /* Offset 0x18: IEEE-PRI Register */ 176ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IEEE_PRI 0x18 177ccba8f3aSVivien Didelot 178ccba8f3aSVivien Didelot /* Offset 0x19: Core Tag Type */ 179ccba8f3aSVivien Didelot #define MV88E6185_G1_CORE_TAG_TYPE 0x19 180101515c8SVivien Didelot 181101515c8SVivien Didelot /* Offset 0x1A: Monitor Control */ 182101515c8SVivien Didelot #define MV88E6185_G1_MONITOR_CTL 0x1a 183101515c8SVivien Didelot #define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK 0xf000 184101515c8SVivien Didelot #define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK 0x0f00 185101515c8SVivien Didelot #define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK 0x00f0 186101515c8SVivien Didelot #define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK 0x00f0 187101515c8SVivien Didelot #define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK 0x000f 188101515c8SVivien Didelot 189101515c8SVivien Didelot /* Offset 0x1A: Monitor & MGMT Control Register */ 190101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL 0x1a 191101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE 0x8000 192101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK 0x3f00 193989f405aSRasmus Villemoes #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO 0x0000 194989f405aSRasmus Villemoes #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI 0x0100 195989f405aSRasmus Villemoes #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO 0x0200 196989f405aSRasmus Villemoes #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI 0x0300 197101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST 0x2000 198101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST 0x2100 199101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST 0x3000 200101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK 0x00ff 201d77f4321SVivien Didelot 202d77f4321SVivien Didelot /* Offset 0x1C: Global Control 2 */ 203d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL2 0x1c 20402317e68SVivien Didelot #define MV88E6185_G1_CTL2_CASCADE_PORT_MASK 0xf000 20502317e68SVivien Didelot #define MV88E6185_G1_CTL2_CASCADE_PORT_NONE 0xe000 20602317e68SVivien Didelot #define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI 0xf000 207408d2debSVivien Didelot #define MV88E6352_G1_CTL2_HEADER_TYPE_MASK 0xc000 208408d2debSVivien Didelot #define MV88E6352_G1_CTL2_HEADER_TYPE_ORIG 0x0000 209408d2debSVivien Didelot #define MV88E6352_G1_CTL2_HEADER_TYPE_MGMT 0x4000 210408d2debSVivien Didelot #define MV88E6390_G1_CTL2_HEADER_TYPE_LAG 0x8000 2119e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_RMU_MODE_MASK 0x3000 2129e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_RMU_MODE_DISABLED 0x0000 2139e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_RMU_MODE_PORT_4 0x1000 2149e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_RMU_MODE_PORT_5 0x2000 2159e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_RMU_MODE_PORT_6 0x3000 2169e5baf9bSVivien Didelot #define MV88E6085_G1_CTL2_DA_CHECK 0x4000 2179e5baf9bSVivien Didelot #define MV88E6085_G1_CTL2_P10RM 0x2000 2189e5baf9bSVivien Didelot #define MV88E6085_G1_CTL2_RM_ENABLE 0x1000 2199e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_DA_CHECK 0x0800 2209e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_MASK 0x0700 2219e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_PORT_0 0x0000 2229e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_PORT_1 0x0100 2239e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_PORT_9 0x0200 2249e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_PORT_10 0x0300 2259e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA 0x0600 2269e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_DISABLED 0x0700 227408d2debSVivien Didelot #define MV88E6390_G1_CTL2_HIST_MODE_MASK 0x00c0 228408d2debSVivien Didelot #define MV88E6390_G1_CTL2_HIST_MODE_RX 0x0040 229408d2debSVivien Didelot #define MV88E6390_G1_CTL2_HIST_MODE_TX 0x0080 230408d2debSVivien Didelot #define MV88E6352_G1_CTL2_CTR_MODE_MASK 0x0060 231408d2debSVivien Didelot #define MV88E6390_G1_CTL2_CTR_MODE 0x0020 23223c98919SVivien Didelot #define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK 0x001f 233d77f4321SVivien Didelot 23457d1ef38SVivien Didelot /* Offset 0x1D: Stats Operation Register */ 23557d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP 0x1d 23657d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_BUSY 0x8000 23757d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_NOP 0x0000 23857d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_FLUSH_ALL 0x1000 23957d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_FLUSH_PORT 0x2000 24057d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_READ_CAPTURED 0x4000 24157d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT 0x5000 24257d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_HIST_RX 0x0400 24357d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_HIST_TX 0x0800 24457d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_HIST_RX_TX 0x0c00 24557d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9 0x0200 24657d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10 0x0400 24757d1ef38SVivien Didelot 24857d1ef38SVivien Didelot /* Offset 0x1E: Stats Counter Register Bytes 3 & 2 24957d1ef38SVivien Didelot * Offset 0x1F: Stats Counter Register Bytes 1 & 0 25057d1ef38SVivien Didelot */ 25157d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_COUNTER_32 0x1e 25257d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_COUNTER_01 0x1f 253e097097bSVivien Didelot 254a935c052SVivien Didelot int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); 255a935c052SVivien Didelot int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val); 256a935c052SVivien Didelot int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask); 25717e708baSVivien Didelot 2584b0c4817SVivien Didelot int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr); 2594b0c4817SVivien Didelot 26017e708baSVivien Didelot int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip); 26117e708baSVivien Didelot int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip); 26217e708baSVivien Didelot 263a199d8b6SVivien Didelot int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip); 264a199d8b6SVivien Didelot int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip); 265a199d8b6SVivien Didelot 2667f9ef3afSAndrew Lunn int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip); 267a605a0feSAndrew Lunn int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); 268a605a0feSAndrew Lunn int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); 26979523473SAndrew Lunn int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); 27040cff8fcSAndrew Lunn int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip); 271de227387SAndrew Lunn int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip); 2727f9ef3afSAndrew Lunn void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val); 27340cff8fcSAndrew Lunn int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip); 27433641994SAndrew Lunn int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port); 27533641994SAndrew Lunn int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port); 27633641994SAndrew Lunn int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port); 27733641994SAndrew Lunn int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port); 2786e55f698SAndrew Lunn int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 279a935c052SVivien Didelot 28093e18d61SVivien Didelot int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip); 28193e18d61SVivien Didelot int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip); 28293e18d61SVivien Didelot 28302317e68SVivien Didelot int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port); 28402317e68SVivien Didelot 2859e5baf9bSVivien Didelot int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip); 2869e5baf9bSVivien Didelot int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip); 2879e5baf9bSVivien Didelot int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip); 2889e5baf9bSVivien Didelot 28923c98919SVivien Didelot int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index); 29023c98919SVivien Didelot 291c3a7d4adSVivien Didelot int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all); 292720c6343SVivien Didelot int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip, 293720c6343SVivien Didelot unsigned int msecs); 294dabc1a96SVivien Didelot int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 295dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry); 2969c13c026SVivien Didelot int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid, 2979c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry); 298daefc943SVivien Didelot int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all); 299e606ca36SVivien Didelot int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port, 300e606ca36SVivien Didelot bool all); 3010977644cSAndrew Lunn int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip); 3020977644cSAndrew Lunn void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip); 303720c6343SVivien Didelot 304f1394b78SVivien Didelot int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 305f1394b78SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 3060ad5daf6SVivien Didelot int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, 3070ad5daf6SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 308f1394b78SVivien Didelot int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 309f1394b78SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 3100ad5daf6SVivien Didelot int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, 3110ad5daf6SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 312931d1822SVivien Didelot int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 313931d1822SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 314931d1822SVivien Didelot int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, 315931d1822SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 316b486d7c9SVivien Didelot int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip); 31762eb1162SAndrew Lunn int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip *chip); 31862eb1162SAndrew Lunn void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip *chip); 319332aa5ccSVivien Didelot 320a935c052SVivien Didelot #endif /* _MV88E6XXX_GLOBAL1_H */ 321