xref: /openbmc/linux/drivers/net/dsa/mv88e6xxx/chip.h (revision e7253313)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Marvell 88E6xxx Ethernet switch single-chip definition
4  *
5  * Copyright (c) 2008 Marvell Semiconductor
6  */
7 
8 #ifndef _MV88E6XXX_CHIP_H
9 #define _MV88E6XXX_CHIP_H
10 
11 #include <linux/idr.h>
12 #include <linux/if_vlan.h>
13 #include <linux/irq.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/kthread.h>
16 #include <linux/phy.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/timecounter.h>
19 #include <net/dsa.h>
20 
21 #define MV88E6XXX_N_FID		4096
22 
23 /* PVT limits for 4-bit port and 5-bit switch */
24 #define MV88E6XXX_MAX_PVT_SWITCHES	32
25 #define MV88E6XXX_MAX_PVT_PORTS		16
26 
27 #define MV88E6XXX_MAX_GPIO	16
28 
29 enum mv88e6xxx_egress_mode {
30 	MV88E6XXX_EGRESS_MODE_UNMODIFIED,
31 	MV88E6XXX_EGRESS_MODE_UNTAGGED,
32 	MV88E6XXX_EGRESS_MODE_TAGGED,
33 	MV88E6XXX_EGRESS_MODE_ETHERTYPE,
34 };
35 
36 enum mv88e6xxx_egress_direction {
37         MV88E6XXX_EGRESS_DIR_INGRESS,
38         MV88E6XXX_EGRESS_DIR_EGRESS,
39 };
40 
41 enum mv88e6xxx_frame_mode {
42 	MV88E6XXX_FRAME_MODE_NORMAL,
43 	MV88E6XXX_FRAME_MODE_DSA,
44 	MV88E6XXX_FRAME_MODE_PROVIDER,
45 	MV88E6XXX_FRAME_MODE_ETHERTYPE,
46 };
47 
48 /* List of supported models */
49 enum mv88e6xxx_model {
50 	MV88E6085,
51 	MV88E6095,
52 	MV88E6097,
53 	MV88E6123,
54 	MV88E6131,
55 	MV88E6141,
56 	MV88E6161,
57 	MV88E6165,
58 	MV88E6171,
59 	MV88E6172,
60 	MV88E6175,
61 	MV88E6176,
62 	MV88E6185,
63 	MV88E6190,
64 	MV88E6190X,
65 	MV88E6191,
66 	MV88E6220,
67 	MV88E6240,
68 	MV88E6250,
69 	MV88E6290,
70 	MV88E6320,
71 	MV88E6321,
72 	MV88E6341,
73 	MV88E6350,
74 	MV88E6351,
75 	MV88E6352,
76 	MV88E6390,
77 	MV88E6390X,
78 };
79 
80 enum mv88e6xxx_family {
81 	MV88E6XXX_FAMILY_NONE,
82 	MV88E6XXX_FAMILY_6065,	/* 6031 6035 6061 6065 */
83 	MV88E6XXX_FAMILY_6095,	/* 6092 6095 */
84 	MV88E6XXX_FAMILY_6097,	/* 6046 6085 6096 6097 */
85 	MV88E6XXX_FAMILY_6165,	/* 6123 6161 6165 */
86 	MV88E6XXX_FAMILY_6185,	/* 6108 6121 6122 6131 6152 6155 6182 6185 */
87 	MV88E6XXX_FAMILY_6250,	/* 6220 6250 */
88 	MV88E6XXX_FAMILY_6320,	/* 6320 6321 */
89 	MV88E6XXX_FAMILY_6341,	/* 6141 6341 */
90 	MV88E6XXX_FAMILY_6351,	/* 6171 6175 6350 6351 */
91 	MV88E6XXX_FAMILY_6352,	/* 6172 6176 6240 6352 */
92 	MV88E6XXX_FAMILY_6390,  /* 6190 6190X 6191 6290 6390 6390X */
93 };
94 
95 struct mv88e6xxx_ops;
96 
97 struct mv88e6xxx_info {
98 	enum mv88e6xxx_family family;
99 	u16 prod_num;
100 	const char *name;
101 	unsigned int num_databases;
102 	unsigned int num_macs;
103 	unsigned int num_ports;
104 	unsigned int num_internal_phys;
105 	unsigned int num_gpio;
106 	unsigned int max_vid;
107 	unsigned int port_base_addr;
108 	unsigned int phy_base_addr;
109 	unsigned int global1_addr;
110 	unsigned int global2_addr;
111 	unsigned int age_time_coeff;
112 	unsigned int g1_irqs;
113 	unsigned int g2_irqs;
114 	bool pvt;
115 
116 	/* Mark certain ports as invalid. This is required for example for the
117 	 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
118 	 * ports 2-4 are not routet to pins.
119 	 */
120 	unsigned int invalid_port_mask;
121 	/* Multi-chip Addressing Mode.
122 	 * Some chips respond to only 2 registers of its own SMI device address
123 	 * when it is non-zero, and use indirect access to internal registers.
124 	 */
125 	bool multi_chip;
126 	/* Dual-chip Addressing Mode
127 	 * Some chips respond to only half of the 32 SMI addresses,
128 	 * allowing two to coexist on the same SMI interface.
129 	 */
130 	bool dual_chip;
131 
132 	enum dsa_tag_protocol tag_protocol;
133 
134 	/* Mask for FromPort and ToPort value of PortVec used in ATU Move
135 	 * operation. 0 means that the ATU Move operation is not supported.
136 	 */
137 	u8 atu_move_port_mask;
138 	const struct mv88e6xxx_ops *ops;
139 
140 	/* Supports PTP */
141 	bool ptp_support;
142 };
143 
144 struct mv88e6xxx_atu_entry {
145 	u8	state;
146 	bool	trunk;
147 	u16	portvec;
148 	u8	mac[ETH_ALEN];
149 };
150 
151 struct mv88e6xxx_vtu_entry {
152 	u16	vid;
153 	u16	fid;
154 	u8	sid;
155 	bool	valid;
156 	u8	member[DSA_MAX_PORTS];
157 	u8	state[DSA_MAX_PORTS];
158 };
159 
160 struct mv88e6xxx_bus_ops;
161 struct mv88e6xxx_irq_ops;
162 struct mv88e6xxx_gpio_ops;
163 struct mv88e6xxx_avb_ops;
164 struct mv88e6xxx_ptp_ops;
165 
166 struct mv88e6xxx_irq {
167 	u16 masked;
168 	struct irq_chip chip;
169 	struct irq_domain *domain;
170 	unsigned int nirqs;
171 };
172 
173 /* state flags for mv88e6xxx_port_hwtstamp::state */
174 enum {
175 	MV88E6XXX_HWTSTAMP_ENABLED,
176 	MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
177 };
178 
179 struct mv88e6xxx_port_hwtstamp {
180 	/* Port index */
181 	int port_id;
182 
183 	/* Timestamping state */
184 	unsigned long state;
185 
186 	/* Resources for receive timestamping */
187 	struct sk_buff_head rx_queue;
188 	struct sk_buff_head rx_queue2;
189 
190 	/* Resources for transmit timestamping */
191 	unsigned long tx_tstamp_start;
192 	struct sk_buff *tx_skb;
193 	u16 tx_seq_id;
194 
195 	/* Current timestamp configuration */
196 	struct hwtstamp_config tstamp_config;
197 };
198 
199 enum mv88e6xxx_policy_mapping {
200 	MV88E6XXX_POLICY_MAPPING_DA,
201 	MV88E6XXX_POLICY_MAPPING_SA,
202 	MV88E6XXX_POLICY_MAPPING_VTU,
203 	MV88E6XXX_POLICY_MAPPING_ETYPE,
204 	MV88E6XXX_POLICY_MAPPING_PPPOE,
205 	MV88E6XXX_POLICY_MAPPING_VBAS,
206 	MV88E6XXX_POLICY_MAPPING_OPT82,
207 	MV88E6XXX_POLICY_MAPPING_UDP,
208 };
209 
210 enum mv88e6xxx_policy_action {
211 	MV88E6XXX_POLICY_ACTION_NORMAL,
212 	MV88E6XXX_POLICY_ACTION_MIRROR,
213 	MV88E6XXX_POLICY_ACTION_TRAP,
214 	MV88E6XXX_POLICY_ACTION_DISCARD,
215 };
216 
217 struct mv88e6xxx_policy {
218 	enum mv88e6xxx_policy_mapping mapping;
219 	enum mv88e6xxx_policy_action action;
220 	struct ethtool_rx_flow_spec fs;
221 	u8 addr[ETH_ALEN];
222 	int port;
223 	u16 vid;
224 };
225 
226 struct mv88e6xxx_port {
227 	struct mv88e6xxx_chip *chip;
228 	int port;
229 	u64 serdes_stats[2];
230 	u64 atu_member_violation;
231 	u64 atu_miss_violation;
232 	u64 atu_full_violation;
233 	u64 vtu_member_violation;
234 	u64 vtu_miss_violation;
235 	u8 cmode;
236 	bool mirror_ingress;
237 	bool mirror_egress;
238 	unsigned int serdes_irq;
239 };
240 
241 struct mv88e6xxx_chip {
242 	const struct mv88e6xxx_info *info;
243 
244 	/* The dsa_switch this private structure is related to */
245 	struct dsa_switch *ds;
246 
247 	/* The device this structure is associated to */
248 	struct device *dev;
249 
250 	/* This mutex protects the access to the switch registers */
251 	struct mutex reg_lock;
252 
253 	/* The MII bus and the address on the bus that is used to
254 	 * communication with the switch
255 	 */
256 	const struct mv88e6xxx_bus_ops *smi_ops;
257 	struct mii_bus *bus;
258 	int sw_addr;
259 
260 	/* Handles automatic disabling and re-enabling of the PHY
261 	 * polling unit.
262 	 */
263 	const struct mv88e6xxx_bus_ops *phy_ops;
264 	struct mutex		ppu_mutex;
265 	int			ppu_disabled;
266 	struct work_struct	ppu_work;
267 	struct timer_list	ppu_timer;
268 
269 	/* This mutex serialises access to the statistics unit.
270 	 * Hold this mutex over snapshot + dump sequences.
271 	 */
272 	struct mutex	stats_mutex;
273 
274 	/* A switch may have a GPIO line tied to its reset pin. Parse
275 	 * this from the device tree, and use it before performing
276 	 * switch soft reset.
277 	 */
278 	struct gpio_desc *reset;
279 
280 	/* set to size of eeprom if supported by the switch */
281 	u32 eeprom_len;
282 
283 	/* List of mdio busses */
284 	struct list_head mdios;
285 
286 	/* Policy Control List IDs and rules */
287 	struct idr policies;
288 
289 	/* There can be two interrupt controllers, which are chained
290 	 * off a GPIO as interrupt source
291 	 */
292 	struct mv88e6xxx_irq g1_irq;
293 	struct mv88e6xxx_irq g2_irq;
294 	int irq;
295 	int device_irq;
296 	int watchdog_irq;
297 
298 	int atu_prob_irq;
299 	int vtu_prob_irq;
300 	struct kthread_worker *kworker;
301 	struct kthread_delayed_work irq_poll_work;
302 
303 	/* GPIO resources */
304 	u8 gpio_data[2];
305 
306 	/* This cyclecounter abstracts the switch PTP time.
307 	 * reg_lock must be held for any operation that read()s.
308 	 */
309 	struct cyclecounter	tstamp_cc;
310 	struct timecounter	tstamp_tc;
311 	struct delayed_work	overflow_work;
312 
313 	struct ptp_clock	*ptp_clock;
314 	struct ptp_clock_info	ptp_clock_info;
315 	struct delayed_work	tai_event_work;
316 	struct ptp_pin_desc	pin_config[MV88E6XXX_MAX_GPIO];
317 	u16 trig_config;
318 	u16 evcap_config;
319 	u16 enable_count;
320 
321 	/* Current ingress and egress monitor ports */
322 	int egress_dest_port;
323 	int ingress_dest_port;
324 
325 	/* Per-port timestamping resources. */
326 	struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
327 
328 	/* Array of port structures. */
329 	struct mv88e6xxx_port ports[DSA_MAX_PORTS];
330 };
331 
332 struct mv88e6xxx_bus_ops {
333 	int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
334 	int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
335 };
336 
337 struct mv88e6xxx_mdio_bus {
338 	struct mii_bus *bus;
339 	struct mv88e6xxx_chip *chip;
340 	struct list_head list;
341 	bool external;
342 };
343 
344 struct mv88e6xxx_ops {
345 	/* Switch Setup Errata, called early in the switch setup to
346 	 * allow any errata actions to be performed
347 	 */
348 	int (*setup_errata)(struct mv88e6xxx_chip *chip);
349 
350 	int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
351 	int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
352 
353 	/* Ingress Rate Limit unit (IRL) operations */
354 	int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
355 
356 	int (*get_eeprom)(struct mv88e6xxx_chip *chip,
357 			  struct ethtool_eeprom *eeprom, u8 *data);
358 	int (*set_eeprom)(struct mv88e6xxx_chip *chip,
359 			  struct ethtool_eeprom *eeprom, u8 *data);
360 
361 	int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
362 
363 	int (*phy_read)(struct mv88e6xxx_chip *chip,
364 			struct mii_bus *bus,
365 			int addr, int reg, u16 *val);
366 	int (*phy_write)(struct mv88e6xxx_chip *chip,
367 			 struct mii_bus *bus,
368 			 int addr, int reg, u16 val);
369 
370 	/* Priority Override Table operations */
371 	int (*pot_clear)(struct mv88e6xxx_chip *chip);
372 
373 	/* PHY Polling Unit (PPU) operations */
374 	int (*ppu_enable)(struct mv88e6xxx_chip *chip);
375 	int (*ppu_disable)(struct mv88e6xxx_chip *chip);
376 
377 	/* Switch Software Reset */
378 	int (*reset)(struct mv88e6xxx_chip *chip);
379 
380 	/* RGMII Receive/Transmit Timing Control
381 	 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
382 	 */
383 	int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
384 				    phy_interface_t mode);
385 
386 #define LINK_FORCED_DOWN	0
387 #define LINK_FORCED_UP		1
388 #define LINK_UNFORCED		-2
389 
390 	/* Port's MAC link state
391 	 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
392 	 * or LINK_UNFORCED for normal link detection.
393 	 */
394 	int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
395 
396 #define DUPLEX_UNFORCED		-2
397 
398 	/* Port's MAC duplex mode
399 	 *
400 	 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
401 	 * or DUPLEX_UNFORCED for normal duplex detection.
402 	 */
403 	int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup);
404 
405 #define PAUSE_ON		1
406 #define PAUSE_OFF		0
407 
408 	/* Enable/disable sending Pause */
409 	int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
410 			      int pause);
411 
412 #define SPEED_MAX		INT_MAX
413 #define SPEED_UNFORCED		-2
414 
415 	/* Port's MAC speed (in Mbps)
416 	 *
417 	 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
418 	 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
419 	 */
420 	int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed);
421 
422 	/* What interface mode should be used for maximum speed? */
423 	phy_interface_t (*port_max_speed_mode)(int port);
424 
425 	int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
426 
427 	int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
428 			       enum mv88e6xxx_policy_mapping mapping,
429 			       enum mv88e6xxx_policy_action action);
430 
431 	int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
432 				   enum mv88e6xxx_frame_mode mode);
433 	int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,
434 				      bool unicast, bool multicast);
435 	int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
436 				   u16 etype);
437 	int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
438 				   size_t size);
439 
440 	int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
441 	int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
442 				u8 out);
443 	int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
444 	int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
445 	int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
446 
447 	/* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
448 	 * Some chips allow this to be configured on specific ports.
449 	 */
450 	int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
451 			      phy_interface_t mode);
452 	int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
453 
454 	/* Some devices have a per port register indicating what is
455 	 * the upstream port this port should forward to.
456 	 */
457 	int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
458 				      int upstream_port);
459 	/* Return the port link state, as required by phylink */
460 	int (*port_link_state)(struct mv88e6xxx_chip *chip, int port,
461 			       struct phylink_link_state *state);
462 
463 	/* Snapshot the statistics for a port. The statistics can then
464 	 * be read back a leisure but still with a consistent view.
465 	 */
466 	int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
467 
468 	/* Set the histogram mode for statistics, when the control registers
469 	 * are separated out of the STATS_OP register.
470 	 */
471 	int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
472 
473 	/* Return the number of strings describing statistics */
474 	int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
475 	int (*stats_get_strings)(struct mv88e6xxx_chip *chip,  uint8_t *data);
476 	int (*stats_get_stats)(struct mv88e6xxx_chip *chip,  int port,
477 			       uint64_t *data);
478 	int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
479 	int (*set_egress_port)(struct mv88e6xxx_chip *chip,
480 			       enum mv88e6xxx_egress_direction direction,
481 			       int port);
482 
483 #define MV88E6XXX_CASCADE_PORT_NONE		0xe
484 #define MV88E6XXX_CASCADE_PORT_MULTIPLE		0xf
485 
486 	int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
487 
488 	const struct mv88e6xxx_irq_ops *watchdog_ops;
489 
490 	int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
491 
492 	/* Power on/off a SERDES interface */
493 	int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane,
494 			    bool up);
495 
496 	/* SERDES lane mapping */
497 	u8 (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
498 
499 	/* SERDES interrupt handling */
500 	unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
501 					   int port);
502 	int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane,
503 				 bool enable);
504 	irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port,
505 					 u8 lane);
506 
507 	/* Statistics from the SERDES interface */
508 	int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
509 	int (*serdes_get_strings)(struct mv88e6xxx_chip *chip,  int port,
510 				  uint8_t *data);
511 	int (*serdes_get_stats)(struct mv88e6xxx_chip *chip,  int port,
512 				uint64_t *data);
513 
514 	/* Address Translation Unit operations */
515 	int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash);
516 	int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash);
517 
518 	/* VLAN Translation Unit operations */
519 	int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
520 			   struct mv88e6xxx_vtu_entry *entry);
521 	int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
522 			     struct mv88e6xxx_vtu_entry *entry);
523 
524 	/* GPIO operations */
525 	const struct mv88e6xxx_gpio_ops *gpio_ops;
526 
527 	/* Interface to the AVB/PTP registers */
528 	const struct mv88e6xxx_avb_ops *avb_ops;
529 
530 	/* Remote Management Unit operations */
531 	int (*rmu_disable)(struct mv88e6xxx_chip *chip);
532 
533 	/* Precision Time Protocol operations */
534 	const struct mv88e6xxx_ptp_ops *ptp_ops;
535 
536 	/* Phylink */
537 	void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
538 				 unsigned long *mask,
539 				 struct phylink_link_state *state);
540 };
541 
542 struct mv88e6xxx_irq_ops {
543 	/* Action to be performed when the interrupt happens */
544 	int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
545 	/* Setup the hardware to generate the interrupt */
546 	int (*irq_setup)(struct mv88e6xxx_chip *chip);
547 	/* Reset the hardware to stop generating the interrupt */
548 	void (*irq_free)(struct mv88e6xxx_chip *chip);
549 };
550 
551 struct mv88e6xxx_gpio_ops {
552 	/* Get/set data on GPIO pin */
553 	int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
554 	int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
555 			int value);
556 
557 	/* get/set GPIO direction */
558 	int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
559 	int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
560 		       bool input);
561 
562 	/* get/set GPIO pin control */
563 	int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
564 			int *func);
565 	int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
566 			int func);
567 };
568 
569 struct mv88e6xxx_avb_ops {
570 	/* Access port-scoped Precision Time Protocol registers */
571 	int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
572 			     u16 *data, int len);
573 	int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
574 			      u16 data);
575 
576 	/* Access global Precision Time Protocol registers */
577 	int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
578 			int len);
579 	int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
580 
581 	/* Access global Time Application Interface registers */
582 	int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
583 			int len);
584 	int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
585 };
586 
587 struct mv88e6xxx_ptp_ops {
588 	u64 (*clock_read)(const struct cyclecounter *cc);
589 	int (*ptp_enable)(struct ptp_clock_info *ptp,
590 			  struct ptp_clock_request *rq, int on);
591 	int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
592 			  enum ptp_pin_function func, unsigned int chan);
593 	void (*event_work)(struct work_struct *ugly);
594 	int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
595 	int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
596 	int (*global_enable)(struct mv88e6xxx_chip *chip);
597 	int (*global_disable)(struct mv88e6xxx_chip *chip);
598 	int n_ext_ts;
599 	int arr0_sts_reg;
600 	int arr1_sts_reg;
601 	int dep_sts_reg;
602 	u32 rx_filters;
603 	u32 cc_shift;
604 	u32 cc_mult;
605 	u32 cc_mult_num;
606 	u32 cc_mult_dem;
607 };
608 
609 #define STATS_TYPE_PORT		BIT(0)
610 #define STATS_TYPE_BANK0	BIT(1)
611 #define STATS_TYPE_BANK1	BIT(2)
612 
613 struct mv88e6xxx_hw_stat {
614 	char string[ETH_GSTRING_LEN];
615 	size_t size;
616 	int reg;
617 	int type;
618 };
619 
620 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
621 {
622 	return chip->info->pvt;
623 }
624 
625 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
626 {
627 	return chip->info->num_databases;
628 }
629 
630 static inline unsigned int mv88e6xxx_num_macs(struct  mv88e6xxx_chip *chip)
631 {
632 	return chip->info->num_macs;
633 }
634 
635 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
636 {
637 	return chip->info->num_ports;
638 }
639 
640 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
641 {
642 	return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
643 }
644 
645 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
646 {
647 	return chip->info->num_gpio;
648 }
649 
650 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
651 {
652 	return (chip->info->invalid_port_mask & BIT(port)) != 0;
653 }
654 
655 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
656 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
657 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
658 			u16 mask, u16 val);
659 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
660 		       int bit, int val);
661 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
662 			     int speed, int duplex, int pause,
663 			     phy_interface_t mode);
664 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
665 
666 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
667 {
668 	mutex_lock(&chip->reg_lock);
669 }
670 
671 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
672 {
673 	mutex_unlock(&chip->reg_lock);
674 }
675 
676 #endif /* _MV88E6XXX_CHIP_H */
677