1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Ethernet switch single-chip definition 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 */ 7 8 #ifndef _MV88E6XXX_CHIP_H 9 #define _MV88E6XXX_CHIP_H 10 11 #include <linux/idr.h> 12 #include <linux/if_vlan.h> 13 #include <linux/irq.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/kthread.h> 16 #include <linux/phy.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/timecounter.h> 19 #include <net/dsa.h> 20 21 #define EDSA_HLEN 8 22 #define MV88E6XXX_N_FID 4096 23 #define MV88E6XXX_N_SID 64 24 25 #define MV88E6XXX_FID_STANDALONE 0 26 #define MV88E6XXX_FID_BRIDGED 1 27 28 /* PVT limits for 4-bit port and 5-bit switch */ 29 #define MV88E6XXX_MAX_PVT_SWITCHES 32 30 #define MV88E6XXX_MAX_PVT_PORTS 16 31 #define MV88E6XXX_MAX_PVT_ENTRIES \ 32 (MV88E6XXX_MAX_PVT_SWITCHES * MV88E6XXX_MAX_PVT_PORTS) 33 34 #define MV88E6XXX_MAX_GPIO 16 35 36 enum mv88e6xxx_egress_mode { 37 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 38 MV88E6XXX_EGRESS_MODE_UNTAGGED, 39 MV88E6XXX_EGRESS_MODE_TAGGED, 40 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 41 }; 42 43 enum mv88e6xxx_egress_direction { 44 MV88E6XXX_EGRESS_DIR_INGRESS, 45 MV88E6XXX_EGRESS_DIR_EGRESS, 46 }; 47 48 enum mv88e6xxx_frame_mode { 49 MV88E6XXX_FRAME_MODE_NORMAL, 50 MV88E6XXX_FRAME_MODE_DSA, 51 MV88E6XXX_FRAME_MODE_PROVIDER, 52 MV88E6XXX_FRAME_MODE_ETHERTYPE, 53 }; 54 55 /* List of supported models */ 56 enum mv88e6xxx_model { 57 MV88E6020, 58 MV88E6071, 59 MV88E6085, 60 MV88E6095, 61 MV88E6097, 62 MV88E6123, 63 MV88E6131, 64 MV88E6141, 65 MV88E6161, 66 MV88E6165, 67 MV88E6171, 68 MV88E6172, 69 MV88E6175, 70 MV88E6176, 71 MV88E6185, 72 MV88E6190, 73 MV88E6190X, 74 MV88E6191, 75 MV88E6191X, 76 MV88E6193X, 77 MV88E6220, 78 MV88E6240, 79 MV88E6250, 80 MV88E6290, 81 MV88E6320, 82 MV88E6321, 83 MV88E6341, 84 MV88E6350, 85 MV88E6351, 86 MV88E6352, 87 MV88E6361, 88 MV88E6390, 89 MV88E6390X, 90 MV88E6393X, 91 }; 92 93 enum mv88e6xxx_family { 94 MV88E6XXX_FAMILY_NONE, 95 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 96 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 97 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 98 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 99 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 100 MV88E6XXX_FAMILY_6250, /* 6220 6250 6020 6071 */ 101 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 102 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 103 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 104 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 105 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 106 MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6361 6393X */ 107 }; 108 109 /** 110 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level 111 * @MV88E6XXX_EDSA_UNSUPPORTED: Device has no support for EDSA tags 112 * @MV88E6XXX_EDSA_UNDOCUMENTED: Documentation indicates that 113 * egressing FORWARD frames with an EDSA 114 * tag is reserved for future use, but 115 * empirical data shows that this mode 116 * is supported. 117 * @MV88E6XXX_EDSA_SUPPORTED: EDSA tags are fully supported. 118 */ 119 enum mv88e6xxx_edsa_support { 120 MV88E6XXX_EDSA_UNSUPPORTED = 0, 121 MV88E6XXX_EDSA_UNDOCUMENTED, 122 MV88E6XXX_EDSA_SUPPORTED, 123 }; 124 125 struct mv88e6xxx_ops; 126 127 struct mv88e6xxx_info { 128 enum mv88e6xxx_family family; 129 u16 prod_num; 130 const char *name; 131 unsigned int num_databases; 132 unsigned int num_macs; 133 unsigned int num_ports; 134 unsigned int num_internal_phys; 135 unsigned int num_gpio; 136 unsigned int max_vid; 137 unsigned int max_sid; 138 unsigned int port_base_addr; 139 unsigned int phy_base_addr; 140 unsigned int global1_addr; 141 unsigned int global2_addr; 142 unsigned int age_time_coeff; 143 unsigned int g1_irqs; 144 unsigned int g2_irqs; 145 bool pvt; 146 147 /* Mark certain ports as invalid. This is required for example for the 148 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the 149 * ports 2-4 are not routet to pins. 150 */ 151 unsigned int invalid_port_mask; 152 /* Multi-chip Addressing Mode. 153 * Some chips respond to only 2 registers of its own SMI device address 154 * when it is non-zero, and use indirect access to internal registers. 155 */ 156 bool multi_chip; 157 /* Dual-chip Addressing Mode 158 * Some chips respond to only half of the 32 SMI addresses, 159 * allowing two to coexist on the same SMI interface. 160 */ 161 bool dual_chip; 162 163 enum mv88e6xxx_edsa_support edsa_support; 164 165 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 166 * operation. 0 means that the ATU Move operation is not supported. 167 */ 168 u8 atu_move_port_mask; 169 const struct mv88e6xxx_ops *ops; 170 171 /* Supports PTP */ 172 bool ptp_support; 173 174 /* Internal PHY start index. 0 means that internal PHYs range starts at 175 * port 0, 1 means internal PHYs range starts at port 1, etc 176 */ 177 unsigned int internal_phys_offset; 178 }; 179 180 struct mv88e6xxx_atu_entry { 181 u8 state; 182 bool trunk; 183 u16 portvec; 184 u8 mac[ETH_ALEN]; 185 }; 186 187 struct mv88e6xxx_vtu_entry { 188 u16 vid; 189 u16 fid; 190 u8 sid; 191 bool valid; 192 bool policy; 193 u8 member[DSA_MAX_PORTS]; 194 u8 state[DSA_MAX_PORTS]; /* Older silicon has no STU */ 195 }; 196 197 struct mv88e6xxx_stu_entry { 198 u8 sid; 199 bool valid; 200 u8 state[DSA_MAX_PORTS]; 201 }; 202 203 struct mv88e6xxx_bus_ops; 204 struct mv88e6xxx_irq_ops; 205 struct mv88e6xxx_gpio_ops; 206 struct mv88e6xxx_avb_ops; 207 struct mv88e6xxx_ptp_ops; 208 209 struct mv88e6xxx_irq { 210 u16 masked; 211 struct irq_chip chip; 212 struct irq_domain *domain; 213 int nirqs; 214 }; 215 216 /* state flags for mv88e6xxx_port_hwtstamp::state */ 217 enum { 218 MV88E6XXX_HWTSTAMP_ENABLED, 219 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 220 }; 221 222 struct mv88e6xxx_port_hwtstamp { 223 /* Port index */ 224 int port_id; 225 226 /* Timestamping state */ 227 unsigned long state; 228 229 /* Resources for receive timestamping */ 230 struct sk_buff_head rx_queue; 231 struct sk_buff_head rx_queue2; 232 233 /* Resources for transmit timestamping */ 234 unsigned long tx_tstamp_start; 235 struct sk_buff *tx_skb; 236 u16 tx_seq_id; 237 238 /* Current timestamp configuration */ 239 struct hwtstamp_config tstamp_config; 240 }; 241 242 enum mv88e6xxx_policy_mapping { 243 MV88E6XXX_POLICY_MAPPING_DA, 244 MV88E6XXX_POLICY_MAPPING_SA, 245 MV88E6XXX_POLICY_MAPPING_VTU, 246 MV88E6XXX_POLICY_MAPPING_ETYPE, 247 MV88E6XXX_POLICY_MAPPING_PPPOE, 248 MV88E6XXX_POLICY_MAPPING_VBAS, 249 MV88E6XXX_POLICY_MAPPING_OPT82, 250 MV88E6XXX_POLICY_MAPPING_UDP, 251 }; 252 253 enum mv88e6xxx_policy_action { 254 MV88E6XXX_POLICY_ACTION_NORMAL, 255 MV88E6XXX_POLICY_ACTION_MIRROR, 256 MV88E6XXX_POLICY_ACTION_TRAP, 257 MV88E6XXX_POLICY_ACTION_DISCARD, 258 }; 259 260 struct mv88e6xxx_policy { 261 enum mv88e6xxx_policy_mapping mapping; 262 enum mv88e6xxx_policy_action action; 263 struct ethtool_rx_flow_spec fs; 264 u8 addr[ETH_ALEN]; 265 int port; 266 u16 vid; 267 }; 268 269 struct mv88e6xxx_vlan { 270 u16 vid; 271 bool valid; 272 }; 273 274 struct mv88e6xxx_port { 275 struct mv88e6xxx_chip *chip; 276 int port; 277 struct mv88e6xxx_vlan bridge_pvid; 278 u64 serdes_stats[2]; 279 u64 atu_member_violation; 280 u64 atu_miss_violation; 281 u64 atu_full_violation; 282 u64 vtu_member_violation; 283 u64 vtu_miss_violation; 284 phy_interface_t interface; 285 u8 cmode; 286 bool mirror_ingress; 287 bool mirror_egress; 288 unsigned int serdes_irq; 289 char serdes_irq_name[64]; 290 struct devlink_region *region; 291 292 /* MacAuth Bypass control flag */ 293 bool mab; 294 }; 295 296 enum mv88e6xxx_region_id { 297 MV88E6XXX_REGION_GLOBAL1 = 0, 298 MV88E6XXX_REGION_GLOBAL2, 299 MV88E6XXX_REGION_ATU, 300 MV88E6XXX_REGION_VTU, 301 MV88E6XXX_REGION_STU, 302 MV88E6XXX_REGION_PVT, 303 304 _MV88E6XXX_REGION_MAX, 305 }; 306 307 struct mv88e6xxx_region_priv { 308 enum mv88e6xxx_region_id id; 309 }; 310 311 struct mv88e6xxx_mst { 312 struct list_head node; 313 314 refcount_t refcnt; 315 struct net_device *br; 316 u16 msti; 317 318 struct mv88e6xxx_stu_entry stu; 319 }; 320 321 struct mv88e6xxx_chip { 322 const struct mv88e6xxx_info *info; 323 324 /* Currently configured tagging protocol */ 325 enum dsa_tag_protocol tag_protocol; 326 327 /* The dsa_switch this private structure is related to */ 328 struct dsa_switch *ds; 329 330 /* The device this structure is associated to */ 331 struct device *dev; 332 333 /* This mutex protects the access to the switch registers */ 334 struct mutex reg_lock; 335 336 /* The MII bus and the address on the bus that is used to 337 * communication with the switch 338 */ 339 const struct mv88e6xxx_bus_ops *smi_ops; 340 struct mii_bus *bus; 341 int sw_addr; 342 343 /* Handles automatic disabling and re-enabling of the PHY 344 * polling unit. 345 */ 346 const struct mv88e6xxx_bus_ops *phy_ops; 347 struct mutex ppu_mutex; 348 int ppu_disabled; 349 struct work_struct ppu_work; 350 struct timer_list ppu_timer; 351 352 /* This mutex serialises access to the statistics unit. 353 * Hold this mutex over snapshot + dump sequences. 354 */ 355 struct mutex stats_mutex; 356 357 /* A switch may have a GPIO line tied to its reset pin. Parse 358 * this from the device tree, and use it before performing 359 * switch soft reset. 360 */ 361 struct gpio_desc *reset; 362 363 /* set to size of eeprom if supported by the switch */ 364 u32 eeprom_len; 365 366 /* List of mdio busses */ 367 struct list_head mdios; 368 369 /* Policy Control List IDs and rules */ 370 struct idr policies; 371 372 /* There can be two interrupt controllers, which are chained 373 * off a GPIO as interrupt source 374 */ 375 struct mv88e6xxx_irq g1_irq; 376 struct mv88e6xxx_irq g2_irq; 377 int irq; 378 char irq_name[64]; 379 int device_irq; 380 char device_irq_name[64]; 381 int watchdog_irq; 382 char watchdog_irq_name[64]; 383 384 int atu_prob_irq; 385 char atu_prob_irq_name[64]; 386 int vtu_prob_irq; 387 char vtu_prob_irq_name[64]; 388 struct kthread_worker *kworker; 389 struct kthread_delayed_work irq_poll_work; 390 391 /* GPIO resources */ 392 u8 gpio_data[2]; 393 394 /* This cyclecounter abstracts the switch PTP time. 395 * reg_lock must be held for any operation that read()s. 396 */ 397 struct cyclecounter tstamp_cc; 398 struct timecounter tstamp_tc; 399 struct delayed_work overflow_work; 400 401 struct ptp_clock *ptp_clock; 402 struct ptp_clock_info ptp_clock_info; 403 struct delayed_work tai_event_work; 404 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 405 u16 trig_config; 406 u16 evcap_config; 407 u16 enable_count; 408 409 /* Current ingress and egress monitor ports */ 410 int egress_dest_port; 411 int ingress_dest_port; 412 413 /* Per-port timestamping resources. */ 414 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 415 416 /* Array of port structures. */ 417 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 418 419 /* devlink regions */ 420 struct devlink_region *regions[_MV88E6XXX_REGION_MAX]; 421 422 /* Bridge MST to SID mappings */ 423 struct list_head msts; 424 }; 425 426 struct mv88e6xxx_bus_ops { 427 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 428 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 429 int (*init)(struct mv88e6xxx_chip *chip); 430 }; 431 432 struct mv88e6xxx_mdio_bus { 433 struct mii_bus *bus; 434 struct mv88e6xxx_chip *chip; 435 struct list_head list; 436 bool external; 437 }; 438 439 struct mv88e6xxx_ops { 440 /* Switch Setup Errata, called early in the switch setup to 441 * allow any errata actions to be performed 442 */ 443 int (*setup_errata)(struct mv88e6xxx_chip *chip); 444 445 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 446 int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 447 448 /* Ingress Rate Limit unit (IRL) operations */ 449 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 450 451 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 452 struct ethtool_eeprom *eeprom, u8 *data); 453 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 454 struct ethtool_eeprom *eeprom, u8 *data); 455 456 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 457 458 int (*phy_read)(struct mv88e6xxx_chip *chip, 459 struct mii_bus *bus, 460 int addr, int reg, u16 *val); 461 int (*phy_write)(struct mv88e6xxx_chip *chip, 462 struct mii_bus *bus, 463 int addr, int reg, u16 val); 464 465 int (*phy_read_c45)(struct mv88e6xxx_chip *chip, 466 struct mii_bus *bus, 467 int addr, int devad, int reg, u16 *val); 468 int (*phy_write_c45)(struct mv88e6xxx_chip *chip, 469 struct mii_bus *bus, 470 int addr, int devad, int reg, u16 val); 471 472 /* Priority Override Table operations */ 473 int (*pot_clear)(struct mv88e6xxx_chip *chip); 474 475 /* PHY Polling Unit (PPU) operations */ 476 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 477 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 478 479 /* Switch Software Reset */ 480 int (*reset)(struct mv88e6xxx_chip *chip); 481 482 /* RGMII Receive/Transmit Timing Control 483 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 484 */ 485 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 486 phy_interface_t mode); 487 488 #define LINK_FORCED_DOWN 0 489 #define LINK_FORCED_UP 1 490 #define LINK_UNFORCED -2 491 492 /* Port's MAC link state 493 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 494 * or LINK_UNFORCED for normal link detection. 495 */ 496 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 497 498 /* Synchronise the port link state with that of the SERDES 499 */ 500 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 501 502 #define PAUSE_ON 1 503 #define PAUSE_OFF 0 504 505 /* Enable/disable sending Pause */ 506 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 507 int pause); 508 509 #define SPEED_UNFORCED -2 510 #define DUPLEX_UNFORCED -2 511 512 /* Port's MAC speed (in Mbps) and MAC duplex mode 513 * 514 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 515 * Use SPEED_UNFORCED for normal detection. 516 * 517 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 518 * or DUPLEX_UNFORCED for normal duplex detection. 519 */ 520 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port, 521 int speed, int duplex); 522 523 /* What interface mode should be used for maximum speed? */ 524 phy_interface_t (*port_max_speed_mode)(struct mv88e6xxx_chip *chip, 525 int port); 526 527 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 528 529 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port, 530 enum mv88e6xxx_policy_mapping mapping, 531 enum mv88e6xxx_policy_action action); 532 533 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 534 enum mv88e6xxx_frame_mode mode); 535 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port, 536 bool unicast); 537 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port, 538 bool multicast); 539 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 540 u16 etype); 541 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 542 size_t size); 543 544 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 545 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 546 u8 out); 547 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 548 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 549 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port); 550 551 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 552 * Some chips allow this to be configured on specific ports. 553 */ 554 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 555 phy_interface_t mode); 556 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 557 558 /* Some devices have a per port register indicating what is 559 * the upstream port this port should forward to. 560 */ 561 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 562 int upstream_port); 563 564 /* Snapshot the statistics for a port. The statistics can then 565 * be read back a leisure but still with a consistent view. 566 */ 567 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 568 569 /* Set the histogram mode for statistics, when the control registers 570 * are separated out of the STATS_OP register. 571 */ 572 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 573 574 /* Return the number of strings describing statistics */ 575 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 576 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 577 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 578 uint64_t *data); 579 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 580 int (*set_egress_port)(struct mv88e6xxx_chip *chip, 581 enum mv88e6xxx_egress_direction direction, 582 int port); 583 584 #define MV88E6XXX_CASCADE_PORT_NONE 0xe 585 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 586 587 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 588 589 const struct mv88e6xxx_irq_ops *watchdog_ops; 590 591 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 592 593 /* Power on/off a SERDES interface */ 594 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, int lane, 595 bool up); 596 597 /* SERDES lane mapping */ 598 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); 599 600 int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port, 601 int lane, struct phylink_link_state *state); 602 int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port, 603 int lane, unsigned int mode, 604 phy_interface_t interface, 605 const unsigned long *advertise); 606 int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port, 607 int lane); 608 int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port, 609 int lane, int speed, int duplex); 610 611 /* SERDES interrupt handling */ 612 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, 613 int port); 614 int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, int lane, 615 bool enable); 616 irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port, 617 int lane); 618 619 /* Statistics from the SERDES interface */ 620 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 621 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 622 uint8_t *data); 623 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 624 uint64_t *data); 625 626 /* SERDES registers for ethtool */ 627 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port); 628 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port, 629 void *_p); 630 631 /* SERDES SGMII/Fiber Output Amplitude */ 632 int (*serdes_set_tx_amplitude)(struct mv88e6xxx_chip *chip, int port, 633 int val); 634 635 /* Address Translation Unit operations */ 636 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash); 637 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash); 638 639 /* VLAN Translation Unit operations */ 640 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 641 struct mv88e6xxx_vtu_entry *entry); 642 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 643 struct mv88e6xxx_vtu_entry *entry); 644 645 /* Spanning Tree Unit operations */ 646 int (*stu_getnext)(struct mv88e6xxx_chip *chip, 647 struct mv88e6xxx_stu_entry *entry); 648 int (*stu_loadpurge)(struct mv88e6xxx_chip *chip, 649 struct mv88e6xxx_stu_entry *entry); 650 651 /* GPIO operations */ 652 const struct mv88e6xxx_gpio_ops *gpio_ops; 653 654 /* Interface to the AVB/PTP registers */ 655 const struct mv88e6xxx_avb_ops *avb_ops; 656 657 /* Remote Management Unit operations */ 658 int (*rmu_disable)(struct mv88e6xxx_chip *chip); 659 660 /* Precision Time Protocol operations */ 661 const struct mv88e6xxx_ptp_ops *ptp_ops; 662 663 /* Phylink */ 664 void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port, 665 struct phylink_config *config); 666 667 /* Max Frame Size */ 668 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu); 669 }; 670 671 struct mv88e6xxx_irq_ops { 672 /* Action to be performed when the interrupt happens */ 673 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 674 /* Setup the hardware to generate the interrupt */ 675 int (*irq_setup)(struct mv88e6xxx_chip *chip); 676 /* Reset the hardware to stop generating the interrupt */ 677 void (*irq_free)(struct mv88e6xxx_chip *chip); 678 }; 679 680 struct mv88e6xxx_gpio_ops { 681 /* Get/set data on GPIO pin */ 682 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 683 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 684 int value); 685 686 /* get/set GPIO direction */ 687 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 688 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 689 bool input); 690 691 /* get/set GPIO pin control */ 692 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 693 int *func); 694 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 695 int func); 696 }; 697 698 struct mv88e6xxx_avb_ops { 699 /* Access port-scoped Precision Time Protocol registers */ 700 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 701 u16 *data, int len); 702 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 703 u16 data); 704 705 /* Access global Precision Time Protocol registers */ 706 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 707 int len); 708 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 709 710 /* Access global Time Application Interface registers */ 711 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 712 int len); 713 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 714 }; 715 716 struct mv88e6xxx_ptp_ops { 717 u64 (*clock_read)(const struct cyclecounter *cc); 718 int (*ptp_enable)(struct ptp_clock_info *ptp, 719 struct ptp_clock_request *rq, int on); 720 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 721 enum ptp_pin_function func, unsigned int chan); 722 void (*event_work)(struct work_struct *ugly); 723 int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 724 int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 725 int (*global_enable)(struct mv88e6xxx_chip *chip); 726 int (*global_disable)(struct mv88e6xxx_chip *chip); 727 int (*set_ptp_cpu_port)(struct mv88e6xxx_chip *chip, int port); 728 int n_ext_ts; 729 int arr0_sts_reg; 730 int arr1_sts_reg; 731 int dep_sts_reg; 732 u32 rx_filters; 733 u32 cc_shift; 734 u32 cc_mult; 735 u32 cc_mult_num; 736 u32 cc_mult_dem; 737 }; 738 739 #define STATS_TYPE_PORT BIT(0) 740 #define STATS_TYPE_BANK0 BIT(1) 741 #define STATS_TYPE_BANK1 BIT(2) 742 743 struct mv88e6xxx_hw_stat { 744 char string[ETH_GSTRING_LEN]; 745 size_t size; 746 int reg; 747 int type; 748 }; 749 750 static inline bool mv88e6xxx_has_stu(struct mv88e6xxx_chip *chip) 751 { 752 return chip->info->max_sid > 0 && 753 chip->info->ops->stu_loadpurge && 754 chip->info->ops->stu_getnext; 755 } 756 757 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 758 { 759 return chip->info->pvt; 760 } 761 762 static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip) 763 { 764 return !!chip->info->global2_addr; 765 } 766 767 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 768 { 769 return chip->info->num_databases; 770 } 771 772 static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip) 773 { 774 return chip->info->num_macs; 775 } 776 777 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 778 { 779 return chip->info->num_ports; 780 } 781 782 static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip) 783 { 784 return chip->info->max_vid; 785 } 786 787 static inline unsigned int mv88e6xxx_max_sid(struct mv88e6xxx_chip *chip) 788 { 789 return chip->info->max_sid; 790 } 791 792 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 793 { 794 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0); 795 } 796 797 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 798 { 799 return chip->info->num_gpio; 800 } 801 802 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port) 803 { 804 return (chip->info->invalid_port_mask & BIT(port)) != 0; 805 } 806 807 static inline void mv88e6xxx_port_set_mab(struct mv88e6xxx_chip *chip, 808 int port, bool mab) 809 { 810 chip->ports[port].mab = mab; 811 } 812 813 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 814 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 815 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 816 u16 mask, u16 val); 817 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 818 int bit, int val); 819 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 820 821 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) 822 { 823 mutex_lock(&chip->reg_lock); 824 } 825 826 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) 827 { 828 mutex_unlock(&chip->reg_lock); 829 } 830 831 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 832 int (*cb)(struct mv88e6xxx_chip *chip, 833 const struct mv88e6xxx_vtu_entry *entry, 834 void *priv), 835 void *priv); 836 837 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap); 838 839 #endif /* _MV88E6XXX_CHIP_H */ 840