1 /* 2 * Marvell 88E6xxx Ethernet switch single-chip definition 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #ifndef _MV88E6XXX_CHIP_H 13 #define _MV88E6XXX_CHIP_H 14 15 #include <linux/if_vlan.h> 16 #include <linux/irq.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/phy.h> 19 #include <net/dsa.h> 20 21 #ifndef UINT64_MAX 22 #define UINT64_MAX (u64)(~((u64)0)) 23 #endif 24 25 #define SMI_CMD 0x00 26 #define SMI_CMD_BUSY BIT(15) 27 #define SMI_CMD_CLAUSE_22 BIT(12) 28 #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 29 #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 30 #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY) 31 #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY) 32 #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY) 33 #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY) 34 #define SMI_DATA 0x01 35 36 #define MV88E6XXX_N_FID 4096 37 38 /* PVT limits for 4-bit port and 5-bit switch */ 39 #define MV88E6XXX_MAX_PVT_SWITCHES 32 40 #define MV88E6XXX_MAX_PVT_PORTS 16 41 42 enum mv88e6xxx_egress_mode { 43 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 44 MV88E6XXX_EGRESS_MODE_UNTAGGED, 45 MV88E6XXX_EGRESS_MODE_TAGGED, 46 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 47 }; 48 49 enum mv88e6xxx_frame_mode { 50 MV88E6XXX_FRAME_MODE_NORMAL, 51 MV88E6XXX_FRAME_MODE_DSA, 52 MV88E6XXX_FRAME_MODE_PROVIDER, 53 MV88E6XXX_FRAME_MODE_ETHERTYPE, 54 }; 55 56 /* List of supported models */ 57 enum mv88e6xxx_model { 58 MV88E6085, 59 MV88E6095, 60 MV88E6097, 61 MV88E6123, 62 MV88E6131, 63 MV88E6141, 64 MV88E6161, 65 MV88E6165, 66 MV88E6171, 67 MV88E6172, 68 MV88E6175, 69 MV88E6176, 70 MV88E6185, 71 MV88E6190, 72 MV88E6190X, 73 MV88E6191, 74 MV88E6240, 75 MV88E6290, 76 MV88E6320, 77 MV88E6321, 78 MV88E6341, 79 MV88E6350, 80 MV88E6351, 81 MV88E6352, 82 MV88E6390, 83 MV88E6390X, 84 }; 85 86 enum mv88e6xxx_family { 87 MV88E6XXX_FAMILY_NONE, 88 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 89 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 90 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 91 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 92 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 93 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 94 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 95 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 96 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 97 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 98 }; 99 100 enum mv88e6xxx_cap { 101 /* Energy Efficient Ethernet. 102 */ 103 MV88E6XXX_CAP_EEE, 104 105 /* Multi-chip Addressing Mode. 106 * Some chips respond to only 2 registers of its own SMI device address 107 * when it is non-zero, and use indirect access to internal registers. 108 */ 109 MV88E6XXX_CAP_SMI_CMD, /* (0x00) SMI Command */ 110 MV88E6XXX_CAP_SMI_DATA, /* (0x01) SMI Data */ 111 112 /* Switch Global (1) Registers. 113 */ 114 MV88E6XXX_CAP_G1_ATU_FID, /* (0x01) ATU FID Register */ 115 MV88E6XXX_CAP_G1_VTU_FID, /* (0x02) VTU FID Register */ 116 117 /* Switch Global 2 Registers. 118 * The device contains a second set of global 16-bit registers. 119 */ 120 MV88E6XXX_CAP_GLOBAL2, 121 MV88E6XXX_CAP_G2_INT, /* (0x00) Interrupt Status */ 122 MV88E6XXX_CAP_G2_MGMT_EN_2X, /* (0x02) MGMT Enable Register 2x */ 123 MV88E6XXX_CAP_G2_MGMT_EN_0X, /* (0x03) MGMT Enable Register 0x */ 124 MV88E6XXX_CAP_G2_POT, /* (0x0f) Priority Override Table */ 125 126 /* Per VLAN Spanning Tree Unit (STU). 127 * The Port State database, if present, is accessed through VTU 128 * operations and dedicated SID registers. See MV88E6352_G1_VTU_SID. 129 */ 130 MV88E6XXX_CAP_STU, 131 132 /* VLAN Table Unit. 133 * The VTU is used to program 802.1Q VLANs. See MV88E6XXX_G1_VTU_OP. 134 */ 135 MV88E6XXX_CAP_VTU, 136 }; 137 138 /* Bitmask of capabilities */ 139 #define MV88E6XXX_FLAG_EEE BIT_ULL(MV88E6XXX_CAP_EEE) 140 141 #define MV88E6XXX_FLAG_SMI_CMD BIT_ULL(MV88E6XXX_CAP_SMI_CMD) 142 #define MV88E6XXX_FLAG_SMI_DATA BIT_ULL(MV88E6XXX_CAP_SMI_DATA) 143 144 #define MV88E6XXX_FLAG_G1_VTU_FID BIT_ULL(MV88E6XXX_CAP_G1_VTU_FID) 145 146 #define MV88E6XXX_FLAG_GLOBAL2 BIT_ULL(MV88E6XXX_CAP_GLOBAL2) 147 #define MV88E6XXX_FLAG_G2_INT BIT_ULL(MV88E6XXX_CAP_G2_INT) 148 #define MV88E6XXX_FLAG_G2_MGMT_EN_2X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_2X) 149 #define MV88E6XXX_FLAG_G2_MGMT_EN_0X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_0X) 150 #define MV88E6XXX_FLAG_G2_POT BIT_ULL(MV88E6XXX_CAP_G2_POT) 151 152 /* Multi-chip Addressing Mode */ 153 #define MV88E6XXX_FLAGS_MULTI_CHIP \ 154 (MV88E6XXX_FLAG_SMI_CMD | \ 155 MV88E6XXX_FLAG_SMI_DATA) 156 157 #define MV88E6XXX_FLAGS_FAMILY_6095 \ 158 (MV88E6XXX_FLAG_GLOBAL2 | \ 159 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ 160 MV88E6XXX_FLAGS_MULTI_CHIP) 161 162 #define MV88E6XXX_FLAGS_FAMILY_6097 \ 163 (MV88E6XXX_FLAG_G1_VTU_FID | \ 164 MV88E6XXX_FLAG_GLOBAL2 | \ 165 MV88E6XXX_FLAG_G2_INT | \ 166 MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ 167 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ 168 MV88E6XXX_FLAG_G2_POT | \ 169 MV88E6XXX_FLAGS_MULTI_CHIP) 170 171 #define MV88E6XXX_FLAGS_FAMILY_6165 \ 172 (MV88E6XXX_FLAG_G1_VTU_FID | \ 173 MV88E6XXX_FLAG_GLOBAL2 | \ 174 MV88E6XXX_FLAG_G2_INT | \ 175 MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ 176 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ 177 MV88E6XXX_FLAG_G2_POT | \ 178 MV88E6XXX_FLAGS_MULTI_CHIP) 179 180 #define MV88E6XXX_FLAGS_FAMILY_6185 \ 181 (MV88E6XXX_FLAG_GLOBAL2 | \ 182 MV88E6XXX_FLAG_G2_INT | \ 183 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ 184 MV88E6XXX_FLAGS_MULTI_CHIP) 185 186 #define MV88E6XXX_FLAGS_FAMILY_6320 \ 187 (MV88E6XXX_FLAG_EEE | \ 188 MV88E6XXX_FLAG_GLOBAL2 | \ 189 MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ 190 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ 191 MV88E6XXX_FLAG_G2_POT | \ 192 MV88E6XXX_FLAGS_MULTI_CHIP) 193 194 #define MV88E6XXX_FLAGS_FAMILY_6341 \ 195 (MV88E6XXX_FLAG_EEE | \ 196 MV88E6XXX_FLAG_G1_VTU_FID | \ 197 MV88E6XXX_FLAG_GLOBAL2 | \ 198 MV88E6XXX_FLAG_G2_INT | \ 199 MV88E6XXX_FLAG_G2_POT | \ 200 MV88E6XXX_FLAGS_MULTI_CHIP) 201 202 #define MV88E6XXX_FLAGS_FAMILY_6351 \ 203 (MV88E6XXX_FLAG_G1_VTU_FID | \ 204 MV88E6XXX_FLAG_GLOBAL2 | \ 205 MV88E6XXX_FLAG_G2_INT | \ 206 MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ 207 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ 208 MV88E6XXX_FLAG_G2_POT | \ 209 MV88E6XXX_FLAGS_MULTI_CHIP) 210 211 #define MV88E6XXX_FLAGS_FAMILY_6352 \ 212 (MV88E6XXX_FLAG_EEE | \ 213 MV88E6XXX_FLAG_G1_VTU_FID | \ 214 MV88E6XXX_FLAG_GLOBAL2 | \ 215 MV88E6XXX_FLAG_G2_INT | \ 216 MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ 217 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ 218 MV88E6XXX_FLAG_G2_POT | \ 219 MV88E6XXX_FLAGS_MULTI_CHIP) 220 221 #define MV88E6XXX_FLAGS_FAMILY_6390 \ 222 (MV88E6XXX_FLAG_EEE | \ 223 MV88E6XXX_FLAG_GLOBAL2 | \ 224 MV88E6XXX_FLAG_G2_INT | \ 225 MV88E6XXX_FLAGS_MULTI_CHIP) 226 227 struct mv88e6xxx_ops; 228 229 struct mv88e6xxx_info { 230 enum mv88e6xxx_family family; 231 u16 prod_num; 232 const char *name; 233 unsigned int num_databases; 234 unsigned int num_ports; 235 unsigned int max_vid; 236 unsigned int port_base_addr; 237 unsigned int global1_addr; 238 unsigned int age_time_coeff; 239 unsigned int g1_irqs; 240 bool pvt; 241 enum dsa_tag_protocol tag_protocol; 242 unsigned long long flags; 243 244 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 245 * operation. 0 means that the ATU Move operation is not supported. 246 */ 247 u8 atu_move_port_mask; 248 const struct mv88e6xxx_ops *ops; 249 }; 250 251 struct mv88e6xxx_atu_entry { 252 u8 state; 253 bool trunk; 254 u16 portvec; 255 u8 mac[ETH_ALEN]; 256 }; 257 258 struct mv88e6xxx_vtu_entry { 259 u16 vid; 260 u16 fid; 261 u8 sid; 262 bool valid; 263 u8 member[DSA_MAX_PORTS]; 264 u8 state[DSA_MAX_PORTS]; 265 }; 266 267 struct mv88e6xxx_bus_ops; 268 struct mv88e6xxx_irq_ops; 269 270 struct mv88e6xxx_irq { 271 u16 masked; 272 struct irq_chip chip; 273 struct irq_domain *domain; 274 unsigned int nirqs; 275 }; 276 277 struct mv88e6xxx_chip { 278 const struct mv88e6xxx_info *info; 279 280 /* The dsa_switch this private structure is related to */ 281 struct dsa_switch *ds; 282 283 /* The device this structure is associated to */ 284 struct device *dev; 285 286 /* This mutex protects the access to the switch registers */ 287 struct mutex reg_lock; 288 289 /* The MII bus and the address on the bus that is used to 290 * communication with the switch 291 */ 292 const struct mv88e6xxx_bus_ops *smi_ops; 293 struct mii_bus *bus; 294 int sw_addr; 295 296 /* Handles automatic disabling and re-enabling of the PHY 297 * polling unit. 298 */ 299 const struct mv88e6xxx_bus_ops *phy_ops; 300 struct mutex ppu_mutex; 301 int ppu_disabled; 302 struct work_struct ppu_work; 303 struct timer_list ppu_timer; 304 305 /* This mutex serialises access to the statistics unit. 306 * Hold this mutex over snapshot + dump sequences. 307 */ 308 struct mutex stats_mutex; 309 310 /* A switch may have a GPIO line tied to its reset pin. Parse 311 * this from the device tree, and use it before performing 312 * switch soft reset. 313 */ 314 struct gpio_desc *reset; 315 316 /* set to size of eeprom if supported by the switch */ 317 int eeprom_len; 318 319 /* List of mdio busses */ 320 struct list_head mdios; 321 322 /* There can be two interrupt controllers, which are chained 323 * off a GPIO as interrupt source 324 */ 325 struct mv88e6xxx_irq g1_irq; 326 struct mv88e6xxx_irq g2_irq; 327 int irq; 328 int device_irq; 329 int watchdog_irq; 330 }; 331 332 struct mv88e6xxx_bus_ops { 333 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 334 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 335 }; 336 337 struct mv88e6xxx_mdio_bus { 338 struct mii_bus *bus; 339 struct mv88e6xxx_chip *chip; 340 struct list_head list; 341 bool external; 342 }; 343 344 struct mv88e6xxx_ops { 345 /* Ingress Rate Limit unit (IRL) operations */ 346 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 347 348 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 349 struct ethtool_eeprom *eeprom, u8 *data); 350 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 351 struct ethtool_eeprom *eeprom, u8 *data); 352 353 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 354 355 int (*phy_read)(struct mv88e6xxx_chip *chip, 356 struct mii_bus *bus, 357 int addr, int reg, u16 *val); 358 int (*phy_write)(struct mv88e6xxx_chip *chip, 359 struct mii_bus *bus, 360 int addr, int reg, u16 val); 361 362 /* PHY Polling Unit (PPU) operations */ 363 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 364 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 365 366 /* Switch Software Reset */ 367 int (*reset)(struct mv88e6xxx_chip *chip); 368 369 /* RGMII Receive/Transmit Timing Control 370 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 371 */ 372 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 373 phy_interface_t mode); 374 375 #define LINK_FORCED_DOWN 0 376 #define LINK_FORCED_UP 1 377 #define LINK_UNFORCED -2 378 379 /* Port's MAC link state 380 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 381 * or LINK_UNFORCED for normal link detection. 382 */ 383 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 384 385 #define DUPLEX_UNFORCED -2 386 387 /* Port's MAC duplex mode 388 * 389 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 390 * or DUPLEX_UNFORCED for normal duplex detection. 391 */ 392 int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup); 393 394 #define SPEED_MAX INT_MAX 395 #define SPEED_UNFORCED -2 396 397 /* Port's MAC speed (in Mbps) 398 * 399 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 400 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 401 */ 402 int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed); 403 404 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 405 406 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 407 enum mv88e6xxx_frame_mode mode); 408 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port, 409 bool unicast, bool multicast); 410 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 411 u16 etype); 412 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 413 size_t size); 414 415 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 416 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 417 u8 out); 418 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 419 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 420 421 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 422 * Some chips allow this to be configured on specific ports. 423 */ 424 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 425 phy_interface_t mode); 426 427 /* Some devices have a per port register indicating what is 428 * the upstream port this port should forward to. 429 */ 430 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 431 int upstream_port); 432 433 /* Snapshot the statistics for a port. The statistics can then 434 * be read back a leisure but still with a consistent view. 435 */ 436 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 437 438 /* Set the histogram mode for statistics, when the control registers 439 * are separated out of the STATS_OP register. 440 */ 441 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 442 443 /* Return the number of strings describing statistics */ 444 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 445 void (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 446 void (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 447 uint64_t *data); 448 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 449 int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port); 450 const struct mv88e6xxx_irq_ops *watchdog_ops; 451 452 /* Can be either in g1 or g2, so don't use a prefix */ 453 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 454 455 /* Power on/off a SERDES interface */ 456 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on); 457 458 /* VLAN Translation Unit operations */ 459 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 460 struct mv88e6xxx_vtu_entry *entry); 461 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 462 struct mv88e6xxx_vtu_entry *entry); 463 }; 464 465 struct mv88e6xxx_irq_ops { 466 /* Action to be performed when the interrupt happens */ 467 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 468 /* Setup the hardware to generate the interrupt */ 469 int (*irq_setup)(struct mv88e6xxx_chip *chip); 470 /* Reset the hardware to stop generating the interrupt */ 471 void (*irq_free)(struct mv88e6xxx_chip *chip); 472 }; 473 474 #define STATS_TYPE_PORT BIT(0) 475 #define STATS_TYPE_BANK0 BIT(1) 476 #define STATS_TYPE_BANK1 BIT(2) 477 478 struct mv88e6xxx_hw_stat { 479 char string[ETH_GSTRING_LEN]; 480 int sizeof_stat; 481 int reg; 482 int type; 483 }; 484 485 static inline bool mv88e6xxx_has(struct mv88e6xxx_chip *chip, 486 unsigned long flags) 487 { 488 return (chip->info->flags & flags) == flags; 489 } 490 491 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 492 { 493 return chip->info->pvt; 494 } 495 496 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 497 { 498 return chip->info->num_databases; 499 } 500 501 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 502 { 503 return chip->info->num_ports; 504 } 505 506 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 507 { 508 return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0); 509 } 510 511 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 512 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 513 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, 514 u16 update); 515 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask); 516 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 517 518 #endif /* _MV88E6XXX_CHIP_H */ 519