1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Ethernet switch single-chip definition 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 */ 7 8 #ifndef _MV88E6XXX_CHIP_H 9 #define _MV88E6XXX_CHIP_H 10 11 #include <linux/idr.h> 12 #include <linux/if_vlan.h> 13 #include <linux/irq.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/kthread.h> 16 #include <linux/phy.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/timecounter.h> 19 #include <net/dsa.h> 20 21 #define EDSA_HLEN 8 22 #define MV88E6XXX_N_FID 4096 23 #define MV88E6XXX_N_SID 64 24 25 #define MV88E6XXX_FID_STANDALONE 0 26 #define MV88E6XXX_FID_BRIDGED 1 27 28 /* PVT limits for 4-bit port and 5-bit switch */ 29 #define MV88E6XXX_MAX_PVT_SWITCHES 32 30 #define MV88E6XXX_MAX_PVT_PORTS 16 31 #define MV88E6XXX_MAX_PVT_ENTRIES \ 32 (MV88E6XXX_MAX_PVT_SWITCHES * MV88E6XXX_MAX_PVT_PORTS) 33 34 #define MV88E6XXX_MAX_GPIO 16 35 36 enum mv88e6xxx_egress_mode { 37 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 38 MV88E6XXX_EGRESS_MODE_UNTAGGED, 39 MV88E6XXX_EGRESS_MODE_TAGGED, 40 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 41 }; 42 43 enum mv88e6xxx_egress_direction { 44 MV88E6XXX_EGRESS_DIR_INGRESS, 45 MV88E6XXX_EGRESS_DIR_EGRESS, 46 }; 47 48 enum mv88e6xxx_frame_mode { 49 MV88E6XXX_FRAME_MODE_NORMAL, 50 MV88E6XXX_FRAME_MODE_DSA, 51 MV88E6XXX_FRAME_MODE_PROVIDER, 52 MV88E6XXX_FRAME_MODE_ETHERTYPE, 53 }; 54 55 /* List of supported models */ 56 enum mv88e6xxx_model { 57 MV88E6085, 58 MV88E6095, 59 MV88E6097, 60 MV88E6123, 61 MV88E6131, 62 MV88E6141, 63 MV88E6161, 64 MV88E6165, 65 MV88E6171, 66 MV88E6172, 67 MV88E6175, 68 MV88E6176, 69 MV88E6185, 70 MV88E6190, 71 MV88E6190X, 72 MV88E6191, 73 MV88E6191X, 74 MV88E6193X, 75 MV88E6220, 76 MV88E6240, 77 MV88E6250, 78 MV88E6290, 79 MV88E6320, 80 MV88E6321, 81 MV88E6341, 82 MV88E6350, 83 MV88E6351, 84 MV88E6352, 85 MV88E6390, 86 MV88E6390X, 87 MV88E6393X, 88 }; 89 90 enum mv88e6xxx_family { 91 MV88E6XXX_FAMILY_NONE, 92 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 93 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 94 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 95 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 96 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 97 MV88E6XXX_FAMILY_6250, /* 6220 6250 */ 98 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 99 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 100 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 101 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 102 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 103 MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6393X */ 104 }; 105 106 /** 107 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level 108 * @MV88E6XXX_EDSA_UNSUPPORTED: Device has no support for EDSA tags 109 * @MV88E6XXX_EDSA_UNDOCUMENTED: Documentation indicates that 110 * egressing FORWARD frames with an EDSA 111 * tag is reserved for future use, but 112 * empirical data shows that this mode 113 * is supported. 114 * @MV88E6XXX_EDSA_SUPPORTED: EDSA tags are fully supported. 115 */ 116 enum mv88e6xxx_edsa_support { 117 MV88E6XXX_EDSA_UNSUPPORTED = 0, 118 MV88E6XXX_EDSA_UNDOCUMENTED, 119 MV88E6XXX_EDSA_SUPPORTED, 120 }; 121 122 struct mv88e6xxx_ops; 123 124 struct mv88e6xxx_info { 125 enum mv88e6xxx_family family; 126 u16 prod_num; 127 const char *name; 128 unsigned int num_databases; 129 unsigned int num_macs; 130 unsigned int num_ports; 131 unsigned int num_internal_phys; 132 unsigned int num_gpio; 133 unsigned int max_vid; 134 unsigned int max_sid; 135 unsigned int port_base_addr; 136 unsigned int phy_base_addr; 137 unsigned int global1_addr; 138 unsigned int global2_addr; 139 unsigned int age_time_coeff; 140 unsigned int g1_irqs; 141 unsigned int g2_irqs; 142 bool pvt; 143 144 /* Mark certain ports as invalid. This is required for example for the 145 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the 146 * ports 2-4 are not routet to pins. 147 */ 148 unsigned int invalid_port_mask; 149 /* Multi-chip Addressing Mode. 150 * Some chips respond to only 2 registers of its own SMI device address 151 * when it is non-zero, and use indirect access to internal registers. 152 */ 153 bool multi_chip; 154 /* Dual-chip Addressing Mode 155 * Some chips respond to only half of the 32 SMI addresses, 156 * allowing two to coexist on the same SMI interface. 157 */ 158 bool dual_chip; 159 160 enum mv88e6xxx_edsa_support edsa_support; 161 162 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 163 * operation. 0 means that the ATU Move operation is not supported. 164 */ 165 u8 atu_move_port_mask; 166 const struct mv88e6xxx_ops *ops; 167 168 /* Supports PTP */ 169 bool ptp_support; 170 }; 171 172 struct mv88e6xxx_atu_entry { 173 u8 state; 174 bool trunk; 175 u16 portvec; 176 u8 mac[ETH_ALEN]; 177 }; 178 179 struct mv88e6xxx_vtu_entry { 180 u16 vid; 181 u16 fid; 182 u8 sid; 183 bool valid; 184 bool policy; 185 u8 member[DSA_MAX_PORTS]; 186 u8 state[DSA_MAX_PORTS]; /* Older silicon has no STU */ 187 }; 188 189 struct mv88e6xxx_stu_entry { 190 u8 sid; 191 bool valid; 192 u8 state[DSA_MAX_PORTS]; 193 }; 194 195 struct mv88e6xxx_bus_ops; 196 struct mv88e6xxx_irq_ops; 197 struct mv88e6xxx_gpio_ops; 198 struct mv88e6xxx_avb_ops; 199 struct mv88e6xxx_ptp_ops; 200 201 struct mv88e6xxx_irq { 202 u16 masked; 203 struct irq_chip chip; 204 struct irq_domain *domain; 205 int nirqs; 206 }; 207 208 /* state flags for mv88e6xxx_port_hwtstamp::state */ 209 enum { 210 MV88E6XXX_HWTSTAMP_ENABLED, 211 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 212 }; 213 214 struct mv88e6xxx_port_hwtstamp { 215 /* Port index */ 216 int port_id; 217 218 /* Timestamping state */ 219 unsigned long state; 220 221 /* Resources for receive timestamping */ 222 struct sk_buff_head rx_queue; 223 struct sk_buff_head rx_queue2; 224 225 /* Resources for transmit timestamping */ 226 unsigned long tx_tstamp_start; 227 struct sk_buff *tx_skb; 228 u16 tx_seq_id; 229 230 /* Current timestamp configuration */ 231 struct hwtstamp_config tstamp_config; 232 }; 233 234 enum mv88e6xxx_policy_mapping { 235 MV88E6XXX_POLICY_MAPPING_DA, 236 MV88E6XXX_POLICY_MAPPING_SA, 237 MV88E6XXX_POLICY_MAPPING_VTU, 238 MV88E6XXX_POLICY_MAPPING_ETYPE, 239 MV88E6XXX_POLICY_MAPPING_PPPOE, 240 MV88E6XXX_POLICY_MAPPING_VBAS, 241 MV88E6XXX_POLICY_MAPPING_OPT82, 242 MV88E6XXX_POLICY_MAPPING_UDP, 243 }; 244 245 enum mv88e6xxx_policy_action { 246 MV88E6XXX_POLICY_ACTION_NORMAL, 247 MV88E6XXX_POLICY_ACTION_MIRROR, 248 MV88E6XXX_POLICY_ACTION_TRAP, 249 MV88E6XXX_POLICY_ACTION_DISCARD, 250 }; 251 252 struct mv88e6xxx_policy { 253 enum mv88e6xxx_policy_mapping mapping; 254 enum mv88e6xxx_policy_action action; 255 struct ethtool_rx_flow_spec fs; 256 u8 addr[ETH_ALEN]; 257 int port; 258 u16 vid; 259 }; 260 261 struct mv88e6xxx_vlan { 262 u16 vid; 263 bool valid; 264 }; 265 266 struct mv88e6xxx_port { 267 struct mv88e6xxx_chip *chip; 268 int port; 269 struct mv88e6xxx_vlan bridge_pvid; 270 u64 serdes_stats[2]; 271 u64 atu_member_violation; 272 u64 atu_miss_violation; 273 u64 atu_full_violation; 274 u64 vtu_member_violation; 275 u64 vtu_miss_violation; 276 phy_interface_t interface; 277 u8 cmode; 278 bool mirror_ingress; 279 bool mirror_egress; 280 unsigned int serdes_irq; 281 char serdes_irq_name[64]; 282 struct devlink_region *region; 283 284 /* MacAuth Bypass control flag */ 285 bool mab; 286 }; 287 288 enum mv88e6xxx_region_id { 289 MV88E6XXX_REGION_GLOBAL1 = 0, 290 MV88E6XXX_REGION_GLOBAL2, 291 MV88E6XXX_REGION_ATU, 292 MV88E6XXX_REGION_VTU, 293 MV88E6XXX_REGION_STU, 294 MV88E6XXX_REGION_PVT, 295 296 _MV88E6XXX_REGION_MAX, 297 }; 298 299 struct mv88e6xxx_region_priv { 300 enum mv88e6xxx_region_id id; 301 }; 302 303 struct mv88e6xxx_mst { 304 struct list_head node; 305 306 refcount_t refcnt; 307 struct net_device *br; 308 u16 msti; 309 310 struct mv88e6xxx_stu_entry stu; 311 }; 312 313 struct mv88e6xxx_chip { 314 const struct mv88e6xxx_info *info; 315 316 /* Currently configured tagging protocol */ 317 enum dsa_tag_protocol tag_protocol; 318 319 /* The dsa_switch this private structure is related to */ 320 struct dsa_switch *ds; 321 322 /* The device this structure is associated to */ 323 struct device *dev; 324 325 /* This mutex protects the access to the switch registers */ 326 struct mutex reg_lock; 327 328 /* The MII bus and the address on the bus that is used to 329 * communication with the switch 330 */ 331 const struct mv88e6xxx_bus_ops *smi_ops; 332 struct mii_bus *bus; 333 int sw_addr; 334 335 /* Handles automatic disabling and re-enabling of the PHY 336 * polling unit. 337 */ 338 const struct mv88e6xxx_bus_ops *phy_ops; 339 struct mutex ppu_mutex; 340 int ppu_disabled; 341 struct work_struct ppu_work; 342 struct timer_list ppu_timer; 343 344 /* This mutex serialises access to the statistics unit. 345 * Hold this mutex over snapshot + dump sequences. 346 */ 347 struct mutex stats_mutex; 348 349 /* A switch may have a GPIO line tied to its reset pin. Parse 350 * this from the device tree, and use it before performing 351 * switch soft reset. 352 */ 353 struct gpio_desc *reset; 354 355 /* set to size of eeprom if supported by the switch */ 356 u32 eeprom_len; 357 358 /* List of mdio busses */ 359 struct list_head mdios; 360 361 /* Policy Control List IDs and rules */ 362 struct idr policies; 363 364 /* There can be two interrupt controllers, which are chained 365 * off a GPIO as interrupt source 366 */ 367 struct mv88e6xxx_irq g1_irq; 368 struct mv88e6xxx_irq g2_irq; 369 int irq; 370 char irq_name[64]; 371 int device_irq; 372 char device_irq_name[64]; 373 int watchdog_irq; 374 char watchdog_irq_name[64]; 375 376 int atu_prob_irq; 377 char atu_prob_irq_name[64]; 378 int vtu_prob_irq; 379 char vtu_prob_irq_name[64]; 380 struct kthread_worker *kworker; 381 struct kthread_delayed_work irq_poll_work; 382 383 /* GPIO resources */ 384 u8 gpio_data[2]; 385 386 /* This cyclecounter abstracts the switch PTP time. 387 * reg_lock must be held for any operation that read()s. 388 */ 389 struct cyclecounter tstamp_cc; 390 struct timecounter tstamp_tc; 391 struct delayed_work overflow_work; 392 393 struct ptp_clock *ptp_clock; 394 struct ptp_clock_info ptp_clock_info; 395 struct delayed_work tai_event_work; 396 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 397 u16 trig_config; 398 u16 evcap_config; 399 u16 enable_count; 400 401 /* Current ingress and egress monitor ports */ 402 int egress_dest_port; 403 int ingress_dest_port; 404 405 /* Per-port timestamping resources. */ 406 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 407 408 /* Array of port structures. */ 409 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 410 411 /* devlink regions */ 412 struct devlink_region *regions[_MV88E6XXX_REGION_MAX]; 413 414 /* Bridge MST to SID mappings */ 415 struct list_head msts; 416 }; 417 418 struct mv88e6xxx_bus_ops { 419 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 420 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 421 int (*init)(struct mv88e6xxx_chip *chip); 422 }; 423 424 struct mv88e6xxx_mdio_bus { 425 struct mii_bus *bus; 426 struct mv88e6xxx_chip *chip; 427 struct list_head list; 428 bool external; 429 }; 430 431 struct mv88e6xxx_ops { 432 /* Switch Setup Errata, called early in the switch setup to 433 * allow any errata actions to be performed 434 */ 435 int (*setup_errata)(struct mv88e6xxx_chip *chip); 436 437 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 438 int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 439 440 /* Ingress Rate Limit unit (IRL) operations */ 441 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 442 443 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 444 struct ethtool_eeprom *eeprom, u8 *data); 445 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 446 struct ethtool_eeprom *eeprom, u8 *data); 447 448 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 449 450 int (*phy_read)(struct mv88e6xxx_chip *chip, 451 struct mii_bus *bus, 452 int addr, int reg, u16 *val); 453 int (*phy_write)(struct mv88e6xxx_chip *chip, 454 struct mii_bus *bus, 455 int addr, int reg, u16 val); 456 457 int (*phy_read_c45)(struct mv88e6xxx_chip *chip, 458 struct mii_bus *bus, 459 int addr, int devad, int reg, u16 *val); 460 int (*phy_write_c45)(struct mv88e6xxx_chip *chip, 461 struct mii_bus *bus, 462 int addr, int devad, int reg, u16 val); 463 464 /* Priority Override Table operations */ 465 int (*pot_clear)(struct mv88e6xxx_chip *chip); 466 467 /* PHY Polling Unit (PPU) operations */ 468 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 469 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 470 471 /* Switch Software Reset */ 472 int (*reset)(struct mv88e6xxx_chip *chip); 473 474 /* RGMII Receive/Transmit Timing Control 475 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 476 */ 477 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 478 phy_interface_t mode); 479 480 #define LINK_FORCED_DOWN 0 481 #define LINK_FORCED_UP 1 482 #define LINK_UNFORCED -2 483 484 /* Port's MAC link state 485 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 486 * or LINK_UNFORCED for normal link detection. 487 */ 488 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 489 490 /* Synchronise the port link state with that of the SERDES 491 */ 492 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 493 494 #define PAUSE_ON 1 495 #define PAUSE_OFF 0 496 497 /* Enable/disable sending Pause */ 498 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 499 int pause); 500 501 #define SPEED_UNFORCED -2 502 #define DUPLEX_UNFORCED -2 503 504 /* Port's MAC speed (in Mbps) and MAC duplex mode 505 * 506 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 507 * Use SPEED_UNFORCED for normal detection. 508 * 509 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 510 * or DUPLEX_UNFORCED for normal duplex detection. 511 */ 512 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port, 513 int speed, int duplex); 514 515 /* What interface mode should be used for maximum speed? */ 516 phy_interface_t (*port_max_speed_mode)(int port); 517 518 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 519 520 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port, 521 enum mv88e6xxx_policy_mapping mapping, 522 enum mv88e6xxx_policy_action action); 523 524 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 525 enum mv88e6xxx_frame_mode mode); 526 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port, 527 bool unicast); 528 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port, 529 bool multicast); 530 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 531 u16 etype); 532 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 533 size_t size); 534 535 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 536 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 537 u8 out); 538 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 539 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 540 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port); 541 542 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 543 * Some chips allow this to be configured on specific ports. 544 */ 545 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 546 phy_interface_t mode); 547 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 548 549 /* Some devices have a per port register indicating what is 550 * the upstream port this port should forward to. 551 */ 552 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 553 int upstream_port); 554 555 /* Snapshot the statistics for a port. The statistics can then 556 * be read back a leisure but still with a consistent view. 557 */ 558 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 559 560 /* Set the histogram mode for statistics, when the control registers 561 * are separated out of the STATS_OP register. 562 */ 563 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 564 565 /* Return the number of strings describing statistics */ 566 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 567 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 568 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 569 uint64_t *data); 570 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 571 int (*set_egress_port)(struct mv88e6xxx_chip *chip, 572 enum mv88e6xxx_egress_direction direction, 573 int port); 574 575 #define MV88E6XXX_CASCADE_PORT_NONE 0xe 576 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 577 578 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 579 580 const struct mv88e6xxx_irq_ops *watchdog_ops; 581 582 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 583 584 /* Power on/off a SERDES interface */ 585 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, int lane, 586 bool up); 587 588 /* SERDES lane mapping */ 589 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); 590 591 int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port, 592 int lane, struct phylink_link_state *state); 593 int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port, 594 int lane, unsigned int mode, 595 phy_interface_t interface, 596 const unsigned long *advertise); 597 int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port, 598 int lane); 599 int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port, 600 int lane, int speed, int duplex); 601 602 /* SERDES interrupt handling */ 603 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, 604 int port); 605 int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, int lane, 606 bool enable); 607 irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port, 608 int lane); 609 610 /* Statistics from the SERDES interface */ 611 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 612 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 613 uint8_t *data); 614 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 615 uint64_t *data); 616 617 /* SERDES registers for ethtool */ 618 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port); 619 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port, 620 void *_p); 621 622 /* SERDES SGMII/Fiber Output Amplitude */ 623 int (*serdes_set_tx_amplitude)(struct mv88e6xxx_chip *chip, int port, 624 int val); 625 626 /* Address Translation Unit operations */ 627 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash); 628 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash); 629 630 /* VLAN Translation Unit operations */ 631 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 632 struct mv88e6xxx_vtu_entry *entry); 633 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 634 struct mv88e6xxx_vtu_entry *entry); 635 636 /* Spanning Tree Unit operations */ 637 int (*stu_getnext)(struct mv88e6xxx_chip *chip, 638 struct mv88e6xxx_stu_entry *entry); 639 int (*stu_loadpurge)(struct mv88e6xxx_chip *chip, 640 struct mv88e6xxx_stu_entry *entry); 641 642 /* GPIO operations */ 643 const struct mv88e6xxx_gpio_ops *gpio_ops; 644 645 /* Interface to the AVB/PTP registers */ 646 const struct mv88e6xxx_avb_ops *avb_ops; 647 648 /* Remote Management Unit operations */ 649 int (*rmu_disable)(struct mv88e6xxx_chip *chip); 650 651 /* Precision Time Protocol operations */ 652 const struct mv88e6xxx_ptp_ops *ptp_ops; 653 654 /* Phylink */ 655 void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port, 656 struct phylink_config *config); 657 658 /* Max Frame Size */ 659 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu); 660 }; 661 662 struct mv88e6xxx_irq_ops { 663 /* Action to be performed when the interrupt happens */ 664 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 665 /* Setup the hardware to generate the interrupt */ 666 int (*irq_setup)(struct mv88e6xxx_chip *chip); 667 /* Reset the hardware to stop generating the interrupt */ 668 void (*irq_free)(struct mv88e6xxx_chip *chip); 669 }; 670 671 struct mv88e6xxx_gpio_ops { 672 /* Get/set data on GPIO pin */ 673 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 674 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 675 int value); 676 677 /* get/set GPIO direction */ 678 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 679 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 680 bool input); 681 682 /* get/set GPIO pin control */ 683 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 684 int *func); 685 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 686 int func); 687 }; 688 689 struct mv88e6xxx_avb_ops { 690 /* Access port-scoped Precision Time Protocol registers */ 691 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 692 u16 *data, int len); 693 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 694 u16 data); 695 696 /* Access global Precision Time Protocol registers */ 697 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 698 int len); 699 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 700 701 /* Access global Time Application Interface registers */ 702 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 703 int len); 704 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 705 }; 706 707 struct mv88e6xxx_ptp_ops { 708 u64 (*clock_read)(const struct cyclecounter *cc); 709 int (*ptp_enable)(struct ptp_clock_info *ptp, 710 struct ptp_clock_request *rq, int on); 711 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 712 enum ptp_pin_function func, unsigned int chan); 713 void (*event_work)(struct work_struct *ugly); 714 int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 715 int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 716 int (*global_enable)(struct mv88e6xxx_chip *chip); 717 int (*global_disable)(struct mv88e6xxx_chip *chip); 718 int (*set_ptp_cpu_port)(struct mv88e6xxx_chip *chip, int port); 719 int n_ext_ts; 720 int arr0_sts_reg; 721 int arr1_sts_reg; 722 int dep_sts_reg; 723 u32 rx_filters; 724 u32 cc_shift; 725 u32 cc_mult; 726 u32 cc_mult_num; 727 u32 cc_mult_dem; 728 }; 729 730 #define STATS_TYPE_PORT BIT(0) 731 #define STATS_TYPE_BANK0 BIT(1) 732 #define STATS_TYPE_BANK1 BIT(2) 733 734 struct mv88e6xxx_hw_stat { 735 char string[ETH_GSTRING_LEN]; 736 size_t size; 737 int reg; 738 int type; 739 }; 740 741 static inline bool mv88e6xxx_has_stu(struct mv88e6xxx_chip *chip) 742 { 743 return chip->info->max_sid > 0 && 744 chip->info->ops->stu_loadpurge && 745 chip->info->ops->stu_getnext; 746 } 747 748 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 749 { 750 return chip->info->pvt; 751 } 752 753 static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip) 754 { 755 return !!chip->info->global2_addr; 756 } 757 758 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 759 { 760 return chip->info->num_databases; 761 } 762 763 static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip) 764 { 765 return chip->info->num_macs; 766 } 767 768 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 769 { 770 return chip->info->num_ports; 771 } 772 773 static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip) 774 { 775 return chip->info->max_vid; 776 } 777 778 static inline unsigned int mv88e6xxx_max_sid(struct mv88e6xxx_chip *chip) 779 { 780 return chip->info->max_sid; 781 } 782 783 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 784 { 785 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0); 786 } 787 788 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 789 { 790 return chip->info->num_gpio; 791 } 792 793 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port) 794 { 795 return (chip->info->invalid_port_mask & BIT(port)) != 0; 796 } 797 798 static inline void mv88e6xxx_port_set_mab(struct mv88e6xxx_chip *chip, 799 int port, bool mab) 800 { 801 chip->ports[port].mab = mab; 802 } 803 804 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 805 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 806 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 807 u16 mask, u16 val); 808 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 809 int bit, int val); 810 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 811 812 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) 813 { 814 mutex_lock(&chip->reg_lock); 815 } 816 817 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) 818 { 819 mutex_unlock(&chip->reg_lock); 820 } 821 822 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 823 int (*cb)(struct mv88e6xxx_chip *chip, 824 const struct mv88e6xxx_vtu_entry *entry, 825 void *priv), 826 void *priv); 827 828 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap); 829 830 #endif /* _MV88E6XXX_CHIP_H */ 831