1 /* 2 * Marvell 88E6xxx Ethernet switch single-chip definition 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #ifndef _MV88E6XXX_CHIP_H 13 #define _MV88E6XXX_CHIP_H 14 15 #include <linux/if_vlan.h> 16 #include <linux/irq.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/kthread.h> 19 #include <linux/phy.h> 20 #include <linux/ptp_clock_kernel.h> 21 #include <linux/timecounter.h> 22 #include <net/dsa.h> 23 24 #define SMI_CMD 0x00 25 #define SMI_CMD_BUSY BIT(15) 26 #define SMI_CMD_CLAUSE_22 BIT(12) 27 #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 28 #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 29 #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY) 30 #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY) 31 #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY) 32 #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY) 33 #define SMI_DATA 0x01 34 35 #define MV88E6XXX_N_FID 4096 36 37 /* PVT limits for 4-bit port and 5-bit switch */ 38 #define MV88E6XXX_MAX_PVT_SWITCHES 32 39 #define MV88E6XXX_MAX_PVT_PORTS 16 40 41 #define MV88E6XXX_MAX_GPIO 16 42 43 enum mv88e6xxx_egress_mode { 44 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 45 MV88E6XXX_EGRESS_MODE_UNTAGGED, 46 MV88E6XXX_EGRESS_MODE_TAGGED, 47 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 48 }; 49 50 enum mv88e6xxx_frame_mode { 51 MV88E6XXX_FRAME_MODE_NORMAL, 52 MV88E6XXX_FRAME_MODE_DSA, 53 MV88E6XXX_FRAME_MODE_PROVIDER, 54 MV88E6XXX_FRAME_MODE_ETHERTYPE, 55 }; 56 57 /* List of supported models */ 58 enum mv88e6xxx_model { 59 MV88E6085, 60 MV88E6095, 61 MV88E6097, 62 MV88E6123, 63 MV88E6131, 64 MV88E6141, 65 MV88E6161, 66 MV88E6165, 67 MV88E6171, 68 MV88E6172, 69 MV88E6175, 70 MV88E6176, 71 MV88E6185, 72 MV88E6190, 73 MV88E6190X, 74 MV88E6191, 75 MV88E6240, 76 MV88E6290, 77 MV88E6320, 78 MV88E6321, 79 MV88E6341, 80 MV88E6350, 81 MV88E6351, 82 MV88E6352, 83 MV88E6390, 84 MV88E6390X, 85 }; 86 87 enum mv88e6xxx_family { 88 MV88E6XXX_FAMILY_NONE, 89 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 90 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 91 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 92 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 93 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 94 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 95 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 96 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 97 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 98 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 99 }; 100 101 struct mv88e6xxx_ops; 102 103 struct mv88e6xxx_info { 104 enum mv88e6xxx_family family; 105 u16 prod_num; 106 const char *name; 107 unsigned int num_databases; 108 unsigned int num_ports; 109 unsigned int num_internal_phys; 110 unsigned int num_gpio; 111 unsigned int max_vid; 112 unsigned int port_base_addr; 113 unsigned int phy_base_addr; 114 unsigned int global1_addr; 115 unsigned int global2_addr; 116 unsigned int age_time_coeff; 117 unsigned int g1_irqs; 118 unsigned int g2_irqs; 119 bool pvt; 120 121 /* Multi-chip Addressing Mode. 122 * Some chips respond to only 2 registers of its own SMI device address 123 * when it is non-zero, and use indirect access to internal registers. 124 */ 125 bool multi_chip; 126 enum dsa_tag_protocol tag_protocol; 127 128 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 129 * operation. 0 means that the ATU Move operation is not supported. 130 */ 131 u8 atu_move_port_mask; 132 const struct mv88e6xxx_ops *ops; 133 134 /* Supports PTP */ 135 bool ptp_support; 136 }; 137 138 struct mv88e6xxx_atu_entry { 139 u8 state; 140 bool trunk; 141 u16 portvec; 142 u8 mac[ETH_ALEN]; 143 }; 144 145 struct mv88e6xxx_vtu_entry { 146 u16 vid; 147 u16 fid; 148 u8 sid; 149 bool valid; 150 u8 member[DSA_MAX_PORTS]; 151 u8 state[DSA_MAX_PORTS]; 152 }; 153 154 struct mv88e6xxx_bus_ops; 155 struct mv88e6xxx_irq_ops; 156 struct mv88e6xxx_gpio_ops; 157 struct mv88e6xxx_avb_ops; 158 159 struct mv88e6xxx_irq { 160 u16 masked; 161 struct irq_chip chip; 162 struct irq_domain *domain; 163 unsigned int nirqs; 164 }; 165 166 /* state flags for mv88e6xxx_port_hwtstamp::state */ 167 enum { 168 MV88E6XXX_HWTSTAMP_ENABLED, 169 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 170 }; 171 172 struct mv88e6xxx_port_hwtstamp { 173 /* Port index */ 174 int port_id; 175 176 /* Timestamping state */ 177 unsigned long state; 178 179 /* Resources for receive timestamping */ 180 struct sk_buff_head rx_queue; 181 struct sk_buff_head rx_queue2; 182 183 /* Resources for transmit timestamping */ 184 unsigned long tx_tstamp_start; 185 struct sk_buff *tx_skb; 186 u16 tx_seq_id; 187 188 /* Current timestamp configuration */ 189 struct hwtstamp_config tstamp_config; 190 }; 191 192 struct mv88e6xxx_port { 193 u64 serdes_stats[2]; 194 u64 atu_member_violation; 195 u64 atu_miss_violation; 196 u64 atu_full_violation; 197 u64 vtu_member_violation; 198 u64 vtu_miss_violation; 199 }; 200 201 struct mv88e6xxx_chip { 202 const struct mv88e6xxx_info *info; 203 204 /* The dsa_switch this private structure is related to */ 205 struct dsa_switch *ds; 206 207 /* The device this structure is associated to */ 208 struct device *dev; 209 210 /* This mutex protects the access to the switch registers */ 211 struct mutex reg_lock; 212 213 /* The MII bus and the address on the bus that is used to 214 * communication with the switch 215 */ 216 const struct mv88e6xxx_bus_ops *smi_ops; 217 struct mii_bus *bus; 218 int sw_addr; 219 220 /* Handles automatic disabling and re-enabling of the PHY 221 * polling unit. 222 */ 223 const struct mv88e6xxx_bus_ops *phy_ops; 224 struct mutex ppu_mutex; 225 int ppu_disabled; 226 struct work_struct ppu_work; 227 struct timer_list ppu_timer; 228 229 /* This mutex serialises access to the statistics unit. 230 * Hold this mutex over snapshot + dump sequences. 231 */ 232 struct mutex stats_mutex; 233 234 /* A switch may have a GPIO line tied to its reset pin. Parse 235 * this from the device tree, and use it before performing 236 * switch soft reset. 237 */ 238 struct gpio_desc *reset; 239 240 /* set to size of eeprom if supported by the switch */ 241 u32 eeprom_len; 242 243 /* List of mdio busses */ 244 struct list_head mdios; 245 246 /* There can be two interrupt controllers, which are chained 247 * off a GPIO as interrupt source 248 */ 249 struct mv88e6xxx_irq g1_irq; 250 struct mv88e6xxx_irq g2_irq; 251 int irq; 252 int device_irq; 253 int watchdog_irq; 254 255 int atu_prob_irq; 256 int vtu_prob_irq; 257 struct kthread_worker *kworker; 258 struct kthread_delayed_work irq_poll_work; 259 260 /* GPIO resources */ 261 u8 gpio_data[2]; 262 263 /* This cyclecounter abstracts the switch PTP time. 264 * reg_lock must be held for any operation that read()s. 265 */ 266 struct cyclecounter tstamp_cc; 267 struct timecounter tstamp_tc; 268 struct delayed_work overflow_work; 269 270 struct ptp_clock *ptp_clock; 271 struct ptp_clock_info ptp_clock_info; 272 struct delayed_work tai_event_work; 273 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 274 u16 trig_config; 275 u16 evcap_config; 276 277 /* Per-port timestamping resources. */ 278 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 279 280 /* Array of port structures. */ 281 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 282 }; 283 284 struct mv88e6xxx_bus_ops { 285 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 286 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 287 }; 288 289 struct mv88e6xxx_mdio_bus { 290 struct mii_bus *bus; 291 struct mv88e6xxx_chip *chip; 292 struct list_head list; 293 bool external; 294 }; 295 296 struct mv88e6xxx_ops { 297 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 298 int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 299 300 /* Ingress Rate Limit unit (IRL) operations */ 301 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 302 303 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 304 struct ethtool_eeprom *eeprom, u8 *data); 305 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 306 struct ethtool_eeprom *eeprom, u8 *data); 307 308 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 309 310 int (*phy_read)(struct mv88e6xxx_chip *chip, 311 struct mii_bus *bus, 312 int addr, int reg, u16 *val); 313 int (*phy_write)(struct mv88e6xxx_chip *chip, 314 struct mii_bus *bus, 315 int addr, int reg, u16 val); 316 317 /* Priority Override Table operations */ 318 int (*pot_clear)(struct mv88e6xxx_chip *chip); 319 320 /* PHY Polling Unit (PPU) operations */ 321 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 322 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 323 324 /* Switch Software Reset */ 325 int (*reset)(struct mv88e6xxx_chip *chip); 326 327 /* RGMII Receive/Transmit Timing Control 328 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 329 */ 330 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 331 phy_interface_t mode); 332 333 #define LINK_FORCED_DOWN 0 334 #define LINK_FORCED_UP 1 335 #define LINK_UNFORCED -2 336 337 /* Port's MAC link state 338 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 339 * or LINK_UNFORCED for normal link detection. 340 */ 341 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 342 343 #define DUPLEX_UNFORCED -2 344 345 /* Port's MAC duplex mode 346 * 347 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 348 * or DUPLEX_UNFORCED for normal duplex detection. 349 */ 350 int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup); 351 352 #define SPEED_MAX INT_MAX 353 #define SPEED_UNFORCED -2 354 355 /* Port's MAC speed (in Mbps) 356 * 357 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 358 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 359 */ 360 int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed); 361 362 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 363 364 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 365 enum mv88e6xxx_frame_mode mode); 366 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port, 367 bool unicast, bool multicast); 368 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 369 u16 etype); 370 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 371 size_t size); 372 373 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 374 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 375 u8 out); 376 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 377 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 378 379 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 380 * Some chips allow this to be configured on specific ports. 381 */ 382 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 383 phy_interface_t mode); 384 385 /* Some devices have a per port register indicating what is 386 * the upstream port this port should forward to. 387 */ 388 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 389 int upstream_port); 390 391 /* Snapshot the statistics for a port. The statistics can then 392 * be read back a leisure but still with a consistent view. 393 */ 394 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 395 396 /* Set the histogram mode for statistics, when the control registers 397 * are separated out of the STATS_OP register. 398 */ 399 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 400 401 /* Return the number of strings describing statistics */ 402 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 403 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 404 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 405 uint64_t *data); 406 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 407 int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port); 408 409 #define MV88E6XXX_CASCADE_PORT_NONE 0xe 410 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 411 412 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 413 414 const struct mv88e6xxx_irq_ops *watchdog_ops; 415 416 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 417 418 /* Power on/off a SERDES interface */ 419 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on); 420 421 /* Statistics from the SERDES interface */ 422 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 423 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 424 uint8_t *data); 425 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 426 uint64_t *data); 427 428 /* VLAN Translation Unit operations */ 429 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 430 struct mv88e6xxx_vtu_entry *entry); 431 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 432 struct mv88e6xxx_vtu_entry *entry); 433 434 /* GPIO operations */ 435 const struct mv88e6xxx_gpio_ops *gpio_ops; 436 437 /* Interface to the AVB/PTP registers */ 438 const struct mv88e6xxx_avb_ops *avb_ops; 439 440 /* Remote Management Unit operations */ 441 int (*rmu_disable)(struct mv88e6xxx_chip *chip); 442 }; 443 444 struct mv88e6xxx_irq_ops { 445 /* Action to be performed when the interrupt happens */ 446 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 447 /* Setup the hardware to generate the interrupt */ 448 int (*irq_setup)(struct mv88e6xxx_chip *chip); 449 /* Reset the hardware to stop generating the interrupt */ 450 void (*irq_free)(struct mv88e6xxx_chip *chip); 451 }; 452 453 struct mv88e6xxx_gpio_ops { 454 /* Get/set data on GPIO pin */ 455 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 456 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 457 int value); 458 459 /* get/set GPIO direction */ 460 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 461 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 462 bool input); 463 464 /* get/set GPIO pin control */ 465 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 466 int *func); 467 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 468 int func); 469 }; 470 471 struct mv88e6xxx_avb_ops { 472 /* Access port-scoped Precision Time Protocol registers */ 473 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 474 u16 *data, int len); 475 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 476 u16 data); 477 478 /* Access global Precision Time Protocol registers */ 479 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 480 int len); 481 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 482 483 /* Access global Time Application Interface registers */ 484 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 485 int len); 486 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 487 }; 488 489 #define STATS_TYPE_PORT BIT(0) 490 #define STATS_TYPE_BANK0 BIT(1) 491 #define STATS_TYPE_BANK1 BIT(2) 492 493 struct mv88e6xxx_hw_stat { 494 char string[ETH_GSTRING_LEN]; 495 size_t size; 496 int reg; 497 int type; 498 }; 499 500 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 501 { 502 return chip->info->pvt; 503 } 504 505 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 506 { 507 return chip->info->num_databases; 508 } 509 510 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 511 { 512 return chip->info->num_ports; 513 } 514 515 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 516 { 517 return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0); 518 } 519 520 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 521 { 522 return chip->info->num_gpio; 523 } 524 525 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 526 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 527 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, 528 u16 update); 529 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask); 530 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 531 532 #endif /* _MV88E6XXX_CHIP_H */ 533