1 /* 2 * Marvell 88E6xxx Ethernet switch single-chip definition 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #ifndef _MV88E6XXX_CHIP_H 13 #define _MV88E6XXX_CHIP_H 14 15 #include <linux/if_vlan.h> 16 #include <linux/irq.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/kthread.h> 19 #include <linux/phy.h> 20 #include <linux/ptp_clock_kernel.h> 21 #include <linux/timecounter.h> 22 #include <net/dsa.h> 23 24 #define SMI_CMD 0x00 25 #define SMI_CMD_BUSY BIT(15) 26 #define SMI_CMD_CLAUSE_22 BIT(12) 27 #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 28 #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 29 #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY) 30 #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY) 31 #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY) 32 #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY) 33 #define SMI_DATA 0x01 34 35 #define MV88E6XXX_N_FID 4096 36 37 /* PVT limits for 4-bit port and 5-bit switch */ 38 #define MV88E6XXX_MAX_PVT_SWITCHES 32 39 #define MV88E6XXX_MAX_PVT_PORTS 16 40 41 #define MV88E6XXX_MAX_GPIO 16 42 43 enum mv88e6xxx_egress_mode { 44 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 45 MV88E6XXX_EGRESS_MODE_UNTAGGED, 46 MV88E6XXX_EGRESS_MODE_TAGGED, 47 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 48 }; 49 50 enum mv88e6xxx_frame_mode { 51 MV88E6XXX_FRAME_MODE_NORMAL, 52 MV88E6XXX_FRAME_MODE_DSA, 53 MV88E6XXX_FRAME_MODE_PROVIDER, 54 MV88E6XXX_FRAME_MODE_ETHERTYPE, 55 }; 56 57 /* List of supported models */ 58 enum mv88e6xxx_model { 59 MV88E6085, 60 MV88E6095, 61 MV88E6097, 62 MV88E6123, 63 MV88E6131, 64 MV88E6141, 65 MV88E6161, 66 MV88E6165, 67 MV88E6171, 68 MV88E6172, 69 MV88E6175, 70 MV88E6176, 71 MV88E6185, 72 MV88E6190, 73 MV88E6190X, 74 MV88E6191, 75 MV88E6240, 76 MV88E6290, 77 MV88E6320, 78 MV88E6321, 79 MV88E6341, 80 MV88E6350, 81 MV88E6351, 82 MV88E6352, 83 MV88E6390, 84 MV88E6390X, 85 }; 86 87 enum mv88e6xxx_family { 88 MV88E6XXX_FAMILY_NONE, 89 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 90 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 91 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 92 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 93 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 94 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 95 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 96 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 97 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 98 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 99 }; 100 101 struct mv88e6xxx_ops; 102 103 struct mv88e6xxx_info { 104 enum mv88e6xxx_family family; 105 u16 prod_num; 106 const char *name; 107 unsigned int num_databases; 108 unsigned int num_ports; 109 unsigned int num_internal_phys; 110 unsigned int num_gpio; 111 unsigned int max_vid; 112 unsigned int port_base_addr; 113 unsigned int phy_base_addr; 114 unsigned int global1_addr; 115 unsigned int global2_addr; 116 unsigned int age_time_coeff; 117 unsigned int g1_irqs; 118 unsigned int g2_irqs; 119 bool pvt; 120 121 /* Multi-chip Addressing Mode. 122 * Some chips respond to only 2 registers of its own SMI device address 123 * when it is non-zero, and use indirect access to internal registers. 124 */ 125 bool multi_chip; 126 enum dsa_tag_protocol tag_protocol; 127 128 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 129 * operation. 0 means that the ATU Move operation is not supported. 130 */ 131 u8 atu_move_port_mask; 132 const struct mv88e6xxx_ops *ops; 133 134 /* Supports PTP */ 135 bool ptp_support; 136 }; 137 138 struct mv88e6xxx_atu_entry { 139 u8 state; 140 bool trunk; 141 u16 portvec; 142 u8 mac[ETH_ALEN]; 143 }; 144 145 struct mv88e6xxx_vtu_entry { 146 u16 vid; 147 u16 fid; 148 u8 sid; 149 bool valid; 150 u8 member[DSA_MAX_PORTS]; 151 u8 state[DSA_MAX_PORTS]; 152 }; 153 154 struct mv88e6xxx_bus_ops; 155 struct mv88e6xxx_irq_ops; 156 struct mv88e6xxx_gpio_ops; 157 struct mv88e6xxx_avb_ops; 158 struct mv88e6xxx_ptp_ops; 159 160 struct mv88e6xxx_irq { 161 u16 masked; 162 struct irq_chip chip; 163 struct irq_domain *domain; 164 unsigned int nirqs; 165 }; 166 167 /* state flags for mv88e6xxx_port_hwtstamp::state */ 168 enum { 169 MV88E6XXX_HWTSTAMP_ENABLED, 170 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 171 }; 172 173 struct mv88e6xxx_port_hwtstamp { 174 /* Port index */ 175 int port_id; 176 177 /* Timestamping state */ 178 unsigned long state; 179 180 /* Resources for receive timestamping */ 181 struct sk_buff_head rx_queue; 182 struct sk_buff_head rx_queue2; 183 184 /* Resources for transmit timestamping */ 185 unsigned long tx_tstamp_start; 186 struct sk_buff *tx_skb; 187 u16 tx_seq_id; 188 189 /* Current timestamp configuration */ 190 struct hwtstamp_config tstamp_config; 191 }; 192 193 struct mv88e6xxx_port { 194 struct mv88e6xxx_chip *chip; 195 int port; 196 u64 serdes_stats[2]; 197 u64 atu_member_violation; 198 u64 atu_miss_violation; 199 u64 atu_full_violation; 200 u64 vtu_member_violation; 201 u64 vtu_miss_violation; 202 u8 cmode; 203 int serdes_irq; 204 }; 205 206 struct mv88e6xxx_chip { 207 const struct mv88e6xxx_info *info; 208 209 /* The dsa_switch this private structure is related to */ 210 struct dsa_switch *ds; 211 212 /* The device this structure is associated to */ 213 struct device *dev; 214 215 /* This mutex protects the access to the switch registers */ 216 struct mutex reg_lock; 217 218 /* The MII bus and the address on the bus that is used to 219 * communication with the switch 220 */ 221 const struct mv88e6xxx_bus_ops *smi_ops; 222 struct mii_bus *bus; 223 int sw_addr; 224 225 /* Handles automatic disabling and re-enabling of the PHY 226 * polling unit. 227 */ 228 const struct mv88e6xxx_bus_ops *phy_ops; 229 struct mutex ppu_mutex; 230 int ppu_disabled; 231 struct work_struct ppu_work; 232 struct timer_list ppu_timer; 233 234 /* This mutex serialises access to the statistics unit. 235 * Hold this mutex over snapshot + dump sequences. 236 */ 237 struct mutex stats_mutex; 238 239 /* A switch may have a GPIO line tied to its reset pin. Parse 240 * this from the device tree, and use it before performing 241 * switch soft reset. 242 */ 243 struct gpio_desc *reset; 244 245 /* set to size of eeprom if supported by the switch */ 246 u32 eeprom_len; 247 248 /* List of mdio busses */ 249 struct list_head mdios; 250 251 /* There can be two interrupt controllers, which are chained 252 * off a GPIO as interrupt source 253 */ 254 struct mv88e6xxx_irq g1_irq; 255 struct mv88e6xxx_irq g2_irq; 256 int irq; 257 int device_irq; 258 int watchdog_irq; 259 260 int atu_prob_irq; 261 int vtu_prob_irq; 262 struct kthread_worker *kworker; 263 struct kthread_delayed_work irq_poll_work; 264 265 /* GPIO resources */ 266 u8 gpio_data[2]; 267 268 /* This cyclecounter abstracts the switch PTP time. 269 * reg_lock must be held for any operation that read()s. 270 */ 271 struct cyclecounter tstamp_cc; 272 struct timecounter tstamp_tc; 273 struct delayed_work overflow_work; 274 275 struct ptp_clock *ptp_clock; 276 struct ptp_clock_info ptp_clock_info; 277 struct delayed_work tai_event_work; 278 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 279 u16 trig_config; 280 u16 evcap_config; 281 u16 enable_count; 282 283 /* Per-port timestamping resources. */ 284 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 285 286 /* Array of port structures. */ 287 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 288 }; 289 290 struct mv88e6xxx_bus_ops { 291 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 292 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 293 }; 294 295 struct mv88e6xxx_mdio_bus { 296 struct mii_bus *bus; 297 struct mv88e6xxx_chip *chip; 298 struct list_head list; 299 bool external; 300 }; 301 302 struct mv88e6xxx_ops { 303 /* Switch Setup Errata, called early in the switch setup to 304 * allow any errata actions to be performed 305 */ 306 int (*setup_errata)(struct mv88e6xxx_chip *chip); 307 308 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 309 int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 310 311 /* Ingress Rate Limit unit (IRL) operations */ 312 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 313 314 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 315 struct ethtool_eeprom *eeprom, u8 *data); 316 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 317 struct ethtool_eeprom *eeprom, u8 *data); 318 319 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 320 321 int (*phy_read)(struct mv88e6xxx_chip *chip, 322 struct mii_bus *bus, 323 int addr, int reg, u16 *val); 324 int (*phy_write)(struct mv88e6xxx_chip *chip, 325 struct mii_bus *bus, 326 int addr, int reg, u16 val); 327 328 /* Priority Override Table operations */ 329 int (*pot_clear)(struct mv88e6xxx_chip *chip); 330 331 /* PHY Polling Unit (PPU) operations */ 332 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 333 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 334 335 /* Switch Software Reset */ 336 int (*reset)(struct mv88e6xxx_chip *chip); 337 338 /* RGMII Receive/Transmit Timing Control 339 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 340 */ 341 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 342 phy_interface_t mode); 343 344 #define LINK_FORCED_DOWN 0 345 #define LINK_FORCED_UP 1 346 #define LINK_UNFORCED -2 347 348 /* Port's MAC link state 349 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 350 * or LINK_UNFORCED for normal link detection. 351 */ 352 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 353 354 #define DUPLEX_UNFORCED -2 355 356 /* Port's MAC duplex mode 357 * 358 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 359 * or DUPLEX_UNFORCED for normal duplex detection. 360 */ 361 int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup); 362 363 #define PAUSE_ON 1 364 #define PAUSE_OFF 0 365 366 /* Enable/disable sending Pause */ 367 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 368 int pause); 369 370 #define SPEED_MAX INT_MAX 371 #define SPEED_UNFORCED -2 372 373 /* Port's MAC speed (in Mbps) 374 * 375 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 376 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 377 */ 378 int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed); 379 380 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 381 382 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 383 enum mv88e6xxx_frame_mode mode); 384 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port, 385 bool unicast, bool multicast); 386 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 387 u16 etype); 388 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 389 size_t size); 390 391 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 392 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 393 u8 out); 394 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 395 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 396 397 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 398 * Some chips allow this to be configured on specific ports. 399 */ 400 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 401 phy_interface_t mode); 402 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 403 404 /* Some devices have a per port register indicating what is 405 * the upstream port this port should forward to. 406 */ 407 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 408 int upstream_port); 409 /* Return the port link state, as required by phylink */ 410 int (*port_link_state)(struct mv88e6xxx_chip *chip, int port, 411 struct phylink_link_state *state); 412 413 /* Snapshot the statistics for a port. The statistics can then 414 * be read back a leisure but still with a consistent view. 415 */ 416 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 417 418 /* Set the histogram mode for statistics, when the control registers 419 * are separated out of the STATS_OP register. 420 */ 421 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 422 423 /* Return the number of strings describing statistics */ 424 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 425 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 426 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 427 uint64_t *data); 428 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 429 int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port); 430 431 #define MV88E6XXX_CASCADE_PORT_NONE 0xe 432 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 433 434 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 435 436 const struct mv88e6xxx_irq_ops *watchdog_ops; 437 438 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 439 440 /* Power on/off a SERDES interface */ 441 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on); 442 443 /* SERDES interrupt handling */ 444 int (*serdes_irq_setup)(struct mv88e6xxx_chip *chip, int port); 445 void (*serdes_irq_free)(struct mv88e6xxx_chip *chip, int port); 446 447 /* Statistics from the SERDES interface */ 448 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 449 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 450 uint8_t *data); 451 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 452 uint64_t *data); 453 454 /* VLAN Translation Unit operations */ 455 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 456 struct mv88e6xxx_vtu_entry *entry); 457 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 458 struct mv88e6xxx_vtu_entry *entry); 459 460 /* GPIO operations */ 461 const struct mv88e6xxx_gpio_ops *gpio_ops; 462 463 /* Interface to the AVB/PTP registers */ 464 const struct mv88e6xxx_avb_ops *avb_ops; 465 466 /* Remote Management Unit operations */ 467 int (*rmu_disable)(struct mv88e6xxx_chip *chip); 468 469 /* Precision Time Protocol operations */ 470 const struct mv88e6xxx_ptp_ops *ptp_ops; 471 472 /* Phylink */ 473 void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port, 474 unsigned long *mask, 475 struct phylink_link_state *state); 476 }; 477 478 struct mv88e6xxx_irq_ops { 479 /* Action to be performed when the interrupt happens */ 480 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 481 /* Setup the hardware to generate the interrupt */ 482 int (*irq_setup)(struct mv88e6xxx_chip *chip); 483 /* Reset the hardware to stop generating the interrupt */ 484 void (*irq_free)(struct mv88e6xxx_chip *chip); 485 }; 486 487 struct mv88e6xxx_gpio_ops { 488 /* Get/set data on GPIO pin */ 489 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 490 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 491 int value); 492 493 /* get/set GPIO direction */ 494 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 495 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 496 bool input); 497 498 /* get/set GPIO pin control */ 499 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 500 int *func); 501 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 502 int func); 503 }; 504 505 struct mv88e6xxx_avb_ops { 506 /* Access port-scoped Precision Time Protocol registers */ 507 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 508 u16 *data, int len); 509 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 510 u16 data); 511 512 /* Access global Precision Time Protocol registers */ 513 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 514 int len); 515 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 516 517 /* Access global Time Application Interface registers */ 518 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 519 int len); 520 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 521 }; 522 523 struct mv88e6xxx_ptp_ops { 524 u64 (*clock_read)(const struct cyclecounter *cc); 525 int (*ptp_enable)(struct ptp_clock_info *ptp, 526 struct ptp_clock_request *rq, int on); 527 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 528 enum ptp_pin_function func, unsigned int chan); 529 void (*event_work)(struct work_struct *ugly); 530 int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 531 int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 532 int (*global_enable)(struct mv88e6xxx_chip *chip); 533 int (*global_disable)(struct mv88e6xxx_chip *chip); 534 int n_ext_ts; 535 int arr0_sts_reg; 536 int arr1_sts_reg; 537 int dep_sts_reg; 538 u32 rx_filters; 539 }; 540 541 #define STATS_TYPE_PORT BIT(0) 542 #define STATS_TYPE_BANK0 BIT(1) 543 #define STATS_TYPE_BANK1 BIT(2) 544 545 struct mv88e6xxx_hw_stat { 546 char string[ETH_GSTRING_LEN]; 547 size_t size; 548 int reg; 549 int type; 550 }; 551 552 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 553 { 554 return chip->info->pvt; 555 } 556 557 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 558 { 559 return chip->info->num_databases; 560 } 561 562 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 563 { 564 return chip->info->num_ports; 565 } 566 567 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 568 { 569 return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0); 570 } 571 572 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 573 { 574 return chip->info->num_gpio; 575 } 576 577 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 578 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 579 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, 580 u16 update); 581 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask); 582 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 583 584 #endif /* _MV88E6XXX_CHIP_H */ 585