1 /* 2 * Marvell 88E6xxx Ethernet switch single-chip definition 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #ifndef _MV88E6XXX_CHIP_H 13 #define _MV88E6XXX_CHIP_H 14 15 #include <linux/if_vlan.h> 16 #include <linux/irq.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/phy.h> 19 #include <linux/ptp_clock_kernel.h> 20 #include <linux/timecounter.h> 21 #include <net/dsa.h> 22 23 #ifndef UINT64_MAX 24 #define UINT64_MAX (u64)(~((u64)0)) 25 #endif 26 27 #define SMI_CMD 0x00 28 #define SMI_CMD_BUSY BIT(15) 29 #define SMI_CMD_CLAUSE_22 BIT(12) 30 #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 31 #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 32 #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY) 33 #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY) 34 #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY) 35 #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY) 36 #define SMI_DATA 0x01 37 38 #define MV88E6XXX_N_FID 4096 39 40 /* PVT limits for 4-bit port and 5-bit switch */ 41 #define MV88E6XXX_MAX_PVT_SWITCHES 32 42 #define MV88E6XXX_MAX_PVT_PORTS 16 43 44 #define MV88E6XXX_MAX_GPIO 16 45 46 enum mv88e6xxx_egress_mode { 47 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 48 MV88E6XXX_EGRESS_MODE_UNTAGGED, 49 MV88E6XXX_EGRESS_MODE_TAGGED, 50 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 51 }; 52 53 enum mv88e6xxx_frame_mode { 54 MV88E6XXX_FRAME_MODE_NORMAL, 55 MV88E6XXX_FRAME_MODE_DSA, 56 MV88E6XXX_FRAME_MODE_PROVIDER, 57 MV88E6XXX_FRAME_MODE_ETHERTYPE, 58 }; 59 60 /* List of supported models */ 61 enum mv88e6xxx_model { 62 MV88E6085, 63 MV88E6095, 64 MV88E6097, 65 MV88E6123, 66 MV88E6131, 67 MV88E6141, 68 MV88E6161, 69 MV88E6165, 70 MV88E6171, 71 MV88E6172, 72 MV88E6175, 73 MV88E6176, 74 MV88E6185, 75 MV88E6190, 76 MV88E6190X, 77 MV88E6191, 78 MV88E6240, 79 MV88E6290, 80 MV88E6320, 81 MV88E6321, 82 MV88E6341, 83 MV88E6350, 84 MV88E6351, 85 MV88E6352, 86 MV88E6390, 87 MV88E6390X, 88 }; 89 90 enum mv88e6xxx_family { 91 MV88E6XXX_FAMILY_NONE, 92 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 93 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 94 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 95 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 96 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 97 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 98 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 99 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 100 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 101 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 102 }; 103 104 struct mv88e6xxx_ops; 105 106 struct mv88e6xxx_info { 107 enum mv88e6xxx_family family; 108 u16 prod_num; 109 const char *name; 110 unsigned int num_databases; 111 unsigned int num_ports; 112 unsigned int num_gpio; 113 unsigned int max_vid; 114 unsigned int port_base_addr; 115 unsigned int global1_addr; 116 unsigned int global2_addr; 117 unsigned int age_time_coeff; 118 unsigned int g1_irqs; 119 unsigned int g2_irqs; 120 bool pvt; 121 122 /* Multi-chip Addressing Mode. 123 * Some chips respond to only 2 registers of its own SMI device address 124 * when it is non-zero, and use indirect access to internal registers. 125 */ 126 bool multi_chip; 127 enum dsa_tag_protocol tag_protocol; 128 129 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 130 * operation. 0 means that the ATU Move operation is not supported. 131 */ 132 u8 atu_move_port_mask; 133 const struct mv88e6xxx_ops *ops; 134 135 /* Supports PTP */ 136 bool ptp_support; 137 }; 138 139 struct mv88e6xxx_atu_entry { 140 u8 state; 141 bool trunk; 142 u16 portvec; 143 u8 mac[ETH_ALEN]; 144 }; 145 146 struct mv88e6xxx_vtu_entry { 147 u16 vid; 148 u16 fid; 149 u8 sid; 150 bool valid; 151 u8 member[DSA_MAX_PORTS]; 152 u8 state[DSA_MAX_PORTS]; 153 }; 154 155 struct mv88e6xxx_bus_ops; 156 struct mv88e6xxx_irq_ops; 157 struct mv88e6xxx_gpio_ops; 158 struct mv88e6xxx_avb_ops; 159 160 struct mv88e6xxx_irq { 161 u16 masked; 162 struct irq_chip chip; 163 struct irq_domain *domain; 164 unsigned int nirqs; 165 }; 166 167 /* state flags for mv88e6xxx_port_hwtstamp::state */ 168 enum { 169 MV88E6XXX_HWTSTAMP_ENABLED, 170 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 171 }; 172 173 struct mv88e6xxx_port_hwtstamp { 174 /* Port index */ 175 int port_id; 176 177 /* Timestamping state */ 178 unsigned long state; 179 180 /* Resources for receive timestamping */ 181 struct sk_buff_head rx_queue; 182 struct sk_buff_head rx_queue2; 183 184 /* Resources for transmit timestamping */ 185 unsigned long tx_tstamp_start; 186 struct sk_buff *tx_skb; 187 u16 tx_seq_id; 188 189 /* Current timestamp configuration */ 190 struct hwtstamp_config tstamp_config; 191 }; 192 193 struct mv88e6xxx_chip { 194 const struct mv88e6xxx_info *info; 195 196 /* The dsa_switch this private structure is related to */ 197 struct dsa_switch *ds; 198 199 /* The device this structure is associated to */ 200 struct device *dev; 201 202 /* This mutex protects the access to the switch registers */ 203 struct mutex reg_lock; 204 205 /* The MII bus and the address on the bus that is used to 206 * communication with the switch 207 */ 208 const struct mv88e6xxx_bus_ops *smi_ops; 209 struct mii_bus *bus; 210 int sw_addr; 211 212 /* Handles automatic disabling and re-enabling of the PHY 213 * polling unit. 214 */ 215 const struct mv88e6xxx_bus_ops *phy_ops; 216 struct mutex ppu_mutex; 217 int ppu_disabled; 218 struct work_struct ppu_work; 219 struct timer_list ppu_timer; 220 221 /* This mutex serialises access to the statistics unit. 222 * Hold this mutex over snapshot + dump sequences. 223 */ 224 struct mutex stats_mutex; 225 226 /* A switch may have a GPIO line tied to its reset pin. Parse 227 * this from the device tree, and use it before performing 228 * switch soft reset. 229 */ 230 struct gpio_desc *reset; 231 232 /* set to size of eeprom if supported by the switch */ 233 int eeprom_len; 234 235 /* List of mdio busses */ 236 struct list_head mdios; 237 238 /* There can be two interrupt controllers, which are chained 239 * off a GPIO as interrupt source 240 */ 241 struct mv88e6xxx_irq g1_irq; 242 struct mv88e6xxx_irq g2_irq; 243 int irq; 244 int device_irq; 245 int watchdog_irq; 246 int atu_prob_irq; 247 int vtu_prob_irq; 248 249 /* GPIO resources */ 250 u8 gpio_data[2]; 251 252 /* This cyclecounter abstracts the switch PTP time. 253 * reg_lock must be held for any operation that read()s. 254 */ 255 struct cyclecounter tstamp_cc; 256 struct timecounter tstamp_tc; 257 struct delayed_work overflow_work; 258 259 struct ptp_clock *ptp_clock; 260 struct ptp_clock_info ptp_clock_info; 261 struct delayed_work tai_event_work; 262 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 263 u16 trig_config; 264 u16 evcap_config; 265 266 /* Per-port timestamping resources. */ 267 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 268 }; 269 270 struct mv88e6xxx_bus_ops { 271 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 272 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 273 }; 274 275 struct mv88e6xxx_mdio_bus { 276 struct mii_bus *bus; 277 struct mv88e6xxx_chip *chip; 278 struct list_head list; 279 bool external; 280 }; 281 282 struct mv88e6xxx_ops { 283 /* Ingress Rate Limit unit (IRL) operations */ 284 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 285 286 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 287 struct ethtool_eeprom *eeprom, u8 *data); 288 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 289 struct ethtool_eeprom *eeprom, u8 *data); 290 291 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 292 293 int (*phy_read)(struct mv88e6xxx_chip *chip, 294 struct mii_bus *bus, 295 int addr, int reg, u16 *val); 296 int (*phy_write)(struct mv88e6xxx_chip *chip, 297 struct mii_bus *bus, 298 int addr, int reg, u16 val); 299 300 /* Priority Override Table operations */ 301 int (*pot_clear)(struct mv88e6xxx_chip *chip); 302 303 /* PHY Polling Unit (PPU) operations */ 304 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 305 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 306 307 /* Switch Software Reset */ 308 int (*reset)(struct mv88e6xxx_chip *chip); 309 310 /* RGMII Receive/Transmit Timing Control 311 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 312 */ 313 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 314 phy_interface_t mode); 315 316 #define LINK_FORCED_DOWN 0 317 #define LINK_FORCED_UP 1 318 #define LINK_UNFORCED -2 319 320 /* Port's MAC link state 321 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 322 * or LINK_UNFORCED for normal link detection. 323 */ 324 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 325 326 #define DUPLEX_UNFORCED -2 327 328 /* Port's MAC duplex mode 329 * 330 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 331 * or DUPLEX_UNFORCED for normal duplex detection. 332 */ 333 int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup); 334 335 #define SPEED_MAX INT_MAX 336 #define SPEED_UNFORCED -2 337 338 /* Port's MAC speed (in Mbps) 339 * 340 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 341 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 342 */ 343 int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed); 344 345 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 346 347 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 348 enum mv88e6xxx_frame_mode mode); 349 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port, 350 bool unicast, bool multicast); 351 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 352 u16 etype); 353 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 354 size_t size); 355 356 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 357 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 358 u8 out); 359 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 360 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 361 362 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 363 * Some chips allow this to be configured on specific ports. 364 */ 365 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 366 phy_interface_t mode); 367 368 /* Some devices have a per port register indicating what is 369 * the upstream port this port should forward to. 370 */ 371 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 372 int upstream_port); 373 374 /* Snapshot the statistics for a port. The statistics can then 375 * be read back a leisure but still with a consistent view. 376 */ 377 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 378 379 /* Set the histogram mode for statistics, when the control registers 380 * are separated out of the STATS_OP register. 381 */ 382 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 383 384 /* Return the number of strings describing statistics */ 385 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 386 void (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 387 void (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 388 uint64_t *data); 389 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 390 int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port); 391 const struct mv88e6xxx_irq_ops *watchdog_ops; 392 393 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 394 395 /* Power on/off a SERDES interface */ 396 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on); 397 398 /* VLAN Translation Unit operations */ 399 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 400 struct mv88e6xxx_vtu_entry *entry); 401 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 402 struct mv88e6xxx_vtu_entry *entry); 403 404 /* GPIO operations */ 405 const struct mv88e6xxx_gpio_ops *gpio_ops; 406 407 /* Interface to the AVB/PTP registers */ 408 const struct mv88e6xxx_avb_ops *avb_ops; 409 }; 410 411 struct mv88e6xxx_irq_ops { 412 /* Action to be performed when the interrupt happens */ 413 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 414 /* Setup the hardware to generate the interrupt */ 415 int (*irq_setup)(struct mv88e6xxx_chip *chip); 416 /* Reset the hardware to stop generating the interrupt */ 417 void (*irq_free)(struct mv88e6xxx_chip *chip); 418 }; 419 420 struct mv88e6xxx_gpio_ops { 421 /* Get/set data on GPIO pin */ 422 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 423 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 424 int value); 425 426 /* get/set GPIO direction */ 427 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 428 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 429 bool input); 430 431 /* get/set GPIO pin control */ 432 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 433 int *func); 434 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 435 int func); 436 }; 437 438 struct mv88e6xxx_avb_ops { 439 /* Access port-scoped Precision Time Protocol registers */ 440 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 441 u16 *data, int len); 442 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 443 u16 data); 444 445 /* Access global Precision Time Protocol registers */ 446 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 447 int len); 448 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 449 450 /* Access global Time Application Interface registers */ 451 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 452 int len); 453 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 454 }; 455 456 #define STATS_TYPE_PORT BIT(0) 457 #define STATS_TYPE_BANK0 BIT(1) 458 #define STATS_TYPE_BANK1 BIT(2) 459 460 struct mv88e6xxx_hw_stat { 461 char string[ETH_GSTRING_LEN]; 462 int sizeof_stat; 463 int reg; 464 int type; 465 }; 466 467 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 468 { 469 return chip->info->pvt; 470 } 471 472 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 473 { 474 return chip->info->num_databases; 475 } 476 477 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 478 { 479 return chip->info->num_ports; 480 } 481 482 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 483 { 484 return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0); 485 } 486 487 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 488 { 489 return chip->info->num_gpio; 490 } 491 492 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 493 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 494 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, 495 u16 update); 496 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask); 497 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 498 499 #endif /* _MV88E6XXX_CHIP_H */ 500