1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Ethernet switch single-chip definition 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 */ 7 8 #ifndef _MV88E6XXX_CHIP_H 9 #define _MV88E6XXX_CHIP_H 10 11 #include <linux/idr.h> 12 #include <linux/if_vlan.h> 13 #include <linux/irq.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/kthread.h> 16 #include <linux/phy.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/timecounter.h> 19 #include <net/dsa.h> 20 21 #define MV88E6XXX_N_FID 4096 22 23 /* PVT limits for 4-bit port and 5-bit switch */ 24 #define MV88E6XXX_MAX_PVT_SWITCHES 32 25 #define MV88E6XXX_MAX_PVT_PORTS 16 26 27 #define MV88E6XXX_MAX_GPIO 16 28 29 enum mv88e6xxx_egress_mode { 30 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 31 MV88E6XXX_EGRESS_MODE_UNTAGGED, 32 MV88E6XXX_EGRESS_MODE_TAGGED, 33 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 34 }; 35 36 enum mv88e6xxx_egress_direction { 37 MV88E6XXX_EGRESS_DIR_INGRESS, 38 MV88E6XXX_EGRESS_DIR_EGRESS, 39 }; 40 41 enum mv88e6xxx_frame_mode { 42 MV88E6XXX_FRAME_MODE_NORMAL, 43 MV88E6XXX_FRAME_MODE_DSA, 44 MV88E6XXX_FRAME_MODE_PROVIDER, 45 MV88E6XXX_FRAME_MODE_ETHERTYPE, 46 }; 47 48 /* List of supported models */ 49 enum mv88e6xxx_model { 50 MV88E6085, 51 MV88E6095, 52 MV88E6097, 53 MV88E6123, 54 MV88E6131, 55 MV88E6141, 56 MV88E6161, 57 MV88E6165, 58 MV88E6171, 59 MV88E6172, 60 MV88E6175, 61 MV88E6176, 62 MV88E6185, 63 MV88E6190, 64 MV88E6190X, 65 MV88E6191, 66 MV88E6191X, 67 MV88E6193X, 68 MV88E6220, 69 MV88E6240, 70 MV88E6250, 71 MV88E6290, 72 MV88E6320, 73 MV88E6321, 74 MV88E6341, 75 MV88E6350, 76 MV88E6351, 77 MV88E6352, 78 MV88E6390, 79 MV88E6390X, 80 MV88E6393X, 81 }; 82 83 enum mv88e6xxx_family { 84 MV88E6XXX_FAMILY_NONE, 85 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 86 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 87 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 88 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 89 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 90 MV88E6XXX_FAMILY_6250, /* 6220 6250 */ 91 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 92 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 93 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 94 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 95 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 96 MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6393X */ 97 }; 98 99 struct mv88e6xxx_ops; 100 101 struct mv88e6xxx_info { 102 enum mv88e6xxx_family family; 103 u16 prod_num; 104 const char *name; 105 unsigned int num_databases; 106 unsigned int num_macs; 107 unsigned int num_ports; 108 unsigned int num_internal_phys; 109 unsigned int num_gpio; 110 unsigned int max_vid; 111 unsigned int port_base_addr; 112 unsigned int phy_base_addr; 113 unsigned int global1_addr; 114 unsigned int global2_addr; 115 unsigned int age_time_coeff; 116 unsigned int g1_irqs; 117 unsigned int g2_irqs; 118 bool pvt; 119 120 /* Mark certain ports as invalid. This is required for example for the 121 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the 122 * ports 2-4 are not routet to pins. 123 */ 124 unsigned int invalid_port_mask; 125 /* Multi-chip Addressing Mode. 126 * Some chips respond to only 2 registers of its own SMI device address 127 * when it is non-zero, and use indirect access to internal registers. 128 */ 129 bool multi_chip; 130 /* Dual-chip Addressing Mode 131 * Some chips respond to only half of the 32 SMI addresses, 132 * allowing two to coexist on the same SMI interface. 133 */ 134 bool dual_chip; 135 136 enum dsa_tag_protocol tag_protocol; 137 138 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 139 * operation. 0 means that the ATU Move operation is not supported. 140 */ 141 u8 atu_move_port_mask; 142 const struct mv88e6xxx_ops *ops; 143 144 /* Supports PTP */ 145 bool ptp_support; 146 }; 147 148 struct mv88e6xxx_atu_entry { 149 u8 state; 150 bool trunk; 151 u16 portvec; 152 u8 mac[ETH_ALEN]; 153 }; 154 155 struct mv88e6xxx_vtu_entry { 156 u16 vid; 157 u16 fid; 158 u8 sid; 159 bool valid; 160 u8 member[DSA_MAX_PORTS]; 161 u8 state[DSA_MAX_PORTS]; 162 }; 163 164 struct mv88e6xxx_bus_ops; 165 struct mv88e6xxx_irq_ops; 166 struct mv88e6xxx_gpio_ops; 167 struct mv88e6xxx_avb_ops; 168 struct mv88e6xxx_ptp_ops; 169 170 struct mv88e6xxx_irq { 171 u16 masked; 172 struct irq_chip chip; 173 struct irq_domain *domain; 174 int nirqs; 175 }; 176 177 /* state flags for mv88e6xxx_port_hwtstamp::state */ 178 enum { 179 MV88E6XXX_HWTSTAMP_ENABLED, 180 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 181 }; 182 183 struct mv88e6xxx_port_hwtstamp { 184 /* Port index */ 185 int port_id; 186 187 /* Timestamping state */ 188 unsigned long state; 189 190 /* Resources for receive timestamping */ 191 struct sk_buff_head rx_queue; 192 struct sk_buff_head rx_queue2; 193 194 /* Resources for transmit timestamping */ 195 unsigned long tx_tstamp_start; 196 struct sk_buff *tx_skb; 197 u16 tx_seq_id; 198 199 /* Current timestamp configuration */ 200 struct hwtstamp_config tstamp_config; 201 }; 202 203 enum mv88e6xxx_policy_mapping { 204 MV88E6XXX_POLICY_MAPPING_DA, 205 MV88E6XXX_POLICY_MAPPING_SA, 206 MV88E6XXX_POLICY_MAPPING_VTU, 207 MV88E6XXX_POLICY_MAPPING_ETYPE, 208 MV88E6XXX_POLICY_MAPPING_PPPOE, 209 MV88E6XXX_POLICY_MAPPING_VBAS, 210 MV88E6XXX_POLICY_MAPPING_OPT82, 211 MV88E6XXX_POLICY_MAPPING_UDP, 212 }; 213 214 enum mv88e6xxx_policy_action { 215 MV88E6XXX_POLICY_ACTION_NORMAL, 216 MV88E6XXX_POLICY_ACTION_MIRROR, 217 MV88E6XXX_POLICY_ACTION_TRAP, 218 MV88E6XXX_POLICY_ACTION_DISCARD, 219 }; 220 221 struct mv88e6xxx_policy { 222 enum mv88e6xxx_policy_mapping mapping; 223 enum mv88e6xxx_policy_action action; 224 struct ethtool_rx_flow_spec fs; 225 u8 addr[ETH_ALEN]; 226 int port; 227 u16 vid; 228 }; 229 230 struct mv88e6xxx_port { 231 struct mv88e6xxx_chip *chip; 232 int port; 233 u64 serdes_stats[2]; 234 u64 atu_member_violation; 235 u64 atu_miss_violation; 236 u64 atu_full_violation; 237 u64 vtu_member_violation; 238 u64 vtu_miss_violation; 239 phy_interface_t interface; 240 u8 cmode; 241 bool mirror_ingress; 242 bool mirror_egress; 243 unsigned int serdes_irq; 244 char serdes_irq_name[64]; 245 struct devlink_region *region; 246 }; 247 248 enum mv88e6xxx_region_id { 249 MV88E6XXX_REGION_GLOBAL1 = 0, 250 MV88E6XXX_REGION_GLOBAL2, 251 MV88E6XXX_REGION_ATU, 252 MV88E6XXX_REGION_VTU, 253 254 _MV88E6XXX_REGION_MAX, 255 }; 256 257 struct mv88e6xxx_region_priv { 258 enum mv88e6xxx_region_id id; 259 }; 260 261 struct mv88e6xxx_chip { 262 const struct mv88e6xxx_info *info; 263 264 /* The dsa_switch this private structure is related to */ 265 struct dsa_switch *ds; 266 267 /* The device this structure is associated to */ 268 struct device *dev; 269 270 /* This mutex protects the access to the switch registers */ 271 struct mutex reg_lock; 272 273 /* The MII bus and the address on the bus that is used to 274 * communication with the switch 275 */ 276 const struct mv88e6xxx_bus_ops *smi_ops; 277 struct mii_bus *bus; 278 int sw_addr; 279 280 /* Handles automatic disabling and re-enabling of the PHY 281 * polling unit. 282 */ 283 const struct mv88e6xxx_bus_ops *phy_ops; 284 struct mutex ppu_mutex; 285 int ppu_disabled; 286 struct work_struct ppu_work; 287 struct timer_list ppu_timer; 288 289 /* This mutex serialises access to the statistics unit. 290 * Hold this mutex over snapshot + dump sequences. 291 */ 292 struct mutex stats_mutex; 293 294 /* A switch may have a GPIO line tied to its reset pin. Parse 295 * this from the device tree, and use it before performing 296 * switch soft reset. 297 */ 298 struct gpio_desc *reset; 299 300 /* set to size of eeprom if supported by the switch */ 301 u32 eeprom_len; 302 303 /* List of mdio busses */ 304 struct list_head mdios; 305 306 /* Policy Control List IDs and rules */ 307 struct idr policies; 308 309 /* There can be two interrupt controllers, which are chained 310 * off a GPIO as interrupt source 311 */ 312 struct mv88e6xxx_irq g1_irq; 313 struct mv88e6xxx_irq g2_irq; 314 int irq; 315 char irq_name[64]; 316 int device_irq; 317 char device_irq_name[64]; 318 int watchdog_irq; 319 char watchdog_irq_name[64]; 320 321 int atu_prob_irq; 322 char atu_prob_irq_name[64]; 323 int vtu_prob_irq; 324 char vtu_prob_irq_name[64]; 325 struct kthread_worker *kworker; 326 struct kthread_delayed_work irq_poll_work; 327 328 /* GPIO resources */ 329 u8 gpio_data[2]; 330 331 /* This cyclecounter abstracts the switch PTP time. 332 * reg_lock must be held for any operation that read()s. 333 */ 334 struct cyclecounter tstamp_cc; 335 struct timecounter tstamp_tc; 336 struct delayed_work overflow_work; 337 338 struct ptp_clock *ptp_clock; 339 struct ptp_clock_info ptp_clock_info; 340 struct delayed_work tai_event_work; 341 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 342 u16 trig_config; 343 u16 evcap_config; 344 u16 enable_count; 345 346 /* Current ingress and egress monitor ports */ 347 int egress_dest_port; 348 int ingress_dest_port; 349 350 /* Per-port timestamping resources. */ 351 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 352 353 /* Array of port structures. */ 354 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 355 356 /* devlink regions */ 357 struct devlink_region *regions[_MV88E6XXX_REGION_MAX]; 358 }; 359 360 struct mv88e6xxx_bus_ops { 361 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 362 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 363 }; 364 365 struct mv88e6xxx_mdio_bus { 366 struct mii_bus *bus; 367 struct mv88e6xxx_chip *chip; 368 struct list_head list; 369 bool external; 370 }; 371 372 struct mv88e6xxx_ops { 373 /* Switch Setup Errata, called early in the switch setup to 374 * allow any errata actions to be performed 375 */ 376 int (*setup_errata)(struct mv88e6xxx_chip *chip); 377 378 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 379 int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 380 381 /* Ingress Rate Limit unit (IRL) operations */ 382 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 383 384 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 385 struct ethtool_eeprom *eeprom, u8 *data); 386 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 387 struct ethtool_eeprom *eeprom, u8 *data); 388 389 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 390 391 int (*phy_read)(struct mv88e6xxx_chip *chip, 392 struct mii_bus *bus, 393 int addr, int reg, u16 *val); 394 int (*phy_write)(struct mv88e6xxx_chip *chip, 395 struct mii_bus *bus, 396 int addr, int reg, u16 val); 397 398 /* Priority Override Table operations */ 399 int (*pot_clear)(struct mv88e6xxx_chip *chip); 400 401 /* PHY Polling Unit (PPU) operations */ 402 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 403 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 404 405 /* Switch Software Reset */ 406 int (*reset)(struct mv88e6xxx_chip *chip); 407 408 /* RGMII Receive/Transmit Timing Control 409 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 410 */ 411 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 412 phy_interface_t mode); 413 414 #define LINK_FORCED_DOWN 0 415 #define LINK_FORCED_UP 1 416 #define LINK_UNFORCED -2 417 418 /* Port's MAC link state 419 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 420 * or LINK_UNFORCED for normal link detection. 421 */ 422 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 423 424 /* Synchronise the port link state with that of the SERDES 425 */ 426 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 427 428 #define PAUSE_ON 1 429 #define PAUSE_OFF 0 430 431 /* Enable/disable sending Pause */ 432 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 433 int pause); 434 435 #define SPEED_MAX INT_MAX 436 #define SPEED_UNFORCED -2 437 #define DUPLEX_UNFORCED -2 438 439 /* Port's MAC speed (in Mbps) and MAC duplex mode 440 * 441 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 442 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 443 * 444 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 445 * or DUPLEX_UNFORCED for normal duplex detection. 446 */ 447 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port, 448 int speed, int duplex); 449 450 /* What interface mode should be used for maximum speed? */ 451 phy_interface_t (*port_max_speed_mode)(int port); 452 453 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 454 455 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port, 456 enum mv88e6xxx_policy_mapping mapping, 457 enum mv88e6xxx_policy_action action); 458 459 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 460 enum mv88e6xxx_frame_mode mode); 461 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port, 462 bool unicast); 463 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port, 464 bool multicast); 465 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 466 u16 etype); 467 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 468 size_t size); 469 470 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 471 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 472 u8 out); 473 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 474 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 475 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port); 476 477 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 478 * Some chips allow this to be configured on specific ports. 479 */ 480 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 481 phy_interface_t mode); 482 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 483 484 /* Some devices have a per port register indicating what is 485 * the upstream port this port should forward to. 486 */ 487 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 488 int upstream_port); 489 490 /* Snapshot the statistics for a port. The statistics can then 491 * be read back a leisure but still with a consistent view. 492 */ 493 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 494 495 /* Set the histogram mode for statistics, when the control registers 496 * are separated out of the STATS_OP register. 497 */ 498 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 499 500 /* Return the number of strings describing statistics */ 501 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 502 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 503 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 504 uint64_t *data); 505 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 506 int (*set_egress_port)(struct mv88e6xxx_chip *chip, 507 enum mv88e6xxx_egress_direction direction, 508 int port); 509 510 #define MV88E6XXX_CASCADE_PORT_NONE 0xe 511 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 512 513 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 514 515 const struct mv88e6xxx_irq_ops *watchdog_ops; 516 517 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 518 519 /* Power on/off a SERDES interface */ 520 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, int lane, 521 bool up); 522 523 /* SERDES lane mapping */ 524 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); 525 526 int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port, 527 int lane, struct phylink_link_state *state); 528 int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port, 529 int lane, unsigned int mode, 530 phy_interface_t interface, 531 const unsigned long *advertise); 532 int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port, 533 int lane); 534 int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port, 535 int lane, int speed, int duplex); 536 537 /* SERDES interrupt handling */ 538 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, 539 int port); 540 int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, int lane, 541 bool enable); 542 irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port, 543 int lane); 544 545 /* Statistics from the SERDES interface */ 546 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 547 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 548 uint8_t *data); 549 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 550 uint64_t *data); 551 552 /* SERDES registers for ethtool */ 553 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port); 554 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port, 555 void *_p); 556 557 /* Address Translation Unit operations */ 558 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash); 559 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash); 560 561 /* VLAN Translation Unit operations */ 562 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 563 struct mv88e6xxx_vtu_entry *entry); 564 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 565 struct mv88e6xxx_vtu_entry *entry); 566 567 /* GPIO operations */ 568 const struct mv88e6xxx_gpio_ops *gpio_ops; 569 570 /* Interface to the AVB/PTP registers */ 571 const struct mv88e6xxx_avb_ops *avb_ops; 572 573 /* Remote Management Unit operations */ 574 int (*rmu_disable)(struct mv88e6xxx_chip *chip); 575 576 /* Precision Time Protocol operations */ 577 const struct mv88e6xxx_ptp_ops *ptp_ops; 578 579 /* Phylink */ 580 void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port, 581 unsigned long *mask, 582 struct phylink_link_state *state); 583 584 /* Max Frame Size */ 585 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu); 586 }; 587 588 struct mv88e6xxx_irq_ops { 589 /* Action to be performed when the interrupt happens */ 590 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 591 /* Setup the hardware to generate the interrupt */ 592 int (*irq_setup)(struct mv88e6xxx_chip *chip); 593 /* Reset the hardware to stop generating the interrupt */ 594 void (*irq_free)(struct mv88e6xxx_chip *chip); 595 }; 596 597 struct mv88e6xxx_gpio_ops { 598 /* Get/set data on GPIO pin */ 599 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 600 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 601 int value); 602 603 /* get/set GPIO direction */ 604 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 605 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 606 bool input); 607 608 /* get/set GPIO pin control */ 609 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 610 int *func); 611 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 612 int func); 613 }; 614 615 struct mv88e6xxx_avb_ops { 616 /* Access port-scoped Precision Time Protocol registers */ 617 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 618 u16 *data, int len); 619 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 620 u16 data); 621 622 /* Access global Precision Time Protocol registers */ 623 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 624 int len); 625 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 626 627 /* Access global Time Application Interface registers */ 628 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 629 int len); 630 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 631 }; 632 633 struct mv88e6xxx_ptp_ops { 634 u64 (*clock_read)(const struct cyclecounter *cc); 635 int (*ptp_enable)(struct ptp_clock_info *ptp, 636 struct ptp_clock_request *rq, int on); 637 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 638 enum ptp_pin_function func, unsigned int chan); 639 void (*event_work)(struct work_struct *ugly); 640 int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 641 int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 642 int (*global_enable)(struct mv88e6xxx_chip *chip); 643 int (*global_disable)(struct mv88e6xxx_chip *chip); 644 int n_ext_ts; 645 int arr0_sts_reg; 646 int arr1_sts_reg; 647 int dep_sts_reg; 648 u32 rx_filters; 649 u32 cc_shift; 650 u32 cc_mult; 651 u32 cc_mult_num; 652 u32 cc_mult_dem; 653 }; 654 655 #define STATS_TYPE_PORT BIT(0) 656 #define STATS_TYPE_BANK0 BIT(1) 657 #define STATS_TYPE_BANK1 BIT(2) 658 659 struct mv88e6xxx_hw_stat { 660 char string[ETH_GSTRING_LEN]; 661 size_t size; 662 int reg; 663 int type; 664 }; 665 666 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 667 { 668 return chip->info->pvt; 669 } 670 671 static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip) 672 { 673 return !!chip->info->global2_addr; 674 } 675 676 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 677 { 678 return chip->info->num_databases; 679 } 680 681 static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip) 682 { 683 return chip->info->num_macs; 684 } 685 686 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 687 { 688 return chip->info->num_ports; 689 } 690 691 static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip) 692 { 693 return chip->info->max_vid; 694 } 695 696 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 697 { 698 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0); 699 } 700 701 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 702 { 703 return chip->info->num_gpio; 704 } 705 706 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port) 707 { 708 return (chip->info->invalid_port_mask & BIT(port)) != 0; 709 } 710 711 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 712 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 713 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 714 u16 mask, u16 val); 715 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 716 int bit, int val); 717 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 718 719 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) 720 { 721 mutex_lock(&chip->reg_lock); 722 } 723 724 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) 725 { 726 mutex_unlock(&chip->reg_lock); 727 } 728 729 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap); 730 731 #endif /* _MV88E6XXX_CHIP_H */ 732