1 /* 2 * Marvell 88E6xxx Ethernet switch single-chip definition 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #ifndef _MV88E6XXX_CHIP_H 13 #define _MV88E6XXX_CHIP_H 14 15 #include <linux/if_vlan.h> 16 #include <linux/irq.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/phy.h> 19 #include <net/dsa.h> 20 21 #ifndef UINT64_MAX 22 #define UINT64_MAX (u64)(~((u64)0)) 23 #endif 24 25 #define SMI_CMD 0x00 26 #define SMI_CMD_BUSY BIT(15) 27 #define SMI_CMD_CLAUSE_22 BIT(12) 28 #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 29 #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 30 #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY) 31 #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY) 32 #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY) 33 #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY) 34 #define SMI_DATA 0x01 35 36 #define MV88E6XXX_N_FID 4096 37 38 /* PVT limits for 4-bit port and 5-bit switch */ 39 #define MV88E6XXX_MAX_PVT_SWITCHES 32 40 #define MV88E6XXX_MAX_PVT_PORTS 16 41 42 enum mv88e6xxx_egress_mode { 43 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 44 MV88E6XXX_EGRESS_MODE_UNTAGGED, 45 MV88E6XXX_EGRESS_MODE_TAGGED, 46 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 47 }; 48 49 enum mv88e6xxx_frame_mode { 50 MV88E6XXX_FRAME_MODE_NORMAL, 51 MV88E6XXX_FRAME_MODE_DSA, 52 MV88E6XXX_FRAME_MODE_PROVIDER, 53 MV88E6XXX_FRAME_MODE_ETHERTYPE, 54 }; 55 56 /* List of supported models */ 57 enum mv88e6xxx_model { 58 MV88E6085, 59 MV88E6095, 60 MV88E6097, 61 MV88E6123, 62 MV88E6131, 63 MV88E6141, 64 MV88E6161, 65 MV88E6165, 66 MV88E6171, 67 MV88E6172, 68 MV88E6175, 69 MV88E6176, 70 MV88E6185, 71 MV88E6190, 72 MV88E6190X, 73 MV88E6191, 74 MV88E6240, 75 MV88E6290, 76 MV88E6320, 77 MV88E6321, 78 MV88E6341, 79 MV88E6350, 80 MV88E6351, 81 MV88E6352, 82 MV88E6390, 83 MV88E6390X, 84 }; 85 86 enum mv88e6xxx_family { 87 MV88E6XXX_FAMILY_NONE, 88 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 89 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 90 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 91 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 92 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 93 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 94 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 95 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 96 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 97 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 98 }; 99 100 struct mv88e6xxx_ops; 101 102 struct mv88e6xxx_info { 103 enum mv88e6xxx_family family; 104 u16 prod_num; 105 const char *name; 106 unsigned int num_databases; 107 unsigned int num_ports; 108 unsigned int max_vid; 109 unsigned int port_base_addr; 110 unsigned int global1_addr; 111 unsigned int global2_addr; 112 unsigned int age_time_coeff; 113 unsigned int g1_irqs; 114 unsigned int g2_irqs; 115 bool pvt; 116 117 /* Multi-chip Addressing Mode. 118 * Some chips respond to only 2 registers of its own SMI device address 119 * when it is non-zero, and use indirect access to internal registers. 120 */ 121 bool multi_chip; 122 enum dsa_tag_protocol tag_protocol; 123 124 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 125 * operation. 0 means that the ATU Move operation is not supported. 126 */ 127 u8 atu_move_port_mask; 128 const struct mv88e6xxx_ops *ops; 129 }; 130 131 struct mv88e6xxx_atu_entry { 132 u8 state; 133 bool trunk; 134 u16 portvec; 135 u8 mac[ETH_ALEN]; 136 }; 137 138 struct mv88e6xxx_vtu_entry { 139 u16 vid; 140 u16 fid; 141 u8 sid; 142 bool valid; 143 u8 member[DSA_MAX_PORTS]; 144 u8 state[DSA_MAX_PORTS]; 145 }; 146 147 struct mv88e6xxx_bus_ops; 148 struct mv88e6xxx_irq_ops; 149 150 struct mv88e6xxx_irq { 151 u16 masked; 152 struct irq_chip chip; 153 struct irq_domain *domain; 154 unsigned int nirqs; 155 }; 156 157 struct mv88e6xxx_chip { 158 const struct mv88e6xxx_info *info; 159 160 /* The dsa_switch this private structure is related to */ 161 struct dsa_switch *ds; 162 163 /* The device this structure is associated to */ 164 struct device *dev; 165 166 /* This mutex protects the access to the switch registers */ 167 struct mutex reg_lock; 168 169 /* The MII bus and the address on the bus that is used to 170 * communication with the switch 171 */ 172 const struct mv88e6xxx_bus_ops *smi_ops; 173 struct mii_bus *bus; 174 int sw_addr; 175 176 /* Handles automatic disabling and re-enabling of the PHY 177 * polling unit. 178 */ 179 const struct mv88e6xxx_bus_ops *phy_ops; 180 struct mutex ppu_mutex; 181 int ppu_disabled; 182 struct work_struct ppu_work; 183 struct timer_list ppu_timer; 184 185 /* This mutex serialises access to the statistics unit. 186 * Hold this mutex over snapshot + dump sequences. 187 */ 188 struct mutex stats_mutex; 189 190 /* A switch may have a GPIO line tied to its reset pin. Parse 191 * this from the device tree, and use it before performing 192 * switch soft reset. 193 */ 194 struct gpio_desc *reset; 195 196 /* set to size of eeprom if supported by the switch */ 197 int eeprom_len; 198 199 /* List of mdio busses */ 200 struct list_head mdios; 201 202 /* There can be two interrupt controllers, which are chained 203 * off a GPIO as interrupt source 204 */ 205 struct mv88e6xxx_irq g1_irq; 206 struct mv88e6xxx_irq g2_irq; 207 int irq; 208 int device_irq; 209 int watchdog_irq; 210 int atu_prob_irq; 211 int vtu_prob_irq; 212 }; 213 214 struct mv88e6xxx_bus_ops { 215 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 216 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 217 }; 218 219 struct mv88e6xxx_mdio_bus { 220 struct mii_bus *bus; 221 struct mv88e6xxx_chip *chip; 222 struct list_head list; 223 bool external; 224 }; 225 226 struct mv88e6xxx_ops { 227 /* Ingress Rate Limit unit (IRL) operations */ 228 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 229 230 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 231 struct ethtool_eeprom *eeprom, u8 *data); 232 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 233 struct ethtool_eeprom *eeprom, u8 *data); 234 235 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 236 237 int (*phy_read)(struct mv88e6xxx_chip *chip, 238 struct mii_bus *bus, 239 int addr, int reg, u16 *val); 240 int (*phy_write)(struct mv88e6xxx_chip *chip, 241 struct mii_bus *bus, 242 int addr, int reg, u16 val); 243 244 /* Priority Override Table operations */ 245 int (*pot_clear)(struct mv88e6xxx_chip *chip); 246 247 /* PHY Polling Unit (PPU) operations */ 248 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 249 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 250 251 /* Switch Software Reset */ 252 int (*reset)(struct mv88e6xxx_chip *chip); 253 254 /* RGMII Receive/Transmit Timing Control 255 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 256 */ 257 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 258 phy_interface_t mode); 259 260 #define LINK_FORCED_DOWN 0 261 #define LINK_FORCED_UP 1 262 #define LINK_UNFORCED -2 263 264 /* Port's MAC link state 265 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 266 * or LINK_UNFORCED for normal link detection. 267 */ 268 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 269 270 #define DUPLEX_UNFORCED -2 271 272 /* Port's MAC duplex mode 273 * 274 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 275 * or DUPLEX_UNFORCED for normal duplex detection. 276 */ 277 int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup); 278 279 #define SPEED_MAX INT_MAX 280 #define SPEED_UNFORCED -2 281 282 /* Port's MAC speed (in Mbps) 283 * 284 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 285 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 286 */ 287 int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed); 288 289 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 290 291 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 292 enum mv88e6xxx_frame_mode mode); 293 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port, 294 bool unicast, bool multicast); 295 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 296 u16 etype); 297 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 298 size_t size); 299 300 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 301 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 302 u8 out); 303 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 304 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 305 306 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 307 * Some chips allow this to be configured on specific ports. 308 */ 309 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 310 phy_interface_t mode); 311 312 /* Some devices have a per port register indicating what is 313 * the upstream port this port should forward to. 314 */ 315 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 316 int upstream_port); 317 318 /* Snapshot the statistics for a port. The statistics can then 319 * be read back a leisure but still with a consistent view. 320 */ 321 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 322 323 /* Set the histogram mode for statistics, when the control registers 324 * are separated out of the STATS_OP register. 325 */ 326 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 327 328 /* Return the number of strings describing statistics */ 329 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 330 void (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 331 void (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 332 uint64_t *data); 333 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 334 int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port); 335 const struct mv88e6xxx_irq_ops *watchdog_ops; 336 337 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 338 339 /* Power on/off a SERDES interface */ 340 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on); 341 342 /* VLAN Translation Unit operations */ 343 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 344 struct mv88e6xxx_vtu_entry *entry); 345 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 346 struct mv88e6xxx_vtu_entry *entry); 347 }; 348 349 struct mv88e6xxx_irq_ops { 350 /* Action to be performed when the interrupt happens */ 351 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 352 /* Setup the hardware to generate the interrupt */ 353 int (*irq_setup)(struct mv88e6xxx_chip *chip); 354 /* Reset the hardware to stop generating the interrupt */ 355 void (*irq_free)(struct mv88e6xxx_chip *chip); 356 }; 357 358 #define STATS_TYPE_PORT BIT(0) 359 #define STATS_TYPE_BANK0 BIT(1) 360 #define STATS_TYPE_BANK1 BIT(2) 361 362 struct mv88e6xxx_hw_stat { 363 char string[ETH_GSTRING_LEN]; 364 int sizeof_stat; 365 int reg; 366 int type; 367 }; 368 369 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 370 { 371 return chip->info->pvt; 372 } 373 374 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 375 { 376 return chip->info->num_databases; 377 } 378 379 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 380 { 381 return chip->info->num_ports; 382 } 383 384 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 385 { 386 return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0); 387 } 388 389 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 390 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 391 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, 392 u16 update); 393 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask); 394 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 395 396 #endif /* _MV88E6XXX_CHIP_H */ 397