1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Ethernet switch single-chip definition 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 */ 7 8 #ifndef _MV88E6XXX_CHIP_H 9 #define _MV88E6XXX_CHIP_H 10 11 #include <linux/idr.h> 12 #include <linux/if_vlan.h> 13 #include <linux/irq.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/kthread.h> 16 #include <linux/phy.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/timecounter.h> 19 #include <net/dsa.h> 20 21 #define MV88E6XXX_N_FID 4096 22 23 /* PVT limits for 4-bit port and 5-bit switch */ 24 #define MV88E6XXX_MAX_PVT_SWITCHES 32 25 #define MV88E6XXX_MAX_PVT_PORTS 16 26 27 #define MV88E6XXX_MAX_GPIO 16 28 29 enum mv88e6xxx_egress_mode { 30 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 31 MV88E6XXX_EGRESS_MODE_UNTAGGED, 32 MV88E6XXX_EGRESS_MODE_TAGGED, 33 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 34 }; 35 36 enum mv88e6xxx_egress_direction { 37 MV88E6XXX_EGRESS_DIR_INGRESS, 38 MV88E6XXX_EGRESS_DIR_EGRESS, 39 }; 40 41 enum mv88e6xxx_frame_mode { 42 MV88E6XXX_FRAME_MODE_NORMAL, 43 MV88E6XXX_FRAME_MODE_DSA, 44 MV88E6XXX_FRAME_MODE_PROVIDER, 45 MV88E6XXX_FRAME_MODE_ETHERTYPE, 46 }; 47 48 /* List of supported models */ 49 enum mv88e6xxx_model { 50 MV88E6085, 51 MV88E6095, 52 MV88E6097, 53 MV88E6123, 54 MV88E6131, 55 MV88E6141, 56 MV88E6161, 57 MV88E6165, 58 MV88E6171, 59 MV88E6172, 60 MV88E6175, 61 MV88E6176, 62 MV88E6185, 63 MV88E6190, 64 MV88E6190X, 65 MV88E6191, 66 MV88E6220, 67 MV88E6240, 68 MV88E6250, 69 MV88E6290, 70 MV88E6320, 71 MV88E6321, 72 MV88E6341, 73 MV88E6350, 74 MV88E6351, 75 MV88E6352, 76 MV88E6390, 77 MV88E6390X, 78 }; 79 80 enum mv88e6xxx_family { 81 MV88E6XXX_FAMILY_NONE, 82 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 83 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 84 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 85 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 86 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 87 MV88E6XXX_FAMILY_6250, /* 6220 6250 */ 88 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 89 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 90 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 91 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 92 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 93 }; 94 95 struct mv88e6xxx_ops; 96 97 struct mv88e6xxx_info { 98 enum mv88e6xxx_family family; 99 u16 prod_num; 100 const char *name; 101 unsigned int num_databases; 102 unsigned int num_macs; 103 unsigned int num_ports; 104 unsigned int num_internal_phys; 105 unsigned int num_gpio; 106 unsigned int max_vid; 107 unsigned int port_base_addr; 108 unsigned int phy_base_addr; 109 unsigned int global1_addr; 110 unsigned int global2_addr; 111 unsigned int age_time_coeff; 112 unsigned int g1_irqs; 113 unsigned int g2_irqs; 114 bool pvt; 115 116 /* Mark certain ports as invalid. This is required for example for the 117 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the 118 * ports 2-4 are not routet to pins. 119 */ 120 unsigned int invalid_port_mask; 121 /* Multi-chip Addressing Mode. 122 * Some chips respond to only 2 registers of its own SMI device address 123 * when it is non-zero, and use indirect access to internal registers. 124 */ 125 bool multi_chip; 126 /* Dual-chip Addressing Mode 127 * Some chips respond to only half of the 32 SMI addresses, 128 * allowing two to coexist on the same SMI interface. 129 */ 130 bool dual_chip; 131 132 enum dsa_tag_protocol tag_protocol; 133 134 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 135 * operation. 0 means that the ATU Move operation is not supported. 136 */ 137 u8 atu_move_port_mask; 138 const struct mv88e6xxx_ops *ops; 139 140 /* Supports PTP */ 141 bool ptp_support; 142 }; 143 144 struct mv88e6xxx_atu_entry { 145 u8 state; 146 bool trunk; 147 u16 portvec; 148 u8 mac[ETH_ALEN]; 149 }; 150 151 struct mv88e6xxx_vtu_entry { 152 u16 vid; 153 u16 fid; 154 u8 sid; 155 bool valid; 156 u8 member[DSA_MAX_PORTS]; 157 u8 state[DSA_MAX_PORTS]; 158 }; 159 160 struct mv88e6xxx_bus_ops; 161 struct mv88e6xxx_irq_ops; 162 struct mv88e6xxx_gpio_ops; 163 struct mv88e6xxx_avb_ops; 164 struct mv88e6xxx_ptp_ops; 165 166 struct mv88e6xxx_irq { 167 u16 masked; 168 struct irq_chip chip; 169 struct irq_domain *domain; 170 int nirqs; 171 }; 172 173 /* state flags for mv88e6xxx_port_hwtstamp::state */ 174 enum { 175 MV88E6XXX_HWTSTAMP_ENABLED, 176 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 177 }; 178 179 struct mv88e6xxx_port_hwtstamp { 180 /* Port index */ 181 int port_id; 182 183 /* Timestamping state */ 184 unsigned long state; 185 186 /* Resources for receive timestamping */ 187 struct sk_buff_head rx_queue; 188 struct sk_buff_head rx_queue2; 189 190 /* Resources for transmit timestamping */ 191 unsigned long tx_tstamp_start; 192 struct sk_buff *tx_skb; 193 u16 tx_seq_id; 194 195 /* Current timestamp configuration */ 196 struct hwtstamp_config tstamp_config; 197 }; 198 199 enum mv88e6xxx_policy_mapping { 200 MV88E6XXX_POLICY_MAPPING_DA, 201 MV88E6XXX_POLICY_MAPPING_SA, 202 MV88E6XXX_POLICY_MAPPING_VTU, 203 MV88E6XXX_POLICY_MAPPING_ETYPE, 204 MV88E6XXX_POLICY_MAPPING_PPPOE, 205 MV88E6XXX_POLICY_MAPPING_VBAS, 206 MV88E6XXX_POLICY_MAPPING_OPT82, 207 MV88E6XXX_POLICY_MAPPING_UDP, 208 }; 209 210 enum mv88e6xxx_policy_action { 211 MV88E6XXX_POLICY_ACTION_NORMAL, 212 MV88E6XXX_POLICY_ACTION_MIRROR, 213 MV88E6XXX_POLICY_ACTION_TRAP, 214 MV88E6XXX_POLICY_ACTION_DISCARD, 215 }; 216 217 struct mv88e6xxx_policy { 218 enum mv88e6xxx_policy_mapping mapping; 219 enum mv88e6xxx_policy_action action; 220 struct ethtool_rx_flow_spec fs; 221 u8 addr[ETH_ALEN]; 222 int port; 223 u16 vid; 224 }; 225 226 struct mv88e6xxx_port { 227 struct mv88e6xxx_chip *chip; 228 int port; 229 u64 serdes_stats[2]; 230 u64 atu_member_violation; 231 u64 atu_miss_violation; 232 u64 atu_full_violation; 233 u64 vtu_member_violation; 234 u64 vtu_miss_violation; 235 phy_interface_t interface; 236 u8 cmode; 237 bool mirror_ingress; 238 bool mirror_egress; 239 unsigned int serdes_irq; 240 char serdes_irq_name[64]; 241 struct devlink_region *region; 242 }; 243 244 enum mv88e6xxx_region_id { 245 MV88E6XXX_REGION_GLOBAL1 = 0, 246 MV88E6XXX_REGION_GLOBAL2, 247 MV88E6XXX_REGION_ATU, 248 249 _MV88E6XXX_REGION_MAX, 250 }; 251 252 struct mv88e6xxx_region_priv { 253 enum mv88e6xxx_region_id id; 254 }; 255 256 struct mv88e6xxx_chip { 257 const struct mv88e6xxx_info *info; 258 259 /* The dsa_switch this private structure is related to */ 260 struct dsa_switch *ds; 261 262 /* The device this structure is associated to */ 263 struct device *dev; 264 265 /* This mutex protects the access to the switch registers */ 266 struct mutex reg_lock; 267 268 /* The MII bus and the address on the bus that is used to 269 * communication with the switch 270 */ 271 const struct mv88e6xxx_bus_ops *smi_ops; 272 struct mii_bus *bus; 273 int sw_addr; 274 275 /* Handles automatic disabling and re-enabling of the PHY 276 * polling unit. 277 */ 278 const struct mv88e6xxx_bus_ops *phy_ops; 279 struct mutex ppu_mutex; 280 int ppu_disabled; 281 struct work_struct ppu_work; 282 struct timer_list ppu_timer; 283 284 /* This mutex serialises access to the statistics unit. 285 * Hold this mutex over snapshot + dump sequences. 286 */ 287 struct mutex stats_mutex; 288 289 /* A switch may have a GPIO line tied to its reset pin. Parse 290 * this from the device tree, and use it before performing 291 * switch soft reset. 292 */ 293 struct gpio_desc *reset; 294 295 /* set to size of eeprom if supported by the switch */ 296 u32 eeprom_len; 297 298 /* List of mdio busses */ 299 struct list_head mdios; 300 301 /* Policy Control List IDs and rules */ 302 struct idr policies; 303 304 /* There can be two interrupt controllers, which are chained 305 * off a GPIO as interrupt source 306 */ 307 struct mv88e6xxx_irq g1_irq; 308 struct mv88e6xxx_irq g2_irq; 309 int irq; 310 char irq_name[64]; 311 int device_irq; 312 char device_irq_name[64]; 313 int watchdog_irq; 314 char watchdog_irq_name[64]; 315 316 int atu_prob_irq; 317 char atu_prob_irq_name[64]; 318 int vtu_prob_irq; 319 char vtu_prob_irq_name[64]; 320 struct kthread_worker *kworker; 321 struct kthread_delayed_work irq_poll_work; 322 323 /* GPIO resources */ 324 u8 gpio_data[2]; 325 326 /* This cyclecounter abstracts the switch PTP time. 327 * reg_lock must be held for any operation that read()s. 328 */ 329 struct cyclecounter tstamp_cc; 330 struct timecounter tstamp_tc; 331 struct delayed_work overflow_work; 332 333 struct ptp_clock *ptp_clock; 334 struct ptp_clock_info ptp_clock_info; 335 struct delayed_work tai_event_work; 336 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 337 u16 trig_config; 338 u16 evcap_config; 339 u16 enable_count; 340 341 /* Current ingress and egress monitor ports */ 342 int egress_dest_port; 343 int ingress_dest_port; 344 345 /* Per-port timestamping resources. */ 346 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 347 348 /* Array of port structures. */ 349 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 350 351 /* devlink regions */ 352 struct devlink_region *regions[_MV88E6XXX_REGION_MAX]; 353 }; 354 355 struct mv88e6xxx_bus_ops { 356 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 357 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 358 }; 359 360 struct mv88e6xxx_mdio_bus { 361 struct mii_bus *bus; 362 struct mv88e6xxx_chip *chip; 363 struct list_head list; 364 bool external; 365 }; 366 367 struct mv88e6xxx_ops { 368 /* Switch Setup Errata, called early in the switch setup to 369 * allow any errata actions to be performed 370 */ 371 int (*setup_errata)(struct mv88e6xxx_chip *chip); 372 373 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 374 int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 375 376 /* Ingress Rate Limit unit (IRL) operations */ 377 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 378 379 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 380 struct ethtool_eeprom *eeprom, u8 *data); 381 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 382 struct ethtool_eeprom *eeprom, u8 *data); 383 384 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 385 386 int (*phy_read)(struct mv88e6xxx_chip *chip, 387 struct mii_bus *bus, 388 int addr, int reg, u16 *val); 389 int (*phy_write)(struct mv88e6xxx_chip *chip, 390 struct mii_bus *bus, 391 int addr, int reg, u16 val); 392 393 /* Priority Override Table operations */ 394 int (*pot_clear)(struct mv88e6xxx_chip *chip); 395 396 /* PHY Polling Unit (PPU) operations */ 397 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 398 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 399 400 /* Switch Software Reset */ 401 int (*reset)(struct mv88e6xxx_chip *chip); 402 403 /* RGMII Receive/Transmit Timing Control 404 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 405 */ 406 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 407 phy_interface_t mode); 408 409 #define LINK_FORCED_DOWN 0 410 #define LINK_FORCED_UP 1 411 #define LINK_UNFORCED -2 412 413 /* Port's MAC link state 414 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 415 * or LINK_UNFORCED for normal link detection. 416 */ 417 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 418 419 #define PAUSE_ON 1 420 #define PAUSE_OFF 0 421 422 /* Enable/disable sending Pause */ 423 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 424 int pause); 425 426 #define SPEED_MAX INT_MAX 427 #define SPEED_UNFORCED -2 428 #define DUPLEX_UNFORCED -2 429 430 /* Port's MAC speed (in Mbps) and MAC duplex mode 431 * 432 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 433 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 434 * 435 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 436 * or DUPLEX_UNFORCED for normal duplex detection. 437 */ 438 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port, 439 int speed, int duplex); 440 441 /* What interface mode should be used for maximum speed? */ 442 phy_interface_t (*port_max_speed_mode)(int port); 443 444 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 445 446 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port, 447 enum mv88e6xxx_policy_mapping mapping, 448 enum mv88e6xxx_policy_action action); 449 450 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 451 enum mv88e6xxx_frame_mode mode); 452 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port, 453 bool unicast, bool multicast); 454 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 455 u16 etype); 456 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 457 size_t size); 458 459 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 460 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 461 u8 out); 462 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 463 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 464 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port); 465 466 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 467 * Some chips allow this to be configured on specific ports. 468 */ 469 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 470 phy_interface_t mode); 471 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 472 473 /* Some devices have a per port register indicating what is 474 * the upstream port this port should forward to. 475 */ 476 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 477 int upstream_port); 478 479 /* Snapshot the statistics for a port. The statistics can then 480 * be read back a leisure but still with a consistent view. 481 */ 482 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 483 484 /* Set the histogram mode for statistics, when the control registers 485 * are separated out of the STATS_OP register. 486 */ 487 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 488 489 /* Return the number of strings describing statistics */ 490 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 491 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 492 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 493 uint64_t *data); 494 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 495 int (*set_egress_port)(struct mv88e6xxx_chip *chip, 496 enum mv88e6xxx_egress_direction direction, 497 int port); 498 499 #define MV88E6XXX_CASCADE_PORT_NONE 0xe 500 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 501 502 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 503 504 const struct mv88e6xxx_irq_ops *watchdog_ops; 505 506 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 507 508 /* Power on/off a SERDES interface */ 509 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane, 510 bool up); 511 512 /* SERDES lane mapping */ 513 u8 (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); 514 515 int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port, 516 u8 lane, struct phylink_link_state *state); 517 int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port, 518 u8 lane, unsigned int mode, 519 phy_interface_t interface, 520 const unsigned long *advertise); 521 int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port, 522 u8 lane); 523 int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port, 524 u8 lane, int speed, int duplex); 525 526 /* SERDES interrupt handling */ 527 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, 528 int port); 529 int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane, 530 bool enable); 531 irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port, 532 u8 lane); 533 534 /* Statistics from the SERDES interface */ 535 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 536 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 537 uint8_t *data); 538 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 539 uint64_t *data); 540 541 /* SERDES registers for ethtool */ 542 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port); 543 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port, 544 void *_p); 545 546 /* Address Translation Unit operations */ 547 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash); 548 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash); 549 550 /* VLAN Translation Unit operations */ 551 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 552 struct mv88e6xxx_vtu_entry *entry); 553 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 554 struct mv88e6xxx_vtu_entry *entry); 555 556 /* GPIO operations */ 557 const struct mv88e6xxx_gpio_ops *gpio_ops; 558 559 /* Interface to the AVB/PTP registers */ 560 const struct mv88e6xxx_avb_ops *avb_ops; 561 562 /* Remote Management Unit operations */ 563 int (*rmu_disable)(struct mv88e6xxx_chip *chip); 564 565 /* Precision Time Protocol operations */ 566 const struct mv88e6xxx_ptp_ops *ptp_ops; 567 568 /* Phylink */ 569 void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port, 570 unsigned long *mask, 571 struct phylink_link_state *state); 572 573 /* Max Frame Size */ 574 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu); 575 }; 576 577 struct mv88e6xxx_irq_ops { 578 /* Action to be performed when the interrupt happens */ 579 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 580 /* Setup the hardware to generate the interrupt */ 581 int (*irq_setup)(struct mv88e6xxx_chip *chip); 582 /* Reset the hardware to stop generating the interrupt */ 583 void (*irq_free)(struct mv88e6xxx_chip *chip); 584 }; 585 586 struct mv88e6xxx_gpio_ops { 587 /* Get/set data on GPIO pin */ 588 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 589 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 590 int value); 591 592 /* get/set GPIO direction */ 593 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 594 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 595 bool input); 596 597 /* get/set GPIO pin control */ 598 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 599 int *func); 600 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 601 int func); 602 }; 603 604 struct mv88e6xxx_avb_ops { 605 /* Access port-scoped Precision Time Protocol registers */ 606 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 607 u16 *data, int len); 608 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 609 u16 data); 610 611 /* Access global Precision Time Protocol registers */ 612 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 613 int len); 614 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 615 616 /* Access global Time Application Interface registers */ 617 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 618 int len); 619 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 620 }; 621 622 struct mv88e6xxx_ptp_ops { 623 u64 (*clock_read)(const struct cyclecounter *cc); 624 int (*ptp_enable)(struct ptp_clock_info *ptp, 625 struct ptp_clock_request *rq, int on); 626 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 627 enum ptp_pin_function func, unsigned int chan); 628 void (*event_work)(struct work_struct *ugly); 629 int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 630 int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 631 int (*global_enable)(struct mv88e6xxx_chip *chip); 632 int (*global_disable)(struct mv88e6xxx_chip *chip); 633 int n_ext_ts; 634 int arr0_sts_reg; 635 int arr1_sts_reg; 636 int dep_sts_reg; 637 u32 rx_filters; 638 u32 cc_shift; 639 u32 cc_mult; 640 u32 cc_mult_num; 641 u32 cc_mult_dem; 642 }; 643 644 #define STATS_TYPE_PORT BIT(0) 645 #define STATS_TYPE_BANK0 BIT(1) 646 #define STATS_TYPE_BANK1 BIT(2) 647 648 struct mv88e6xxx_hw_stat { 649 char string[ETH_GSTRING_LEN]; 650 size_t size; 651 int reg; 652 int type; 653 }; 654 655 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 656 { 657 return chip->info->pvt; 658 } 659 660 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 661 { 662 return chip->info->num_databases; 663 } 664 665 static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip) 666 { 667 return chip->info->num_macs; 668 } 669 670 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 671 { 672 return chip->info->num_ports; 673 } 674 675 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 676 { 677 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0); 678 } 679 680 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 681 { 682 return chip->info->num_gpio; 683 } 684 685 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port) 686 { 687 return (chip->info->invalid_port_mask & BIT(port)) != 0; 688 } 689 690 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 691 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 692 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 693 u16 mask, u16 val); 694 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 695 int bit, int val); 696 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 697 698 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) 699 { 700 mutex_lock(&chip->reg_lock); 701 } 702 703 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) 704 { 705 mutex_unlock(&chip->reg_lock); 706 } 707 708 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap); 709 710 #endif /* _MV88E6XXX_CHIP_H */ 711