xref: /openbmc/linux/drivers/net/dsa/mv88e6xxx/chip.h (revision 7f877908)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Marvell 88E6xxx Ethernet switch single-chip definition
4  *
5  * Copyright (c) 2008 Marvell Semiconductor
6  */
7 
8 #ifndef _MV88E6XXX_CHIP_H
9 #define _MV88E6XXX_CHIP_H
10 
11 #include <linux/idr.h>
12 #include <linux/if_vlan.h>
13 #include <linux/irq.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/kthread.h>
16 #include <linux/phy.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/timecounter.h>
19 #include <net/dsa.h>
20 
21 #define MV88E6XXX_N_FID		4096
22 
23 /* PVT limits for 4-bit port and 5-bit switch */
24 #define MV88E6XXX_MAX_PVT_SWITCHES	32
25 #define MV88E6XXX_MAX_PVT_PORTS		16
26 
27 #define MV88E6XXX_MAX_GPIO	16
28 
29 enum mv88e6xxx_egress_mode {
30 	MV88E6XXX_EGRESS_MODE_UNMODIFIED,
31 	MV88E6XXX_EGRESS_MODE_UNTAGGED,
32 	MV88E6XXX_EGRESS_MODE_TAGGED,
33 	MV88E6XXX_EGRESS_MODE_ETHERTYPE,
34 };
35 
36 enum mv88e6xxx_egress_direction {
37         MV88E6XXX_EGRESS_DIR_INGRESS,
38         MV88E6XXX_EGRESS_DIR_EGRESS,
39 };
40 
41 enum mv88e6xxx_frame_mode {
42 	MV88E6XXX_FRAME_MODE_NORMAL,
43 	MV88E6XXX_FRAME_MODE_DSA,
44 	MV88E6XXX_FRAME_MODE_PROVIDER,
45 	MV88E6XXX_FRAME_MODE_ETHERTYPE,
46 };
47 
48 /* List of supported models */
49 enum mv88e6xxx_model {
50 	MV88E6085,
51 	MV88E6095,
52 	MV88E6097,
53 	MV88E6123,
54 	MV88E6131,
55 	MV88E6141,
56 	MV88E6161,
57 	MV88E6165,
58 	MV88E6171,
59 	MV88E6172,
60 	MV88E6175,
61 	MV88E6176,
62 	MV88E6185,
63 	MV88E6190,
64 	MV88E6190X,
65 	MV88E6191,
66 	MV88E6220,
67 	MV88E6240,
68 	MV88E6250,
69 	MV88E6290,
70 	MV88E6320,
71 	MV88E6321,
72 	MV88E6341,
73 	MV88E6350,
74 	MV88E6351,
75 	MV88E6352,
76 	MV88E6390,
77 	MV88E6390X,
78 };
79 
80 enum mv88e6xxx_family {
81 	MV88E6XXX_FAMILY_NONE,
82 	MV88E6XXX_FAMILY_6065,	/* 6031 6035 6061 6065 */
83 	MV88E6XXX_FAMILY_6095,	/* 6092 6095 */
84 	MV88E6XXX_FAMILY_6097,	/* 6046 6085 6096 6097 */
85 	MV88E6XXX_FAMILY_6165,	/* 6123 6161 6165 */
86 	MV88E6XXX_FAMILY_6185,	/* 6108 6121 6122 6131 6152 6155 6182 6185 */
87 	MV88E6XXX_FAMILY_6250,	/* 6220 6250 */
88 	MV88E6XXX_FAMILY_6320,	/* 6320 6321 */
89 	MV88E6XXX_FAMILY_6341,	/* 6141 6341 */
90 	MV88E6XXX_FAMILY_6351,	/* 6171 6175 6350 6351 */
91 	MV88E6XXX_FAMILY_6352,	/* 6172 6176 6240 6352 */
92 	MV88E6XXX_FAMILY_6390,  /* 6190 6190X 6191 6290 6390 6390X */
93 };
94 
95 struct mv88e6xxx_ops;
96 
97 struct mv88e6xxx_info {
98 	enum mv88e6xxx_family family;
99 	u16 prod_num;
100 	const char *name;
101 	unsigned int num_databases;
102 	unsigned int num_macs;
103 	unsigned int num_ports;
104 	unsigned int num_internal_phys;
105 	unsigned int num_gpio;
106 	unsigned int max_vid;
107 	unsigned int port_base_addr;
108 	unsigned int phy_base_addr;
109 	unsigned int global1_addr;
110 	unsigned int global2_addr;
111 	unsigned int age_time_coeff;
112 	unsigned int g1_irqs;
113 	unsigned int g2_irqs;
114 	bool pvt;
115 
116 	/* Mark certain ports as invalid. This is required for example for the
117 	 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
118 	 * ports 2-4 are not routet to pins.
119 	 */
120 	unsigned int invalid_port_mask;
121 	/* Multi-chip Addressing Mode.
122 	 * Some chips respond to only 2 registers of its own SMI device address
123 	 * when it is non-zero, and use indirect access to internal registers.
124 	 */
125 	bool multi_chip;
126 	/* Dual-chip Addressing Mode
127 	 * Some chips respond to only half of the 32 SMI addresses,
128 	 * allowing two to coexist on the same SMI interface.
129 	 */
130 	bool dual_chip;
131 
132 	enum dsa_tag_protocol tag_protocol;
133 
134 	/* Mask for FromPort and ToPort value of PortVec used in ATU Move
135 	 * operation. 0 means that the ATU Move operation is not supported.
136 	 */
137 	u8 atu_move_port_mask;
138 	const struct mv88e6xxx_ops *ops;
139 
140 	/* Supports PTP */
141 	bool ptp_support;
142 };
143 
144 struct mv88e6xxx_atu_entry {
145 	u8	state;
146 	bool	trunk;
147 	u16	portvec;
148 	u8	mac[ETH_ALEN];
149 };
150 
151 struct mv88e6xxx_vtu_entry {
152 	u16	vid;
153 	u16	fid;
154 	u8	sid;
155 	bool	valid;
156 	u8	member[DSA_MAX_PORTS];
157 	u8	state[DSA_MAX_PORTS];
158 };
159 
160 struct mv88e6xxx_bus_ops;
161 struct mv88e6xxx_irq_ops;
162 struct mv88e6xxx_gpio_ops;
163 struct mv88e6xxx_avb_ops;
164 struct mv88e6xxx_ptp_ops;
165 
166 struct mv88e6xxx_irq {
167 	u16 masked;
168 	struct irq_chip chip;
169 	struct irq_domain *domain;
170 	unsigned int nirqs;
171 };
172 
173 /* state flags for mv88e6xxx_port_hwtstamp::state */
174 enum {
175 	MV88E6XXX_HWTSTAMP_ENABLED,
176 	MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
177 };
178 
179 struct mv88e6xxx_port_hwtstamp {
180 	/* Port index */
181 	int port_id;
182 
183 	/* Timestamping state */
184 	unsigned long state;
185 
186 	/* Resources for receive timestamping */
187 	struct sk_buff_head rx_queue;
188 	struct sk_buff_head rx_queue2;
189 
190 	/* Resources for transmit timestamping */
191 	unsigned long tx_tstamp_start;
192 	struct sk_buff *tx_skb;
193 	u16 tx_seq_id;
194 
195 	/* Current timestamp configuration */
196 	struct hwtstamp_config tstamp_config;
197 };
198 
199 enum mv88e6xxx_policy_mapping {
200 	MV88E6XXX_POLICY_MAPPING_DA,
201 	MV88E6XXX_POLICY_MAPPING_SA,
202 	MV88E6XXX_POLICY_MAPPING_VTU,
203 	MV88E6XXX_POLICY_MAPPING_ETYPE,
204 	MV88E6XXX_POLICY_MAPPING_PPPOE,
205 	MV88E6XXX_POLICY_MAPPING_VBAS,
206 	MV88E6XXX_POLICY_MAPPING_OPT82,
207 	MV88E6XXX_POLICY_MAPPING_UDP,
208 };
209 
210 enum mv88e6xxx_policy_action {
211 	MV88E6XXX_POLICY_ACTION_NORMAL,
212 	MV88E6XXX_POLICY_ACTION_MIRROR,
213 	MV88E6XXX_POLICY_ACTION_TRAP,
214 	MV88E6XXX_POLICY_ACTION_DISCARD,
215 };
216 
217 struct mv88e6xxx_policy {
218 	enum mv88e6xxx_policy_mapping mapping;
219 	enum mv88e6xxx_policy_action action;
220 	struct ethtool_rx_flow_spec fs;
221 	u8 addr[ETH_ALEN];
222 	int port;
223 	u16 vid;
224 };
225 
226 struct mv88e6xxx_port {
227 	struct mv88e6xxx_chip *chip;
228 	int port;
229 	u64 serdes_stats[2];
230 	u64 atu_member_violation;
231 	u64 atu_miss_violation;
232 	u64 atu_full_violation;
233 	u64 vtu_member_violation;
234 	u64 vtu_miss_violation;
235 	u8 cmode;
236 	bool mirror_ingress;
237 	bool mirror_egress;
238 	unsigned int serdes_irq;
239 	char serdes_irq_name[32];
240 };
241 
242 struct mv88e6xxx_chip {
243 	const struct mv88e6xxx_info *info;
244 
245 	/* The dsa_switch this private structure is related to */
246 	struct dsa_switch *ds;
247 
248 	/* The device this structure is associated to */
249 	struct device *dev;
250 
251 	/* This mutex protects the access to the switch registers */
252 	struct mutex reg_lock;
253 
254 	/* The MII bus and the address on the bus that is used to
255 	 * communication with the switch
256 	 */
257 	const struct mv88e6xxx_bus_ops *smi_ops;
258 	struct mii_bus *bus;
259 	int sw_addr;
260 
261 	/* Handles automatic disabling and re-enabling of the PHY
262 	 * polling unit.
263 	 */
264 	const struct mv88e6xxx_bus_ops *phy_ops;
265 	struct mutex		ppu_mutex;
266 	int			ppu_disabled;
267 	struct work_struct	ppu_work;
268 	struct timer_list	ppu_timer;
269 
270 	/* This mutex serialises access to the statistics unit.
271 	 * Hold this mutex over snapshot + dump sequences.
272 	 */
273 	struct mutex	stats_mutex;
274 
275 	/* A switch may have a GPIO line tied to its reset pin. Parse
276 	 * this from the device tree, and use it before performing
277 	 * switch soft reset.
278 	 */
279 	struct gpio_desc *reset;
280 
281 	/* set to size of eeprom if supported by the switch */
282 	u32 eeprom_len;
283 
284 	/* List of mdio busses */
285 	struct list_head mdios;
286 
287 	/* Policy Control List IDs and rules */
288 	struct idr policies;
289 
290 	/* There can be two interrupt controllers, which are chained
291 	 * off a GPIO as interrupt source
292 	 */
293 	struct mv88e6xxx_irq g1_irq;
294 	struct mv88e6xxx_irq g2_irq;
295 	int irq;
296 	char irq_name[32];
297 	int device_irq;
298 	char device_irq_name[32];
299 	int watchdog_irq;
300 	char watchdog_irq_name[32];
301 
302 	int atu_prob_irq;
303 	char atu_prob_irq_name[32];
304 	int vtu_prob_irq;
305 	char vtu_prob_irq_name[32];
306 	struct kthread_worker *kworker;
307 	struct kthread_delayed_work irq_poll_work;
308 
309 	/* GPIO resources */
310 	u8 gpio_data[2];
311 
312 	/* This cyclecounter abstracts the switch PTP time.
313 	 * reg_lock must be held for any operation that read()s.
314 	 */
315 	struct cyclecounter	tstamp_cc;
316 	struct timecounter	tstamp_tc;
317 	struct delayed_work	overflow_work;
318 
319 	struct ptp_clock	*ptp_clock;
320 	struct ptp_clock_info	ptp_clock_info;
321 	struct delayed_work	tai_event_work;
322 	struct ptp_pin_desc	pin_config[MV88E6XXX_MAX_GPIO];
323 	u16 trig_config;
324 	u16 evcap_config;
325 	u16 enable_count;
326 
327 	/* Current ingress and egress monitor ports */
328 	int egress_dest_port;
329 	int ingress_dest_port;
330 
331 	/* Per-port timestamping resources. */
332 	struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
333 
334 	/* Array of port structures. */
335 	struct mv88e6xxx_port ports[DSA_MAX_PORTS];
336 };
337 
338 struct mv88e6xxx_bus_ops {
339 	int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
340 	int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
341 };
342 
343 struct mv88e6xxx_mdio_bus {
344 	struct mii_bus *bus;
345 	struct mv88e6xxx_chip *chip;
346 	struct list_head list;
347 	bool external;
348 };
349 
350 struct mv88e6xxx_ops {
351 	/* Switch Setup Errata, called early in the switch setup to
352 	 * allow any errata actions to be performed
353 	 */
354 	int (*setup_errata)(struct mv88e6xxx_chip *chip);
355 
356 	int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
357 	int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
358 
359 	/* Ingress Rate Limit unit (IRL) operations */
360 	int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
361 
362 	int (*get_eeprom)(struct mv88e6xxx_chip *chip,
363 			  struct ethtool_eeprom *eeprom, u8 *data);
364 	int (*set_eeprom)(struct mv88e6xxx_chip *chip,
365 			  struct ethtool_eeprom *eeprom, u8 *data);
366 
367 	int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
368 
369 	int (*phy_read)(struct mv88e6xxx_chip *chip,
370 			struct mii_bus *bus,
371 			int addr, int reg, u16 *val);
372 	int (*phy_write)(struct mv88e6xxx_chip *chip,
373 			 struct mii_bus *bus,
374 			 int addr, int reg, u16 val);
375 
376 	/* Priority Override Table operations */
377 	int (*pot_clear)(struct mv88e6xxx_chip *chip);
378 
379 	/* PHY Polling Unit (PPU) operations */
380 	int (*ppu_enable)(struct mv88e6xxx_chip *chip);
381 	int (*ppu_disable)(struct mv88e6xxx_chip *chip);
382 
383 	/* Switch Software Reset */
384 	int (*reset)(struct mv88e6xxx_chip *chip);
385 
386 	/* RGMII Receive/Transmit Timing Control
387 	 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
388 	 */
389 	int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
390 				    phy_interface_t mode);
391 
392 #define LINK_FORCED_DOWN	0
393 #define LINK_FORCED_UP		1
394 #define LINK_UNFORCED		-2
395 
396 	/* Port's MAC link state
397 	 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
398 	 * or LINK_UNFORCED for normal link detection.
399 	 */
400 	int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
401 
402 #define DUPLEX_UNFORCED		-2
403 
404 	/* Port's MAC duplex mode
405 	 *
406 	 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
407 	 * or DUPLEX_UNFORCED for normal duplex detection.
408 	 */
409 	int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup);
410 
411 #define PAUSE_ON		1
412 #define PAUSE_OFF		0
413 
414 	/* Enable/disable sending Pause */
415 	int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
416 			      int pause);
417 
418 #define SPEED_MAX		INT_MAX
419 #define SPEED_UNFORCED		-2
420 
421 	/* Port's MAC speed (in Mbps)
422 	 *
423 	 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
424 	 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
425 	 */
426 	int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed);
427 
428 	/* What interface mode should be used for maximum speed? */
429 	phy_interface_t (*port_max_speed_mode)(int port);
430 
431 	int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
432 
433 	int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
434 			       enum mv88e6xxx_policy_mapping mapping,
435 			       enum mv88e6xxx_policy_action action);
436 
437 	int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
438 				   enum mv88e6xxx_frame_mode mode);
439 	int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,
440 				      bool unicast, bool multicast);
441 	int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
442 				   u16 etype);
443 	int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
444 				   size_t size);
445 
446 	int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
447 	int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
448 				u8 out);
449 	int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
450 	int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
451 	int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
452 
453 	/* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
454 	 * Some chips allow this to be configured on specific ports.
455 	 */
456 	int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
457 			      phy_interface_t mode);
458 	int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
459 
460 	/* Some devices have a per port register indicating what is
461 	 * the upstream port this port should forward to.
462 	 */
463 	int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
464 				      int upstream_port);
465 	/* Return the port link state, as required by phylink */
466 	int (*port_link_state)(struct mv88e6xxx_chip *chip, int port,
467 			       struct phylink_link_state *state);
468 
469 	/* Snapshot the statistics for a port. The statistics can then
470 	 * be read back a leisure but still with a consistent view.
471 	 */
472 	int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
473 
474 	/* Set the histogram mode for statistics, when the control registers
475 	 * are separated out of the STATS_OP register.
476 	 */
477 	int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
478 
479 	/* Return the number of strings describing statistics */
480 	int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
481 	int (*stats_get_strings)(struct mv88e6xxx_chip *chip,  uint8_t *data);
482 	int (*stats_get_stats)(struct mv88e6xxx_chip *chip,  int port,
483 			       uint64_t *data);
484 	int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
485 	int (*set_egress_port)(struct mv88e6xxx_chip *chip,
486 			       enum mv88e6xxx_egress_direction direction,
487 			       int port);
488 
489 #define MV88E6XXX_CASCADE_PORT_NONE		0xe
490 #define MV88E6XXX_CASCADE_PORT_MULTIPLE		0xf
491 
492 	int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
493 
494 	const struct mv88e6xxx_irq_ops *watchdog_ops;
495 
496 	int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
497 
498 	/* Power on/off a SERDES interface */
499 	int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane,
500 			    bool up);
501 
502 	/* SERDES lane mapping */
503 	u8 (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
504 
505 	/* SERDES interrupt handling */
506 	unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
507 					   int port);
508 	int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane,
509 				 bool enable);
510 	irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port,
511 					 u8 lane);
512 
513 	/* Statistics from the SERDES interface */
514 	int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
515 	int (*serdes_get_strings)(struct mv88e6xxx_chip *chip,  int port,
516 				  uint8_t *data);
517 	int (*serdes_get_stats)(struct mv88e6xxx_chip *chip,  int port,
518 				uint64_t *data);
519 
520 	/* Address Translation Unit operations */
521 	int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash);
522 	int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash);
523 
524 	/* VLAN Translation Unit operations */
525 	int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
526 			   struct mv88e6xxx_vtu_entry *entry);
527 	int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
528 			     struct mv88e6xxx_vtu_entry *entry);
529 
530 	/* GPIO operations */
531 	const struct mv88e6xxx_gpio_ops *gpio_ops;
532 
533 	/* Interface to the AVB/PTP registers */
534 	const struct mv88e6xxx_avb_ops *avb_ops;
535 
536 	/* Remote Management Unit operations */
537 	int (*rmu_disable)(struct mv88e6xxx_chip *chip);
538 
539 	/* Precision Time Protocol operations */
540 	const struct mv88e6xxx_ptp_ops *ptp_ops;
541 
542 	/* Phylink */
543 	void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
544 				 unsigned long *mask,
545 				 struct phylink_link_state *state);
546 };
547 
548 struct mv88e6xxx_irq_ops {
549 	/* Action to be performed when the interrupt happens */
550 	int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
551 	/* Setup the hardware to generate the interrupt */
552 	int (*irq_setup)(struct mv88e6xxx_chip *chip);
553 	/* Reset the hardware to stop generating the interrupt */
554 	void (*irq_free)(struct mv88e6xxx_chip *chip);
555 };
556 
557 struct mv88e6xxx_gpio_ops {
558 	/* Get/set data on GPIO pin */
559 	int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
560 	int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
561 			int value);
562 
563 	/* get/set GPIO direction */
564 	int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
565 	int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
566 		       bool input);
567 
568 	/* get/set GPIO pin control */
569 	int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
570 			int *func);
571 	int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
572 			int func);
573 };
574 
575 struct mv88e6xxx_avb_ops {
576 	/* Access port-scoped Precision Time Protocol registers */
577 	int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
578 			     u16 *data, int len);
579 	int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
580 			      u16 data);
581 
582 	/* Access global Precision Time Protocol registers */
583 	int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
584 			int len);
585 	int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
586 
587 	/* Access global Time Application Interface registers */
588 	int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
589 			int len);
590 	int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
591 };
592 
593 struct mv88e6xxx_ptp_ops {
594 	u64 (*clock_read)(const struct cyclecounter *cc);
595 	int (*ptp_enable)(struct ptp_clock_info *ptp,
596 			  struct ptp_clock_request *rq, int on);
597 	int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
598 			  enum ptp_pin_function func, unsigned int chan);
599 	void (*event_work)(struct work_struct *ugly);
600 	int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
601 	int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
602 	int (*global_enable)(struct mv88e6xxx_chip *chip);
603 	int (*global_disable)(struct mv88e6xxx_chip *chip);
604 	int n_ext_ts;
605 	int arr0_sts_reg;
606 	int arr1_sts_reg;
607 	int dep_sts_reg;
608 	u32 rx_filters;
609 	u32 cc_shift;
610 	u32 cc_mult;
611 	u32 cc_mult_num;
612 	u32 cc_mult_dem;
613 };
614 
615 #define STATS_TYPE_PORT		BIT(0)
616 #define STATS_TYPE_BANK0	BIT(1)
617 #define STATS_TYPE_BANK1	BIT(2)
618 
619 struct mv88e6xxx_hw_stat {
620 	char string[ETH_GSTRING_LEN];
621 	size_t size;
622 	int reg;
623 	int type;
624 };
625 
626 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
627 {
628 	return chip->info->pvt;
629 }
630 
631 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
632 {
633 	return chip->info->num_databases;
634 }
635 
636 static inline unsigned int mv88e6xxx_num_macs(struct  mv88e6xxx_chip *chip)
637 {
638 	return chip->info->num_macs;
639 }
640 
641 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
642 {
643 	return chip->info->num_ports;
644 }
645 
646 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
647 {
648 	return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
649 }
650 
651 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
652 {
653 	return chip->info->num_gpio;
654 }
655 
656 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
657 {
658 	return (chip->info->invalid_port_mask & BIT(port)) != 0;
659 }
660 
661 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
662 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
663 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
664 			u16 mask, u16 val);
665 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
666 		       int bit, int val);
667 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
668 			     int speed, int duplex, int pause,
669 			     phy_interface_t mode);
670 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
671 
672 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
673 {
674 	mutex_lock(&chip->reg_lock);
675 }
676 
677 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
678 {
679 	mutex_unlock(&chip->reg_lock);
680 }
681 
682 #endif /* _MV88E6XXX_CHIP_H */
683