1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Ethernet switch single-chip definition 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 */ 7 8 #ifndef _MV88E6XXX_CHIP_H 9 #define _MV88E6XXX_CHIP_H 10 11 #include <linux/if_vlan.h> 12 #include <linux/irq.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/kthread.h> 15 #include <linux/phy.h> 16 #include <linux/ptp_clock_kernel.h> 17 #include <linux/timecounter.h> 18 #include <net/dsa.h> 19 20 #define MV88E6XXX_N_FID 4096 21 22 /* PVT limits for 4-bit port and 5-bit switch */ 23 #define MV88E6XXX_MAX_PVT_SWITCHES 32 24 #define MV88E6XXX_MAX_PVT_PORTS 16 25 26 #define MV88E6XXX_MAX_GPIO 16 27 28 enum mv88e6xxx_egress_mode { 29 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 30 MV88E6XXX_EGRESS_MODE_UNTAGGED, 31 MV88E6XXX_EGRESS_MODE_TAGGED, 32 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 33 }; 34 35 enum mv88e6xxx_frame_mode { 36 MV88E6XXX_FRAME_MODE_NORMAL, 37 MV88E6XXX_FRAME_MODE_DSA, 38 MV88E6XXX_FRAME_MODE_PROVIDER, 39 MV88E6XXX_FRAME_MODE_ETHERTYPE, 40 }; 41 42 /* List of supported models */ 43 enum mv88e6xxx_model { 44 MV88E6085, 45 MV88E6095, 46 MV88E6097, 47 MV88E6123, 48 MV88E6131, 49 MV88E6141, 50 MV88E6161, 51 MV88E6165, 52 MV88E6171, 53 MV88E6172, 54 MV88E6175, 55 MV88E6176, 56 MV88E6185, 57 MV88E6190, 58 MV88E6190X, 59 MV88E6191, 60 MV88E6220, 61 MV88E6240, 62 MV88E6250, 63 MV88E6290, 64 MV88E6320, 65 MV88E6321, 66 MV88E6341, 67 MV88E6350, 68 MV88E6351, 69 MV88E6352, 70 MV88E6390, 71 MV88E6390X, 72 }; 73 74 enum mv88e6xxx_family { 75 MV88E6XXX_FAMILY_NONE, 76 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 77 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 78 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 79 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 80 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 81 MV88E6XXX_FAMILY_6250, /* 6220 6250 */ 82 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 83 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 84 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 85 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 86 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 87 }; 88 89 struct mv88e6xxx_ops; 90 91 struct mv88e6xxx_info { 92 enum mv88e6xxx_family family; 93 u16 prod_num; 94 const char *name; 95 unsigned int num_databases; 96 unsigned int num_ports; 97 unsigned int num_internal_phys; 98 unsigned int num_gpio; 99 unsigned int max_vid; 100 unsigned int port_base_addr; 101 unsigned int phy_base_addr; 102 unsigned int global1_addr; 103 unsigned int global2_addr; 104 unsigned int age_time_coeff; 105 unsigned int g1_irqs; 106 unsigned int g2_irqs; 107 bool pvt; 108 109 /* Mark certain ports as invalid. This is required for example for the 110 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the 111 * ports 2-4 are not routet to pins. 112 */ 113 unsigned int invalid_port_mask; 114 /* Multi-chip Addressing Mode. 115 * Some chips respond to only 2 registers of its own SMI device address 116 * when it is non-zero, and use indirect access to internal registers. 117 */ 118 bool multi_chip; 119 /* Dual-chip Addressing Mode 120 * Some chips respond to only half of the 32 SMI addresses, 121 * allowing two to coexist on the same SMI interface. 122 */ 123 bool dual_chip; 124 125 enum dsa_tag_protocol tag_protocol; 126 127 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 128 * operation. 0 means that the ATU Move operation is not supported. 129 */ 130 u8 atu_move_port_mask; 131 const struct mv88e6xxx_ops *ops; 132 133 /* Supports PTP */ 134 bool ptp_support; 135 }; 136 137 struct mv88e6xxx_atu_entry { 138 u8 state; 139 bool trunk; 140 u16 portvec; 141 u8 mac[ETH_ALEN]; 142 }; 143 144 struct mv88e6xxx_vtu_entry { 145 u16 vid; 146 u16 fid; 147 u8 sid; 148 bool valid; 149 u8 member[DSA_MAX_PORTS]; 150 u8 state[DSA_MAX_PORTS]; 151 }; 152 153 struct mv88e6xxx_bus_ops; 154 struct mv88e6xxx_irq_ops; 155 struct mv88e6xxx_gpio_ops; 156 struct mv88e6xxx_avb_ops; 157 struct mv88e6xxx_ptp_ops; 158 159 struct mv88e6xxx_irq { 160 u16 masked; 161 struct irq_chip chip; 162 struct irq_domain *domain; 163 unsigned int nirqs; 164 }; 165 166 /* state flags for mv88e6xxx_port_hwtstamp::state */ 167 enum { 168 MV88E6XXX_HWTSTAMP_ENABLED, 169 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 170 }; 171 172 struct mv88e6xxx_port_hwtstamp { 173 /* Port index */ 174 int port_id; 175 176 /* Timestamping state */ 177 unsigned long state; 178 179 /* Resources for receive timestamping */ 180 struct sk_buff_head rx_queue; 181 struct sk_buff_head rx_queue2; 182 183 /* Resources for transmit timestamping */ 184 unsigned long tx_tstamp_start; 185 struct sk_buff *tx_skb; 186 u16 tx_seq_id; 187 188 /* Current timestamp configuration */ 189 struct hwtstamp_config tstamp_config; 190 }; 191 192 struct mv88e6xxx_port { 193 struct mv88e6xxx_chip *chip; 194 int port; 195 u64 serdes_stats[2]; 196 u64 atu_member_violation; 197 u64 atu_miss_violation; 198 u64 atu_full_violation; 199 u64 vtu_member_violation; 200 u64 vtu_miss_violation; 201 u8 cmode; 202 unsigned int serdes_irq; 203 }; 204 205 struct mv88e6xxx_chip { 206 const struct mv88e6xxx_info *info; 207 208 /* The dsa_switch this private structure is related to */ 209 struct dsa_switch *ds; 210 211 /* The device this structure is associated to */ 212 struct device *dev; 213 214 /* This mutex protects the access to the switch registers */ 215 struct mutex reg_lock; 216 217 /* The MII bus and the address on the bus that is used to 218 * communication with the switch 219 */ 220 const struct mv88e6xxx_bus_ops *smi_ops; 221 struct mii_bus *bus; 222 int sw_addr; 223 224 /* Handles automatic disabling and re-enabling of the PHY 225 * polling unit. 226 */ 227 const struct mv88e6xxx_bus_ops *phy_ops; 228 struct mutex ppu_mutex; 229 int ppu_disabled; 230 struct work_struct ppu_work; 231 struct timer_list ppu_timer; 232 233 /* This mutex serialises access to the statistics unit. 234 * Hold this mutex over snapshot + dump sequences. 235 */ 236 struct mutex stats_mutex; 237 238 /* A switch may have a GPIO line tied to its reset pin. Parse 239 * this from the device tree, and use it before performing 240 * switch soft reset. 241 */ 242 struct gpio_desc *reset; 243 244 /* set to size of eeprom if supported by the switch */ 245 u32 eeprom_len; 246 247 /* List of mdio busses */ 248 struct list_head mdios; 249 250 /* There can be two interrupt controllers, which are chained 251 * off a GPIO as interrupt source 252 */ 253 struct mv88e6xxx_irq g1_irq; 254 struct mv88e6xxx_irq g2_irq; 255 int irq; 256 int device_irq; 257 int watchdog_irq; 258 259 int atu_prob_irq; 260 int vtu_prob_irq; 261 struct kthread_worker *kworker; 262 struct kthread_delayed_work irq_poll_work; 263 264 /* GPIO resources */ 265 u8 gpio_data[2]; 266 267 /* This cyclecounter abstracts the switch PTP time. 268 * reg_lock must be held for any operation that read()s. 269 */ 270 struct cyclecounter tstamp_cc; 271 struct timecounter tstamp_tc; 272 struct delayed_work overflow_work; 273 274 struct ptp_clock *ptp_clock; 275 struct ptp_clock_info ptp_clock_info; 276 struct delayed_work tai_event_work; 277 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 278 u16 trig_config; 279 u16 evcap_config; 280 u16 enable_count; 281 282 /* Per-port timestamping resources. */ 283 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 284 285 /* Array of port structures. */ 286 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 287 }; 288 289 struct mv88e6xxx_bus_ops { 290 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 291 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 292 }; 293 294 struct mv88e6xxx_mdio_bus { 295 struct mii_bus *bus; 296 struct mv88e6xxx_chip *chip; 297 struct list_head list; 298 bool external; 299 }; 300 301 struct mv88e6xxx_ops { 302 /* Switch Setup Errata, called early in the switch setup to 303 * allow any errata actions to be performed 304 */ 305 int (*setup_errata)(struct mv88e6xxx_chip *chip); 306 307 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 308 int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 309 310 /* Ingress Rate Limit unit (IRL) operations */ 311 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 312 313 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 314 struct ethtool_eeprom *eeprom, u8 *data); 315 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 316 struct ethtool_eeprom *eeprom, u8 *data); 317 318 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 319 320 int (*phy_read)(struct mv88e6xxx_chip *chip, 321 struct mii_bus *bus, 322 int addr, int reg, u16 *val); 323 int (*phy_write)(struct mv88e6xxx_chip *chip, 324 struct mii_bus *bus, 325 int addr, int reg, u16 val); 326 327 /* Priority Override Table operations */ 328 int (*pot_clear)(struct mv88e6xxx_chip *chip); 329 330 /* PHY Polling Unit (PPU) operations */ 331 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 332 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 333 334 /* Switch Software Reset */ 335 int (*reset)(struct mv88e6xxx_chip *chip); 336 337 /* RGMII Receive/Transmit Timing Control 338 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 339 */ 340 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 341 phy_interface_t mode); 342 343 #define LINK_FORCED_DOWN 0 344 #define LINK_FORCED_UP 1 345 #define LINK_UNFORCED -2 346 347 /* Port's MAC link state 348 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 349 * or LINK_UNFORCED for normal link detection. 350 */ 351 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 352 353 #define DUPLEX_UNFORCED -2 354 355 /* Port's MAC duplex mode 356 * 357 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 358 * or DUPLEX_UNFORCED for normal duplex detection. 359 */ 360 int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup); 361 362 #define PAUSE_ON 1 363 #define PAUSE_OFF 0 364 365 /* Enable/disable sending Pause */ 366 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 367 int pause); 368 369 #define SPEED_MAX INT_MAX 370 #define SPEED_UNFORCED -2 371 372 /* Port's MAC speed (in Mbps) 373 * 374 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 375 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 376 */ 377 int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed); 378 379 /* What interface mode should be used for maximum speed? */ 380 phy_interface_t (*port_max_speed_mode)(int port); 381 382 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 383 384 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 385 enum mv88e6xxx_frame_mode mode); 386 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port, 387 bool unicast, bool multicast); 388 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 389 u16 etype); 390 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 391 size_t size); 392 393 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 394 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 395 u8 out); 396 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 397 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 398 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port); 399 400 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 401 * Some chips allow this to be configured on specific ports. 402 */ 403 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 404 phy_interface_t mode); 405 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 406 407 /* Some devices have a per port register indicating what is 408 * the upstream port this port should forward to. 409 */ 410 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 411 int upstream_port); 412 /* Return the port link state, as required by phylink */ 413 int (*port_link_state)(struct mv88e6xxx_chip *chip, int port, 414 struct phylink_link_state *state); 415 416 /* Snapshot the statistics for a port. The statistics can then 417 * be read back a leisure but still with a consistent view. 418 */ 419 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 420 421 /* Set the histogram mode for statistics, when the control registers 422 * are separated out of the STATS_OP register. 423 */ 424 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 425 426 /* Return the number of strings describing statistics */ 427 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 428 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 429 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 430 uint64_t *data); 431 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 432 int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port); 433 434 #define MV88E6XXX_CASCADE_PORT_NONE 0xe 435 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 436 437 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 438 439 const struct mv88e6xxx_irq_ops *watchdog_ops; 440 441 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 442 443 /* Power on/off a SERDES interface */ 444 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane, 445 bool up); 446 447 /* SERDES lane mapping */ 448 u8 (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); 449 450 /* SERDES interrupt handling */ 451 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, 452 int port); 453 int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane, 454 bool enable); 455 irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port, 456 u8 lane); 457 458 /* Statistics from the SERDES interface */ 459 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 460 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 461 uint8_t *data); 462 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 463 uint64_t *data); 464 465 /* VLAN Translation Unit operations */ 466 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 467 struct mv88e6xxx_vtu_entry *entry); 468 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 469 struct mv88e6xxx_vtu_entry *entry); 470 471 /* GPIO operations */ 472 const struct mv88e6xxx_gpio_ops *gpio_ops; 473 474 /* Interface to the AVB/PTP registers */ 475 const struct mv88e6xxx_avb_ops *avb_ops; 476 477 /* Remote Management Unit operations */ 478 int (*rmu_disable)(struct mv88e6xxx_chip *chip); 479 480 /* Precision Time Protocol operations */ 481 const struct mv88e6xxx_ptp_ops *ptp_ops; 482 483 /* Phylink */ 484 void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port, 485 unsigned long *mask, 486 struct phylink_link_state *state); 487 }; 488 489 struct mv88e6xxx_irq_ops { 490 /* Action to be performed when the interrupt happens */ 491 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 492 /* Setup the hardware to generate the interrupt */ 493 int (*irq_setup)(struct mv88e6xxx_chip *chip); 494 /* Reset the hardware to stop generating the interrupt */ 495 void (*irq_free)(struct mv88e6xxx_chip *chip); 496 }; 497 498 struct mv88e6xxx_gpio_ops { 499 /* Get/set data on GPIO pin */ 500 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 501 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 502 int value); 503 504 /* get/set GPIO direction */ 505 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 506 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 507 bool input); 508 509 /* get/set GPIO pin control */ 510 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 511 int *func); 512 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 513 int func); 514 }; 515 516 struct mv88e6xxx_avb_ops { 517 /* Access port-scoped Precision Time Protocol registers */ 518 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 519 u16 *data, int len); 520 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 521 u16 data); 522 523 /* Access global Precision Time Protocol registers */ 524 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 525 int len); 526 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 527 528 /* Access global Time Application Interface registers */ 529 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 530 int len); 531 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 532 }; 533 534 struct mv88e6xxx_ptp_ops { 535 u64 (*clock_read)(const struct cyclecounter *cc); 536 int (*ptp_enable)(struct ptp_clock_info *ptp, 537 struct ptp_clock_request *rq, int on); 538 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 539 enum ptp_pin_function func, unsigned int chan); 540 void (*event_work)(struct work_struct *ugly); 541 int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 542 int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 543 int (*global_enable)(struct mv88e6xxx_chip *chip); 544 int (*global_disable)(struct mv88e6xxx_chip *chip); 545 int n_ext_ts; 546 int arr0_sts_reg; 547 int arr1_sts_reg; 548 int dep_sts_reg; 549 u32 rx_filters; 550 u32 cc_shift; 551 u32 cc_mult; 552 u32 cc_mult_num; 553 u32 cc_mult_dem; 554 }; 555 556 #define STATS_TYPE_PORT BIT(0) 557 #define STATS_TYPE_BANK0 BIT(1) 558 #define STATS_TYPE_BANK1 BIT(2) 559 560 struct mv88e6xxx_hw_stat { 561 char string[ETH_GSTRING_LEN]; 562 size_t size; 563 int reg; 564 int type; 565 }; 566 567 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 568 { 569 return chip->info->pvt; 570 } 571 572 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 573 { 574 return chip->info->num_databases; 575 } 576 577 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 578 { 579 return chip->info->num_ports; 580 } 581 582 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 583 { 584 return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0); 585 } 586 587 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 588 { 589 return chip->info->num_gpio; 590 } 591 592 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port) 593 { 594 return (chip->info->invalid_port_mask & BIT(port)) != 0; 595 } 596 597 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 598 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 599 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 600 u16 mask, u16 val); 601 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 602 int bit, int val); 603 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link, 604 int speed, int duplex, int pause, 605 phy_interface_t mode); 606 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 607 608 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) 609 { 610 mutex_lock(&chip->reg_lock); 611 } 612 613 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) 614 { 615 mutex_unlock(&chip->reg_lock); 616 } 617 618 #endif /* _MV88E6XXX_CHIP_H */ 619