1 /* 2 * Marvell 88E6xxx Ethernet switch single-chip definition 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #ifndef _MV88E6XXX_CHIP_H 13 #define _MV88E6XXX_CHIP_H 14 15 #include <linux/if_vlan.h> 16 #include <linux/irq.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/kthread.h> 19 #include <linux/phy.h> 20 #include <linux/ptp_clock_kernel.h> 21 #include <linux/timecounter.h> 22 #include <net/dsa.h> 23 24 #ifndef UINT64_MAX 25 #define UINT64_MAX (u64)(~((u64)0)) 26 #endif 27 28 #define SMI_CMD 0x00 29 #define SMI_CMD_BUSY BIT(15) 30 #define SMI_CMD_CLAUSE_22 BIT(12) 31 #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 32 #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 33 #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY) 34 #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY) 35 #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY) 36 #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY) 37 #define SMI_DATA 0x01 38 39 #define MV88E6XXX_N_FID 4096 40 41 /* PVT limits for 4-bit port and 5-bit switch */ 42 #define MV88E6XXX_MAX_PVT_SWITCHES 32 43 #define MV88E6XXX_MAX_PVT_PORTS 16 44 45 #define MV88E6XXX_MAX_GPIO 16 46 47 enum mv88e6xxx_egress_mode { 48 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 49 MV88E6XXX_EGRESS_MODE_UNTAGGED, 50 MV88E6XXX_EGRESS_MODE_TAGGED, 51 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 52 }; 53 54 enum mv88e6xxx_frame_mode { 55 MV88E6XXX_FRAME_MODE_NORMAL, 56 MV88E6XXX_FRAME_MODE_DSA, 57 MV88E6XXX_FRAME_MODE_PROVIDER, 58 MV88E6XXX_FRAME_MODE_ETHERTYPE, 59 }; 60 61 /* List of supported models */ 62 enum mv88e6xxx_model { 63 MV88E6085, 64 MV88E6095, 65 MV88E6097, 66 MV88E6123, 67 MV88E6131, 68 MV88E6141, 69 MV88E6161, 70 MV88E6165, 71 MV88E6171, 72 MV88E6172, 73 MV88E6175, 74 MV88E6176, 75 MV88E6185, 76 MV88E6190, 77 MV88E6190X, 78 MV88E6191, 79 MV88E6240, 80 MV88E6290, 81 MV88E6320, 82 MV88E6321, 83 MV88E6341, 84 MV88E6350, 85 MV88E6351, 86 MV88E6352, 87 MV88E6390, 88 MV88E6390X, 89 }; 90 91 enum mv88e6xxx_family { 92 MV88E6XXX_FAMILY_NONE, 93 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 94 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 95 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 96 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 97 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 98 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 99 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 100 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 101 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 102 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 103 }; 104 105 struct mv88e6xxx_ops; 106 107 struct mv88e6xxx_info { 108 enum mv88e6xxx_family family; 109 u16 prod_num; 110 const char *name; 111 unsigned int num_databases; 112 unsigned int num_ports; 113 unsigned int num_internal_phys; 114 unsigned int num_gpio; 115 unsigned int max_vid; 116 unsigned int port_base_addr; 117 unsigned int phy_base_addr; 118 unsigned int global1_addr; 119 unsigned int global2_addr; 120 unsigned int age_time_coeff; 121 unsigned int g1_irqs; 122 unsigned int g2_irqs; 123 bool pvt; 124 125 /* Multi-chip Addressing Mode. 126 * Some chips respond to only 2 registers of its own SMI device address 127 * when it is non-zero, and use indirect access to internal registers. 128 */ 129 bool multi_chip; 130 enum dsa_tag_protocol tag_protocol; 131 132 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 133 * operation. 0 means that the ATU Move operation is not supported. 134 */ 135 u8 atu_move_port_mask; 136 const struct mv88e6xxx_ops *ops; 137 138 /* Supports PTP */ 139 bool ptp_support; 140 }; 141 142 struct mv88e6xxx_atu_entry { 143 u8 state; 144 bool trunk; 145 u16 portvec; 146 u8 mac[ETH_ALEN]; 147 }; 148 149 struct mv88e6xxx_vtu_entry { 150 u16 vid; 151 u16 fid; 152 u8 sid; 153 bool valid; 154 u8 member[DSA_MAX_PORTS]; 155 u8 state[DSA_MAX_PORTS]; 156 }; 157 158 struct mv88e6xxx_bus_ops; 159 struct mv88e6xxx_irq_ops; 160 struct mv88e6xxx_gpio_ops; 161 struct mv88e6xxx_avb_ops; 162 163 struct mv88e6xxx_irq { 164 u16 masked; 165 struct irq_chip chip; 166 struct irq_domain *domain; 167 unsigned int nirqs; 168 }; 169 170 /* state flags for mv88e6xxx_port_hwtstamp::state */ 171 enum { 172 MV88E6XXX_HWTSTAMP_ENABLED, 173 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 174 }; 175 176 struct mv88e6xxx_port_hwtstamp { 177 /* Port index */ 178 int port_id; 179 180 /* Timestamping state */ 181 unsigned long state; 182 183 /* Resources for receive timestamping */ 184 struct sk_buff_head rx_queue; 185 struct sk_buff_head rx_queue2; 186 187 /* Resources for transmit timestamping */ 188 unsigned long tx_tstamp_start; 189 struct sk_buff *tx_skb; 190 u16 tx_seq_id; 191 192 /* Current timestamp configuration */ 193 struct hwtstamp_config tstamp_config; 194 }; 195 196 struct mv88e6xxx_port { 197 u64 serdes_stats[2]; 198 u64 atu_member_violation; 199 u64 atu_miss_violation; 200 u64 atu_full_violation; 201 u64 vtu_member_violation; 202 u64 vtu_miss_violation; 203 }; 204 205 struct mv88e6xxx_chip { 206 const struct mv88e6xxx_info *info; 207 208 /* The dsa_switch this private structure is related to */ 209 struct dsa_switch *ds; 210 211 /* The device this structure is associated to */ 212 struct device *dev; 213 214 /* This mutex protects the access to the switch registers */ 215 struct mutex reg_lock; 216 217 /* The MII bus and the address on the bus that is used to 218 * communication with the switch 219 */ 220 const struct mv88e6xxx_bus_ops *smi_ops; 221 struct mii_bus *bus; 222 int sw_addr; 223 224 /* Handles automatic disabling and re-enabling of the PHY 225 * polling unit. 226 */ 227 const struct mv88e6xxx_bus_ops *phy_ops; 228 struct mutex ppu_mutex; 229 int ppu_disabled; 230 struct work_struct ppu_work; 231 struct timer_list ppu_timer; 232 233 /* This mutex serialises access to the statistics unit. 234 * Hold this mutex over snapshot + dump sequences. 235 */ 236 struct mutex stats_mutex; 237 238 /* A switch may have a GPIO line tied to its reset pin. Parse 239 * this from the device tree, and use it before performing 240 * switch soft reset. 241 */ 242 struct gpio_desc *reset; 243 244 /* set to size of eeprom if supported by the switch */ 245 int eeprom_len; 246 247 /* List of mdio busses */ 248 struct list_head mdios; 249 250 /* There can be two interrupt controllers, which are chained 251 * off a GPIO as interrupt source 252 */ 253 struct mv88e6xxx_irq g1_irq; 254 struct mv88e6xxx_irq g2_irq; 255 int irq; 256 int device_irq; 257 int watchdog_irq; 258 259 int atu_prob_irq; 260 int vtu_prob_irq; 261 struct kthread_worker *kworker; 262 struct kthread_delayed_work irq_poll_work; 263 264 /* GPIO resources */ 265 u8 gpio_data[2]; 266 267 /* This cyclecounter abstracts the switch PTP time. 268 * reg_lock must be held for any operation that read()s. 269 */ 270 struct cyclecounter tstamp_cc; 271 struct timecounter tstamp_tc; 272 struct delayed_work overflow_work; 273 274 struct ptp_clock *ptp_clock; 275 struct ptp_clock_info ptp_clock_info; 276 struct delayed_work tai_event_work; 277 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 278 u16 trig_config; 279 u16 evcap_config; 280 281 /* Per-port timestamping resources. */ 282 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 283 284 /* Array of port structures. */ 285 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 286 }; 287 288 struct mv88e6xxx_bus_ops { 289 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 290 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 291 }; 292 293 struct mv88e6xxx_mdio_bus { 294 struct mii_bus *bus; 295 struct mv88e6xxx_chip *chip; 296 struct list_head list; 297 bool external; 298 }; 299 300 struct mv88e6xxx_ops { 301 /* Ingress Rate Limit unit (IRL) operations */ 302 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 303 304 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 305 struct ethtool_eeprom *eeprom, u8 *data); 306 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 307 struct ethtool_eeprom *eeprom, u8 *data); 308 309 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 310 311 int (*phy_read)(struct mv88e6xxx_chip *chip, 312 struct mii_bus *bus, 313 int addr, int reg, u16 *val); 314 int (*phy_write)(struct mv88e6xxx_chip *chip, 315 struct mii_bus *bus, 316 int addr, int reg, u16 val); 317 318 /* Priority Override Table operations */ 319 int (*pot_clear)(struct mv88e6xxx_chip *chip); 320 321 /* PHY Polling Unit (PPU) operations */ 322 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 323 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 324 325 /* Switch Software Reset */ 326 int (*reset)(struct mv88e6xxx_chip *chip); 327 328 /* RGMII Receive/Transmit Timing Control 329 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 330 */ 331 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 332 phy_interface_t mode); 333 334 #define LINK_FORCED_DOWN 0 335 #define LINK_FORCED_UP 1 336 #define LINK_UNFORCED -2 337 338 /* Port's MAC link state 339 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 340 * or LINK_UNFORCED for normal link detection. 341 */ 342 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 343 344 #define DUPLEX_UNFORCED -2 345 346 /* Port's MAC duplex mode 347 * 348 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 349 * or DUPLEX_UNFORCED for normal duplex detection. 350 */ 351 int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup); 352 353 #define SPEED_MAX INT_MAX 354 #define SPEED_UNFORCED -2 355 356 /* Port's MAC speed (in Mbps) 357 * 358 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 359 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 360 */ 361 int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed); 362 363 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 364 365 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 366 enum mv88e6xxx_frame_mode mode); 367 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port, 368 bool unicast, bool multicast); 369 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 370 u16 etype); 371 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 372 size_t size); 373 374 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 375 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 376 u8 out); 377 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 378 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 379 380 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 381 * Some chips allow this to be configured on specific ports. 382 */ 383 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 384 phy_interface_t mode); 385 386 /* Some devices have a per port register indicating what is 387 * the upstream port this port should forward to. 388 */ 389 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 390 int upstream_port); 391 392 /* Snapshot the statistics for a port. The statistics can then 393 * be read back a leisure but still with a consistent view. 394 */ 395 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 396 397 /* Set the histogram mode for statistics, when the control registers 398 * are separated out of the STATS_OP register. 399 */ 400 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 401 402 /* Return the number of strings describing statistics */ 403 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 404 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 405 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 406 uint64_t *data); 407 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 408 int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port); 409 const struct mv88e6xxx_irq_ops *watchdog_ops; 410 411 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 412 413 /* Power on/off a SERDES interface */ 414 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on); 415 416 /* Statistics from the SERDES interface */ 417 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 418 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 419 uint8_t *data); 420 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 421 uint64_t *data); 422 423 /* VLAN Translation Unit operations */ 424 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 425 struct mv88e6xxx_vtu_entry *entry); 426 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 427 struct mv88e6xxx_vtu_entry *entry); 428 429 /* GPIO operations */ 430 const struct mv88e6xxx_gpio_ops *gpio_ops; 431 432 /* Interface to the AVB/PTP registers */ 433 const struct mv88e6xxx_avb_ops *avb_ops; 434 }; 435 436 struct mv88e6xxx_irq_ops { 437 /* Action to be performed when the interrupt happens */ 438 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 439 /* Setup the hardware to generate the interrupt */ 440 int (*irq_setup)(struct mv88e6xxx_chip *chip); 441 /* Reset the hardware to stop generating the interrupt */ 442 void (*irq_free)(struct mv88e6xxx_chip *chip); 443 }; 444 445 struct mv88e6xxx_gpio_ops { 446 /* Get/set data on GPIO pin */ 447 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 448 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 449 int value); 450 451 /* get/set GPIO direction */ 452 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 453 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 454 bool input); 455 456 /* get/set GPIO pin control */ 457 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 458 int *func); 459 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 460 int func); 461 }; 462 463 struct mv88e6xxx_avb_ops { 464 /* Access port-scoped Precision Time Protocol registers */ 465 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 466 u16 *data, int len); 467 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 468 u16 data); 469 470 /* Access global Precision Time Protocol registers */ 471 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 472 int len); 473 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 474 475 /* Access global Time Application Interface registers */ 476 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 477 int len); 478 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 479 }; 480 481 #define STATS_TYPE_PORT BIT(0) 482 #define STATS_TYPE_BANK0 BIT(1) 483 #define STATS_TYPE_BANK1 BIT(2) 484 485 struct mv88e6xxx_hw_stat { 486 char string[ETH_GSTRING_LEN]; 487 size_t size; 488 int reg; 489 int type; 490 }; 491 492 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 493 { 494 return chip->info->pvt; 495 } 496 497 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 498 { 499 return chip->info->num_databases; 500 } 501 502 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 503 { 504 return chip->info->num_ports; 505 } 506 507 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 508 { 509 return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0); 510 } 511 512 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 513 { 514 return chip->info->num_gpio; 515 } 516 517 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 518 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 519 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, 520 u16 update); 521 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask); 522 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 523 524 #endif /* _MV88E6XXX_CHIP_H */ 525