1 /* 2 * Marvell 88E6xxx Ethernet switch single-chip definition 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #ifndef _MV88E6XXX_CHIP_H 13 #define _MV88E6XXX_CHIP_H 14 15 #include <linux/if_vlan.h> 16 #include <linux/irq.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/kthread.h> 19 #include <linux/phy.h> 20 #include <linux/ptp_clock_kernel.h> 21 #include <linux/timecounter.h> 22 #include <net/dsa.h> 23 24 #ifndef UINT64_MAX 25 #define UINT64_MAX (u64)(~((u64)0)) 26 #endif 27 28 #define SMI_CMD 0x00 29 #define SMI_CMD_BUSY BIT(15) 30 #define SMI_CMD_CLAUSE_22 BIT(12) 31 #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 32 #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 33 #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY) 34 #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY) 35 #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY) 36 #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY) 37 #define SMI_DATA 0x01 38 39 #define MV88E6XXX_N_FID 4096 40 41 /* PVT limits for 4-bit port and 5-bit switch */ 42 #define MV88E6XXX_MAX_PVT_SWITCHES 32 43 #define MV88E6XXX_MAX_PVT_PORTS 16 44 45 #define MV88E6XXX_MAX_GPIO 16 46 47 enum mv88e6xxx_egress_mode { 48 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 49 MV88E6XXX_EGRESS_MODE_UNTAGGED, 50 MV88E6XXX_EGRESS_MODE_TAGGED, 51 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 52 }; 53 54 enum mv88e6xxx_frame_mode { 55 MV88E6XXX_FRAME_MODE_NORMAL, 56 MV88E6XXX_FRAME_MODE_DSA, 57 MV88E6XXX_FRAME_MODE_PROVIDER, 58 MV88E6XXX_FRAME_MODE_ETHERTYPE, 59 }; 60 61 /* List of supported models */ 62 enum mv88e6xxx_model { 63 MV88E6085, 64 MV88E6095, 65 MV88E6097, 66 MV88E6123, 67 MV88E6131, 68 MV88E6141, 69 MV88E6161, 70 MV88E6165, 71 MV88E6171, 72 MV88E6172, 73 MV88E6175, 74 MV88E6176, 75 MV88E6185, 76 MV88E6190, 77 MV88E6190X, 78 MV88E6191, 79 MV88E6240, 80 MV88E6290, 81 MV88E6320, 82 MV88E6321, 83 MV88E6341, 84 MV88E6350, 85 MV88E6351, 86 MV88E6352, 87 MV88E6390, 88 MV88E6390X, 89 }; 90 91 enum mv88e6xxx_family { 92 MV88E6XXX_FAMILY_NONE, 93 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 94 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 95 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 96 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 97 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 98 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 99 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 100 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 101 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 102 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 103 }; 104 105 struct mv88e6xxx_ops; 106 107 struct mv88e6xxx_info { 108 enum mv88e6xxx_family family; 109 u16 prod_num; 110 const char *name; 111 unsigned int num_databases; 112 unsigned int num_ports; 113 unsigned int num_internal_phys; 114 unsigned int num_gpio; 115 unsigned int max_vid; 116 unsigned int port_base_addr; 117 unsigned int global1_addr; 118 unsigned int global2_addr; 119 unsigned int age_time_coeff; 120 unsigned int g1_irqs; 121 unsigned int g2_irqs; 122 bool pvt; 123 124 /* Multi-chip Addressing Mode. 125 * Some chips respond to only 2 registers of its own SMI device address 126 * when it is non-zero, and use indirect access to internal registers. 127 */ 128 bool multi_chip; 129 enum dsa_tag_protocol tag_protocol; 130 131 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 132 * operation. 0 means that the ATU Move operation is not supported. 133 */ 134 u8 atu_move_port_mask; 135 const struct mv88e6xxx_ops *ops; 136 137 /* Supports PTP */ 138 bool ptp_support; 139 }; 140 141 struct mv88e6xxx_atu_entry { 142 u8 state; 143 bool trunk; 144 u16 portvec; 145 u8 mac[ETH_ALEN]; 146 }; 147 148 struct mv88e6xxx_vtu_entry { 149 u16 vid; 150 u16 fid; 151 u8 sid; 152 bool valid; 153 u8 member[DSA_MAX_PORTS]; 154 u8 state[DSA_MAX_PORTS]; 155 }; 156 157 struct mv88e6xxx_bus_ops; 158 struct mv88e6xxx_irq_ops; 159 struct mv88e6xxx_gpio_ops; 160 struct mv88e6xxx_avb_ops; 161 162 struct mv88e6xxx_irq { 163 u16 masked; 164 struct irq_chip chip; 165 struct irq_domain *domain; 166 unsigned int nirqs; 167 }; 168 169 /* state flags for mv88e6xxx_port_hwtstamp::state */ 170 enum { 171 MV88E6XXX_HWTSTAMP_ENABLED, 172 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 173 }; 174 175 struct mv88e6xxx_port_hwtstamp { 176 /* Port index */ 177 int port_id; 178 179 /* Timestamping state */ 180 unsigned long state; 181 182 /* Resources for receive timestamping */ 183 struct sk_buff_head rx_queue; 184 struct sk_buff_head rx_queue2; 185 186 /* Resources for transmit timestamping */ 187 unsigned long tx_tstamp_start; 188 struct sk_buff *tx_skb; 189 u16 tx_seq_id; 190 191 /* Current timestamp configuration */ 192 struct hwtstamp_config tstamp_config; 193 }; 194 195 struct mv88e6xxx_port { 196 u64 serdes_stats[2]; 197 u64 atu_member_violation; 198 u64 atu_miss_violation; 199 u64 atu_full_violation; 200 u64 vtu_member_violation; 201 u64 vtu_miss_violation; 202 }; 203 204 struct mv88e6xxx_chip { 205 const struct mv88e6xxx_info *info; 206 207 /* The dsa_switch this private structure is related to */ 208 struct dsa_switch *ds; 209 210 /* The device this structure is associated to */ 211 struct device *dev; 212 213 /* This mutex protects the access to the switch registers */ 214 struct mutex reg_lock; 215 216 /* The MII bus and the address on the bus that is used to 217 * communication with the switch 218 */ 219 const struct mv88e6xxx_bus_ops *smi_ops; 220 struct mii_bus *bus; 221 int sw_addr; 222 223 /* Handles automatic disabling and re-enabling of the PHY 224 * polling unit. 225 */ 226 const struct mv88e6xxx_bus_ops *phy_ops; 227 struct mutex ppu_mutex; 228 int ppu_disabled; 229 struct work_struct ppu_work; 230 struct timer_list ppu_timer; 231 232 /* This mutex serialises access to the statistics unit. 233 * Hold this mutex over snapshot + dump sequences. 234 */ 235 struct mutex stats_mutex; 236 237 /* A switch may have a GPIO line tied to its reset pin. Parse 238 * this from the device tree, and use it before performing 239 * switch soft reset. 240 */ 241 struct gpio_desc *reset; 242 243 /* set to size of eeprom if supported by the switch */ 244 int eeprom_len; 245 246 /* List of mdio busses */ 247 struct list_head mdios; 248 249 /* There can be two interrupt controllers, which are chained 250 * off a GPIO as interrupt source 251 */ 252 struct mv88e6xxx_irq g1_irq; 253 struct mv88e6xxx_irq g2_irq; 254 int irq; 255 int device_irq; 256 int watchdog_irq; 257 258 int atu_prob_irq; 259 int vtu_prob_irq; 260 struct kthread_worker *kworker; 261 struct kthread_delayed_work irq_poll_work; 262 263 /* GPIO resources */ 264 u8 gpio_data[2]; 265 266 /* This cyclecounter abstracts the switch PTP time. 267 * reg_lock must be held for any operation that read()s. 268 */ 269 struct cyclecounter tstamp_cc; 270 struct timecounter tstamp_tc; 271 struct delayed_work overflow_work; 272 273 struct ptp_clock *ptp_clock; 274 struct ptp_clock_info ptp_clock_info; 275 struct delayed_work tai_event_work; 276 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 277 u16 trig_config; 278 u16 evcap_config; 279 280 /* Per-port timestamping resources. */ 281 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 282 283 /* Array of port structures. */ 284 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 285 }; 286 287 struct mv88e6xxx_bus_ops { 288 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 289 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 290 }; 291 292 struct mv88e6xxx_mdio_bus { 293 struct mii_bus *bus; 294 struct mv88e6xxx_chip *chip; 295 struct list_head list; 296 bool external; 297 }; 298 299 struct mv88e6xxx_ops { 300 /* Ingress Rate Limit unit (IRL) operations */ 301 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 302 303 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 304 struct ethtool_eeprom *eeprom, u8 *data); 305 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 306 struct ethtool_eeprom *eeprom, u8 *data); 307 308 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 309 310 int (*phy_read)(struct mv88e6xxx_chip *chip, 311 struct mii_bus *bus, 312 int addr, int reg, u16 *val); 313 int (*phy_write)(struct mv88e6xxx_chip *chip, 314 struct mii_bus *bus, 315 int addr, int reg, u16 val); 316 317 /* Priority Override Table operations */ 318 int (*pot_clear)(struct mv88e6xxx_chip *chip); 319 320 /* PHY Polling Unit (PPU) operations */ 321 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 322 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 323 324 /* Switch Software Reset */ 325 int (*reset)(struct mv88e6xxx_chip *chip); 326 327 /* RGMII Receive/Transmit Timing Control 328 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 329 */ 330 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 331 phy_interface_t mode); 332 333 #define LINK_FORCED_DOWN 0 334 #define LINK_FORCED_UP 1 335 #define LINK_UNFORCED -2 336 337 /* Port's MAC link state 338 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 339 * or LINK_UNFORCED for normal link detection. 340 */ 341 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 342 343 #define DUPLEX_UNFORCED -2 344 345 /* Port's MAC duplex mode 346 * 347 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 348 * or DUPLEX_UNFORCED for normal duplex detection. 349 */ 350 int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup); 351 352 #define SPEED_MAX INT_MAX 353 #define SPEED_UNFORCED -2 354 355 /* Port's MAC speed (in Mbps) 356 * 357 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 358 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 359 */ 360 int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed); 361 362 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 363 364 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 365 enum mv88e6xxx_frame_mode mode); 366 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port, 367 bool unicast, bool multicast); 368 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 369 u16 etype); 370 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 371 size_t size); 372 373 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 374 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 375 u8 out); 376 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 377 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 378 379 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 380 * Some chips allow this to be configured on specific ports. 381 */ 382 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 383 phy_interface_t mode); 384 385 /* Some devices have a per port register indicating what is 386 * the upstream port this port should forward to. 387 */ 388 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 389 int upstream_port); 390 391 /* Snapshot the statistics for a port. The statistics can then 392 * be read back a leisure but still with a consistent view. 393 */ 394 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 395 396 /* Set the histogram mode for statistics, when the control registers 397 * are separated out of the STATS_OP register. 398 */ 399 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 400 401 /* Return the number of strings describing statistics */ 402 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 403 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 404 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 405 uint64_t *data); 406 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 407 int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port); 408 const struct mv88e6xxx_irq_ops *watchdog_ops; 409 410 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 411 412 /* Power on/off a SERDES interface */ 413 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on); 414 415 /* Statistics from the SERDES interface */ 416 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 417 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 418 uint8_t *data); 419 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 420 uint64_t *data); 421 422 /* VLAN Translation Unit operations */ 423 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 424 struct mv88e6xxx_vtu_entry *entry); 425 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 426 struct mv88e6xxx_vtu_entry *entry); 427 428 /* GPIO operations */ 429 const struct mv88e6xxx_gpio_ops *gpio_ops; 430 431 /* Interface to the AVB/PTP registers */ 432 const struct mv88e6xxx_avb_ops *avb_ops; 433 }; 434 435 struct mv88e6xxx_irq_ops { 436 /* Action to be performed when the interrupt happens */ 437 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 438 /* Setup the hardware to generate the interrupt */ 439 int (*irq_setup)(struct mv88e6xxx_chip *chip); 440 /* Reset the hardware to stop generating the interrupt */ 441 void (*irq_free)(struct mv88e6xxx_chip *chip); 442 }; 443 444 struct mv88e6xxx_gpio_ops { 445 /* Get/set data on GPIO pin */ 446 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 447 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 448 int value); 449 450 /* get/set GPIO direction */ 451 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 452 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 453 bool input); 454 455 /* get/set GPIO pin control */ 456 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 457 int *func); 458 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 459 int func); 460 }; 461 462 struct mv88e6xxx_avb_ops { 463 /* Access port-scoped Precision Time Protocol registers */ 464 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 465 u16 *data, int len); 466 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 467 u16 data); 468 469 /* Access global Precision Time Protocol registers */ 470 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 471 int len); 472 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 473 474 /* Access global Time Application Interface registers */ 475 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 476 int len); 477 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 478 }; 479 480 #define STATS_TYPE_PORT BIT(0) 481 #define STATS_TYPE_BANK0 BIT(1) 482 #define STATS_TYPE_BANK1 BIT(2) 483 484 struct mv88e6xxx_hw_stat { 485 char string[ETH_GSTRING_LEN]; 486 size_t size; 487 int reg; 488 int type; 489 }; 490 491 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 492 { 493 return chip->info->pvt; 494 } 495 496 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 497 { 498 return chip->info->num_databases; 499 } 500 501 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 502 { 503 return chip->info->num_ports; 504 } 505 506 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 507 { 508 return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0); 509 } 510 511 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 512 { 513 return chip->info->num_gpio; 514 } 515 516 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 517 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 518 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, 519 u16 update); 520 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask); 521 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 522 523 #endif /* _MV88E6XXX_CHIP_H */ 524