1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Ethernet switch single-chip definition 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 */ 7 8 #ifndef _MV88E6XXX_CHIP_H 9 #define _MV88E6XXX_CHIP_H 10 11 #include <linux/idr.h> 12 #include <linux/if_vlan.h> 13 #include <linux/irq.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/kthread.h> 16 #include <linux/phy.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/timecounter.h> 19 #include <net/dsa.h> 20 21 #define MV88E6XXX_N_FID 4096 22 23 /* PVT limits for 4-bit port and 5-bit switch */ 24 #define MV88E6XXX_MAX_PVT_SWITCHES 32 25 #define MV88E6XXX_MAX_PVT_PORTS 16 26 27 #define MV88E6XXX_MAX_GPIO 16 28 29 enum mv88e6xxx_egress_mode { 30 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 31 MV88E6XXX_EGRESS_MODE_UNTAGGED, 32 MV88E6XXX_EGRESS_MODE_TAGGED, 33 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 34 }; 35 36 enum mv88e6xxx_egress_direction { 37 MV88E6XXX_EGRESS_DIR_INGRESS, 38 MV88E6XXX_EGRESS_DIR_EGRESS, 39 }; 40 41 enum mv88e6xxx_frame_mode { 42 MV88E6XXX_FRAME_MODE_NORMAL, 43 MV88E6XXX_FRAME_MODE_DSA, 44 MV88E6XXX_FRAME_MODE_PROVIDER, 45 MV88E6XXX_FRAME_MODE_ETHERTYPE, 46 }; 47 48 /* List of supported models */ 49 enum mv88e6xxx_model { 50 MV88E6085, 51 MV88E6095, 52 MV88E6097, 53 MV88E6123, 54 MV88E6131, 55 MV88E6141, 56 MV88E6161, 57 MV88E6165, 58 MV88E6171, 59 MV88E6172, 60 MV88E6175, 61 MV88E6176, 62 MV88E6185, 63 MV88E6190, 64 MV88E6190X, 65 MV88E6191, 66 MV88E6220, 67 MV88E6240, 68 MV88E6250, 69 MV88E6290, 70 MV88E6320, 71 MV88E6321, 72 MV88E6341, 73 MV88E6350, 74 MV88E6351, 75 MV88E6352, 76 MV88E6390, 77 MV88E6390X, 78 }; 79 80 enum mv88e6xxx_family { 81 MV88E6XXX_FAMILY_NONE, 82 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 83 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 84 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 85 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 86 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 87 MV88E6XXX_FAMILY_6250, /* 6220 6250 */ 88 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 89 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 90 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 91 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 92 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 93 }; 94 95 struct mv88e6xxx_ops; 96 97 struct mv88e6xxx_info { 98 enum mv88e6xxx_family family; 99 u16 prod_num; 100 const char *name; 101 unsigned int num_databases; 102 unsigned int num_macs; 103 unsigned int num_ports; 104 unsigned int num_internal_phys; 105 unsigned int num_gpio; 106 unsigned int max_vid; 107 unsigned int port_base_addr; 108 unsigned int phy_base_addr; 109 unsigned int global1_addr; 110 unsigned int global2_addr; 111 unsigned int age_time_coeff; 112 unsigned int g1_irqs; 113 unsigned int g2_irqs; 114 bool pvt; 115 116 /* Mark certain ports as invalid. This is required for example for the 117 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the 118 * ports 2-4 are not routet to pins. 119 */ 120 unsigned int invalid_port_mask; 121 /* Multi-chip Addressing Mode. 122 * Some chips respond to only 2 registers of its own SMI device address 123 * when it is non-zero, and use indirect access to internal registers. 124 */ 125 bool multi_chip; 126 /* Dual-chip Addressing Mode 127 * Some chips respond to only half of the 32 SMI addresses, 128 * allowing two to coexist on the same SMI interface. 129 */ 130 bool dual_chip; 131 132 enum dsa_tag_protocol tag_protocol; 133 134 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 135 * operation. 0 means that the ATU Move operation is not supported. 136 */ 137 u8 atu_move_port_mask; 138 const struct mv88e6xxx_ops *ops; 139 140 /* Supports PTP */ 141 bool ptp_support; 142 }; 143 144 struct mv88e6xxx_atu_entry { 145 u8 state; 146 bool trunk; 147 u16 portvec; 148 u8 mac[ETH_ALEN]; 149 }; 150 151 struct mv88e6xxx_vtu_entry { 152 u16 vid; 153 u16 fid; 154 u8 sid; 155 bool valid; 156 u8 member[DSA_MAX_PORTS]; 157 u8 state[DSA_MAX_PORTS]; 158 }; 159 160 struct mv88e6xxx_bus_ops; 161 struct mv88e6xxx_irq_ops; 162 struct mv88e6xxx_gpio_ops; 163 struct mv88e6xxx_avb_ops; 164 struct mv88e6xxx_ptp_ops; 165 166 struct mv88e6xxx_irq { 167 u16 masked; 168 struct irq_chip chip; 169 struct irq_domain *domain; 170 int nirqs; 171 }; 172 173 /* state flags for mv88e6xxx_port_hwtstamp::state */ 174 enum { 175 MV88E6XXX_HWTSTAMP_ENABLED, 176 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 177 }; 178 179 struct mv88e6xxx_port_hwtstamp { 180 /* Port index */ 181 int port_id; 182 183 /* Timestamping state */ 184 unsigned long state; 185 186 /* Resources for receive timestamping */ 187 struct sk_buff_head rx_queue; 188 struct sk_buff_head rx_queue2; 189 190 /* Resources for transmit timestamping */ 191 unsigned long tx_tstamp_start; 192 struct sk_buff *tx_skb; 193 u16 tx_seq_id; 194 195 /* Current timestamp configuration */ 196 struct hwtstamp_config tstamp_config; 197 }; 198 199 enum mv88e6xxx_policy_mapping { 200 MV88E6XXX_POLICY_MAPPING_DA, 201 MV88E6XXX_POLICY_MAPPING_SA, 202 MV88E6XXX_POLICY_MAPPING_VTU, 203 MV88E6XXX_POLICY_MAPPING_ETYPE, 204 MV88E6XXX_POLICY_MAPPING_PPPOE, 205 MV88E6XXX_POLICY_MAPPING_VBAS, 206 MV88E6XXX_POLICY_MAPPING_OPT82, 207 MV88E6XXX_POLICY_MAPPING_UDP, 208 }; 209 210 enum mv88e6xxx_policy_action { 211 MV88E6XXX_POLICY_ACTION_NORMAL, 212 MV88E6XXX_POLICY_ACTION_MIRROR, 213 MV88E6XXX_POLICY_ACTION_TRAP, 214 MV88E6XXX_POLICY_ACTION_DISCARD, 215 }; 216 217 struct mv88e6xxx_policy { 218 enum mv88e6xxx_policy_mapping mapping; 219 enum mv88e6xxx_policy_action action; 220 struct ethtool_rx_flow_spec fs; 221 u8 addr[ETH_ALEN]; 222 int port; 223 u16 vid; 224 }; 225 226 struct mv88e6xxx_port { 227 struct mv88e6xxx_chip *chip; 228 int port; 229 u64 serdes_stats[2]; 230 u64 atu_member_violation; 231 u64 atu_miss_violation; 232 u64 atu_full_violation; 233 u64 vtu_member_violation; 234 u64 vtu_miss_violation; 235 phy_interface_t interface; 236 u8 cmode; 237 bool mirror_ingress; 238 bool mirror_egress; 239 unsigned int serdes_irq; 240 char serdes_irq_name[64]; 241 struct devlink_region *region; 242 }; 243 244 enum mv88e6xxx_region_id { 245 MV88E6XXX_REGION_GLOBAL1 = 0, 246 MV88E6XXX_REGION_GLOBAL2, 247 MV88E6XXX_REGION_ATU, 248 MV88E6XXX_REGION_VTU, 249 250 _MV88E6XXX_REGION_MAX, 251 }; 252 253 struct mv88e6xxx_region_priv { 254 enum mv88e6xxx_region_id id; 255 }; 256 257 struct mv88e6xxx_chip { 258 const struct mv88e6xxx_info *info; 259 260 /* The dsa_switch this private structure is related to */ 261 struct dsa_switch *ds; 262 263 /* The device this structure is associated to */ 264 struct device *dev; 265 266 /* This mutex protects the access to the switch registers */ 267 struct mutex reg_lock; 268 269 /* The MII bus and the address on the bus that is used to 270 * communication with the switch 271 */ 272 const struct mv88e6xxx_bus_ops *smi_ops; 273 struct mii_bus *bus; 274 int sw_addr; 275 276 /* Handles automatic disabling and re-enabling of the PHY 277 * polling unit. 278 */ 279 const struct mv88e6xxx_bus_ops *phy_ops; 280 struct mutex ppu_mutex; 281 int ppu_disabled; 282 struct work_struct ppu_work; 283 struct timer_list ppu_timer; 284 285 /* This mutex serialises access to the statistics unit. 286 * Hold this mutex over snapshot + dump sequences. 287 */ 288 struct mutex stats_mutex; 289 290 /* A switch may have a GPIO line tied to its reset pin. Parse 291 * this from the device tree, and use it before performing 292 * switch soft reset. 293 */ 294 struct gpio_desc *reset; 295 296 /* set to size of eeprom if supported by the switch */ 297 u32 eeprom_len; 298 299 /* List of mdio busses */ 300 struct list_head mdios; 301 302 /* Policy Control List IDs and rules */ 303 struct idr policies; 304 305 /* There can be two interrupt controllers, which are chained 306 * off a GPIO as interrupt source 307 */ 308 struct mv88e6xxx_irq g1_irq; 309 struct mv88e6xxx_irq g2_irq; 310 int irq; 311 char irq_name[64]; 312 int device_irq; 313 char device_irq_name[64]; 314 int watchdog_irq; 315 char watchdog_irq_name[64]; 316 317 int atu_prob_irq; 318 char atu_prob_irq_name[64]; 319 int vtu_prob_irq; 320 char vtu_prob_irq_name[64]; 321 struct kthread_worker *kworker; 322 struct kthread_delayed_work irq_poll_work; 323 324 /* GPIO resources */ 325 u8 gpio_data[2]; 326 327 /* This cyclecounter abstracts the switch PTP time. 328 * reg_lock must be held for any operation that read()s. 329 */ 330 struct cyclecounter tstamp_cc; 331 struct timecounter tstamp_tc; 332 struct delayed_work overflow_work; 333 334 struct ptp_clock *ptp_clock; 335 struct ptp_clock_info ptp_clock_info; 336 struct delayed_work tai_event_work; 337 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 338 u16 trig_config; 339 u16 evcap_config; 340 u16 enable_count; 341 342 /* Current ingress and egress monitor ports */ 343 int egress_dest_port; 344 int ingress_dest_port; 345 346 /* Per-port timestamping resources. */ 347 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 348 349 /* Array of port structures. */ 350 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 351 352 /* devlink regions */ 353 struct devlink_region *regions[_MV88E6XXX_REGION_MAX]; 354 }; 355 356 struct mv88e6xxx_bus_ops { 357 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 358 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 359 }; 360 361 struct mv88e6xxx_mdio_bus { 362 struct mii_bus *bus; 363 struct mv88e6xxx_chip *chip; 364 struct list_head list; 365 bool external; 366 }; 367 368 struct mv88e6xxx_ops { 369 /* Switch Setup Errata, called early in the switch setup to 370 * allow any errata actions to be performed 371 */ 372 int (*setup_errata)(struct mv88e6xxx_chip *chip); 373 374 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 375 int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 376 377 /* Ingress Rate Limit unit (IRL) operations */ 378 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 379 380 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 381 struct ethtool_eeprom *eeprom, u8 *data); 382 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 383 struct ethtool_eeprom *eeprom, u8 *data); 384 385 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 386 387 int (*phy_read)(struct mv88e6xxx_chip *chip, 388 struct mii_bus *bus, 389 int addr, int reg, u16 *val); 390 int (*phy_write)(struct mv88e6xxx_chip *chip, 391 struct mii_bus *bus, 392 int addr, int reg, u16 val); 393 394 /* Priority Override Table operations */ 395 int (*pot_clear)(struct mv88e6xxx_chip *chip); 396 397 /* PHY Polling Unit (PPU) operations */ 398 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 399 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 400 401 /* Switch Software Reset */ 402 int (*reset)(struct mv88e6xxx_chip *chip); 403 404 /* RGMII Receive/Transmit Timing Control 405 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 406 */ 407 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 408 phy_interface_t mode); 409 410 #define LINK_FORCED_DOWN 0 411 #define LINK_FORCED_UP 1 412 #define LINK_UNFORCED -2 413 414 /* Port's MAC link state 415 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 416 * or LINK_UNFORCED for normal link detection. 417 */ 418 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 419 420 /* Synchronise the port link state with that of the SERDES 421 */ 422 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 423 424 #define PAUSE_ON 1 425 #define PAUSE_OFF 0 426 427 /* Enable/disable sending Pause */ 428 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 429 int pause); 430 431 #define SPEED_MAX INT_MAX 432 #define SPEED_UNFORCED -2 433 #define DUPLEX_UNFORCED -2 434 435 /* Port's MAC speed (in Mbps) and MAC duplex mode 436 * 437 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 438 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 439 * 440 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 441 * or DUPLEX_UNFORCED for normal duplex detection. 442 */ 443 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port, 444 int speed, int duplex); 445 446 /* What interface mode should be used for maximum speed? */ 447 phy_interface_t (*port_max_speed_mode)(int port); 448 449 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 450 451 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port, 452 enum mv88e6xxx_policy_mapping mapping, 453 enum mv88e6xxx_policy_action action); 454 455 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 456 enum mv88e6xxx_frame_mode mode); 457 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port, 458 bool unicast, bool multicast); 459 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 460 u16 etype); 461 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 462 size_t size); 463 464 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 465 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 466 u8 out); 467 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 468 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 469 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port); 470 471 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 472 * Some chips allow this to be configured on specific ports. 473 */ 474 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 475 phy_interface_t mode); 476 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 477 478 /* Some devices have a per port register indicating what is 479 * the upstream port this port should forward to. 480 */ 481 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 482 int upstream_port); 483 484 /* Snapshot the statistics for a port. The statistics can then 485 * be read back a leisure but still with a consistent view. 486 */ 487 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 488 489 /* Set the histogram mode for statistics, when the control registers 490 * are separated out of the STATS_OP register. 491 */ 492 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 493 494 /* Return the number of strings describing statistics */ 495 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 496 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 497 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 498 uint64_t *data); 499 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 500 int (*set_egress_port)(struct mv88e6xxx_chip *chip, 501 enum mv88e6xxx_egress_direction direction, 502 int port); 503 504 #define MV88E6XXX_CASCADE_PORT_NONE 0xe 505 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 506 507 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 508 509 const struct mv88e6xxx_irq_ops *watchdog_ops; 510 511 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 512 513 /* Power on/off a SERDES interface */ 514 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane, 515 bool up); 516 517 /* SERDES lane mapping */ 518 u8 (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); 519 520 int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port, 521 u8 lane, struct phylink_link_state *state); 522 int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port, 523 u8 lane, unsigned int mode, 524 phy_interface_t interface, 525 const unsigned long *advertise); 526 int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port, 527 u8 lane); 528 int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port, 529 u8 lane, int speed, int duplex); 530 531 /* SERDES interrupt handling */ 532 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, 533 int port); 534 int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane, 535 bool enable); 536 irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port, 537 u8 lane); 538 539 /* Statistics from the SERDES interface */ 540 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 541 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 542 uint8_t *data); 543 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 544 uint64_t *data); 545 546 /* SERDES registers for ethtool */ 547 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port); 548 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port, 549 void *_p); 550 551 /* Address Translation Unit operations */ 552 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash); 553 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash); 554 555 /* VLAN Translation Unit operations */ 556 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 557 struct mv88e6xxx_vtu_entry *entry); 558 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 559 struct mv88e6xxx_vtu_entry *entry); 560 561 /* GPIO operations */ 562 const struct mv88e6xxx_gpio_ops *gpio_ops; 563 564 /* Interface to the AVB/PTP registers */ 565 const struct mv88e6xxx_avb_ops *avb_ops; 566 567 /* Remote Management Unit operations */ 568 int (*rmu_disable)(struct mv88e6xxx_chip *chip); 569 570 /* Precision Time Protocol operations */ 571 const struct mv88e6xxx_ptp_ops *ptp_ops; 572 573 /* Phylink */ 574 void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port, 575 unsigned long *mask, 576 struct phylink_link_state *state); 577 578 /* Max Frame Size */ 579 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu); 580 }; 581 582 struct mv88e6xxx_irq_ops { 583 /* Action to be performed when the interrupt happens */ 584 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 585 /* Setup the hardware to generate the interrupt */ 586 int (*irq_setup)(struct mv88e6xxx_chip *chip); 587 /* Reset the hardware to stop generating the interrupt */ 588 void (*irq_free)(struct mv88e6xxx_chip *chip); 589 }; 590 591 struct mv88e6xxx_gpio_ops { 592 /* Get/set data on GPIO pin */ 593 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 594 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 595 int value); 596 597 /* get/set GPIO direction */ 598 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 599 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 600 bool input); 601 602 /* get/set GPIO pin control */ 603 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 604 int *func); 605 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 606 int func); 607 }; 608 609 struct mv88e6xxx_avb_ops { 610 /* Access port-scoped Precision Time Protocol registers */ 611 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 612 u16 *data, int len); 613 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 614 u16 data); 615 616 /* Access global Precision Time Protocol registers */ 617 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 618 int len); 619 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 620 621 /* Access global Time Application Interface registers */ 622 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 623 int len); 624 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 625 }; 626 627 struct mv88e6xxx_ptp_ops { 628 u64 (*clock_read)(const struct cyclecounter *cc); 629 int (*ptp_enable)(struct ptp_clock_info *ptp, 630 struct ptp_clock_request *rq, int on); 631 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 632 enum ptp_pin_function func, unsigned int chan); 633 void (*event_work)(struct work_struct *ugly); 634 int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 635 int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 636 int (*global_enable)(struct mv88e6xxx_chip *chip); 637 int (*global_disable)(struct mv88e6xxx_chip *chip); 638 int n_ext_ts; 639 int arr0_sts_reg; 640 int arr1_sts_reg; 641 int dep_sts_reg; 642 u32 rx_filters; 643 u32 cc_shift; 644 u32 cc_mult; 645 u32 cc_mult_num; 646 u32 cc_mult_dem; 647 }; 648 649 #define STATS_TYPE_PORT BIT(0) 650 #define STATS_TYPE_BANK0 BIT(1) 651 #define STATS_TYPE_BANK1 BIT(2) 652 653 struct mv88e6xxx_hw_stat { 654 char string[ETH_GSTRING_LEN]; 655 size_t size; 656 int reg; 657 int type; 658 }; 659 660 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 661 { 662 return chip->info->pvt; 663 } 664 665 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 666 { 667 return chip->info->num_databases; 668 } 669 670 static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip) 671 { 672 return chip->info->num_macs; 673 } 674 675 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 676 { 677 return chip->info->num_ports; 678 } 679 680 static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip) 681 { 682 return chip->info->max_vid; 683 } 684 685 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 686 { 687 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0); 688 } 689 690 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 691 { 692 return chip->info->num_gpio; 693 } 694 695 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port) 696 { 697 return (chip->info->invalid_port_mask & BIT(port)) != 0; 698 } 699 700 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 701 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 702 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 703 u16 mask, u16 val); 704 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 705 int bit, int val); 706 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 707 708 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) 709 { 710 mutex_lock(&chip->reg_lock); 711 } 712 713 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) 714 { 715 mutex_unlock(&chip->reg_lock); 716 } 717 718 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap); 719 720 #endif /* _MV88E6XXX_CHIP_H */ 721