1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Ethernet switch single-chip definition 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 */ 7 8 #ifndef _MV88E6XXX_CHIP_H 9 #define _MV88E6XXX_CHIP_H 10 11 #include <linux/if_vlan.h> 12 #include <linux/irq.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/kthread.h> 15 #include <linux/phy.h> 16 #include <linux/ptp_clock_kernel.h> 17 #include <linux/timecounter.h> 18 #include <net/dsa.h> 19 20 #define MV88E6XXX_N_FID 4096 21 22 /* PVT limits for 4-bit port and 5-bit switch */ 23 #define MV88E6XXX_MAX_PVT_SWITCHES 32 24 #define MV88E6XXX_MAX_PVT_PORTS 16 25 26 #define MV88E6XXX_MAX_GPIO 16 27 28 enum mv88e6xxx_egress_mode { 29 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 30 MV88E6XXX_EGRESS_MODE_UNTAGGED, 31 MV88E6XXX_EGRESS_MODE_TAGGED, 32 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 33 }; 34 35 enum mv88e6xxx_frame_mode { 36 MV88E6XXX_FRAME_MODE_NORMAL, 37 MV88E6XXX_FRAME_MODE_DSA, 38 MV88E6XXX_FRAME_MODE_PROVIDER, 39 MV88E6XXX_FRAME_MODE_ETHERTYPE, 40 }; 41 42 /* List of supported models */ 43 enum mv88e6xxx_model { 44 MV88E6085, 45 MV88E6095, 46 MV88E6097, 47 MV88E6123, 48 MV88E6131, 49 MV88E6141, 50 MV88E6161, 51 MV88E6165, 52 MV88E6171, 53 MV88E6172, 54 MV88E6175, 55 MV88E6176, 56 MV88E6185, 57 MV88E6190, 58 MV88E6190X, 59 MV88E6191, 60 MV88E6240, 61 MV88E6250, 62 MV88E6290, 63 MV88E6320, 64 MV88E6321, 65 MV88E6341, 66 MV88E6350, 67 MV88E6351, 68 MV88E6352, 69 MV88E6390, 70 MV88E6390X, 71 }; 72 73 enum mv88e6xxx_family { 74 MV88E6XXX_FAMILY_NONE, 75 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 76 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 77 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 78 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 79 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 80 MV88E6XXX_FAMILY_6250, /* 6250 */ 81 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 82 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 83 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 84 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 85 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 86 }; 87 88 struct mv88e6xxx_ops; 89 90 struct mv88e6xxx_info { 91 enum mv88e6xxx_family family; 92 u16 prod_num; 93 const char *name; 94 unsigned int num_databases; 95 unsigned int num_ports; 96 unsigned int num_internal_phys; 97 unsigned int num_gpio; 98 unsigned int max_vid; 99 unsigned int port_base_addr; 100 unsigned int phy_base_addr; 101 unsigned int global1_addr; 102 unsigned int global2_addr; 103 unsigned int age_time_coeff; 104 unsigned int g1_irqs; 105 unsigned int g2_irqs; 106 bool pvt; 107 108 /* Multi-chip Addressing Mode. 109 * Some chips respond to only 2 registers of its own SMI device address 110 * when it is non-zero, and use indirect access to internal registers. 111 */ 112 bool multi_chip; 113 /* Dual-chip Addressing Mode 114 * Some chips respond to only half of the 32 SMI addresses, 115 * allowing two to coexist on the same SMI interface. 116 */ 117 bool dual_chip; 118 119 enum dsa_tag_protocol tag_protocol; 120 121 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 122 * operation. 0 means that the ATU Move operation is not supported. 123 */ 124 u8 atu_move_port_mask; 125 const struct mv88e6xxx_ops *ops; 126 127 /* Supports PTP */ 128 bool ptp_support; 129 }; 130 131 struct mv88e6xxx_atu_entry { 132 u8 state; 133 bool trunk; 134 u16 portvec; 135 u8 mac[ETH_ALEN]; 136 }; 137 138 struct mv88e6xxx_vtu_entry { 139 u16 vid; 140 u16 fid; 141 u8 sid; 142 bool valid; 143 u8 member[DSA_MAX_PORTS]; 144 u8 state[DSA_MAX_PORTS]; 145 }; 146 147 struct mv88e6xxx_bus_ops; 148 struct mv88e6xxx_irq_ops; 149 struct mv88e6xxx_gpio_ops; 150 struct mv88e6xxx_avb_ops; 151 struct mv88e6xxx_ptp_ops; 152 153 struct mv88e6xxx_irq { 154 u16 masked; 155 struct irq_chip chip; 156 struct irq_domain *domain; 157 unsigned int nirqs; 158 }; 159 160 /* state flags for mv88e6xxx_port_hwtstamp::state */ 161 enum { 162 MV88E6XXX_HWTSTAMP_ENABLED, 163 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 164 }; 165 166 struct mv88e6xxx_port_hwtstamp { 167 /* Port index */ 168 int port_id; 169 170 /* Timestamping state */ 171 unsigned long state; 172 173 /* Resources for receive timestamping */ 174 struct sk_buff_head rx_queue; 175 struct sk_buff_head rx_queue2; 176 177 /* Resources for transmit timestamping */ 178 unsigned long tx_tstamp_start; 179 struct sk_buff *tx_skb; 180 u16 tx_seq_id; 181 182 /* Current timestamp configuration */ 183 struct hwtstamp_config tstamp_config; 184 }; 185 186 struct mv88e6xxx_port { 187 struct mv88e6xxx_chip *chip; 188 int port; 189 u64 serdes_stats[2]; 190 u64 atu_member_violation; 191 u64 atu_miss_violation; 192 u64 atu_full_violation; 193 u64 vtu_member_violation; 194 u64 vtu_miss_violation; 195 u8 cmode; 196 int serdes_irq; 197 }; 198 199 struct mv88e6xxx_chip { 200 const struct mv88e6xxx_info *info; 201 202 /* The dsa_switch this private structure is related to */ 203 struct dsa_switch *ds; 204 205 /* The device this structure is associated to */ 206 struct device *dev; 207 208 /* This mutex protects the access to the switch registers */ 209 struct mutex reg_lock; 210 211 /* The MII bus and the address on the bus that is used to 212 * communication with the switch 213 */ 214 const struct mv88e6xxx_bus_ops *smi_ops; 215 struct mii_bus *bus; 216 int sw_addr; 217 218 /* Handles automatic disabling and re-enabling of the PHY 219 * polling unit. 220 */ 221 const struct mv88e6xxx_bus_ops *phy_ops; 222 struct mutex ppu_mutex; 223 int ppu_disabled; 224 struct work_struct ppu_work; 225 struct timer_list ppu_timer; 226 227 /* This mutex serialises access to the statistics unit. 228 * Hold this mutex over snapshot + dump sequences. 229 */ 230 struct mutex stats_mutex; 231 232 /* A switch may have a GPIO line tied to its reset pin. Parse 233 * this from the device tree, and use it before performing 234 * switch soft reset. 235 */ 236 struct gpio_desc *reset; 237 238 /* set to size of eeprom if supported by the switch */ 239 u32 eeprom_len; 240 241 /* List of mdio busses */ 242 struct list_head mdios; 243 244 /* There can be two interrupt controllers, which are chained 245 * off a GPIO as interrupt source 246 */ 247 struct mv88e6xxx_irq g1_irq; 248 struct mv88e6xxx_irq g2_irq; 249 int irq; 250 int device_irq; 251 int watchdog_irq; 252 253 int atu_prob_irq; 254 int vtu_prob_irq; 255 struct kthread_worker *kworker; 256 struct kthread_delayed_work irq_poll_work; 257 258 /* GPIO resources */ 259 u8 gpio_data[2]; 260 261 /* This cyclecounter abstracts the switch PTP time. 262 * reg_lock must be held for any operation that read()s. 263 */ 264 struct cyclecounter tstamp_cc; 265 struct timecounter tstamp_tc; 266 struct delayed_work overflow_work; 267 268 struct ptp_clock *ptp_clock; 269 struct ptp_clock_info ptp_clock_info; 270 struct delayed_work tai_event_work; 271 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 272 u16 trig_config; 273 u16 evcap_config; 274 u16 enable_count; 275 276 /* Per-port timestamping resources. */ 277 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 278 279 /* Array of port structures. */ 280 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 281 }; 282 283 struct mv88e6xxx_bus_ops { 284 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 285 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 286 }; 287 288 struct mv88e6xxx_mdio_bus { 289 struct mii_bus *bus; 290 struct mv88e6xxx_chip *chip; 291 struct list_head list; 292 bool external; 293 }; 294 295 struct mv88e6xxx_ops { 296 /* Switch Setup Errata, called early in the switch setup to 297 * allow any errata actions to be performed 298 */ 299 int (*setup_errata)(struct mv88e6xxx_chip *chip); 300 301 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 302 int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 303 304 /* Ingress Rate Limit unit (IRL) operations */ 305 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 306 307 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 308 struct ethtool_eeprom *eeprom, u8 *data); 309 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 310 struct ethtool_eeprom *eeprom, u8 *data); 311 312 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 313 314 int (*phy_read)(struct mv88e6xxx_chip *chip, 315 struct mii_bus *bus, 316 int addr, int reg, u16 *val); 317 int (*phy_write)(struct mv88e6xxx_chip *chip, 318 struct mii_bus *bus, 319 int addr, int reg, u16 val); 320 321 /* Priority Override Table operations */ 322 int (*pot_clear)(struct mv88e6xxx_chip *chip); 323 324 /* PHY Polling Unit (PPU) operations */ 325 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 326 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 327 328 /* Switch Software Reset */ 329 int (*reset)(struct mv88e6xxx_chip *chip); 330 331 /* RGMII Receive/Transmit Timing Control 332 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 333 */ 334 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 335 phy_interface_t mode); 336 337 #define LINK_FORCED_DOWN 0 338 #define LINK_FORCED_UP 1 339 #define LINK_UNFORCED -2 340 341 /* Port's MAC link state 342 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 343 * or LINK_UNFORCED for normal link detection. 344 */ 345 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 346 347 #define DUPLEX_UNFORCED -2 348 349 /* Port's MAC duplex mode 350 * 351 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 352 * or DUPLEX_UNFORCED for normal duplex detection. 353 */ 354 int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup); 355 356 #define PAUSE_ON 1 357 #define PAUSE_OFF 0 358 359 /* Enable/disable sending Pause */ 360 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 361 int pause); 362 363 #define SPEED_MAX INT_MAX 364 #define SPEED_UNFORCED -2 365 366 /* Port's MAC speed (in Mbps) 367 * 368 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 369 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 370 */ 371 int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed); 372 373 /* What interface mode should be used for maximum speed? */ 374 phy_interface_t (*port_max_speed_mode)(int port); 375 376 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 377 378 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 379 enum mv88e6xxx_frame_mode mode); 380 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port, 381 bool unicast, bool multicast); 382 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 383 u16 etype); 384 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 385 size_t size); 386 387 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 388 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 389 u8 out); 390 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 391 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 392 393 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 394 * Some chips allow this to be configured on specific ports. 395 */ 396 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 397 phy_interface_t mode); 398 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 399 400 /* Some devices have a per port register indicating what is 401 * the upstream port this port should forward to. 402 */ 403 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 404 int upstream_port); 405 /* Return the port link state, as required by phylink */ 406 int (*port_link_state)(struct mv88e6xxx_chip *chip, int port, 407 struct phylink_link_state *state); 408 409 /* Snapshot the statistics for a port. The statistics can then 410 * be read back a leisure but still with a consistent view. 411 */ 412 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 413 414 /* Set the histogram mode for statistics, when the control registers 415 * are separated out of the STATS_OP register. 416 */ 417 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 418 419 /* Return the number of strings describing statistics */ 420 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 421 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 422 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 423 uint64_t *data); 424 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 425 int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port); 426 427 #define MV88E6XXX_CASCADE_PORT_NONE 0xe 428 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 429 430 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 431 432 const struct mv88e6xxx_irq_ops *watchdog_ops; 433 434 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 435 436 /* Power on/off a SERDES interface */ 437 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on); 438 439 /* SERDES interrupt handling */ 440 int (*serdes_irq_setup)(struct mv88e6xxx_chip *chip, int port); 441 void (*serdes_irq_free)(struct mv88e6xxx_chip *chip, int port); 442 443 /* Statistics from the SERDES interface */ 444 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 445 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 446 uint8_t *data); 447 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 448 uint64_t *data); 449 450 /* VLAN Translation Unit operations */ 451 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 452 struct mv88e6xxx_vtu_entry *entry); 453 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 454 struct mv88e6xxx_vtu_entry *entry); 455 456 /* GPIO operations */ 457 const struct mv88e6xxx_gpio_ops *gpio_ops; 458 459 /* Interface to the AVB/PTP registers */ 460 const struct mv88e6xxx_avb_ops *avb_ops; 461 462 /* Remote Management Unit operations */ 463 int (*rmu_disable)(struct mv88e6xxx_chip *chip); 464 465 /* Precision Time Protocol operations */ 466 const struct mv88e6xxx_ptp_ops *ptp_ops; 467 468 /* Phylink */ 469 void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port, 470 unsigned long *mask, 471 struct phylink_link_state *state); 472 }; 473 474 struct mv88e6xxx_irq_ops { 475 /* Action to be performed when the interrupt happens */ 476 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 477 /* Setup the hardware to generate the interrupt */ 478 int (*irq_setup)(struct mv88e6xxx_chip *chip); 479 /* Reset the hardware to stop generating the interrupt */ 480 void (*irq_free)(struct mv88e6xxx_chip *chip); 481 }; 482 483 struct mv88e6xxx_gpio_ops { 484 /* Get/set data on GPIO pin */ 485 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 486 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 487 int value); 488 489 /* get/set GPIO direction */ 490 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 491 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 492 bool input); 493 494 /* get/set GPIO pin control */ 495 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 496 int *func); 497 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 498 int func); 499 }; 500 501 struct mv88e6xxx_avb_ops { 502 /* Access port-scoped Precision Time Protocol registers */ 503 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 504 u16 *data, int len); 505 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 506 u16 data); 507 508 /* Access global Precision Time Protocol registers */ 509 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 510 int len); 511 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 512 513 /* Access global Time Application Interface registers */ 514 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 515 int len); 516 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 517 }; 518 519 struct mv88e6xxx_ptp_ops { 520 u64 (*clock_read)(const struct cyclecounter *cc); 521 int (*ptp_enable)(struct ptp_clock_info *ptp, 522 struct ptp_clock_request *rq, int on); 523 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 524 enum ptp_pin_function func, unsigned int chan); 525 void (*event_work)(struct work_struct *ugly); 526 int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 527 int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 528 int (*global_enable)(struct mv88e6xxx_chip *chip); 529 int (*global_disable)(struct mv88e6xxx_chip *chip); 530 int n_ext_ts; 531 int arr0_sts_reg; 532 int arr1_sts_reg; 533 int dep_sts_reg; 534 u32 rx_filters; 535 }; 536 537 #define STATS_TYPE_PORT BIT(0) 538 #define STATS_TYPE_BANK0 BIT(1) 539 #define STATS_TYPE_BANK1 BIT(2) 540 541 struct mv88e6xxx_hw_stat { 542 char string[ETH_GSTRING_LEN]; 543 size_t size; 544 int reg; 545 int type; 546 }; 547 548 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 549 { 550 return chip->info->pvt; 551 } 552 553 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 554 { 555 return chip->info->num_databases; 556 } 557 558 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 559 { 560 return chip->info->num_ports; 561 } 562 563 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 564 { 565 return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0); 566 } 567 568 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 569 { 570 return chip->info->num_gpio; 571 } 572 573 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 574 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 575 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, 576 u16 update); 577 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask); 578 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link, 579 int speed, int duplex, int pause, 580 phy_interface_t mode); 581 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 582 583 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) 584 { 585 mutex_lock(&chip->reg_lock); 586 } 587 588 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) 589 { 590 mutex_unlock(&chip->reg_lock); 591 } 592 593 #endif /* _MV88E6XXX_CHIP_H */ 594