14d5f2ba7SVivien Didelot /* 24d5f2ba7SVivien Didelot * Marvell 88E6xxx Ethernet switch single-chip definition 34d5f2ba7SVivien Didelot * 44d5f2ba7SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 54d5f2ba7SVivien Didelot * 64d5f2ba7SVivien Didelot * This program is free software; you can redistribute it and/or modify 74d5f2ba7SVivien Didelot * it under the terms of the GNU General Public License as published by 84d5f2ba7SVivien Didelot * the Free Software Foundation; either version 2 of the License, or 94d5f2ba7SVivien Didelot * (at your option) any later version. 104d5f2ba7SVivien Didelot */ 114d5f2ba7SVivien Didelot 124d5f2ba7SVivien Didelot #ifndef _MV88E6XXX_CHIP_H 134d5f2ba7SVivien Didelot #define _MV88E6XXX_CHIP_H 144d5f2ba7SVivien Didelot 154d5f2ba7SVivien Didelot #include <linux/if_vlan.h> 164d5f2ba7SVivien Didelot #include <linux/irq.h> 174d5f2ba7SVivien Didelot #include <linux/gpio/consumer.h> 18294d711eSAndrew Lunn #include <linux/kthread.h> 194d5f2ba7SVivien Didelot #include <linux/phy.h> 202fa8d3afSBrandon Streiff #include <linux/ptp_clock_kernel.h> 212fa8d3afSBrandon Streiff #include <linux/timecounter.h> 224d5f2ba7SVivien Didelot #include <net/dsa.h> 234d5f2ba7SVivien Didelot 244d5f2ba7SVivien Didelot #define SMI_CMD 0x00 254d5f2ba7SVivien Didelot #define SMI_CMD_BUSY BIT(15) 264d5f2ba7SVivien Didelot #define SMI_CMD_CLAUSE_22 BIT(12) 274d5f2ba7SVivien Didelot #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 284d5f2ba7SVivien Didelot #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 294d5f2ba7SVivien Didelot #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY) 304d5f2ba7SVivien Didelot #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY) 314d5f2ba7SVivien Didelot #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY) 324d5f2ba7SVivien Didelot #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY) 334d5f2ba7SVivien Didelot #define SMI_DATA 0x01 344d5f2ba7SVivien Didelot 354d5f2ba7SVivien Didelot #define MV88E6XXX_N_FID 4096 364d5f2ba7SVivien Didelot 374d5f2ba7SVivien Didelot /* PVT limits for 4-bit port and 5-bit switch */ 384d5f2ba7SVivien Didelot #define MV88E6XXX_MAX_PVT_SWITCHES 32 394d5f2ba7SVivien Didelot #define MV88E6XXX_MAX_PVT_PORTS 16 404d5f2ba7SVivien Didelot 41a73ccd61SBrandon Streiff #define MV88E6XXX_MAX_GPIO 16 42a73ccd61SBrandon Streiff 4331bef4e9SVivien Didelot enum mv88e6xxx_egress_mode { 4431bef4e9SVivien Didelot MV88E6XXX_EGRESS_MODE_UNMODIFIED, 4531bef4e9SVivien Didelot MV88E6XXX_EGRESS_MODE_UNTAGGED, 4631bef4e9SVivien Didelot MV88E6XXX_EGRESS_MODE_TAGGED, 4731bef4e9SVivien Didelot MV88E6XXX_EGRESS_MODE_ETHERTYPE, 4831bef4e9SVivien Didelot }; 4931bef4e9SVivien Didelot 504d5f2ba7SVivien Didelot enum mv88e6xxx_frame_mode { 514d5f2ba7SVivien Didelot MV88E6XXX_FRAME_MODE_NORMAL, 524d5f2ba7SVivien Didelot MV88E6XXX_FRAME_MODE_DSA, 534d5f2ba7SVivien Didelot MV88E6XXX_FRAME_MODE_PROVIDER, 544d5f2ba7SVivien Didelot MV88E6XXX_FRAME_MODE_ETHERTYPE, 554d5f2ba7SVivien Didelot }; 564d5f2ba7SVivien Didelot 574d5f2ba7SVivien Didelot /* List of supported models */ 584d5f2ba7SVivien Didelot enum mv88e6xxx_model { 594d5f2ba7SVivien Didelot MV88E6085, 604d5f2ba7SVivien Didelot MV88E6095, 614d5f2ba7SVivien Didelot MV88E6097, 624d5f2ba7SVivien Didelot MV88E6123, 634d5f2ba7SVivien Didelot MV88E6131, 644d5f2ba7SVivien Didelot MV88E6141, 654d5f2ba7SVivien Didelot MV88E6161, 664d5f2ba7SVivien Didelot MV88E6165, 674d5f2ba7SVivien Didelot MV88E6171, 684d5f2ba7SVivien Didelot MV88E6172, 694d5f2ba7SVivien Didelot MV88E6175, 704d5f2ba7SVivien Didelot MV88E6176, 714d5f2ba7SVivien Didelot MV88E6185, 724d5f2ba7SVivien Didelot MV88E6190, 734d5f2ba7SVivien Didelot MV88E6190X, 744d5f2ba7SVivien Didelot MV88E6191, 754d5f2ba7SVivien Didelot MV88E6240, 764d5f2ba7SVivien Didelot MV88E6290, 774d5f2ba7SVivien Didelot MV88E6320, 784d5f2ba7SVivien Didelot MV88E6321, 794d5f2ba7SVivien Didelot MV88E6341, 804d5f2ba7SVivien Didelot MV88E6350, 814d5f2ba7SVivien Didelot MV88E6351, 824d5f2ba7SVivien Didelot MV88E6352, 834d5f2ba7SVivien Didelot MV88E6390, 844d5f2ba7SVivien Didelot MV88E6390X, 854d5f2ba7SVivien Didelot }; 864d5f2ba7SVivien Didelot 874d5f2ba7SVivien Didelot enum mv88e6xxx_family { 884d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_NONE, 894d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 904d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 914d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 924d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 934d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 944d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 954d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 964d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 974d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 984d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 994d5f2ba7SVivien Didelot }; 1004d5f2ba7SVivien Didelot 1014d5f2ba7SVivien Didelot struct mv88e6xxx_ops; 1024d5f2ba7SVivien Didelot 1034d5f2ba7SVivien Didelot struct mv88e6xxx_info { 1044d5f2ba7SVivien Didelot enum mv88e6xxx_family family; 1054d5f2ba7SVivien Didelot u16 prod_num; 1064d5f2ba7SVivien Didelot const char *name; 1074d5f2ba7SVivien Didelot unsigned int num_databases; 1084d5f2ba7SVivien Didelot unsigned int num_ports; 109bc393155SAndrew Lunn unsigned int num_internal_phys; 110a73ccd61SBrandon Streiff unsigned int num_gpio; 1114d5f2ba7SVivien Didelot unsigned int max_vid; 1124d5f2ba7SVivien Didelot unsigned int port_base_addr; 1139255bacdSAndrew Lunn unsigned int phy_base_addr; 1144d5f2ba7SVivien Didelot unsigned int global1_addr; 1159069c13aSVivien Didelot unsigned int global2_addr; 1164d5f2ba7SVivien Didelot unsigned int age_time_coeff; 1174d5f2ba7SVivien Didelot unsigned int g1_irqs; 118d6c5e6afSVivien Didelot unsigned int g2_irqs; 1194d5f2ba7SVivien Didelot bool pvt; 120b3e05aa1SVivien Didelot 121b3e05aa1SVivien Didelot /* Multi-chip Addressing Mode. 122b3e05aa1SVivien Didelot * Some chips respond to only 2 registers of its own SMI device address 123b3e05aa1SVivien Didelot * when it is non-zero, and use indirect access to internal registers. 124b3e05aa1SVivien Didelot */ 125b3e05aa1SVivien Didelot bool multi_chip; 1264d5f2ba7SVivien Didelot enum dsa_tag_protocol tag_protocol; 1274d5f2ba7SVivien Didelot 1284d5f2ba7SVivien Didelot /* Mask for FromPort and ToPort value of PortVec used in ATU Move 1294d5f2ba7SVivien Didelot * operation. 0 means that the ATU Move operation is not supported. 1304d5f2ba7SVivien Didelot */ 1314d5f2ba7SVivien Didelot u8 atu_move_port_mask; 1324d5f2ba7SVivien Didelot const struct mv88e6xxx_ops *ops; 1332fa8d3afSBrandon Streiff 1342fa8d3afSBrandon Streiff /* Supports PTP */ 1352fa8d3afSBrandon Streiff bool ptp_support; 1364d5f2ba7SVivien Didelot }; 1374d5f2ba7SVivien Didelot 1384d5f2ba7SVivien Didelot struct mv88e6xxx_atu_entry { 1394d5f2ba7SVivien Didelot u8 state; 1404d5f2ba7SVivien Didelot bool trunk; 1414d5f2ba7SVivien Didelot u16 portvec; 1424d5f2ba7SVivien Didelot u8 mac[ETH_ALEN]; 1434d5f2ba7SVivien Didelot }; 1444d5f2ba7SVivien Didelot 1454d5f2ba7SVivien Didelot struct mv88e6xxx_vtu_entry { 1464d5f2ba7SVivien Didelot u16 vid; 1474d5f2ba7SVivien Didelot u16 fid; 1484d5f2ba7SVivien Didelot u8 sid; 1494d5f2ba7SVivien Didelot bool valid; 1504d5f2ba7SVivien Didelot u8 member[DSA_MAX_PORTS]; 1514d5f2ba7SVivien Didelot u8 state[DSA_MAX_PORTS]; 1524d5f2ba7SVivien Didelot }; 1534d5f2ba7SVivien Didelot 1544d5f2ba7SVivien Didelot struct mv88e6xxx_bus_ops; 1554d5f2ba7SVivien Didelot struct mv88e6xxx_irq_ops; 156a73ccd61SBrandon Streiff struct mv88e6xxx_gpio_ops; 1570d632c3dSBrandon Streiff struct mv88e6xxx_avb_ops; 1586d2ac8eeSAndrew Lunn struct mv88e6xxx_ptp_ops; 1594d5f2ba7SVivien Didelot 1604d5f2ba7SVivien Didelot struct mv88e6xxx_irq { 1614d5f2ba7SVivien Didelot u16 masked; 1624d5f2ba7SVivien Didelot struct irq_chip chip; 1634d5f2ba7SVivien Didelot struct irq_domain *domain; 1644d5f2ba7SVivien Didelot unsigned int nirqs; 1654d5f2ba7SVivien Didelot }; 1664d5f2ba7SVivien Didelot 167c6fe0ad2SBrandon Streiff /* state flags for mv88e6xxx_port_hwtstamp::state */ 168c6fe0ad2SBrandon Streiff enum { 169c6fe0ad2SBrandon Streiff MV88E6XXX_HWTSTAMP_ENABLED, 170c6fe0ad2SBrandon Streiff MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 171c6fe0ad2SBrandon Streiff }; 172c6fe0ad2SBrandon Streiff 173c6fe0ad2SBrandon Streiff struct mv88e6xxx_port_hwtstamp { 174c6fe0ad2SBrandon Streiff /* Port index */ 175c6fe0ad2SBrandon Streiff int port_id; 176c6fe0ad2SBrandon Streiff 177c6fe0ad2SBrandon Streiff /* Timestamping state */ 178c6fe0ad2SBrandon Streiff unsigned long state; 179c6fe0ad2SBrandon Streiff 180c6fe0ad2SBrandon Streiff /* Resources for receive timestamping */ 181c6fe0ad2SBrandon Streiff struct sk_buff_head rx_queue; 182c6fe0ad2SBrandon Streiff struct sk_buff_head rx_queue2; 183c6fe0ad2SBrandon Streiff 184c6fe0ad2SBrandon Streiff /* Resources for transmit timestamping */ 185c6fe0ad2SBrandon Streiff unsigned long tx_tstamp_start; 186c6fe0ad2SBrandon Streiff struct sk_buff *tx_skb; 187c6fe0ad2SBrandon Streiff u16 tx_seq_id; 188c6fe0ad2SBrandon Streiff 189c6fe0ad2SBrandon Streiff /* Current timestamp configuration */ 190c6fe0ad2SBrandon Streiff struct hwtstamp_config tstamp_config; 191c6fe0ad2SBrandon Streiff }; 192c6fe0ad2SBrandon Streiff 193cda9f4aaSAndrew Lunn struct mv88e6xxx_port { 1947b898469SAndrew Lunn struct mv88e6xxx_chip *chip; 1957b898469SAndrew Lunn int port; 196cda9f4aaSAndrew Lunn u64 serdes_stats[2]; 19765f60e45SAndrew Lunn u64 atu_member_violation; 19865f60e45SAndrew Lunn u64 atu_miss_violation; 19965f60e45SAndrew Lunn u64 atu_full_violation; 20065f60e45SAndrew Lunn u64 vtu_member_violation; 20165f60e45SAndrew Lunn u64 vtu_miss_violation; 2022d2e1dd2SAndrew Lunn u8 cmode; 203efd1ba6aSAndrew Lunn int serdes_irq; 204cda9f4aaSAndrew Lunn }; 205cda9f4aaSAndrew Lunn 2064d5f2ba7SVivien Didelot struct mv88e6xxx_chip { 2074d5f2ba7SVivien Didelot const struct mv88e6xxx_info *info; 2084d5f2ba7SVivien Didelot 2094d5f2ba7SVivien Didelot /* The dsa_switch this private structure is related to */ 2104d5f2ba7SVivien Didelot struct dsa_switch *ds; 2114d5f2ba7SVivien Didelot 2124d5f2ba7SVivien Didelot /* The device this structure is associated to */ 2134d5f2ba7SVivien Didelot struct device *dev; 2144d5f2ba7SVivien Didelot 2154d5f2ba7SVivien Didelot /* This mutex protects the access to the switch registers */ 2164d5f2ba7SVivien Didelot struct mutex reg_lock; 2174d5f2ba7SVivien Didelot 2184d5f2ba7SVivien Didelot /* The MII bus and the address on the bus that is used to 2194d5f2ba7SVivien Didelot * communication with the switch 2204d5f2ba7SVivien Didelot */ 2214d5f2ba7SVivien Didelot const struct mv88e6xxx_bus_ops *smi_ops; 2224d5f2ba7SVivien Didelot struct mii_bus *bus; 2234d5f2ba7SVivien Didelot int sw_addr; 2244d5f2ba7SVivien Didelot 2254d5f2ba7SVivien Didelot /* Handles automatic disabling and re-enabling of the PHY 2264d5f2ba7SVivien Didelot * polling unit. 2274d5f2ba7SVivien Didelot */ 2284d5f2ba7SVivien Didelot const struct mv88e6xxx_bus_ops *phy_ops; 2294d5f2ba7SVivien Didelot struct mutex ppu_mutex; 2304d5f2ba7SVivien Didelot int ppu_disabled; 2314d5f2ba7SVivien Didelot struct work_struct ppu_work; 2324d5f2ba7SVivien Didelot struct timer_list ppu_timer; 2334d5f2ba7SVivien Didelot 2344d5f2ba7SVivien Didelot /* This mutex serialises access to the statistics unit. 2354d5f2ba7SVivien Didelot * Hold this mutex over snapshot + dump sequences. 2364d5f2ba7SVivien Didelot */ 2374d5f2ba7SVivien Didelot struct mutex stats_mutex; 2384d5f2ba7SVivien Didelot 2394d5f2ba7SVivien Didelot /* A switch may have a GPIO line tied to its reset pin. Parse 2404d5f2ba7SVivien Didelot * this from the device tree, and use it before performing 2414d5f2ba7SVivien Didelot * switch soft reset. 2424d5f2ba7SVivien Didelot */ 2434d5f2ba7SVivien Didelot struct gpio_desc *reset; 2444d5f2ba7SVivien Didelot 2454d5f2ba7SVivien Didelot /* set to size of eeprom if supported by the switch */ 24600baabe5SAndrew Lunn u32 eeprom_len; 2474d5f2ba7SVivien Didelot 2484d5f2ba7SVivien Didelot /* List of mdio busses */ 2494d5f2ba7SVivien Didelot struct list_head mdios; 2504d5f2ba7SVivien Didelot 2514d5f2ba7SVivien Didelot /* There can be two interrupt controllers, which are chained 2524d5f2ba7SVivien Didelot * off a GPIO as interrupt source 2534d5f2ba7SVivien Didelot */ 2544d5f2ba7SVivien Didelot struct mv88e6xxx_irq g1_irq; 2554d5f2ba7SVivien Didelot struct mv88e6xxx_irq g2_irq; 2564d5f2ba7SVivien Didelot int irq; 2574d5f2ba7SVivien Didelot int device_irq; 2584d5f2ba7SVivien Didelot int watchdog_irq; 259cda9f4aaSAndrew Lunn 2600977644cSAndrew Lunn int atu_prob_irq; 26162eb1162SAndrew Lunn int vtu_prob_irq; 262294d711eSAndrew Lunn struct kthread_worker *kworker; 263294d711eSAndrew Lunn struct kthread_delayed_work irq_poll_work; 2642fa8d3afSBrandon Streiff 265a73ccd61SBrandon Streiff /* GPIO resources */ 266a73ccd61SBrandon Streiff u8 gpio_data[2]; 267a73ccd61SBrandon Streiff 2682fa8d3afSBrandon Streiff /* This cyclecounter abstracts the switch PTP time. 2692fa8d3afSBrandon Streiff * reg_lock must be held for any operation that read()s. 2702fa8d3afSBrandon Streiff */ 2712fa8d3afSBrandon Streiff struct cyclecounter tstamp_cc; 2722fa8d3afSBrandon Streiff struct timecounter tstamp_tc; 2732fa8d3afSBrandon Streiff struct delayed_work overflow_work; 2742fa8d3afSBrandon Streiff 2752fa8d3afSBrandon Streiff struct ptp_clock *ptp_clock; 2762fa8d3afSBrandon Streiff struct ptp_clock_info ptp_clock_info; 2774eb3be29SBrandon Streiff struct delayed_work tai_event_work; 2784eb3be29SBrandon Streiff struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 2794eb3be29SBrandon Streiff u16 trig_config; 2804eb3be29SBrandon Streiff u16 evcap_config; 281e2294a8bSAndrew Lunn u16 enable_count; 282c6fe0ad2SBrandon Streiff 283c6fe0ad2SBrandon Streiff /* Per-port timestamping resources. */ 284c6fe0ad2SBrandon Streiff struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 285cda9f4aaSAndrew Lunn 286cda9f4aaSAndrew Lunn /* Array of port structures. */ 287cda9f4aaSAndrew Lunn struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 2884d5f2ba7SVivien Didelot }; 2894d5f2ba7SVivien Didelot 2904d5f2ba7SVivien Didelot struct mv88e6xxx_bus_ops { 2914d5f2ba7SVivien Didelot int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 2924d5f2ba7SVivien Didelot int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 2934d5f2ba7SVivien Didelot }; 2944d5f2ba7SVivien Didelot 2954d5f2ba7SVivien Didelot struct mv88e6xxx_mdio_bus { 2964d5f2ba7SVivien Didelot struct mii_bus *bus; 2974d5f2ba7SVivien Didelot struct mv88e6xxx_chip *chip; 2984d5f2ba7SVivien Didelot struct list_head list; 2994d5f2ba7SVivien Didelot bool external; 3004d5f2ba7SVivien Didelot }; 3014d5f2ba7SVivien Didelot 3024d5f2ba7SVivien Didelot struct mv88e6xxx_ops { 30393e18d61SVivien Didelot int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 30493e18d61SVivien Didelot int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 30593e18d61SVivien Didelot 306cd8da8bbSVivien Didelot /* Ingress Rate Limit unit (IRL) operations */ 307cd8da8bbSVivien Didelot int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 308cd8da8bbSVivien Didelot 3094d5f2ba7SVivien Didelot int (*get_eeprom)(struct mv88e6xxx_chip *chip, 3104d5f2ba7SVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 3114d5f2ba7SVivien Didelot int (*set_eeprom)(struct mv88e6xxx_chip *chip, 3124d5f2ba7SVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 3134d5f2ba7SVivien Didelot 3144d5f2ba7SVivien Didelot int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 3154d5f2ba7SVivien Didelot 3164d5f2ba7SVivien Didelot int (*phy_read)(struct mv88e6xxx_chip *chip, 3174d5f2ba7SVivien Didelot struct mii_bus *bus, 3184d5f2ba7SVivien Didelot int addr, int reg, u16 *val); 3194d5f2ba7SVivien Didelot int (*phy_write)(struct mv88e6xxx_chip *chip, 3204d5f2ba7SVivien Didelot struct mii_bus *bus, 3214d5f2ba7SVivien Didelot int addr, int reg, u16 val); 3224d5f2ba7SVivien Didelot 3239e907d73SVivien Didelot /* Priority Override Table operations */ 3249e907d73SVivien Didelot int (*pot_clear)(struct mv88e6xxx_chip *chip); 3259e907d73SVivien Didelot 3264d5f2ba7SVivien Didelot /* PHY Polling Unit (PPU) operations */ 3274d5f2ba7SVivien Didelot int (*ppu_enable)(struct mv88e6xxx_chip *chip); 3284d5f2ba7SVivien Didelot int (*ppu_disable)(struct mv88e6xxx_chip *chip); 3294d5f2ba7SVivien Didelot 3304d5f2ba7SVivien Didelot /* Switch Software Reset */ 3314d5f2ba7SVivien Didelot int (*reset)(struct mv88e6xxx_chip *chip); 3324d5f2ba7SVivien Didelot 3334d5f2ba7SVivien Didelot /* RGMII Receive/Transmit Timing Control 3344d5f2ba7SVivien Didelot * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 3354d5f2ba7SVivien Didelot */ 3364d5f2ba7SVivien Didelot int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 3374d5f2ba7SVivien Didelot phy_interface_t mode); 3384d5f2ba7SVivien Didelot 3394d5f2ba7SVivien Didelot #define LINK_FORCED_DOWN 0 3404d5f2ba7SVivien Didelot #define LINK_FORCED_UP 1 3414d5f2ba7SVivien Didelot #define LINK_UNFORCED -2 3424d5f2ba7SVivien Didelot 3434d5f2ba7SVivien Didelot /* Port's MAC link state 3444d5f2ba7SVivien Didelot * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 3454d5f2ba7SVivien Didelot * or LINK_UNFORCED for normal link detection. 3464d5f2ba7SVivien Didelot */ 3474d5f2ba7SVivien Didelot int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 3484d5f2ba7SVivien Didelot 3494d5f2ba7SVivien Didelot #define DUPLEX_UNFORCED -2 3504d5f2ba7SVivien Didelot 3514d5f2ba7SVivien Didelot /* Port's MAC duplex mode 3524d5f2ba7SVivien Didelot * 3534d5f2ba7SVivien Didelot * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 3544d5f2ba7SVivien Didelot * or DUPLEX_UNFORCED for normal duplex detection. 3554d5f2ba7SVivien Didelot */ 3564d5f2ba7SVivien Didelot int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup); 3574d5f2ba7SVivien Didelot 35854186b91SAndrew Lunn #define PAUSE_ON 1 35954186b91SAndrew Lunn #define PAUSE_OFF 0 36054186b91SAndrew Lunn 36154186b91SAndrew Lunn /* Enable/disable sending Pause */ 36254186b91SAndrew Lunn int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 36354186b91SAndrew Lunn int pause); 36454186b91SAndrew Lunn 3654d5f2ba7SVivien Didelot #define SPEED_MAX INT_MAX 3664d5f2ba7SVivien Didelot #define SPEED_UNFORCED -2 3674d5f2ba7SVivien Didelot 3684d5f2ba7SVivien Didelot /* Port's MAC speed (in Mbps) 3694d5f2ba7SVivien Didelot * 3704d5f2ba7SVivien Didelot * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 3714d5f2ba7SVivien Didelot * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 3724d5f2ba7SVivien Didelot */ 3734d5f2ba7SVivien Didelot int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed); 3744d5f2ba7SVivien Didelot 3754d5f2ba7SVivien Didelot int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 3764d5f2ba7SVivien Didelot 3774d5f2ba7SVivien Didelot int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 3784d5f2ba7SVivien Didelot enum mv88e6xxx_frame_mode mode); 3794d5f2ba7SVivien Didelot int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port, 3804d5f2ba7SVivien Didelot bool unicast, bool multicast); 3814d5f2ba7SVivien Didelot int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 3824d5f2ba7SVivien Didelot u16 etype); 383cd782656SVivien Didelot int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 384cd782656SVivien Didelot size_t size); 3854d5f2ba7SVivien Didelot 3864d5f2ba7SVivien Didelot int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 3870898432cSVivien Didelot int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 3880898432cSVivien Didelot u8 out); 3894d5f2ba7SVivien Didelot int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 3904d5f2ba7SVivien Didelot int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 3914d5f2ba7SVivien Didelot 3924d5f2ba7SVivien Didelot /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 3934d5f2ba7SVivien Didelot * Some chips allow this to be configured on specific ports. 3944d5f2ba7SVivien Didelot */ 3954d5f2ba7SVivien Didelot int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 3964d5f2ba7SVivien Didelot phy_interface_t mode); 3972d2e1dd2SAndrew Lunn int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 3984d5f2ba7SVivien Didelot 3994d5f2ba7SVivien Didelot /* Some devices have a per port register indicating what is 4004d5f2ba7SVivien Didelot * the upstream port this port should forward to. 4014d5f2ba7SVivien Didelot */ 4024d5f2ba7SVivien Didelot int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 4034d5f2ba7SVivien Didelot int upstream_port); 4046c422e34SRussell King /* Return the port link state, as required by phylink */ 4056c422e34SRussell King int (*port_link_state)(struct mv88e6xxx_chip *chip, int port, 4066c422e34SRussell King struct phylink_link_state *state); 4074d5f2ba7SVivien Didelot 4084d5f2ba7SVivien Didelot /* Snapshot the statistics for a port. The statistics can then 4094d5f2ba7SVivien Didelot * be read back a leisure but still with a consistent view. 4104d5f2ba7SVivien Didelot */ 4114d5f2ba7SVivien Didelot int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 4124d5f2ba7SVivien Didelot 4134d5f2ba7SVivien Didelot /* Set the histogram mode for statistics, when the control registers 4144d5f2ba7SVivien Didelot * are separated out of the STATS_OP register. 4154d5f2ba7SVivien Didelot */ 4164d5f2ba7SVivien Didelot int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 4174d5f2ba7SVivien Didelot 4184d5f2ba7SVivien Didelot /* Return the number of strings describing statistics */ 4194d5f2ba7SVivien Didelot int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 420436fe17dSAndrew Lunn int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 421436fe17dSAndrew Lunn int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 4224d5f2ba7SVivien Didelot uint64_t *data); 423fa8d1179SVivien Didelot int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 424fa8d1179SVivien Didelot int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port); 42502317e68SVivien Didelot 42602317e68SVivien Didelot #define MV88E6XXX_CASCADE_PORT_NONE 0xe 42702317e68SVivien Didelot #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 42802317e68SVivien Didelot 42902317e68SVivien Didelot int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 43002317e68SVivien Didelot 4314d5f2ba7SVivien Didelot const struct mv88e6xxx_irq_ops *watchdog_ops; 4324d5f2ba7SVivien Didelot 4334d5f2ba7SVivien Didelot int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 4344d5f2ba7SVivien Didelot 4354d5f2ba7SVivien Didelot /* Power on/off a SERDES interface */ 4364d5f2ba7SVivien Didelot int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on); 4374d5f2ba7SVivien Didelot 438efd1ba6aSAndrew Lunn /* SERDES interrupt handling */ 439efd1ba6aSAndrew Lunn int (*serdes_irq_setup)(struct mv88e6xxx_chip *chip, int port); 440efd1ba6aSAndrew Lunn void (*serdes_irq_free)(struct mv88e6xxx_chip *chip, int port); 441efd1ba6aSAndrew Lunn 442436fe17dSAndrew Lunn /* Statistics from the SERDES interface */ 443436fe17dSAndrew Lunn int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 44465f60e45SAndrew Lunn int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 445436fe17dSAndrew Lunn uint8_t *data); 44665f60e45SAndrew Lunn int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 447436fe17dSAndrew Lunn uint64_t *data); 448436fe17dSAndrew Lunn 4494d5f2ba7SVivien Didelot /* VLAN Translation Unit operations */ 4504d5f2ba7SVivien Didelot int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 4514d5f2ba7SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 4524d5f2ba7SVivien Didelot int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 4534d5f2ba7SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 4540d632c3dSBrandon Streiff 455a73ccd61SBrandon Streiff /* GPIO operations */ 456a73ccd61SBrandon Streiff const struct mv88e6xxx_gpio_ops *gpio_ops; 457a73ccd61SBrandon Streiff 4580d632c3dSBrandon Streiff /* Interface to the AVB/PTP registers */ 4590d632c3dSBrandon Streiff const struct mv88e6xxx_avb_ops *avb_ops; 4609e5baf9bSVivien Didelot 4619e5baf9bSVivien Didelot /* Remote Management Unit operations */ 4629e5baf9bSVivien Didelot int (*rmu_disable)(struct mv88e6xxx_chip *chip); 4636d2ac8eeSAndrew Lunn 4646d2ac8eeSAndrew Lunn /* Precision Time Protocol operations */ 4656d2ac8eeSAndrew Lunn const struct mv88e6xxx_ptp_ops *ptp_ops; 4666c422e34SRussell King 4676c422e34SRussell King /* Phylink */ 4686c422e34SRussell King void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port, 4696c422e34SRussell King unsigned long *mask, 4706c422e34SRussell King struct phylink_link_state *state); 4714d5f2ba7SVivien Didelot }; 4724d5f2ba7SVivien Didelot 4734d5f2ba7SVivien Didelot struct mv88e6xxx_irq_ops { 4744d5f2ba7SVivien Didelot /* Action to be performed when the interrupt happens */ 4754d5f2ba7SVivien Didelot int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 4764d5f2ba7SVivien Didelot /* Setup the hardware to generate the interrupt */ 4774d5f2ba7SVivien Didelot int (*irq_setup)(struct mv88e6xxx_chip *chip); 4784d5f2ba7SVivien Didelot /* Reset the hardware to stop generating the interrupt */ 4794d5f2ba7SVivien Didelot void (*irq_free)(struct mv88e6xxx_chip *chip); 4804d5f2ba7SVivien Didelot }; 4814d5f2ba7SVivien Didelot 482a73ccd61SBrandon Streiff struct mv88e6xxx_gpio_ops { 483a73ccd61SBrandon Streiff /* Get/set data on GPIO pin */ 484a73ccd61SBrandon Streiff int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 485a73ccd61SBrandon Streiff int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 486a73ccd61SBrandon Streiff int value); 487a73ccd61SBrandon Streiff 488a73ccd61SBrandon Streiff /* get/set GPIO direction */ 489a73ccd61SBrandon Streiff int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 490a73ccd61SBrandon Streiff int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 491a73ccd61SBrandon Streiff bool input); 492a73ccd61SBrandon Streiff 493a73ccd61SBrandon Streiff /* get/set GPIO pin control */ 494a73ccd61SBrandon Streiff int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 495a73ccd61SBrandon Streiff int *func); 496a73ccd61SBrandon Streiff int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 497a73ccd61SBrandon Streiff int func); 498a73ccd61SBrandon Streiff }; 499a73ccd61SBrandon Streiff 5000d632c3dSBrandon Streiff struct mv88e6xxx_avb_ops { 5010d632c3dSBrandon Streiff /* Access port-scoped Precision Time Protocol registers */ 5020d632c3dSBrandon Streiff int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 5030d632c3dSBrandon Streiff u16 *data, int len); 5040d632c3dSBrandon Streiff int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 5050d632c3dSBrandon Streiff u16 data); 5060d632c3dSBrandon Streiff 5070d632c3dSBrandon Streiff /* Access global Precision Time Protocol registers */ 5080d632c3dSBrandon Streiff int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 5090d632c3dSBrandon Streiff int len); 5100d632c3dSBrandon Streiff int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 5110d632c3dSBrandon Streiff 5120d632c3dSBrandon Streiff /* Access global Time Application Interface registers */ 5130d632c3dSBrandon Streiff int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 5140d632c3dSBrandon Streiff int len); 5150d632c3dSBrandon Streiff int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 5160d632c3dSBrandon Streiff }; 5170d632c3dSBrandon Streiff 5186d2ac8eeSAndrew Lunn struct mv88e6xxx_ptp_ops { 5196d2ac8eeSAndrew Lunn u64 (*clock_read)(const struct cyclecounter *cc); 5206d2ac8eeSAndrew Lunn int (*ptp_enable)(struct ptp_clock_info *ptp, 5216d2ac8eeSAndrew Lunn struct ptp_clock_request *rq, int on); 5226d2ac8eeSAndrew Lunn int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 5236d2ac8eeSAndrew Lunn enum ptp_pin_function func, unsigned int chan); 5246d2ac8eeSAndrew Lunn void (*event_work)(struct work_struct *ugly); 525ffc705deSAndrew Lunn int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 526ffc705deSAndrew Lunn int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 527e2294a8bSAndrew Lunn int (*global_enable)(struct mv88e6xxx_chip *chip); 528e2294a8bSAndrew Lunn int (*global_disable)(struct mv88e6xxx_chip *chip); 5296d2ac8eeSAndrew Lunn int n_ext_ts; 530ffc705deSAndrew Lunn int arr0_sts_reg; 531ffc705deSAndrew Lunn int arr1_sts_reg; 532ffc705deSAndrew Lunn int dep_sts_reg; 53348cb5e03SAndrew Lunn u32 rx_filters; 5346d2ac8eeSAndrew Lunn }; 5356d2ac8eeSAndrew Lunn 5364d5f2ba7SVivien Didelot #define STATS_TYPE_PORT BIT(0) 5374d5f2ba7SVivien Didelot #define STATS_TYPE_BANK0 BIT(1) 5384d5f2ba7SVivien Didelot #define STATS_TYPE_BANK1 BIT(2) 5394d5f2ba7SVivien Didelot 5404d5f2ba7SVivien Didelot struct mv88e6xxx_hw_stat { 5414d5f2ba7SVivien Didelot char string[ETH_GSTRING_LEN]; 542cda9f4aaSAndrew Lunn size_t size; 5434d5f2ba7SVivien Didelot int reg; 5444d5f2ba7SVivien Didelot int type; 5454d5f2ba7SVivien Didelot }; 5464d5f2ba7SVivien Didelot 5474d5f2ba7SVivien Didelot static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 5484d5f2ba7SVivien Didelot { 5494d5f2ba7SVivien Didelot return chip->info->pvt; 5504d5f2ba7SVivien Didelot } 5514d5f2ba7SVivien Didelot 5524d5f2ba7SVivien Didelot static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 5534d5f2ba7SVivien Didelot { 5544d5f2ba7SVivien Didelot return chip->info->num_databases; 5554d5f2ba7SVivien Didelot } 5564d5f2ba7SVivien Didelot 5574d5f2ba7SVivien Didelot static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 5584d5f2ba7SVivien Didelot { 5594d5f2ba7SVivien Didelot return chip->info->num_ports; 5604d5f2ba7SVivien Didelot } 5614d5f2ba7SVivien Didelot 5624d5f2ba7SVivien Didelot static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 5634d5f2ba7SVivien Didelot { 5644d5f2ba7SVivien Didelot return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0); 5654d5f2ba7SVivien Didelot } 5664d5f2ba7SVivien Didelot 567a73ccd61SBrandon Streiff static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 568a73ccd61SBrandon Streiff { 569a73ccd61SBrandon Streiff return chip->info->num_gpio; 570a73ccd61SBrandon Streiff } 571a73ccd61SBrandon Streiff 5724d5f2ba7SVivien Didelot int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 5734d5f2ba7SVivien Didelot int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 5744d5f2ba7SVivien Didelot int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, 5754d5f2ba7SVivien Didelot u16 update); 5764d5f2ba7SVivien Didelot int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask); 5774d5f2ba7SVivien Didelot struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 5784d5f2ba7SVivien Didelot 5794d5f2ba7SVivien Didelot #endif /* _MV88E6XXX_CHIP_H */ 580