12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 24d5f2ba7SVivien Didelot /* 34d5f2ba7SVivien Didelot * Marvell 88E6xxx Ethernet switch single-chip definition 44d5f2ba7SVivien Didelot * 54d5f2ba7SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 64d5f2ba7SVivien Didelot */ 74d5f2ba7SVivien Didelot 84d5f2ba7SVivien Didelot #ifndef _MV88E6XXX_CHIP_H 94d5f2ba7SVivien Didelot #define _MV88E6XXX_CHIP_H 104d5f2ba7SVivien Didelot 11da7dc875SVivien Didelot #include <linux/idr.h> 124d5f2ba7SVivien Didelot #include <linux/if_vlan.h> 134d5f2ba7SVivien Didelot #include <linux/irq.h> 144d5f2ba7SVivien Didelot #include <linux/gpio/consumer.h> 15294d711eSAndrew Lunn #include <linux/kthread.h> 164d5f2ba7SVivien Didelot #include <linux/phy.h> 172fa8d3afSBrandon Streiff #include <linux/ptp_clock_kernel.h> 182fa8d3afSBrandon Streiff #include <linux/timecounter.h> 194d5f2ba7SVivien Didelot #include <net/dsa.h> 204d5f2ba7SVivien Didelot 214d5f2ba7SVivien Didelot #define MV88E6XXX_N_FID 4096 224d5f2ba7SVivien Didelot 234d5f2ba7SVivien Didelot /* PVT limits for 4-bit port and 5-bit switch */ 244d5f2ba7SVivien Didelot #define MV88E6XXX_MAX_PVT_SWITCHES 32 254d5f2ba7SVivien Didelot #define MV88E6XXX_MAX_PVT_PORTS 16 264d5f2ba7SVivien Didelot 27a73ccd61SBrandon Streiff #define MV88E6XXX_MAX_GPIO 16 28a73ccd61SBrandon Streiff 2931bef4e9SVivien Didelot enum mv88e6xxx_egress_mode { 3031bef4e9SVivien Didelot MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3131bef4e9SVivien Didelot MV88E6XXX_EGRESS_MODE_UNTAGGED, 3231bef4e9SVivien Didelot MV88E6XXX_EGRESS_MODE_TAGGED, 3331bef4e9SVivien Didelot MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3431bef4e9SVivien Didelot }; 3531bef4e9SVivien Didelot 365c74c54cSIwan R Timmer enum mv88e6xxx_egress_direction { 375c74c54cSIwan R Timmer MV88E6XXX_EGRESS_DIR_INGRESS, 385c74c54cSIwan R Timmer MV88E6XXX_EGRESS_DIR_EGRESS, 395c74c54cSIwan R Timmer }; 405c74c54cSIwan R Timmer 414d5f2ba7SVivien Didelot enum mv88e6xxx_frame_mode { 424d5f2ba7SVivien Didelot MV88E6XXX_FRAME_MODE_NORMAL, 434d5f2ba7SVivien Didelot MV88E6XXX_FRAME_MODE_DSA, 444d5f2ba7SVivien Didelot MV88E6XXX_FRAME_MODE_PROVIDER, 454d5f2ba7SVivien Didelot MV88E6XXX_FRAME_MODE_ETHERTYPE, 464d5f2ba7SVivien Didelot }; 474d5f2ba7SVivien Didelot 484d5f2ba7SVivien Didelot /* List of supported models */ 494d5f2ba7SVivien Didelot enum mv88e6xxx_model { 504d5f2ba7SVivien Didelot MV88E6085, 514d5f2ba7SVivien Didelot MV88E6095, 524d5f2ba7SVivien Didelot MV88E6097, 534d5f2ba7SVivien Didelot MV88E6123, 544d5f2ba7SVivien Didelot MV88E6131, 554d5f2ba7SVivien Didelot MV88E6141, 564d5f2ba7SVivien Didelot MV88E6161, 574d5f2ba7SVivien Didelot MV88E6165, 584d5f2ba7SVivien Didelot MV88E6171, 594d5f2ba7SVivien Didelot MV88E6172, 604d5f2ba7SVivien Didelot MV88E6175, 614d5f2ba7SVivien Didelot MV88E6176, 624d5f2ba7SVivien Didelot MV88E6185, 634d5f2ba7SVivien Didelot MV88E6190, 644d5f2ba7SVivien Didelot MV88E6190X, 654d5f2ba7SVivien Didelot MV88E6191, 66*de776d0dSPavana Sharma MV88E6191X, 67*de776d0dSPavana Sharma MV88E6193X, 6849022647SHubert Feurstein MV88E6220, 694d5f2ba7SVivien Didelot MV88E6240, 701f71836fSRasmus Villemoes MV88E6250, 714d5f2ba7SVivien Didelot MV88E6290, 724d5f2ba7SVivien Didelot MV88E6320, 734d5f2ba7SVivien Didelot MV88E6321, 744d5f2ba7SVivien Didelot MV88E6341, 754d5f2ba7SVivien Didelot MV88E6350, 764d5f2ba7SVivien Didelot MV88E6351, 774d5f2ba7SVivien Didelot MV88E6352, 784d5f2ba7SVivien Didelot MV88E6390, 794d5f2ba7SVivien Didelot MV88E6390X, 80*de776d0dSPavana Sharma MV88E6393X, 814d5f2ba7SVivien Didelot }; 824d5f2ba7SVivien Didelot 834d5f2ba7SVivien Didelot enum mv88e6xxx_family { 844d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_NONE, 854d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 864d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 874d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 884d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 894d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 9049022647SHubert Feurstein MV88E6XXX_FAMILY_6250, /* 6220 6250 */ 914d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 924d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 934d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 944d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 954d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 96*de776d0dSPavana Sharma MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6393X */ 974d5f2ba7SVivien Didelot }; 984d5f2ba7SVivien Didelot 994d5f2ba7SVivien Didelot struct mv88e6xxx_ops; 1004d5f2ba7SVivien Didelot 1014d5f2ba7SVivien Didelot struct mv88e6xxx_info { 1024d5f2ba7SVivien Didelot enum mv88e6xxx_family family; 1034d5f2ba7SVivien Didelot u16 prod_num; 1044d5f2ba7SVivien Didelot const char *name; 1054d5f2ba7SVivien Didelot unsigned int num_databases; 106d9ea5620SAndrew Lunn unsigned int num_macs; 1074d5f2ba7SVivien Didelot unsigned int num_ports; 108bc393155SAndrew Lunn unsigned int num_internal_phys; 109a73ccd61SBrandon Streiff unsigned int num_gpio; 1104d5f2ba7SVivien Didelot unsigned int max_vid; 1114d5f2ba7SVivien Didelot unsigned int port_base_addr; 1129255bacdSAndrew Lunn unsigned int phy_base_addr; 1134d5f2ba7SVivien Didelot unsigned int global1_addr; 1149069c13aSVivien Didelot unsigned int global2_addr; 1154d5f2ba7SVivien Didelot unsigned int age_time_coeff; 1164d5f2ba7SVivien Didelot unsigned int g1_irqs; 117d6c5e6afSVivien Didelot unsigned int g2_irqs; 1184d5f2ba7SVivien Didelot bool pvt; 119b3e05aa1SVivien Didelot 120c857486aSHubert Feurstein /* Mark certain ports as invalid. This is required for example for the 121c857486aSHubert Feurstein * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the 122c857486aSHubert Feurstein * ports 2-4 are not routet to pins. 123c857486aSHubert Feurstein */ 124c857486aSHubert Feurstein unsigned int invalid_port_mask; 125b3e05aa1SVivien Didelot /* Multi-chip Addressing Mode. 126b3e05aa1SVivien Didelot * Some chips respond to only 2 registers of its own SMI device address 127b3e05aa1SVivien Didelot * when it is non-zero, and use indirect access to internal registers. 128b3e05aa1SVivien Didelot */ 129b3e05aa1SVivien Didelot bool multi_chip; 130f30a19b8SRasmus Villemoes /* Dual-chip Addressing Mode 131f30a19b8SRasmus Villemoes * Some chips respond to only half of the 32 SMI addresses, 132f30a19b8SRasmus Villemoes * allowing two to coexist on the same SMI interface. 133f30a19b8SRasmus Villemoes */ 134f30a19b8SRasmus Villemoes bool dual_chip; 135f30a19b8SRasmus Villemoes 1364d5f2ba7SVivien Didelot enum dsa_tag_protocol tag_protocol; 1374d5f2ba7SVivien Didelot 1384d5f2ba7SVivien Didelot /* Mask for FromPort and ToPort value of PortVec used in ATU Move 1394d5f2ba7SVivien Didelot * operation. 0 means that the ATU Move operation is not supported. 1404d5f2ba7SVivien Didelot */ 1414d5f2ba7SVivien Didelot u8 atu_move_port_mask; 1424d5f2ba7SVivien Didelot const struct mv88e6xxx_ops *ops; 1432fa8d3afSBrandon Streiff 1442fa8d3afSBrandon Streiff /* Supports PTP */ 1452fa8d3afSBrandon Streiff bool ptp_support; 1464d5f2ba7SVivien Didelot }; 1474d5f2ba7SVivien Didelot 1484d5f2ba7SVivien Didelot struct mv88e6xxx_atu_entry { 1494d5f2ba7SVivien Didelot u8 state; 1504d5f2ba7SVivien Didelot bool trunk; 1514d5f2ba7SVivien Didelot u16 portvec; 1524d5f2ba7SVivien Didelot u8 mac[ETH_ALEN]; 1534d5f2ba7SVivien Didelot }; 1544d5f2ba7SVivien Didelot 1554d5f2ba7SVivien Didelot struct mv88e6xxx_vtu_entry { 1564d5f2ba7SVivien Didelot u16 vid; 1574d5f2ba7SVivien Didelot u16 fid; 1584d5f2ba7SVivien Didelot u8 sid; 1594d5f2ba7SVivien Didelot bool valid; 1604d5f2ba7SVivien Didelot u8 member[DSA_MAX_PORTS]; 1614d5f2ba7SVivien Didelot u8 state[DSA_MAX_PORTS]; 1624d5f2ba7SVivien Didelot }; 1634d5f2ba7SVivien Didelot 1644d5f2ba7SVivien Didelot struct mv88e6xxx_bus_ops; 1654d5f2ba7SVivien Didelot struct mv88e6xxx_irq_ops; 166a73ccd61SBrandon Streiff struct mv88e6xxx_gpio_ops; 1670d632c3dSBrandon Streiff struct mv88e6xxx_avb_ops; 1686d2ac8eeSAndrew Lunn struct mv88e6xxx_ptp_ops; 1694d5f2ba7SVivien Didelot 1704d5f2ba7SVivien Didelot struct mv88e6xxx_irq { 1714d5f2ba7SVivien Didelot u16 masked; 1724d5f2ba7SVivien Didelot struct irq_chip chip; 1734d5f2ba7SVivien Didelot struct irq_domain *domain; 174f1931164SAndrew Lunn int nirqs; 1754d5f2ba7SVivien Didelot }; 1764d5f2ba7SVivien Didelot 177c6fe0ad2SBrandon Streiff /* state flags for mv88e6xxx_port_hwtstamp::state */ 178c6fe0ad2SBrandon Streiff enum { 179c6fe0ad2SBrandon Streiff MV88E6XXX_HWTSTAMP_ENABLED, 180c6fe0ad2SBrandon Streiff MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 181c6fe0ad2SBrandon Streiff }; 182c6fe0ad2SBrandon Streiff 183c6fe0ad2SBrandon Streiff struct mv88e6xxx_port_hwtstamp { 184c6fe0ad2SBrandon Streiff /* Port index */ 185c6fe0ad2SBrandon Streiff int port_id; 186c6fe0ad2SBrandon Streiff 187c6fe0ad2SBrandon Streiff /* Timestamping state */ 188c6fe0ad2SBrandon Streiff unsigned long state; 189c6fe0ad2SBrandon Streiff 190c6fe0ad2SBrandon Streiff /* Resources for receive timestamping */ 191c6fe0ad2SBrandon Streiff struct sk_buff_head rx_queue; 192c6fe0ad2SBrandon Streiff struct sk_buff_head rx_queue2; 193c6fe0ad2SBrandon Streiff 194c6fe0ad2SBrandon Streiff /* Resources for transmit timestamping */ 195c6fe0ad2SBrandon Streiff unsigned long tx_tstamp_start; 196c6fe0ad2SBrandon Streiff struct sk_buff *tx_skb; 197c6fe0ad2SBrandon Streiff u16 tx_seq_id; 198c6fe0ad2SBrandon Streiff 199c6fe0ad2SBrandon Streiff /* Current timestamp configuration */ 200c6fe0ad2SBrandon Streiff struct hwtstamp_config tstamp_config; 201c6fe0ad2SBrandon Streiff }; 202c6fe0ad2SBrandon Streiff 203f3a2cd32SVivien Didelot enum mv88e6xxx_policy_mapping { 204f3a2cd32SVivien Didelot MV88E6XXX_POLICY_MAPPING_DA, 205f3a2cd32SVivien Didelot MV88E6XXX_POLICY_MAPPING_SA, 206f3a2cd32SVivien Didelot MV88E6XXX_POLICY_MAPPING_VTU, 207f3a2cd32SVivien Didelot MV88E6XXX_POLICY_MAPPING_ETYPE, 208f3a2cd32SVivien Didelot MV88E6XXX_POLICY_MAPPING_PPPOE, 209f3a2cd32SVivien Didelot MV88E6XXX_POLICY_MAPPING_VBAS, 210f3a2cd32SVivien Didelot MV88E6XXX_POLICY_MAPPING_OPT82, 211f3a2cd32SVivien Didelot MV88E6XXX_POLICY_MAPPING_UDP, 212f3a2cd32SVivien Didelot }; 213f3a2cd32SVivien Didelot 214f3a2cd32SVivien Didelot enum mv88e6xxx_policy_action { 215f3a2cd32SVivien Didelot MV88E6XXX_POLICY_ACTION_NORMAL, 216f3a2cd32SVivien Didelot MV88E6XXX_POLICY_ACTION_MIRROR, 217f3a2cd32SVivien Didelot MV88E6XXX_POLICY_ACTION_TRAP, 218f3a2cd32SVivien Didelot MV88E6XXX_POLICY_ACTION_DISCARD, 219f3a2cd32SVivien Didelot }; 220f3a2cd32SVivien Didelot 221da7dc875SVivien Didelot struct mv88e6xxx_policy { 222da7dc875SVivien Didelot enum mv88e6xxx_policy_mapping mapping; 223da7dc875SVivien Didelot enum mv88e6xxx_policy_action action; 224da7dc875SVivien Didelot struct ethtool_rx_flow_spec fs; 225da7dc875SVivien Didelot u8 addr[ETH_ALEN]; 226da7dc875SVivien Didelot int port; 227da7dc875SVivien Didelot u16 vid; 228da7dc875SVivien Didelot }; 229da7dc875SVivien Didelot 230cda9f4aaSAndrew Lunn struct mv88e6xxx_port { 2317b898469SAndrew Lunn struct mv88e6xxx_chip *chip; 2327b898469SAndrew Lunn int port; 233cda9f4aaSAndrew Lunn u64 serdes_stats[2]; 23465f60e45SAndrew Lunn u64 atu_member_violation; 23565f60e45SAndrew Lunn u64 atu_miss_violation; 23665f60e45SAndrew Lunn u64 atu_full_violation; 23765f60e45SAndrew Lunn u64 vtu_member_violation; 23865f60e45SAndrew Lunn u64 vtu_miss_violation; 239fad58190SRussell King phy_interface_t interface; 2402d2e1dd2SAndrew Lunn u8 cmode; 241f0942e00SIwan R Timmer bool mirror_ingress; 242f0942e00SIwan R Timmer bool mirror_egress; 243f441ed0fSVivien Didelot unsigned int serdes_irq; 2445d1fbdf2SAndrew Lunn char serdes_irq_name[64]; 245bfb25542SAndrew Lunn struct devlink_region *region; 246bfb25542SAndrew Lunn }; 247bfb25542SAndrew Lunn 248bfb25542SAndrew Lunn enum mv88e6xxx_region_id { 249bfb25542SAndrew Lunn MV88E6XXX_REGION_GLOBAL1 = 0, 250bfb25542SAndrew Lunn MV88E6XXX_REGION_GLOBAL2, 251bfb25542SAndrew Lunn MV88E6XXX_REGION_ATU, 252ca4d632aSTobias Waldekranz MV88E6XXX_REGION_VTU, 253bfb25542SAndrew Lunn 254bfb25542SAndrew Lunn _MV88E6XXX_REGION_MAX, 255bfb25542SAndrew Lunn }; 256bfb25542SAndrew Lunn 257bfb25542SAndrew Lunn struct mv88e6xxx_region_priv { 258bfb25542SAndrew Lunn enum mv88e6xxx_region_id id; 259cda9f4aaSAndrew Lunn }; 260cda9f4aaSAndrew Lunn 2614d5f2ba7SVivien Didelot struct mv88e6xxx_chip { 2624d5f2ba7SVivien Didelot const struct mv88e6xxx_info *info; 2634d5f2ba7SVivien Didelot 2644d5f2ba7SVivien Didelot /* The dsa_switch this private structure is related to */ 2654d5f2ba7SVivien Didelot struct dsa_switch *ds; 2664d5f2ba7SVivien Didelot 2674d5f2ba7SVivien Didelot /* The device this structure is associated to */ 2684d5f2ba7SVivien Didelot struct device *dev; 2694d5f2ba7SVivien Didelot 2704d5f2ba7SVivien Didelot /* This mutex protects the access to the switch registers */ 2714d5f2ba7SVivien Didelot struct mutex reg_lock; 2724d5f2ba7SVivien Didelot 2734d5f2ba7SVivien Didelot /* The MII bus and the address on the bus that is used to 2744d5f2ba7SVivien Didelot * communication with the switch 2754d5f2ba7SVivien Didelot */ 2764d5f2ba7SVivien Didelot const struct mv88e6xxx_bus_ops *smi_ops; 2774d5f2ba7SVivien Didelot struct mii_bus *bus; 2784d5f2ba7SVivien Didelot int sw_addr; 2794d5f2ba7SVivien Didelot 2804d5f2ba7SVivien Didelot /* Handles automatic disabling and re-enabling of the PHY 2814d5f2ba7SVivien Didelot * polling unit. 2824d5f2ba7SVivien Didelot */ 2834d5f2ba7SVivien Didelot const struct mv88e6xxx_bus_ops *phy_ops; 2844d5f2ba7SVivien Didelot struct mutex ppu_mutex; 2854d5f2ba7SVivien Didelot int ppu_disabled; 2864d5f2ba7SVivien Didelot struct work_struct ppu_work; 2874d5f2ba7SVivien Didelot struct timer_list ppu_timer; 2884d5f2ba7SVivien Didelot 2894d5f2ba7SVivien Didelot /* This mutex serialises access to the statistics unit. 2904d5f2ba7SVivien Didelot * Hold this mutex over snapshot + dump sequences. 2914d5f2ba7SVivien Didelot */ 2924d5f2ba7SVivien Didelot struct mutex stats_mutex; 2934d5f2ba7SVivien Didelot 2944d5f2ba7SVivien Didelot /* A switch may have a GPIO line tied to its reset pin. Parse 2954d5f2ba7SVivien Didelot * this from the device tree, and use it before performing 2964d5f2ba7SVivien Didelot * switch soft reset. 2974d5f2ba7SVivien Didelot */ 2984d5f2ba7SVivien Didelot struct gpio_desc *reset; 2994d5f2ba7SVivien Didelot 3004d5f2ba7SVivien Didelot /* set to size of eeprom if supported by the switch */ 30100baabe5SAndrew Lunn u32 eeprom_len; 3024d5f2ba7SVivien Didelot 3034d5f2ba7SVivien Didelot /* List of mdio busses */ 3044d5f2ba7SVivien Didelot struct list_head mdios; 3054d5f2ba7SVivien Didelot 306da7dc875SVivien Didelot /* Policy Control List IDs and rules */ 307da7dc875SVivien Didelot struct idr policies; 308da7dc875SVivien Didelot 3094d5f2ba7SVivien Didelot /* There can be two interrupt controllers, which are chained 3104d5f2ba7SVivien Didelot * off a GPIO as interrupt source 3114d5f2ba7SVivien Didelot */ 3124d5f2ba7SVivien Didelot struct mv88e6xxx_irq g1_irq; 3134d5f2ba7SVivien Didelot struct mv88e6xxx_irq g2_irq; 3144d5f2ba7SVivien Didelot int irq; 3155d1fbdf2SAndrew Lunn char irq_name[64]; 3164d5f2ba7SVivien Didelot int device_irq; 3175d1fbdf2SAndrew Lunn char device_irq_name[64]; 3184d5f2ba7SVivien Didelot int watchdog_irq; 3195d1fbdf2SAndrew Lunn char watchdog_irq_name[64]; 320cda9f4aaSAndrew Lunn 3210977644cSAndrew Lunn int atu_prob_irq; 3225d1fbdf2SAndrew Lunn char atu_prob_irq_name[64]; 32362eb1162SAndrew Lunn int vtu_prob_irq; 3245d1fbdf2SAndrew Lunn char vtu_prob_irq_name[64]; 325294d711eSAndrew Lunn struct kthread_worker *kworker; 326294d711eSAndrew Lunn struct kthread_delayed_work irq_poll_work; 3272fa8d3afSBrandon Streiff 328a73ccd61SBrandon Streiff /* GPIO resources */ 329a73ccd61SBrandon Streiff u8 gpio_data[2]; 330a73ccd61SBrandon Streiff 3312fa8d3afSBrandon Streiff /* This cyclecounter abstracts the switch PTP time. 3322fa8d3afSBrandon Streiff * reg_lock must be held for any operation that read()s. 3332fa8d3afSBrandon Streiff */ 3342fa8d3afSBrandon Streiff struct cyclecounter tstamp_cc; 3352fa8d3afSBrandon Streiff struct timecounter tstamp_tc; 3362fa8d3afSBrandon Streiff struct delayed_work overflow_work; 3372fa8d3afSBrandon Streiff 3382fa8d3afSBrandon Streiff struct ptp_clock *ptp_clock; 3392fa8d3afSBrandon Streiff struct ptp_clock_info ptp_clock_info; 3404eb3be29SBrandon Streiff struct delayed_work tai_event_work; 3414eb3be29SBrandon Streiff struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 3424eb3be29SBrandon Streiff u16 trig_config; 3434eb3be29SBrandon Streiff u16 evcap_config; 344e2294a8bSAndrew Lunn u16 enable_count; 345c6fe0ad2SBrandon Streiff 346f0942e00SIwan R Timmer /* Current ingress and egress monitor ports */ 347f0942e00SIwan R Timmer int egress_dest_port; 348f0942e00SIwan R Timmer int ingress_dest_port; 349f0942e00SIwan R Timmer 350c6fe0ad2SBrandon Streiff /* Per-port timestamping resources. */ 351c6fe0ad2SBrandon Streiff struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 352cda9f4aaSAndrew Lunn 353cda9f4aaSAndrew Lunn /* Array of port structures. */ 354cda9f4aaSAndrew Lunn struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 355bfb25542SAndrew Lunn 356bfb25542SAndrew Lunn /* devlink regions */ 357bfb25542SAndrew Lunn struct devlink_region *regions[_MV88E6XXX_REGION_MAX]; 3584d5f2ba7SVivien Didelot }; 3594d5f2ba7SVivien Didelot 3604d5f2ba7SVivien Didelot struct mv88e6xxx_bus_ops { 3614d5f2ba7SVivien Didelot int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 3624d5f2ba7SVivien Didelot int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 3634d5f2ba7SVivien Didelot }; 3644d5f2ba7SVivien Didelot 3654d5f2ba7SVivien Didelot struct mv88e6xxx_mdio_bus { 3664d5f2ba7SVivien Didelot struct mii_bus *bus; 3674d5f2ba7SVivien Didelot struct mv88e6xxx_chip *chip; 3684d5f2ba7SVivien Didelot struct list_head list; 3694d5f2ba7SVivien Didelot bool external; 3704d5f2ba7SVivien Didelot }; 3714d5f2ba7SVivien Didelot 3724d5f2ba7SVivien Didelot struct mv88e6xxx_ops { 373ea89098eSAndrew Lunn /* Switch Setup Errata, called early in the switch setup to 374ea89098eSAndrew Lunn * allow any errata actions to be performed 375ea89098eSAndrew Lunn */ 376ea89098eSAndrew Lunn int (*setup_errata)(struct mv88e6xxx_chip *chip); 377ea89098eSAndrew Lunn 37893e18d61SVivien Didelot int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 37993e18d61SVivien Didelot int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 38093e18d61SVivien Didelot 381cd8da8bbSVivien Didelot /* Ingress Rate Limit unit (IRL) operations */ 382cd8da8bbSVivien Didelot int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 383cd8da8bbSVivien Didelot 3844d5f2ba7SVivien Didelot int (*get_eeprom)(struct mv88e6xxx_chip *chip, 3854d5f2ba7SVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 3864d5f2ba7SVivien Didelot int (*set_eeprom)(struct mv88e6xxx_chip *chip, 3874d5f2ba7SVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 3884d5f2ba7SVivien Didelot 3894d5f2ba7SVivien Didelot int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 3904d5f2ba7SVivien Didelot 3914d5f2ba7SVivien Didelot int (*phy_read)(struct mv88e6xxx_chip *chip, 3924d5f2ba7SVivien Didelot struct mii_bus *bus, 3934d5f2ba7SVivien Didelot int addr, int reg, u16 *val); 3944d5f2ba7SVivien Didelot int (*phy_write)(struct mv88e6xxx_chip *chip, 3954d5f2ba7SVivien Didelot struct mii_bus *bus, 3964d5f2ba7SVivien Didelot int addr, int reg, u16 val); 3974d5f2ba7SVivien Didelot 3989e907d73SVivien Didelot /* Priority Override Table operations */ 3999e907d73SVivien Didelot int (*pot_clear)(struct mv88e6xxx_chip *chip); 4009e907d73SVivien Didelot 4014d5f2ba7SVivien Didelot /* PHY Polling Unit (PPU) operations */ 4024d5f2ba7SVivien Didelot int (*ppu_enable)(struct mv88e6xxx_chip *chip); 4034d5f2ba7SVivien Didelot int (*ppu_disable)(struct mv88e6xxx_chip *chip); 4044d5f2ba7SVivien Didelot 4054d5f2ba7SVivien Didelot /* Switch Software Reset */ 4064d5f2ba7SVivien Didelot int (*reset)(struct mv88e6xxx_chip *chip); 4074d5f2ba7SVivien Didelot 4084d5f2ba7SVivien Didelot /* RGMII Receive/Transmit Timing Control 4094d5f2ba7SVivien Didelot * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 4104d5f2ba7SVivien Didelot */ 4114d5f2ba7SVivien Didelot int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 4124d5f2ba7SVivien Didelot phy_interface_t mode); 4134d5f2ba7SVivien Didelot 4144d5f2ba7SVivien Didelot #define LINK_FORCED_DOWN 0 4154d5f2ba7SVivien Didelot #define LINK_FORCED_UP 1 4164d5f2ba7SVivien Didelot #define LINK_UNFORCED -2 4174d5f2ba7SVivien Didelot 4184d5f2ba7SVivien Didelot /* Port's MAC link state 4194d5f2ba7SVivien Didelot * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 4204d5f2ba7SVivien Didelot * or LINK_UNFORCED for normal link detection. 4214d5f2ba7SVivien Didelot */ 4224d5f2ba7SVivien Didelot int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 4234d5f2ba7SVivien Didelot 4244efe7662SChris Packham /* Synchronise the port link state with that of the SERDES 4254efe7662SChris Packham */ 4264efe7662SChris Packham int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 4274efe7662SChris Packham 42854186b91SAndrew Lunn #define PAUSE_ON 1 42954186b91SAndrew Lunn #define PAUSE_OFF 0 43054186b91SAndrew Lunn 43154186b91SAndrew Lunn /* Enable/disable sending Pause */ 43254186b91SAndrew Lunn int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 43354186b91SAndrew Lunn int pause); 43454186b91SAndrew Lunn 4354d5f2ba7SVivien Didelot #define SPEED_MAX INT_MAX 4364d5f2ba7SVivien Didelot #define SPEED_UNFORCED -2 437f365c6f7SRussell King #define DUPLEX_UNFORCED -2 4384d5f2ba7SVivien Didelot 439f365c6f7SRussell King /* Port's MAC speed (in Mbps) and MAC duplex mode 4404d5f2ba7SVivien Didelot * 4414d5f2ba7SVivien Didelot * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 4424d5f2ba7SVivien Didelot * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 443f365c6f7SRussell King * 444f365c6f7SRussell King * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 445f365c6f7SRussell King * or DUPLEX_UNFORCED for normal duplex detection. 4464d5f2ba7SVivien Didelot */ 447f365c6f7SRussell King int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port, 448f365c6f7SRussell King int speed, int duplex); 4494d5f2ba7SVivien Didelot 4507cbbee05SAndrew Lunn /* What interface mode should be used for maximum speed? */ 4517cbbee05SAndrew Lunn phy_interface_t (*port_max_speed_mode)(int port); 4527cbbee05SAndrew Lunn 4534d5f2ba7SVivien Didelot int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 4544d5f2ba7SVivien Didelot 455f3a2cd32SVivien Didelot int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port, 456f3a2cd32SVivien Didelot enum mv88e6xxx_policy_mapping mapping, 457f3a2cd32SVivien Didelot enum mv88e6xxx_policy_action action); 458f3a2cd32SVivien Didelot 4594d5f2ba7SVivien Didelot int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 4604d5f2ba7SVivien Didelot enum mv88e6xxx_frame_mode mode); 461a8b659e7SVladimir Oltean int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port, 462a8b659e7SVladimir Oltean bool unicast); 463a8b659e7SVladimir Oltean int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port, 464a8b659e7SVladimir Oltean bool multicast); 4654d5f2ba7SVivien Didelot int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 4664d5f2ba7SVivien Didelot u16 etype); 467cd782656SVivien Didelot int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 468cd782656SVivien Didelot size_t size); 4694d5f2ba7SVivien Didelot 4704d5f2ba7SVivien Didelot int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 4710898432cSVivien Didelot int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 4720898432cSVivien Didelot u8 out); 4734d5f2ba7SVivien Didelot int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 4744d5f2ba7SVivien Didelot int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 475121b8fe2SHubert Feurstein int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port); 4764d5f2ba7SVivien Didelot 4774d5f2ba7SVivien Didelot /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 4784d5f2ba7SVivien Didelot * Some chips allow this to be configured on specific ports. 4794d5f2ba7SVivien Didelot */ 4804d5f2ba7SVivien Didelot int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 4814d5f2ba7SVivien Didelot phy_interface_t mode); 4822d2e1dd2SAndrew Lunn int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 4834d5f2ba7SVivien Didelot 4844d5f2ba7SVivien Didelot /* Some devices have a per port register indicating what is 4854d5f2ba7SVivien Didelot * the upstream port this port should forward to. 4864d5f2ba7SVivien Didelot */ 4874d5f2ba7SVivien Didelot int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 4884d5f2ba7SVivien Didelot int upstream_port); 4894d5f2ba7SVivien Didelot 4904d5f2ba7SVivien Didelot /* Snapshot the statistics for a port. The statistics can then 4914d5f2ba7SVivien Didelot * be read back a leisure but still with a consistent view. 4924d5f2ba7SVivien Didelot */ 4934d5f2ba7SVivien Didelot int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 4944d5f2ba7SVivien Didelot 4954d5f2ba7SVivien Didelot /* Set the histogram mode for statistics, when the control registers 4964d5f2ba7SVivien Didelot * are separated out of the STATS_OP register. 4974d5f2ba7SVivien Didelot */ 4984d5f2ba7SVivien Didelot int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 4994d5f2ba7SVivien Didelot 5004d5f2ba7SVivien Didelot /* Return the number of strings describing statistics */ 5014d5f2ba7SVivien Didelot int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 502436fe17dSAndrew Lunn int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 503436fe17dSAndrew Lunn int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 5044d5f2ba7SVivien Didelot uint64_t *data); 505fa8d1179SVivien Didelot int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 5065c74c54cSIwan R Timmer int (*set_egress_port)(struct mv88e6xxx_chip *chip, 5075c74c54cSIwan R Timmer enum mv88e6xxx_egress_direction direction, 5085c74c54cSIwan R Timmer int port); 50902317e68SVivien Didelot 51002317e68SVivien Didelot #define MV88E6XXX_CASCADE_PORT_NONE 0xe 51102317e68SVivien Didelot #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 51202317e68SVivien Didelot 51302317e68SVivien Didelot int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 51402317e68SVivien Didelot 5154d5f2ba7SVivien Didelot const struct mv88e6xxx_irq_ops *watchdog_ops; 5164d5f2ba7SVivien Didelot 5174d5f2ba7SVivien Didelot int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 5184d5f2ba7SVivien Didelot 5194d5f2ba7SVivien Didelot /* Power on/off a SERDES interface */ 520193c5b26SPavana Sharma int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, int lane, 521dc272f60SVivien Didelot bool up); 5224d5f2ba7SVivien Didelot 52317deaf5cSMarek Behún /* SERDES lane mapping */ 524193c5b26SPavana Sharma int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); 52517deaf5cSMarek Behún 526a5a6858bSRussell King int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port, 527193c5b26SPavana Sharma int lane, struct phylink_link_state *state); 528a5a6858bSRussell King int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port, 529193c5b26SPavana Sharma int lane, unsigned int mode, 530a5a6858bSRussell King phy_interface_t interface, 531a5a6858bSRussell King const unsigned long *advertise); 532a5a6858bSRussell King int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port, 533193c5b26SPavana Sharma int lane); 534a5a6858bSRussell King int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port, 535193c5b26SPavana Sharma int lane, int speed, int duplex); 536a5a6858bSRussell King 537efd1ba6aSAndrew Lunn /* SERDES interrupt handling */ 5384241ef52SVivien Didelot unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, 5394241ef52SVivien Didelot int port); 540193c5b26SPavana Sharma int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, int lane, 54161a46b41SVivien Didelot bool enable); 542907b9b9fSVivien Didelot irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port, 543193c5b26SPavana Sharma int lane); 544efd1ba6aSAndrew Lunn 545436fe17dSAndrew Lunn /* Statistics from the SERDES interface */ 546436fe17dSAndrew Lunn int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 54765f60e45SAndrew Lunn int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 548436fe17dSAndrew Lunn uint8_t *data); 54965f60e45SAndrew Lunn int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 550436fe17dSAndrew Lunn uint64_t *data); 551436fe17dSAndrew Lunn 5520d30bbd0SAndrew Lunn /* SERDES registers for ethtool */ 5530d30bbd0SAndrew Lunn int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port); 5540d30bbd0SAndrew Lunn void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port, 5550d30bbd0SAndrew Lunn void *_p); 5560d30bbd0SAndrew Lunn 55723e8b470SAndrew Lunn /* Address Translation Unit operations */ 55823e8b470SAndrew Lunn int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash); 55923e8b470SAndrew Lunn int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash); 56023e8b470SAndrew Lunn 5614d5f2ba7SVivien Didelot /* VLAN Translation Unit operations */ 5624d5f2ba7SVivien Didelot int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 5634d5f2ba7SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 5644d5f2ba7SVivien Didelot int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 5654d5f2ba7SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 5660d632c3dSBrandon Streiff 567a73ccd61SBrandon Streiff /* GPIO operations */ 568a73ccd61SBrandon Streiff const struct mv88e6xxx_gpio_ops *gpio_ops; 569a73ccd61SBrandon Streiff 5700d632c3dSBrandon Streiff /* Interface to the AVB/PTP registers */ 5710d632c3dSBrandon Streiff const struct mv88e6xxx_avb_ops *avb_ops; 5729e5baf9bSVivien Didelot 5739e5baf9bSVivien Didelot /* Remote Management Unit operations */ 5749e5baf9bSVivien Didelot int (*rmu_disable)(struct mv88e6xxx_chip *chip); 5756d2ac8eeSAndrew Lunn 5766d2ac8eeSAndrew Lunn /* Precision Time Protocol operations */ 5776d2ac8eeSAndrew Lunn const struct mv88e6xxx_ptp_ops *ptp_ops; 5786c422e34SRussell King 5796c422e34SRussell King /* Phylink */ 5806c422e34SRussell King void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port, 5816c422e34SRussell King unsigned long *mask, 5826c422e34SRussell King struct phylink_link_state *state); 5831baf0facSChris Packham 5841baf0facSChris Packham /* Max Frame Size */ 5851baf0facSChris Packham int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu); 5864d5f2ba7SVivien Didelot }; 5874d5f2ba7SVivien Didelot 5884d5f2ba7SVivien Didelot struct mv88e6xxx_irq_ops { 5894d5f2ba7SVivien Didelot /* Action to be performed when the interrupt happens */ 5904d5f2ba7SVivien Didelot int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 5914d5f2ba7SVivien Didelot /* Setup the hardware to generate the interrupt */ 5924d5f2ba7SVivien Didelot int (*irq_setup)(struct mv88e6xxx_chip *chip); 5934d5f2ba7SVivien Didelot /* Reset the hardware to stop generating the interrupt */ 5944d5f2ba7SVivien Didelot void (*irq_free)(struct mv88e6xxx_chip *chip); 5954d5f2ba7SVivien Didelot }; 5964d5f2ba7SVivien Didelot 597a73ccd61SBrandon Streiff struct mv88e6xxx_gpio_ops { 598a73ccd61SBrandon Streiff /* Get/set data on GPIO pin */ 599a73ccd61SBrandon Streiff int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 600a73ccd61SBrandon Streiff int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 601a73ccd61SBrandon Streiff int value); 602a73ccd61SBrandon Streiff 603a73ccd61SBrandon Streiff /* get/set GPIO direction */ 604a73ccd61SBrandon Streiff int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 605a73ccd61SBrandon Streiff int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 606a73ccd61SBrandon Streiff bool input); 607a73ccd61SBrandon Streiff 608a73ccd61SBrandon Streiff /* get/set GPIO pin control */ 609a73ccd61SBrandon Streiff int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 610a73ccd61SBrandon Streiff int *func); 611a73ccd61SBrandon Streiff int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 612a73ccd61SBrandon Streiff int func); 613a73ccd61SBrandon Streiff }; 614a73ccd61SBrandon Streiff 6150d632c3dSBrandon Streiff struct mv88e6xxx_avb_ops { 6160d632c3dSBrandon Streiff /* Access port-scoped Precision Time Protocol registers */ 6170d632c3dSBrandon Streiff int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 6180d632c3dSBrandon Streiff u16 *data, int len); 6190d632c3dSBrandon Streiff int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 6200d632c3dSBrandon Streiff u16 data); 6210d632c3dSBrandon Streiff 6220d632c3dSBrandon Streiff /* Access global Precision Time Protocol registers */ 6230d632c3dSBrandon Streiff int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 6240d632c3dSBrandon Streiff int len); 6250d632c3dSBrandon Streiff int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 6260d632c3dSBrandon Streiff 6270d632c3dSBrandon Streiff /* Access global Time Application Interface registers */ 6280d632c3dSBrandon Streiff int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 6290d632c3dSBrandon Streiff int len); 6300d632c3dSBrandon Streiff int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 6310d632c3dSBrandon Streiff }; 6320d632c3dSBrandon Streiff 6336d2ac8eeSAndrew Lunn struct mv88e6xxx_ptp_ops { 6346d2ac8eeSAndrew Lunn u64 (*clock_read)(const struct cyclecounter *cc); 6356d2ac8eeSAndrew Lunn int (*ptp_enable)(struct ptp_clock_info *ptp, 6366d2ac8eeSAndrew Lunn struct ptp_clock_request *rq, int on); 6376d2ac8eeSAndrew Lunn int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 6386d2ac8eeSAndrew Lunn enum ptp_pin_function func, unsigned int chan); 6396d2ac8eeSAndrew Lunn void (*event_work)(struct work_struct *ugly); 640ffc705deSAndrew Lunn int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 641ffc705deSAndrew Lunn int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 642e2294a8bSAndrew Lunn int (*global_enable)(struct mv88e6xxx_chip *chip); 643e2294a8bSAndrew Lunn int (*global_disable)(struct mv88e6xxx_chip *chip); 6446d2ac8eeSAndrew Lunn int n_ext_ts; 645ffc705deSAndrew Lunn int arr0_sts_reg; 646ffc705deSAndrew Lunn int arr1_sts_reg; 647ffc705deSAndrew Lunn int dep_sts_reg; 64848cb5e03SAndrew Lunn u32 rx_filters; 64971509614SHubert Feurstein u32 cc_shift; 65071509614SHubert Feurstein u32 cc_mult; 65171509614SHubert Feurstein u32 cc_mult_num; 65271509614SHubert Feurstein u32 cc_mult_dem; 6536d2ac8eeSAndrew Lunn }; 6546d2ac8eeSAndrew Lunn 6554d5f2ba7SVivien Didelot #define STATS_TYPE_PORT BIT(0) 6564d5f2ba7SVivien Didelot #define STATS_TYPE_BANK0 BIT(1) 6574d5f2ba7SVivien Didelot #define STATS_TYPE_BANK1 BIT(2) 6584d5f2ba7SVivien Didelot 6594d5f2ba7SVivien Didelot struct mv88e6xxx_hw_stat { 6604d5f2ba7SVivien Didelot char string[ETH_GSTRING_LEN]; 661cda9f4aaSAndrew Lunn size_t size; 6624d5f2ba7SVivien Didelot int reg; 6634d5f2ba7SVivien Didelot int type; 6644d5f2ba7SVivien Didelot }; 6654d5f2ba7SVivien Didelot 6664d5f2ba7SVivien Didelot static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 6674d5f2ba7SVivien Didelot { 6684d5f2ba7SVivien Didelot return chip->info->pvt; 6694d5f2ba7SVivien Didelot } 6704d5f2ba7SVivien Didelot 671b80dc51bSTobias Waldekranz static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip) 672b80dc51bSTobias Waldekranz { 673b80dc51bSTobias Waldekranz return !!chip->info->global2_addr; 674b80dc51bSTobias Waldekranz } 675b80dc51bSTobias Waldekranz 6764d5f2ba7SVivien Didelot static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 6774d5f2ba7SVivien Didelot { 6784d5f2ba7SVivien Didelot return chip->info->num_databases; 6794d5f2ba7SVivien Didelot } 6804d5f2ba7SVivien Didelot 681d9ea5620SAndrew Lunn static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip) 682d9ea5620SAndrew Lunn { 683d9ea5620SAndrew Lunn return chip->info->num_macs; 684d9ea5620SAndrew Lunn } 685d9ea5620SAndrew Lunn 6864d5f2ba7SVivien Didelot static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 6874d5f2ba7SVivien Didelot { 6884d5f2ba7SVivien Didelot return chip->info->num_ports; 6894d5f2ba7SVivien Didelot } 6904d5f2ba7SVivien Didelot 691e545f865STobias Waldekranz static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip) 692e545f865STobias Waldekranz { 693e545f865STobias Waldekranz return chip->info->max_vid; 694e545f865STobias Waldekranz } 695e545f865STobias Waldekranz 6964d5f2ba7SVivien Didelot static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 6974d5f2ba7SVivien Didelot { 698f1931164SAndrew Lunn return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0); 6994d5f2ba7SVivien Didelot } 7004d5f2ba7SVivien Didelot 701a73ccd61SBrandon Streiff static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 702a73ccd61SBrandon Streiff { 703a73ccd61SBrandon Streiff return chip->info->num_gpio; 704a73ccd61SBrandon Streiff } 705a73ccd61SBrandon Streiff 706c857486aSHubert Feurstein static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port) 707c857486aSHubert Feurstein { 708c857486aSHubert Feurstein return (chip->info->invalid_port_mask & BIT(port)) != 0; 709c857486aSHubert Feurstein } 710c857486aSHubert Feurstein 7114d5f2ba7SVivien Didelot int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 7124d5f2ba7SVivien Didelot int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 713683f2244SVivien Didelot int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 714683f2244SVivien Didelot u16 mask, u16 val); 71519fb7f69SVivien Didelot int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 71619fb7f69SVivien Didelot int bit, int val); 7174d5f2ba7SVivien Didelot struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 7184d5f2ba7SVivien Didelot 719c9acece0SRasmus Villemoes static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) 720c9acece0SRasmus Villemoes { 721c9acece0SRasmus Villemoes mutex_lock(&chip->reg_lock); 722c9acece0SRasmus Villemoes } 723c9acece0SRasmus Villemoes 724c9acece0SRasmus Villemoes static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) 725c9acece0SRasmus Villemoes { 726c9acece0SRasmus Villemoes mutex_unlock(&chip->reg_lock); 727c9acece0SRasmus Villemoes } 728c9acece0SRasmus Villemoes 72990b6dbdfSAndrew Lunn int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap); 73090b6dbdfSAndrew Lunn 7314d5f2ba7SVivien Didelot #endif /* _MV88E6XXX_CHIP_H */ 732