12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 24d5f2ba7SVivien Didelot /* 34d5f2ba7SVivien Didelot * Marvell 88E6xxx Ethernet switch single-chip definition 44d5f2ba7SVivien Didelot * 54d5f2ba7SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 64d5f2ba7SVivien Didelot */ 74d5f2ba7SVivien Didelot 84d5f2ba7SVivien Didelot #ifndef _MV88E6XXX_CHIP_H 94d5f2ba7SVivien Didelot #define _MV88E6XXX_CHIP_H 104d5f2ba7SVivien Didelot 11da7dc875SVivien Didelot #include <linux/idr.h> 124d5f2ba7SVivien Didelot #include <linux/if_vlan.h> 134d5f2ba7SVivien Didelot #include <linux/irq.h> 144d5f2ba7SVivien Didelot #include <linux/gpio/consumer.h> 15294d711eSAndrew Lunn #include <linux/kthread.h> 164d5f2ba7SVivien Didelot #include <linux/phy.h> 172fa8d3afSBrandon Streiff #include <linux/ptp_clock_kernel.h> 182fa8d3afSBrandon Streiff #include <linux/timecounter.h> 194d5f2ba7SVivien Didelot #include <net/dsa.h> 204d5f2ba7SVivien Didelot 214d5f2ba7SVivien Didelot #define MV88E6XXX_N_FID 4096 224d5f2ba7SVivien Didelot 234d5f2ba7SVivien Didelot /* PVT limits for 4-bit port and 5-bit switch */ 244d5f2ba7SVivien Didelot #define MV88E6XXX_MAX_PVT_SWITCHES 32 254d5f2ba7SVivien Didelot #define MV88E6XXX_MAX_PVT_PORTS 16 264d5f2ba7SVivien Didelot 27a73ccd61SBrandon Streiff #define MV88E6XXX_MAX_GPIO 16 28a73ccd61SBrandon Streiff 2931bef4e9SVivien Didelot enum mv88e6xxx_egress_mode { 3031bef4e9SVivien Didelot MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3131bef4e9SVivien Didelot MV88E6XXX_EGRESS_MODE_UNTAGGED, 3231bef4e9SVivien Didelot MV88E6XXX_EGRESS_MODE_TAGGED, 3331bef4e9SVivien Didelot MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3431bef4e9SVivien Didelot }; 3531bef4e9SVivien Didelot 365c74c54cSIwan R Timmer enum mv88e6xxx_egress_direction { 375c74c54cSIwan R Timmer MV88E6XXX_EGRESS_DIR_INGRESS, 385c74c54cSIwan R Timmer MV88E6XXX_EGRESS_DIR_EGRESS, 395c74c54cSIwan R Timmer }; 405c74c54cSIwan R Timmer 414d5f2ba7SVivien Didelot enum mv88e6xxx_frame_mode { 424d5f2ba7SVivien Didelot MV88E6XXX_FRAME_MODE_NORMAL, 434d5f2ba7SVivien Didelot MV88E6XXX_FRAME_MODE_DSA, 444d5f2ba7SVivien Didelot MV88E6XXX_FRAME_MODE_PROVIDER, 454d5f2ba7SVivien Didelot MV88E6XXX_FRAME_MODE_ETHERTYPE, 464d5f2ba7SVivien Didelot }; 474d5f2ba7SVivien Didelot 484d5f2ba7SVivien Didelot /* List of supported models */ 494d5f2ba7SVivien Didelot enum mv88e6xxx_model { 504d5f2ba7SVivien Didelot MV88E6085, 514d5f2ba7SVivien Didelot MV88E6095, 524d5f2ba7SVivien Didelot MV88E6097, 534d5f2ba7SVivien Didelot MV88E6123, 544d5f2ba7SVivien Didelot MV88E6131, 554d5f2ba7SVivien Didelot MV88E6141, 564d5f2ba7SVivien Didelot MV88E6161, 574d5f2ba7SVivien Didelot MV88E6165, 584d5f2ba7SVivien Didelot MV88E6171, 594d5f2ba7SVivien Didelot MV88E6172, 604d5f2ba7SVivien Didelot MV88E6175, 614d5f2ba7SVivien Didelot MV88E6176, 624d5f2ba7SVivien Didelot MV88E6185, 634d5f2ba7SVivien Didelot MV88E6190, 644d5f2ba7SVivien Didelot MV88E6190X, 654d5f2ba7SVivien Didelot MV88E6191, 6649022647SHubert Feurstein MV88E6220, 674d5f2ba7SVivien Didelot MV88E6240, 681f71836fSRasmus Villemoes MV88E6250, 694d5f2ba7SVivien Didelot MV88E6290, 704d5f2ba7SVivien Didelot MV88E6320, 714d5f2ba7SVivien Didelot MV88E6321, 724d5f2ba7SVivien Didelot MV88E6341, 734d5f2ba7SVivien Didelot MV88E6350, 744d5f2ba7SVivien Didelot MV88E6351, 754d5f2ba7SVivien Didelot MV88E6352, 764d5f2ba7SVivien Didelot MV88E6390, 774d5f2ba7SVivien Didelot MV88E6390X, 784d5f2ba7SVivien Didelot }; 794d5f2ba7SVivien Didelot 804d5f2ba7SVivien Didelot enum mv88e6xxx_family { 814d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_NONE, 824d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 834d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 844d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 854d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 864d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 8749022647SHubert Feurstein MV88E6XXX_FAMILY_6250, /* 6220 6250 */ 884d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 894d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 904d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 914d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 924d5f2ba7SVivien Didelot MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 934d5f2ba7SVivien Didelot }; 944d5f2ba7SVivien Didelot 954d5f2ba7SVivien Didelot struct mv88e6xxx_ops; 964d5f2ba7SVivien Didelot 974d5f2ba7SVivien Didelot struct mv88e6xxx_info { 984d5f2ba7SVivien Didelot enum mv88e6xxx_family family; 994d5f2ba7SVivien Didelot u16 prod_num; 1004d5f2ba7SVivien Didelot const char *name; 1014d5f2ba7SVivien Didelot unsigned int num_databases; 102d9ea5620SAndrew Lunn unsigned int num_macs; 1034d5f2ba7SVivien Didelot unsigned int num_ports; 104bc393155SAndrew Lunn unsigned int num_internal_phys; 105a73ccd61SBrandon Streiff unsigned int num_gpio; 1064d5f2ba7SVivien Didelot unsigned int max_vid; 1074d5f2ba7SVivien Didelot unsigned int port_base_addr; 1089255bacdSAndrew Lunn unsigned int phy_base_addr; 1094d5f2ba7SVivien Didelot unsigned int global1_addr; 1109069c13aSVivien Didelot unsigned int global2_addr; 1114d5f2ba7SVivien Didelot unsigned int age_time_coeff; 1124d5f2ba7SVivien Didelot unsigned int g1_irqs; 113d6c5e6afSVivien Didelot unsigned int g2_irqs; 1144d5f2ba7SVivien Didelot bool pvt; 115b3e05aa1SVivien Didelot 116c857486aSHubert Feurstein /* Mark certain ports as invalid. This is required for example for the 117c857486aSHubert Feurstein * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the 118c857486aSHubert Feurstein * ports 2-4 are not routet to pins. 119c857486aSHubert Feurstein */ 120c857486aSHubert Feurstein unsigned int invalid_port_mask; 121b3e05aa1SVivien Didelot /* Multi-chip Addressing Mode. 122b3e05aa1SVivien Didelot * Some chips respond to only 2 registers of its own SMI device address 123b3e05aa1SVivien Didelot * when it is non-zero, and use indirect access to internal registers. 124b3e05aa1SVivien Didelot */ 125b3e05aa1SVivien Didelot bool multi_chip; 126f30a19b8SRasmus Villemoes /* Dual-chip Addressing Mode 127f30a19b8SRasmus Villemoes * Some chips respond to only half of the 32 SMI addresses, 128f30a19b8SRasmus Villemoes * allowing two to coexist on the same SMI interface. 129f30a19b8SRasmus Villemoes */ 130f30a19b8SRasmus Villemoes bool dual_chip; 131f30a19b8SRasmus Villemoes 1324d5f2ba7SVivien Didelot enum dsa_tag_protocol tag_protocol; 1334d5f2ba7SVivien Didelot 1344d5f2ba7SVivien Didelot /* Mask for FromPort and ToPort value of PortVec used in ATU Move 1354d5f2ba7SVivien Didelot * operation. 0 means that the ATU Move operation is not supported. 1364d5f2ba7SVivien Didelot */ 1374d5f2ba7SVivien Didelot u8 atu_move_port_mask; 1384d5f2ba7SVivien Didelot const struct mv88e6xxx_ops *ops; 1392fa8d3afSBrandon Streiff 1402fa8d3afSBrandon Streiff /* Supports PTP */ 1412fa8d3afSBrandon Streiff bool ptp_support; 1424d5f2ba7SVivien Didelot }; 1434d5f2ba7SVivien Didelot 1444d5f2ba7SVivien Didelot struct mv88e6xxx_atu_entry { 1454d5f2ba7SVivien Didelot u8 state; 1464d5f2ba7SVivien Didelot bool trunk; 1474d5f2ba7SVivien Didelot u16 portvec; 1484d5f2ba7SVivien Didelot u8 mac[ETH_ALEN]; 1494d5f2ba7SVivien Didelot }; 1504d5f2ba7SVivien Didelot 1514d5f2ba7SVivien Didelot struct mv88e6xxx_vtu_entry { 1524d5f2ba7SVivien Didelot u16 vid; 1534d5f2ba7SVivien Didelot u16 fid; 1544d5f2ba7SVivien Didelot u8 sid; 1554d5f2ba7SVivien Didelot bool valid; 1564d5f2ba7SVivien Didelot u8 member[DSA_MAX_PORTS]; 1574d5f2ba7SVivien Didelot u8 state[DSA_MAX_PORTS]; 1584d5f2ba7SVivien Didelot }; 1594d5f2ba7SVivien Didelot 1604d5f2ba7SVivien Didelot struct mv88e6xxx_bus_ops; 1614d5f2ba7SVivien Didelot struct mv88e6xxx_irq_ops; 162a73ccd61SBrandon Streiff struct mv88e6xxx_gpio_ops; 1630d632c3dSBrandon Streiff struct mv88e6xxx_avb_ops; 1646d2ac8eeSAndrew Lunn struct mv88e6xxx_ptp_ops; 1654d5f2ba7SVivien Didelot 1664d5f2ba7SVivien Didelot struct mv88e6xxx_irq { 1674d5f2ba7SVivien Didelot u16 masked; 1684d5f2ba7SVivien Didelot struct irq_chip chip; 1694d5f2ba7SVivien Didelot struct irq_domain *domain; 170f1931164SAndrew Lunn int nirqs; 1714d5f2ba7SVivien Didelot }; 1724d5f2ba7SVivien Didelot 173c6fe0ad2SBrandon Streiff /* state flags for mv88e6xxx_port_hwtstamp::state */ 174c6fe0ad2SBrandon Streiff enum { 175c6fe0ad2SBrandon Streiff MV88E6XXX_HWTSTAMP_ENABLED, 176c6fe0ad2SBrandon Streiff MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 177c6fe0ad2SBrandon Streiff }; 178c6fe0ad2SBrandon Streiff 179c6fe0ad2SBrandon Streiff struct mv88e6xxx_port_hwtstamp { 180c6fe0ad2SBrandon Streiff /* Port index */ 181c6fe0ad2SBrandon Streiff int port_id; 182c6fe0ad2SBrandon Streiff 183c6fe0ad2SBrandon Streiff /* Timestamping state */ 184c6fe0ad2SBrandon Streiff unsigned long state; 185c6fe0ad2SBrandon Streiff 186c6fe0ad2SBrandon Streiff /* Resources for receive timestamping */ 187c6fe0ad2SBrandon Streiff struct sk_buff_head rx_queue; 188c6fe0ad2SBrandon Streiff struct sk_buff_head rx_queue2; 189c6fe0ad2SBrandon Streiff 190c6fe0ad2SBrandon Streiff /* Resources for transmit timestamping */ 191c6fe0ad2SBrandon Streiff unsigned long tx_tstamp_start; 192c6fe0ad2SBrandon Streiff struct sk_buff *tx_skb; 193c6fe0ad2SBrandon Streiff u16 tx_seq_id; 194c6fe0ad2SBrandon Streiff 195c6fe0ad2SBrandon Streiff /* Current timestamp configuration */ 196c6fe0ad2SBrandon Streiff struct hwtstamp_config tstamp_config; 197c6fe0ad2SBrandon Streiff }; 198c6fe0ad2SBrandon Streiff 199f3a2cd32SVivien Didelot enum mv88e6xxx_policy_mapping { 200f3a2cd32SVivien Didelot MV88E6XXX_POLICY_MAPPING_DA, 201f3a2cd32SVivien Didelot MV88E6XXX_POLICY_MAPPING_SA, 202f3a2cd32SVivien Didelot MV88E6XXX_POLICY_MAPPING_VTU, 203f3a2cd32SVivien Didelot MV88E6XXX_POLICY_MAPPING_ETYPE, 204f3a2cd32SVivien Didelot MV88E6XXX_POLICY_MAPPING_PPPOE, 205f3a2cd32SVivien Didelot MV88E6XXX_POLICY_MAPPING_VBAS, 206f3a2cd32SVivien Didelot MV88E6XXX_POLICY_MAPPING_OPT82, 207f3a2cd32SVivien Didelot MV88E6XXX_POLICY_MAPPING_UDP, 208f3a2cd32SVivien Didelot }; 209f3a2cd32SVivien Didelot 210f3a2cd32SVivien Didelot enum mv88e6xxx_policy_action { 211f3a2cd32SVivien Didelot MV88E6XXX_POLICY_ACTION_NORMAL, 212f3a2cd32SVivien Didelot MV88E6XXX_POLICY_ACTION_MIRROR, 213f3a2cd32SVivien Didelot MV88E6XXX_POLICY_ACTION_TRAP, 214f3a2cd32SVivien Didelot MV88E6XXX_POLICY_ACTION_DISCARD, 215f3a2cd32SVivien Didelot }; 216f3a2cd32SVivien Didelot 217da7dc875SVivien Didelot struct mv88e6xxx_policy { 218da7dc875SVivien Didelot enum mv88e6xxx_policy_mapping mapping; 219da7dc875SVivien Didelot enum mv88e6xxx_policy_action action; 220da7dc875SVivien Didelot struct ethtool_rx_flow_spec fs; 221da7dc875SVivien Didelot u8 addr[ETH_ALEN]; 222da7dc875SVivien Didelot int port; 223da7dc875SVivien Didelot u16 vid; 224da7dc875SVivien Didelot }; 225da7dc875SVivien Didelot 226cda9f4aaSAndrew Lunn struct mv88e6xxx_port { 2277b898469SAndrew Lunn struct mv88e6xxx_chip *chip; 2287b898469SAndrew Lunn int port; 229cda9f4aaSAndrew Lunn u64 serdes_stats[2]; 23065f60e45SAndrew Lunn u64 atu_member_violation; 23165f60e45SAndrew Lunn u64 atu_miss_violation; 23265f60e45SAndrew Lunn u64 atu_full_violation; 23365f60e45SAndrew Lunn u64 vtu_member_violation; 23465f60e45SAndrew Lunn u64 vtu_miss_violation; 235fad58190SRussell King phy_interface_t interface; 2362d2e1dd2SAndrew Lunn u8 cmode; 237f0942e00SIwan R Timmer bool mirror_ingress; 238f0942e00SIwan R Timmer bool mirror_egress; 239f441ed0fSVivien Didelot unsigned int serdes_irq; 2405d1fbdf2SAndrew Lunn char serdes_irq_name[64]; 241bfb25542SAndrew Lunn struct devlink_region *region; 242bfb25542SAndrew Lunn }; 243bfb25542SAndrew Lunn 244bfb25542SAndrew Lunn enum mv88e6xxx_region_id { 245bfb25542SAndrew Lunn MV88E6XXX_REGION_GLOBAL1 = 0, 246bfb25542SAndrew Lunn MV88E6XXX_REGION_GLOBAL2, 247bfb25542SAndrew Lunn MV88E6XXX_REGION_ATU, 248ca4d632aSTobias Waldekranz MV88E6XXX_REGION_VTU, 249bfb25542SAndrew Lunn 250bfb25542SAndrew Lunn _MV88E6XXX_REGION_MAX, 251bfb25542SAndrew Lunn }; 252bfb25542SAndrew Lunn 253bfb25542SAndrew Lunn struct mv88e6xxx_region_priv { 254bfb25542SAndrew Lunn enum mv88e6xxx_region_id id; 255cda9f4aaSAndrew Lunn }; 256cda9f4aaSAndrew Lunn 2574d5f2ba7SVivien Didelot struct mv88e6xxx_chip { 2584d5f2ba7SVivien Didelot const struct mv88e6xxx_info *info; 2594d5f2ba7SVivien Didelot 2604d5f2ba7SVivien Didelot /* The dsa_switch this private structure is related to */ 2614d5f2ba7SVivien Didelot struct dsa_switch *ds; 2624d5f2ba7SVivien Didelot 2634d5f2ba7SVivien Didelot /* The device this structure is associated to */ 2644d5f2ba7SVivien Didelot struct device *dev; 2654d5f2ba7SVivien Didelot 2664d5f2ba7SVivien Didelot /* This mutex protects the access to the switch registers */ 2674d5f2ba7SVivien Didelot struct mutex reg_lock; 2684d5f2ba7SVivien Didelot 2694d5f2ba7SVivien Didelot /* The MII bus and the address on the bus that is used to 2704d5f2ba7SVivien Didelot * communication with the switch 2714d5f2ba7SVivien Didelot */ 2724d5f2ba7SVivien Didelot const struct mv88e6xxx_bus_ops *smi_ops; 2734d5f2ba7SVivien Didelot struct mii_bus *bus; 2744d5f2ba7SVivien Didelot int sw_addr; 2754d5f2ba7SVivien Didelot 2764d5f2ba7SVivien Didelot /* Handles automatic disabling and re-enabling of the PHY 2774d5f2ba7SVivien Didelot * polling unit. 2784d5f2ba7SVivien Didelot */ 2794d5f2ba7SVivien Didelot const struct mv88e6xxx_bus_ops *phy_ops; 2804d5f2ba7SVivien Didelot struct mutex ppu_mutex; 2814d5f2ba7SVivien Didelot int ppu_disabled; 2824d5f2ba7SVivien Didelot struct work_struct ppu_work; 2834d5f2ba7SVivien Didelot struct timer_list ppu_timer; 2844d5f2ba7SVivien Didelot 2854d5f2ba7SVivien Didelot /* This mutex serialises access to the statistics unit. 2864d5f2ba7SVivien Didelot * Hold this mutex over snapshot + dump sequences. 2874d5f2ba7SVivien Didelot */ 2884d5f2ba7SVivien Didelot struct mutex stats_mutex; 2894d5f2ba7SVivien Didelot 2904d5f2ba7SVivien Didelot /* A switch may have a GPIO line tied to its reset pin. Parse 2914d5f2ba7SVivien Didelot * this from the device tree, and use it before performing 2924d5f2ba7SVivien Didelot * switch soft reset. 2934d5f2ba7SVivien Didelot */ 2944d5f2ba7SVivien Didelot struct gpio_desc *reset; 2954d5f2ba7SVivien Didelot 2964d5f2ba7SVivien Didelot /* set to size of eeprom if supported by the switch */ 29700baabe5SAndrew Lunn u32 eeprom_len; 2984d5f2ba7SVivien Didelot 2994d5f2ba7SVivien Didelot /* List of mdio busses */ 3004d5f2ba7SVivien Didelot struct list_head mdios; 3014d5f2ba7SVivien Didelot 302da7dc875SVivien Didelot /* Policy Control List IDs and rules */ 303da7dc875SVivien Didelot struct idr policies; 304da7dc875SVivien Didelot 3054d5f2ba7SVivien Didelot /* There can be two interrupt controllers, which are chained 3064d5f2ba7SVivien Didelot * off a GPIO as interrupt source 3074d5f2ba7SVivien Didelot */ 3084d5f2ba7SVivien Didelot struct mv88e6xxx_irq g1_irq; 3094d5f2ba7SVivien Didelot struct mv88e6xxx_irq g2_irq; 3104d5f2ba7SVivien Didelot int irq; 3115d1fbdf2SAndrew Lunn char irq_name[64]; 3124d5f2ba7SVivien Didelot int device_irq; 3135d1fbdf2SAndrew Lunn char device_irq_name[64]; 3144d5f2ba7SVivien Didelot int watchdog_irq; 3155d1fbdf2SAndrew Lunn char watchdog_irq_name[64]; 316cda9f4aaSAndrew Lunn 3170977644cSAndrew Lunn int atu_prob_irq; 3185d1fbdf2SAndrew Lunn char atu_prob_irq_name[64]; 31962eb1162SAndrew Lunn int vtu_prob_irq; 3205d1fbdf2SAndrew Lunn char vtu_prob_irq_name[64]; 321294d711eSAndrew Lunn struct kthread_worker *kworker; 322294d711eSAndrew Lunn struct kthread_delayed_work irq_poll_work; 3232fa8d3afSBrandon Streiff 324a73ccd61SBrandon Streiff /* GPIO resources */ 325a73ccd61SBrandon Streiff u8 gpio_data[2]; 326a73ccd61SBrandon Streiff 3272fa8d3afSBrandon Streiff /* This cyclecounter abstracts the switch PTP time. 3282fa8d3afSBrandon Streiff * reg_lock must be held for any operation that read()s. 3292fa8d3afSBrandon Streiff */ 3302fa8d3afSBrandon Streiff struct cyclecounter tstamp_cc; 3312fa8d3afSBrandon Streiff struct timecounter tstamp_tc; 3322fa8d3afSBrandon Streiff struct delayed_work overflow_work; 3332fa8d3afSBrandon Streiff 3342fa8d3afSBrandon Streiff struct ptp_clock *ptp_clock; 3352fa8d3afSBrandon Streiff struct ptp_clock_info ptp_clock_info; 3364eb3be29SBrandon Streiff struct delayed_work tai_event_work; 3374eb3be29SBrandon Streiff struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 3384eb3be29SBrandon Streiff u16 trig_config; 3394eb3be29SBrandon Streiff u16 evcap_config; 340e2294a8bSAndrew Lunn u16 enable_count; 341c6fe0ad2SBrandon Streiff 342f0942e00SIwan R Timmer /* Current ingress and egress monitor ports */ 343f0942e00SIwan R Timmer int egress_dest_port; 344f0942e00SIwan R Timmer int ingress_dest_port; 345f0942e00SIwan R Timmer 346c6fe0ad2SBrandon Streiff /* Per-port timestamping resources. */ 347c6fe0ad2SBrandon Streiff struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 348cda9f4aaSAndrew Lunn 349cda9f4aaSAndrew Lunn /* Array of port structures. */ 350cda9f4aaSAndrew Lunn struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 351bfb25542SAndrew Lunn 352bfb25542SAndrew Lunn /* devlink regions */ 353bfb25542SAndrew Lunn struct devlink_region *regions[_MV88E6XXX_REGION_MAX]; 3544d5f2ba7SVivien Didelot }; 3554d5f2ba7SVivien Didelot 3564d5f2ba7SVivien Didelot struct mv88e6xxx_bus_ops { 3574d5f2ba7SVivien Didelot int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 3584d5f2ba7SVivien Didelot int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 3594d5f2ba7SVivien Didelot }; 3604d5f2ba7SVivien Didelot 3614d5f2ba7SVivien Didelot struct mv88e6xxx_mdio_bus { 3624d5f2ba7SVivien Didelot struct mii_bus *bus; 3634d5f2ba7SVivien Didelot struct mv88e6xxx_chip *chip; 3644d5f2ba7SVivien Didelot struct list_head list; 3654d5f2ba7SVivien Didelot bool external; 3664d5f2ba7SVivien Didelot }; 3674d5f2ba7SVivien Didelot 3684d5f2ba7SVivien Didelot struct mv88e6xxx_ops { 369ea89098eSAndrew Lunn /* Switch Setup Errata, called early in the switch setup to 370ea89098eSAndrew Lunn * allow any errata actions to be performed 371ea89098eSAndrew Lunn */ 372ea89098eSAndrew Lunn int (*setup_errata)(struct mv88e6xxx_chip *chip); 373ea89098eSAndrew Lunn 37493e18d61SVivien Didelot int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 37593e18d61SVivien Didelot int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 37693e18d61SVivien Didelot 377cd8da8bbSVivien Didelot /* Ingress Rate Limit unit (IRL) operations */ 378cd8da8bbSVivien Didelot int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 379cd8da8bbSVivien Didelot 3804d5f2ba7SVivien Didelot int (*get_eeprom)(struct mv88e6xxx_chip *chip, 3814d5f2ba7SVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 3824d5f2ba7SVivien Didelot int (*set_eeprom)(struct mv88e6xxx_chip *chip, 3834d5f2ba7SVivien Didelot struct ethtool_eeprom *eeprom, u8 *data); 3844d5f2ba7SVivien Didelot 3854d5f2ba7SVivien Didelot int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 3864d5f2ba7SVivien Didelot 3874d5f2ba7SVivien Didelot int (*phy_read)(struct mv88e6xxx_chip *chip, 3884d5f2ba7SVivien Didelot struct mii_bus *bus, 3894d5f2ba7SVivien Didelot int addr, int reg, u16 *val); 3904d5f2ba7SVivien Didelot int (*phy_write)(struct mv88e6xxx_chip *chip, 3914d5f2ba7SVivien Didelot struct mii_bus *bus, 3924d5f2ba7SVivien Didelot int addr, int reg, u16 val); 3934d5f2ba7SVivien Didelot 3949e907d73SVivien Didelot /* Priority Override Table operations */ 3959e907d73SVivien Didelot int (*pot_clear)(struct mv88e6xxx_chip *chip); 3969e907d73SVivien Didelot 3974d5f2ba7SVivien Didelot /* PHY Polling Unit (PPU) operations */ 3984d5f2ba7SVivien Didelot int (*ppu_enable)(struct mv88e6xxx_chip *chip); 3994d5f2ba7SVivien Didelot int (*ppu_disable)(struct mv88e6xxx_chip *chip); 4004d5f2ba7SVivien Didelot 4014d5f2ba7SVivien Didelot /* Switch Software Reset */ 4024d5f2ba7SVivien Didelot int (*reset)(struct mv88e6xxx_chip *chip); 4034d5f2ba7SVivien Didelot 4044d5f2ba7SVivien Didelot /* RGMII Receive/Transmit Timing Control 4054d5f2ba7SVivien Didelot * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 4064d5f2ba7SVivien Didelot */ 4074d5f2ba7SVivien Didelot int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 4084d5f2ba7SVivien Didelot phy_interface_t mode); 4094d5f2ba7SVivien Didelot 4104d5f2ba7SVivien Didelot #define LINK_FORCED_DOWN 0 4114d5f2ba7SVivien Didelot #define LINK_FORCED_UP 1 4124d5f2ba7SVivien Didelot #define LINK_UNFORCED -2 4134d5f2ba7SVivien Didelot 4144d5f2ba7SVivien Didelot /* Port's MAC link state 4154d5f2ba7SVivien Didelot * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 4164d5f2ba7SVivien Didelot * or LINK_UNFORCED for normal link detection. 4174d5f2ba7SVivien Didelot */ 4184d5f2ba7SVivien Didelot int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 4194d5f2ba7SVivien Didelot 4204efe7662SChris Packham /* Synchronise the port link state with that of the SERDES 4214efe7662SChris Packham */ 4224efe7662SChris Packham int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 4234efe7662SChris Packham 42454186b91SAndrew Lunn #define PAUSE_ON 1 42554186b91SAndrew Lunn #define PAUSE_OFF 0 42654186b91SAndrew Lunn 42754186b91SAndrew Lunn /* Enable/disable sending Pause */ 42854186b91SAndrew Lunn int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 42954186b91SAndrew Lunn int pause); 43054186b91SAndrew Lunn 4314d5f2ba7SVivien Didelot #define SPEED_MAX INT_MAX 4324d5f2ba7SVivien Didelot #define SPEED_UNFORCED -2 433f365c6f7SRussell King #define DUPLEX_UNFORCED -2 4344d5f2ba7SVivien Didelot 435f365c6f7SRussell King /* Port's MAC speed (in Mbps) and MAC duplex mode 4364d5f2ba7SVivien Didelot * 4374d5f2ba7SVivien Didelot * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 4384d5f2ba7SVivien Didelot * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 439f365c6f7SRussell King * 440f365c6f7SRussell King * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 441f365c6f7SRussell King * or DUPLEX_UNFORCED for normal duplex detection. 4424d5f2ba7SVivien Didelot */ 443f365c6f7SRussell King int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port, 444f365c6f7SRussell King int speed, int duplex); 4454d5f2ba7SVivien Didelot 4467cbbee05SAndrew Lunn /* What interface mode should be used for maximum speed? */ 4477cbbee05SAndrew Lunn phy_interface_t (*port_max_speed_mode)(int port); 4487cbbee05SAndrew Lunn 4494d5f2ba7SVivien Didelot int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 4504d5f2ba7SVivien Didelot 451f3a2cd32SVivien Didelot int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port, 452f3a2cd32SVivien Didelot enum mv88e6xxx_policy_mapping mapping, 453f3a2cd32SVivien Didelot enum mv88e6xxx_policy_action action); 454f3a2cd32SVivien Didelot 4554d5f2ba7SVivien Didelot int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 4564d5f2ba7SVivien Didelot enum mv88e6xxx_frame_mode mode); 4574d5f2ba7SVivien Didelot int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port, 4584d5f2ba7SVivien Didelot bool unicast, bool multicast); 4594d5f2ba7SVivien Didelot int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 4604d5f2ba7SVivien Didelot u16 etype); 461cd782656SVivien Didelot int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 462cd782656SVivien Didelot size_t size); 4634d5f2ba7SVivien Didelot 4644d5f2ba7SVivien Didelot int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 4650898432cSVivien Didelot int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 4660898432cSVivien Didelot u8 out); 4674d5f2ba7SVivien Didelot int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 4684d5f2ba7SVivien Didelot int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 469121b8fe2SHubert Feurstein int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port); 4704d5f2ba7SVivien Didelot 4714d5f2ba7SVivien Didelot /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 4724d5f2ba7SVivien Didelot * Some chips allow this to be configured on specific ports. 4734d5f2ba7SVivien Didelot */ 4744d5f2ba7SVivien Didelot int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 4754d5f2ba7SVivien Didelot phy_interface_t mode); 4762d2e1dd2SAndrew Lunn int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 4774d5f2ba7SVivien Didelot 4784d5f2ba7SVivien Didelot /* Some devices have a per port register indicating what is 4794d5f2ba7SVivien Didelot * the upstream port this port should forward to. 4804d5f2ba7SVivien Didelot */ 4814d5f2ba7SVivien Didelot int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 4824d5f2ba7SVivien Didelot int upstream_port); 4834d5f2ba7SVivien Didelot 4844d5f2ba7SVivien Didelot /* Snapshot the statistics for a port. The statistics can then 4854d5f2ba7SVivien Didelot * be read back a leisure but still with a consistent view. 4864d5f2ba7SVivien Didelot */ 4874d5f2ba7SVivien Didelot int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 4884d5f2ba7SVivien Didelot 4894d5f2ba7SVivien Didelot /* Set the histogram mode for statistics, when the control registers 4904d5f2ba7SVivien Didelot * are separated out of the STATS_OP register. 4914d5f2ba7SVivien Didelot */ 4924d5f2ba7SVivien Didelot int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 4934d5f2ba7SVivien Didelot 4944d5f2ba7SVivien Didelot /* Return the number of strings describing statistics */ 4954d5f2ba7SVivien Didelot int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 496436fe17dSAndrew Lunn int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 497436fe17dSAndrew Lunn int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 4984d5f2ba7SVivien Didelot uint64_t *data); 499fa8d1179SVivien Didelot int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 5005c74c54cSIwan R Timmer int (*set_egress_port)(struct mv88e6xxx_chip *chip, 5015c74c54cSIwan R Timmer enum mv88e6xxx_egress_direction direction, 5025c74c54cSIwan R Timmer int port); 50302317e68SVivien Didelot 50402317e68SVivien Didelot #define MV88E6XXX_CASCADE_PORT_NONE 0xe 50502317e68SVivien Didelot #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 50602317e68SVivien Didelot 50702317e68SVivien Didelot int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 50802317e68SVivien Didelot 5094d5f2ba7SVivien Didelot const struct mv88e6xxx_irq_ops *watchdog_ops; 5104d5f2ba7SVivien Didelot 5114d5f2ba7SVivien Didelot int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 5124d5f2ba7SVivien Didelot 5134d5f2ba7SVivien Didelot /* Power on/off a SERDES interface */ 514dc272f60SVivien Didelot int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane, 515dc272f60SVivien Didelot bool up); 5164d5f2ba7SVivien Didelot 51717deaf5cSMarek Behún /* SERDES lane mapping */ 5185122d4ecSVivien Didelot u8 (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); 51917deaf5cSMarek Behún 520a5a6858bSRussell King int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port, 521a5a6858bSRussell King u8 lane, struct phylink_link_state *state); 522a5a6858bSRussell King int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port, 523a5a6858bSRussell King u8 lane, unsigned int mode, 524a5a6858bSRussell King phy_interface_t interface, 525a5a6858bSRussell King const unsigned long *advertise); 526a5a6858bSRussell King int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port, 527a5a6858bSRussell King u8 lane); 528a5a6858bSRussell King int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port, 529a5a6858bSRussell King u8 lane, int speed, int duplex); 530a5a6858bSRussell King 531efd1ba6aSAndrew Lunn /* SERDES interrupt handling */ 5324241ef52SVivien Didelot unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, 5334241ef52SVivien Didelot int port); 53461a46b41SVivien Didelot int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane, 53561a46b41SVivien Didelot bool enable); 536907b9b9fSVivien Didelot irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port, 537907b9b9fSVivien Didelot u8 lane); 538efd1ba6aSAndrew Lunn 539436fe17dSAndrew Lunn /* Statistics from the SERDES interface */ 540436fe17dSAndrew Lunn int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 54165f60e45SAndrew Lunn int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 542436fe17dSAndrew Lunn uint8_t *data); 54365f60e45SAndrew Lunn int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 544436fe17dSAndrew Lunn uint64_t *data); 545436fe17dSAndrew Lunn 5460d30bbd0SAndrew Lunn /* SERDES registers for ethtool */ 5470d30bbd0SAndrew Lunn int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port); 5480d30bbd0SAndrew Lunn void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port, 5490d30bbd0SAndrew Lunn void *_p); 5500d30bbd0SAndrew Lunn 55123e8b470SAndrew Lunn /* Address Translation Unit operations */ 55223e8b470SAndrew Lunn int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash); 55323e8b470SAndrew Lunn int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash); 55423e8b470SAndrew Lunn 5554d5f2ba7SVivien Didelot /* VLAN Translation Unit operations */ 5564d5f2ba7SVivien Didelot int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 5574d5f2ba7SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 5584d5f2ba7SVivien Didelot int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 5594d5f2ba7SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 5600d632c3dSBrandon Streiff 561a73ccd61SBrandon Streiff /* GPIO operations */ 562a73ccd61SBrandon Streiff const struct mv88e6xxx_gpio_ops *gpio_ops; 563a73ccd61SBrandon Streiff 5640d632c3dSBrandon Streiff /* Interface to the AVB/PTP registers */ 5650d632c3dSBrandon Streiff const struct mv88e6xxx_avb_ops *avb_ops; 5669e5baf9bSVivien Didelot 5679e5baf9bSVivien Didelot /* Remote Management Unit operations */ 5689e5baf9bSVivien Didelot int (*rmu_disable)(struct mv88e6xxx_chip *chip); 5696d2ac8eeSAndrew Lunn 5706d2ac8eeSAndrew Lunn /* Precision Time Protocol operations */ 5716d2ac8eeSAndrew Lunn const struct mv88e6xxx_ptp_ops *ptp_ops; 5726c422e34SRussell King 5736c422e34SRussell King /* Phylink */ 5746c422e34SRussell King void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port, 5756c422e34SRussell King unsigned long *mask, 5766c422e34SRussell King struct phylink_link_state *state); 5771baf0facSChris Packham 5781baf0facSChris Packham /* Max Frame Size */ 5791baf0facSChris Packham int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu); 5804d5f2ba7SVivien Didelot }; 5814d5f2ba7SVivien Didelot 5824d5f2ba7SVivien Didelot struct mv88e6xxx_irq_ops { 5834d5f2ba7SVivien Didelot /* Action to be performed when the interrupt happens */ 5844d5f2ba7SVivien Didelot int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 5854d5f2ba7SVivien Didelot /* Setup the hardware to generate the interrupt */ 5864d5f2ba7SVivien Didelot int (*irq_setup)(struct mv88e6xxx_chip *chip); 5874d5f2ba7SVivien Didelot /* Reset the hardware to stop generating the interrupt */ 5884d5f2ba7SVivien Didelot void (*irq_free)(struct mv88e6xxx_chip *chip); 5894d5f2ba7SVivien Didelot }; 5904d5f2ba7SVivien Didelot 591a73ccd61SBrandon Streiff struct mv88e6xxx_gpio_ops { 592a73ccd61SBrandon Streiff /* Get/set data on GPIO pin */ 593a73ccd61SBrandon Streiff int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 594a73ccd61SBrandon Streiff int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 595a73ccd61SBrandon Streiff int value); 596a73ccd61SBrandon Streiff 597a73ccd61SBrandon Streiff /* get/set GPIO direction */ 598a73ccd61SBrandon Streiff int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 599a73ccd61SBrandon Streiff int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 600a73ccd61SBrandon Streiff bool input); 601a73ccd61SBrandon Streiff 602a73ccd61SBrandon Streiff /* get/set GPIO pin control */ 603a73ccd61SBrandon Streiff int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 604a73ccd61SBrandon Streiff int *func); 605a73ccd61SBrandon Streiff int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 606a73ccd61SBrandon Streiff int func); 607a73ccd61SBrandon Streiff }; 608a73ccd61SBrandon Streiff 6090d632c3dSBrandon Streiff struct mv88e6xxx_avb_ops { 6100d632c3dSBrandon Streiff /* Access port-scoped Precision Time Protocol registers */ 6110d632c3dSBrandon Streiff int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 6120d632c3dSBrandon Streiff u16 *data, int len); 6130d632c3dSBrandon Streiff int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 6140d632c3dSBrandon Streiff u16 data); 6150d632c3dSBrandon Streiff 6160d632c3dSBrandon Streiff /* Access global Precision Time Protocol registers */ 6170d632c3dSBrandon Streiff int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 6180d632c3dSBrandon Streiff int len); 6190d632c3dSBrandon Streiff int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 6200d632c3dSBrandon Streiff 6210d632c3dSBrandon Streiff /* Access global Time Application Interface registers */ 6220d632c3dSBrandon Streiff int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 6230d632c3dSBrandon Streiff int len); 6240d632c3dSBrandon Streiff int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 6250d632c3dSBrandon Streiff }; 6260d632c3dSBrandon Streiff 6276d2ac8eeSAndrew Lunn struct mv88e6xxx_ptp_ops { 6286d2ac8eeSAndrew Lunn u64 (*clock_read)(const struct cyclecounter *cc); 6296d2ac8eeSAndrew Lunn int (*ptp_enable)(struct ptp_clock_info *ptp, 6306d2ac8eeSAndrew Lunn struct ptp_clock_request *rq, int on); 6316d2ac8eeSAndrew Lunn int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 6326d2ac8eeSAndrew Lunn enum ptp_pin_function func, unsigned int chan); 6336d2ac8eeSAndrew Lunn void (*event_work)(struct work_struct *ugly); 634ffc705deSAndrew Lunn int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 635ffc705deSAndrew Lunn int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 636e2294a8bSAndrew Lunn int (*global_enable)(struct mv88e6xxx_chip *chip); 637e2294a8bSAndrew Lunn int (*global_disable)(struct mv88e6xxx_chip *chip); 6386d2ac8eeSAndrew Lunn int n_ext_ts; 639ffc705deSAndrew Lunn int arr0_sts_reg; 640ffc705deSAndrew Lunn int arr1_sts_reg; 641ffc705deSAndrew Lunn int dep_sts_reg; 64248cb5e03SAndrew Lunn u32 rx_filters; 64371509614SHubert Feurstein u32 cc_shift; 64471509614SHubert Feurstein u32 cc_mult; 64571509614SHubert Feurstein u32 cc_mult_num; 64671509614SHubert Feurstein u32 cc_mult_dem; 6476d2ac8eeSAndrew Lunn }; 6486d2ac8eeSAndrew Lunn 6494d5f2ba7SVivien Didelot #define STATS_TYPE_PORT BIT(0) 6504d5f2ba7SVivien Didelot #define STATS_TYPE_BANK0 BIT(1) 6514d5f2ba7SVivien Didelot #define STATS_TYPE_BANK1 BIT(2) 6524d5f2ba7SVivien Didelot 6534d5f2ba7SVivien Didelot struct mv88e6xxx_hw_stat { 6544d5f2ba7SVivien Didelot char string[ETH_GSTRING_LEN]; 655cda9f4aaSAndrew Lunn size_t size; 6564d5f2ba7SVivien Didelot int reg; 6574d5f2ba7SVivien Didelot int type; 6584d5f2ba7SVivien Didelot }; 6594d5f2ba7SVivien Didelot 6604d5f2ba7SVivien Didelot static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 6614d5f2ba7SVivien Didelot { 6624d5f2ba7SVivien Didelot return chip->info->pvt; 6634d5f2ba7SVivien Didelot } 6644d5f2ba7SVivien Didelot 665*b80dc51bSTobias Waldekranz static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip) 666*b80dc51bSTobias Waldekranz { 667*b80dc51bSTobias Waldekranz return !!chip->info->global2_addr; 668*b80dc51bSTobias Waldekranz } 669*b80dc51bSTobias Waldekranz 6704d5f2ba7SVivien Didelot static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 6714d5f2ba7SVivien Didelot { 6724d5f2ba7SVivien Didelot return chip->info->num_databases; 6734d5f2ba7SVivien Didelot } 6744d5f2ba7SVivien Didelot 675d9ea5620SAndrew Lunn static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip) 676d9ea5620SAndrew Lunn { 677d9ea5620SAndrew Lunn return chip->info->num_macs; 678d9ea5620SAndrew Lunn } 679d9ea5620SAndrew Lunn 6804d5f2ba7SVivien Didelot static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 6814d5f2ba7SVivien Didelot { 6824d5f2ba7SVivien Didelot return chip->info->num_ports; 6834d5f2ba7SVivien Didelot } 6844d5f2ba7SVivien Didelot 685e545f865STobias Waldekranz static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip) 686e545f865STobias Waldekranz { 687e545f865STobias Waldekranz return chip->info->max_vid; 688e545f865STobias Waldekranz } 689e545f865STobias Waldekranz 6904d5f2ba7SVivien Didelot static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 6914d5f2ba7SVivien Didelot { 692f1931164SAndrew Lunn return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0); 6934d5f2ba7SVivien Didelot } 6944d5f2ba7SVivien Didelot 695a73ccd61SBrandon Streiff static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 696a73ccd61SBrandon Streiff { 697a73ccd61SBrandon Streiff return chip->info->num_gpio; 698a73ccd61SBrandon Streiff } 699a73ccd61SBrandon Streiff 700c857486aSHubert Feurstein static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port) 701c857486aSHubert Feurstein { 702c857486aSHubert Feurstein return (chip->info->invalid_port_mask & BIT(port)) != 0; 703c857486aSHubert Feurstein } 704c857486aSHubert Feurstein 7054d5f2ba7SVivien Didelot int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 7064d5f2ba7SVivien Didelot int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 707683f2244SVivien Didelot int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 708683f2244SVivien Didelot u16 mask, u16 val); 70919fb7f69SVivien Didelot int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 71019fb7f69SVivien Didelot int bit, int val); 7114d5f2ba7SVivien Didelot struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 7124d5f2ba7SVivien Didelot 713c9acece0SRasmus Villemoes static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) 714c9acece0SRasmus Villemoes { 715c9acece0SRasmus Villemoes mutex_lock(&chip->reg_lock); 716c9acece0SRasmus Villemoes } 717c9acece0SRasmus Villemoes 718c9acece0SRasmus Villemoes static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) 719c9acece0SRasmus Villemoes { 720c9acece0SRasmus Villemoes mutex_unlock(&chip->reg_lock); 721c9acece0SRasmus Villemoes } 722c9acece0SRasmus Villemoes 72390b6dbdfSAndrew Lunn int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap); 72490b6dbdfSAndrew Lunn 7254d5f2ba7SVivien Didelot #endif /* _MV88E6XXX_CHIP_H */ 726