1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 u16 data; 90 int err; 91 int i; 92 93 /* There's no bus specific operation to wait for a mask */ 94 for (i = 0; i < 16; i++) { 95 err = mv88e6xxx_read(chip, addr, reg, &data); 96 if (err) 97 return err; 98 99 if ((data & mask) == val) 100 return 0; 101 102 usleep_range(1000, 2000); 103 } 104 105 dev_err(chip->dev, "Timeout while waiting for switch\n"); 106 return -ETIMEDOUT; 107 } 108 109 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 110 int bit, int val) 111 { 112 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 113 val ? BIT(bit) : 0x0000); 114 } 115 116 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 117 { 118 struct mv88e6xxx_mdio_bus *mdio_bus; 119 120 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 121 list); 122 if (!mdio_bus) 123 return NULL; 124 125 return mdio_bus->bus; 126 } 127 128 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 129 { 130 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 131 unsigned int n = d->hwirq; 132 133 chip->g1_irq.masked |= (1 << n); 134 } 135 136 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 137 { 138 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 139 unsigned int n = d->hwirq; 140 141 chip->g1_irq.masked &= ~(1 << n); 142 } 143 144 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 145 { 146 unsigned int nhandled = 0; 147 unsigned int sub_irq; 148 unsigned int n; 149 u16 reg; 150 u16 ctl1; 151 int err; 152 153 mv88e6xxx_reg_lock(chip); 154 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 155 mv88e6xxx_reg_unlock(chip); 156 157 if (err) 158 goto out; 159 160 do { 161 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 162 if (reg & (1 << n)) { 163 sub_irq = irq_find_mapping(chip->g1_irq.domain, 164 n); 165 handle_nested_irq(sub_irq); 166 ++nhandled; 167 } 168 } 169 170 mv88e6xxx_reg_lock(chip); 171 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 172 if (err) 173 goto unlock; 174 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 175 unlock: 176 mv88e6xxx_reg_unlock(chip); 177 if (err) 178 goto out; 179 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 180 } while (reg & ctl1); 181 182 out: 183 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 184 } 185 186 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 187 { 188 struct mv88e6xxx_chip *chip = dev_id; 189 190 return mv88e6xxx_g1_irq_thread_work(chip); 191 } 192 193 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 194 { 195 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 196 197 mv88e6xxx_reg_lock(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 204 u16 reg; 205 int err; 206 207 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 208 if (err) 209 goto out; 210 211 reg &= ~mask; 212 reg |= (~chip->g1_irq.masked & mask); 213 214 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 215 if (err) 216 goto out; 217 218 out: 219 mv88e6xxx_reg_unlock(chip); 220 } 221 222 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 223 .name = "mv88e6xxx-g1", 224 .irq_mask = mv88e6xxx_g1_irq_mask, 225 .irq_unmask = mv88e6xxx_g1_irq_unmask, 226 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 227 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 228 }; 229 230 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 231 unsigned int irq, 232 irq_hw_number_t hwirq) 233 { 234 struct mv88e6xxx_chip *chip = d->host_data; 235 236 irq_set_chip_data(irq, d->host_data); 237 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 238 irq_set_noprobe(irq); 239 240 return 0; 241 } 242 243 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 244 .map = mv88e6xxx_g1_irq_domain_map, 245 .xlate = irq_domain_xlate_twocell, 246 }; 247 248 /* To be called with reg_lock held */ 249 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 250 { 251 int irq, virq; 252 u16 mask; 253 254 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 255 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 256 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 257 258 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 259 virq = irq_find_mapping(chip->g1_irq.domain, irq); 260 irq_dispose_mapping(virq); 261 } 262 263 irq_domain_remove(chip->g1_irq.domain); 264 } 265 266 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 267 { 268 /* 269 * free_irq must be called without reg_lock taken because the irq 270 * handler takes this lock, too. 271 */ 272 free_irq(chip->irq, chip); 273 274 mv88e6xxx_reg_lock(chip); 275 mv88e6xxx_g1_irq_free_common(chip); 276 mv88e6xxx_reg_unlock(chip); 277 } 278 279 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 280 { 281 int err, irq, virq; 282 u16 reg, mask; 283 284 chip->g1_irq.nirqs = chip->info->g1_irqs; 285 chip->g1_irq.domain = irq_domain_add_simple( 286 NULL, chip->g1_irq.nirqs, 0, 287 &mv88e6xxx_g1_irq_domain_ops, chip); 288 if (!chip->g1_irq.domain) 289 return -ENOMEM; 290 291 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 292 irq_create_mapping(chip->g1_irq.domain, irq); 293 294 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 295 chip->g1_irq.masked = ~0; 296 297 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 298 if (err) 299 goto out_mapping; 300 301 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 302 303 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 304 if (err) 305 goto out_disable; 306 307 /* Reading the interrupt status clears (most of) them */ 308 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 309 if (err) 310 goto out_disable; 311 312 return 0; 313 314 out_disable: 315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 316 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 317 318 out_mapping: 319 for (irq = 0; irq < 16; irq++) { 320 virq = irq_find_mapping(chip->g1_irq.domain, irq); 321 irq_dispose_mapping(virq); 322 } 323 324 irq_domain_remove(chip->g1_irq.domain); 325 326 return err; 327 } 328 329 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 330 { 331 static struct lock_class_key lock_key; 332 static struct lock_class_key request_key; 333 int err; 334 335 err = mv88e6xxx_g1_irq_setup_common(chip); 336 if (err) 337 return err; 338 339 /* These lock classes tells lockdep that global 1 irqs are in 340 * a different category than their parent GPIO, so it won't 341 * report false recursion. 342 */ 343 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 344 345 snprintf(chip->irq_name, sizeof(chip->irq_name), 346 "mv88e6xxx-%s", dev_name(chip->dev)); 347 348 mv88e6xxx_reg_unlock(chip); 349 err = request_threaded_irq(chip->irq, NULL, 350 mv88e6xxx_g1_irq_thread_fn, 351 IRQF_ONESHOT | IRQF_SHARED, 352 chip->irq_name, chip); 353 mv88e6xxx_reg_lock(chip); 354 if (err) 355 mv88e6xxx_g1_irq_free_common(chip); 356 357 return err; 358 } 359 360 static void mv88e6xxx_irq_poll(struct kthread_work *work) 361 { 362 struct mv88e6xxx_chip *chip = container_of(work, 363 struct mv88e6xxx_chip, 364 irq_poll_work.work); 365 mv88e6xxx_g1_irq_thread_work(chip); 366 367 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 368 msecs_to_jiffies(100)); 369 } 370 371 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 372 { 373 int err; 374 375 err = mv88e6xxx_g1_irq_setup_common(chip); 376 if (err) 377 return err; 378 379 kthread_init_delayed_work(&chip->irq_poll_work, 380 mv88e6xxx_irq_poll); 381 382 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 383 if (IS_ERR(chip->kworker)) 384 return PTR_ERR(chip->kworker); 385 386 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 387 msecs_to_jiffies(100)); 388 389 return 0; 390 } 391 392 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 393 { 394 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 395 kthread_destroy_worker(chip->kworker); 396 397 mv88e6xxx_reg_lock(chip); 398 mv88e6xxx_g1_irq_free_common(chip); 399 mv88e6xxx_reg_unlock(chip); 400 } 401 402 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 403 int port, phy_interface_t interface) 404 { 405 int err; 406 407 if (chip->info->ops->port_set_rgmii_delay) { 408 err = chip->info->ops->port_set_rgmii_delay(chip, port, 409 interface); 410 if (err && err != -EOPNOTSUPP) 411 return err; 412 } 413 414 if (chip->info->ops->port_set_cmode) { 415 err = chip->info->ops->port_set_cmode(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 return 0; 422 } 423 424 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 425 int link, int speed, int duplex, int pause, 426 phy_interface_t mode) 427 { 428 int err; 429 430 if (!chip->info->ops->port_set_link) 431 return 0; 432 433 /* Port's MAC control must not be changed unless the link is down */ 434 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 435 if (err) 436 return err; 437 438 if (chip->info->ops->port_set_speed_duplex) { 439 err = chip->info->ops->port_set_speed_duplex(chip, port, 440 speed, duplex); 441 if (err && err != -EOPNOTSUPP) 442 goto restore_link; 443 } 444 445 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 446 mode = chip->info->ops->port_max_speed_mode(port); 447 448 if (chip->info->ops->port_set_pause) { 449 err = chip->info->ops->port_set_pause(chip, port, pause); 450 if (err) 451 goto restore_link; 452 } 453 454 err = mv88e6xxx_port_config_interface(chip, port, mode); 455 restore_link: 456 if (chip->info->ops->port_set_link(chip, port, link)) 457 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 458 459 return err; 460 } 461 462 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 463 { 464 struct mv88e6xxx_chip *chip = ds->priv; 465 466 return port < chip->info->num_internal_phys; 467 } 468 469 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 470 { 471 u16 reg; 472 int err; 473 474 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 475 if (err) { 476 dev_err(chip->dev, 477 "p%d: %s: failed to read port status\n", 478 port, __func__); 479 return err; 480 } 481 482 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 483 } 484 485 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 486 struct phylink_link_state *state) 487 { 488 struct mv88e6xxx_chip *chip = ds->priv; 489 int lane; 490 int err; 491 492 mv88e6xxx_reg_lock(chip); 493 lane = mv88e6xxx_serdes_get_lane(chip, port); 494 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 495 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 496 state); 497 else 498 err = -EOPNOTSUPP; 499 mv88e6xxx_reg_unlock(chip); 500 501 return err; 502 } 503 504 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 505 unsigned int mode, 506 phy_interface_t interface, 507 const unsigned long *advertise) 508 { 509 const struct mv88e6xxx_ops *ops = chip->info->ops; 510 int lane; 511 512 if (ops->serdes_pcs_config) { 513 lane = mv88e6xxx_serdes_get_lane(chip, port); 514 if (lane >= 0) 515 return ops->serdes_pcs_config(chip, port, lane, mode, 516 interface, advertise); 517 } 518 519 return 0; 520 } 521 522 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 523 { 524 struct mv88e6xxx_chip *chip = ds->priv; 525 const struct mv88e6xxx_ops *ops; 526 int err = 0; 527 int lane; 528 529 ops = chip->info->ops; 530 531 if (ops->serdes_pcs_an_restart) { 532 mv88e6xxx_reg_lock(chip); 533 lane = mv88e6xxx_serdes_get_lane(chip, port); 534 if (lane >= 0) 535 err = ops->serdes_pcs_an_restart(chip, port, lane); 536 mv88e6xxx_reg_unlock(chip); 537 538 if (err) 539 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 540 } 541 } 542 543 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 544 unsigned int mode, 545 int speed, int duplex) 546 { 547 const struct mv88e6xxx_ops *ops = chip->info->ops; 548 int lane; 549 550 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 551 lane = mv88e6xxx_serdes_get_lane(chip, port); 552 if (lane >= 0) 553 return ops->serdes_pcs_link_up(chip, port, lane, 554 speed, duplex); 555 } 556 557 return 0; 558 } 559 560 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 561 unsigned long *mask, 562 struct phylink_link_state *state) 563 { 564 if (!phy_interface_mode_is_8023z(state->interface)) { 565 /* 10M and 100M are only supported in non-802.3z mode */ 566 phylink_set(mask, 10baseT_Half); 567 phylink_set(mask, 10baseT_Full); 568 phylink_set(mask, 100baseT_Half); 569 phylink_set(mask, 100baseT_Full); 570 } 571 } 572 573 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 574 unsigned long *mask, 575 struct phylink_link_state *state) 576 { 577 /* FIXME: if the port is in 1000Base-X mode, then it only supports 578 * 1000M FD speeds. In this case, CMODE will indicate 5. 579 */ 580 phylink_set(mask, 1000baseT_Full); 581 phylink_set(mask, 1000baseX_Full); 582 583 mv88e6065_phylink_validate(chip, port, mask, state); 584 } 585 586 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 587 unsigned long *mask, 588 struct phylink_link_state *state) 589 { 590 if (port >= 5) 591 phylink_set(mask, 2500baseX_Full); 592 593 /* No ethtool bits for 200Mbps */ 594 phylink_set(mask, 1000baseT_Full); 595 phylink_set(mask, 1000baseX_Full); 596 597 mv88e6065_phylink_validate(chip, port, mask, state); 598 } 599 600 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 601 unsigned long *mask, 602 struct phylink_link_state *state) 603 { 604 /* No ethtool bits for 200Mbps */ 605 phylink_set(mask, 1000baseT_Full); 606 phylink_set(mask, 1000baseX_Full); 607 608 mv88e6065_phylink_validate(chip, port, mask, state); 609 } 610 611 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 612 unsigned long *mask, 613 struct phylink_link_state *state) 614 { 615 if (port >= 9) { 616 phylink_set(mask, 2500baseX_Full); 617 phylink_set(mask, 2500baseT_Full); 618 } 619 620 /* No ethtool bits for 200Mbps */ 621 phylink_set(mask, 1000baseT_Full); 622 phylink_set(mask, 1000baseX_Full); 623 624 mv88e6065_phylink_validate(chip, port, mask, state); 625 } 626 627 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 628 unsigned long *mask, 629 struct phylink_link_state *state) 630 { 631 if (port >= 9) { 632 phylink_set(mask, 10000baseT_Full); 633 phylink_set(mask, 10000baseKR_Full); 634 } 635 636 mv88e6390_phylink_validate(chip, port, mask, state); 637 } 638 639 static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 640 unsigned long *mask, 641 struct phylink_link_state *state) 642 { 643 bool is_6191x = 644 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 645 646 if (((port == 0 || port == 9) && !is_6191x) || port == 10) { 647 phylink_set(mask, 10000baseT_Full); 648 phylink_set(mask, 10000baseKR_Full); 649 phylink_set(mask, 10000baseCR_Full); 650 phylink_set(mask, 10000baseSR_Full); 651 phylink_set(mask, 10000baseLR_Full); 652 phylink_set(mask, 10000baseLRM_Full); 653 phylink_set(mask, 10000baseER_Full); 654 phylink_set(mask, 5000baseT_Full); 655 phylink_set(mask, 2500baseX_Full); 656 phylink_set(mask, 2500baseT_Full); 657 } 658 659 phylink_set(mask, 1000baseT_Full); 660 phylink_set(mask, 1000baseX_Full); 661 662 mv88e6065_phylink_validate(chip, port, mask, state); 663 } 664 665 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 666 unsigned long *supported, 667 struct phylink_link_state *state) 668 { 669 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 670 struct mv88e6xxx_chip *chip = ds->priv; 671 672 /* Allow all the expected bits */ 673 phylink_set(mask, Autoneg); 674 phylink_set(mask, Pause); 675 phylink_set_port_modes(mask); 676 677 if (chip->info->ops->phylink_validate) 678 chip->info->ops->phylink_validate(chip, port, mask, state); 679 680 linkmode_and(supported, supported, mask); 681 linkmode_and(state->advertising, state->advertising, mask); 682 683 /* We can only operate at 2500BaseX or 1000BaseX. If requested 684 * to advertise both, only report advertising at 2500BaseX. 685 */ 686 phylink_helper_basex_speed(state); 687 } 688 689 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 690 unsigned int mode, 691 const struct phylink_link_state *state) 692 { 693 struct mv88e6xxx_chip *chip = ds->priv; 694 struct mv88e6xxx_port *p; 695 int err; 696 697 p = &chip->ports[port]; 698 699 /* FIXME: is this the correct test? If we're in fixed mode on an 700 * internal port, why should we process this any different from 701 * PHY mode? On the other hand, the port may be automedia between 702 * an internal PHY and the serdes... 703 */ 704 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 705 return; 706 707 mv88e6xxx_reg_lock(chip); 708 /* In inband mode, the link may come up at any time while the link 709 * is not forced down. Force the link down while we reconfigure the 710 * interface mode. 711 */ 712 if (mode == MLO_AN_INBAND && p->interface != state->interface && 713 chip->info->ops->port_set_link) 714 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 715 716 err = mv88e6xxx_port_config_interface(chip, port, state->interface); 717 if (err && err != -EOPNOTSUPP) 718 goto err_unlock; 719 720 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface, 721 state->advertising); 722 /* FIXME: we should restart negotiation if something changed - which 723 * is something we get if we convert to using phylinks PCS operations. 724 */ 725 if (err > 0) 726 err = 0; 727 728 /* Undo the forced down state above after completing configuration 729 * irrespective of its state on entry, which allows the link to come up. 730 */ 731 if (mode == MLO_AN_INBAND && p->interface != state->interface && 732 chip->info->ops->port_set_link) 733 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 734 735 p->interface = state->interface; 736 737 err_unlock: 738 mv88e6xxx_reg_unlock(chip); 739 740 if (err && err != -EOPNOTSUPP) 741 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 742 } 743 744 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 745 unsigned int mode, 746 phy_interface_t interface) 747 { 748 struct mv88e6xxx_chip *chip = ds->priv; 749 const struct mv88e6xxx_ops *ops; 750 int err = 0; 751 752 ops = chip->info->ops; 753 754 mv88e6xxx_reg_lock(chip); 755 /* Internal PHYs propagate their configuration directly to the MAC. 756 * External PHYs depend on whether the PPU is enabled for this port. 757 */ 758 if (((!mv88e6xxx_phy_is_internal(ds, port) && 759 !mv88e6xxx_port_ppu_updates(chip, port)) || 760 mode == MLO_AN_FIXED) && ops->port_sync_link) 761 err = ops->port_sync_link(chip, port, mode, false); 762 mv88e6xxx_reg_unlock(chip); 763 764 if (err) 765 dev_err(chip->dev, 766 "p%d: failed to force MAC link down\n", port); 767 } 768 769 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 770 unsigned int mode, phy_interface_t interface, 771 struct phy_device *phydev, 772 int speed, int duplex, 773 bool tx_pause, bool rx_pause) 774 { 775 struct mv88e6xxx_chip *chip = ds->priv; 776 const struct mv88e6xxx_ops *ops; 777 int err = 0; 778 779 ops = chip->info->ops; 780 781 mv88e6xxx_reg_lock(chip); 782 /* Internal PHYs propagate their configuration directly to the MAC. 783 * External PHYs depend on whether the PPU is enabled for this port. 784 */ 785 if ((!mv88e6xxx_phy_is_internal(ds, port) && 786 !mv88e6xxx_port_ppu_updates(chip, port)) || 787 mode == MLO_AN_FIXED) { 788 /* FIXME: for an automedia port, should we force the link 789 * down here - what if the link comes up due to "other" media 790 * while we're bringing the port up, how is the exclusivity 791 * handled in the Marvell hardware? E.g. port 2 on 88E6390 792 * shared between internal PHY and Serdes. 793 */ 794 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 795 duplex); 796 if (err) 797 goto error; 798 799 if (ops->port_set_speed_duplex) { 800 err = ops->port_set_speed_duplex(chip, port, 801 speed, duplex); 802 if (err && err != -EOPNOTSUPP) 803 goto error; 804 } 805 806 if (ops->port_sync_link) 807 err = ops->port_sync_link(chip, port, mode, true); 808 } 809 error: 810 mv88e6xxx_reg_unlock(chip); 811 812 if (err && err != -EOPNOTSUPP) 813 dev_err(ds->dev, 814 "p%d: failed to configure MAC link up\n", port); 815 } 816 817 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 818 { 819 if (!chip->info->ops->stats_snapshot) 820 return -EOPNOTSUPP; 821 822 return chip->info->ops->stats_snapshot(chip, port); 823 } 824 825 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 826 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 827 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 828 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 829 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 830 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 831 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 832 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 833 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 834 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 835 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 836 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 837 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 838 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 839 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 840 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 841 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 842 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 843 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 844 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 845 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 846 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 847 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 848 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 849 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 850 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 851 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 852 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 853 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 854 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 855 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 856 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 857 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 858 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 859 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 860 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 861 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 862 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 863 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 864 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 865 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 866 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 867 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 868 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 869 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 870 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 871 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 872 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 873 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 874 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 875 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 876 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 877 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 878 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 879 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 880 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 881 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 882 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 883 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 884 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 885 }; 886 887 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 888 struct mv88e6xxx_hw_stat *s, 889 int port, u16 bank1_select, 890 u16 histogram) 891 { 892 u32 low; 893 u32 high = 0; 894 u16 reg = 0; 895 int err; 896 u64 value; 897 898 switch (s->type) { 899 case STATS_TYPE_PORT: 900 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 901 if (err) 902 return U64_MAX; 903 904 low = reg; 905 if (s->size == 4) { 906 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 907 if (err) 908 return U64_MAX; 909 low |= ((u32)reg) << 16; 910 } 911 break; 912 case STATS_TYPE_BANK1: 913 reg = bank1_select; 914 fallthrough; 915 case STATS_TYPE_BANK0: 916 reg |= s->reg | histogram; 917 mv88e6xxx_g1_stats_read(chip, reg, &low); 918 if (s->size == 8) 919 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 920 break; 921 default: 922 return U64_MAX; 923 } 924 value = (((u64)high) << 32) | low; 925 return value; 926 } 927 928 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 929 uint8_t *data, int types) 930 { 931 struct mv88e6xxx_hw_stat *stat; 932 int i, j; 933 934 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 935 stat = &mv88e6xxx_hw_stats[i]; 936 if (stat->type & types) { 937 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 938 ETH_GSTRING_LEN); 939 j++; 940 } 941 } 942 943 return j; 944 } 945 946 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 947 uint8_t *data) 948 { 949 return mv88e6xxx_stats_get_strings(chip, data, 950 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 951 } 952 953 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 954 uint8_t *data) 955 { 956 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 957 } 958 959 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 960 uint8_t *data) 961 { 962 return mv88e6xxx_stats_get_strings(chip, data, 963 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 964 } 965 966 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 967 "atu_member_violation", 968 "atu_miss_violation", 969 "atu_full_violation", 970 "vtu_member_violation", 971 "vtu_miss_violation", 972 }; 973 974 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 975 { 976 unsigned int i; 977 978 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 979 strlcpy(data + i * ETH_GSTRING_LEN, 980 mv88e6xxx_atu_vtu_stats_strings[i], 981 ETH_GSTRING_LEN); 982 } 983 984 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 985 u32 stringset, uint8_t *data) 986 { 987 struct mv88e6xxx_chip *chip = ds->priv; 988 int count = 0; 989 990 if (stringset != ETH_SS_STATS) 991 return; 992 993 mv88e6xxx_reg_lock(chip); 994 995 if (chip->info->ops->stats_get_strings) 996 count = chip->info->ops->stats_get_strings(chip, data); 997 998 if (chip->info->ops->serdes_get_strings) { 999 data += count * ETH_GSTRING_LEN; 1000 count = chip->info->ops->serdes_get_strings(chip, port, data); 1001 } 1002 1003 data += count * ETH_GSTRING_LEN; 1004 mv88e6xxx_atu_vtu_get_strings(data); 1005 1006 mv88e6xxx_reg_unlock(chip); 1007 } 1008 1009 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1010 int types) 1011 { 1012 struct mv88e6xxx_hw_stat *stat; 1013 int i, j; 1014 1015 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1016 stat = &mv88e6xxx_hw_stats[i]; 1017 if (stat->type & types) 1018 j++; 1019 } 1020 return j; 1021 } 1022 1023 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1024 { 1025 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1026 STATS_TYPE_PORT); 1027 } 1028 1029 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1030 { 1031 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1032 } 1033 1034 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1035 { 1036 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1037 STATS_TYPE_BANK1); 1038 } 1039 1040 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1041 { 1042 struct mv88e6xxx_chip *chip = ds->priv; 1043 int serdes_count = 0; 1044 int count = 0; 1045 1046 if (sset != ETH_SS_STATS) 1047 return 0; 1048 1049 mv88e6xxx_reg_lock(chip); 1050 if (chip->info->ops->stats_get_sset_count) 1051 count = chip->info->ops->stats_get_sset_count(chip); 1052 if (count < 0) 1053 goto out; 1054 1055 if (chip->info->ops->serdes_get_sset_count) 1056 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1057 port); 1058 if (serdes_count < 0) { 1059 count = serdes_count; 1060 goto out; 1061 } 1062 count += serdes_count; 1063 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1064 1065 out: 1066 mv88e6xxx_reg_unlock(chip); 1067 1068 return count; 1069 } 1070 1071 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1072 uint64_t *data, int types, 1073 u16 bank1_select, u16 histogram) 1074 { 1075 struct mv88e6xxx_hw_stat *stat; 1076 int i, j; 1077 1078 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1079 stat = &mv88e6xxx_hw_stats[i]; 1080 if (stat->type & types) { 1081 mv88e6xxx_reg_lock(chip); 1082 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1083 bank1_select, 1084 histogram); 1085 mv88e6xxx_reg_unlock(chip); 1086 1087 j++; 1088 } 1089 } 1090 return j; 1091 } 1092 1093 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1094 uint64_t *data) 1095 { 1096 return mv88e6xxx_stats_get_stats(chip, port, data, 1097 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1098 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1099 } 1100 1101 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1102 uint64_t *data) 1103 { 1104 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1105 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1106 } 1107 1108 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1109 uint64_t *data) 1110 { 1111 return mv88e6xxx_stats_get_stats(chip, port, data, 1112 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1113 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1114 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1115 } 1116 1117 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1118 uint64_t *data) 1119 { 1120 return mv88e6xxx_stats_get_stats(chip, port, data, 1121 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1122 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1123 0); 1124 } 1125 1126 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1127 uint64_t *data) 1128 { 1129 *data++ = chip->ports[port].atu_member_violation; 1130 *data++ = chip->ports[port].atu_miss_violation; 1131 *data++ = chip->ports[port].atu_full_violation; 1132 *data++ = chip->ports[port].vtu_member_violation; 1133 *data++ = chip->ports[port].vtu_miss_violation; 1134 } 1135 1136 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1137 uint64_t *data) 1138 { 1139 int count = 0; 1140 1141 if (chip->info->ops->stats_get_stats) 1142 count = chip->info->ops->stats_get_stats(chip, port, data); 1143 1144 mv88e6xxx_reg_lock(chip); 1145 if (chip->info->ops->serdes_get_stats) { 1146 data += count; 1147 count = chip->info->ops->serdes_get_stats(chip, port, data); 1148 } 1149 data += count; 1150 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1151 mv88e6xxx_reg_unlock(chip); 1152 } 1153 1154 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1155 uint64_t *data) 1156 { 1157 struct mv88e6xxx_chip *chip = ds->priv; 1158 int ret; 1159 1160 mv88e6xxx_reg_lock(chip); 1161 1162 ret = mv88e6xxx_stats_snapshot(chip, port); 1163 mv88e6xxx_reg_unlock(chip); 1164 1165 if (ret < 0) 1166 return; 1167 1168 mv88e6xxx_get_stats(chip, port, data); 1169 1170 } 1171 1172 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1173 { 1174 struct mv88e6xxx_chip *chip = ds->priv; 1175 int len; 1176 1177 len = 32 * sizeof(u16); 1178 if (chip->info->ops->serdes_get_regs_len) 1179 len += chip->info->ops->serdes_get_regs_len(chip, port); 1180 1181 return len; 1182 } 1183 1184 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1185 struct ethtool_regs *regs, void *_p) 1186 { 1187 struct mv88e6xxx_chip *chip = ds->priv; 1188 int err; 1189 u16 reg; 1190 u16 *p = _p; 1191 int i; 1192 1193 regs->version = chip->info->prod_num; 1194 1195 memset(p, 0xff, 32 * sizeof(u16)); 1196 1197 mv88e6xxx_reg_lock(chip); 1198 1199 for (i = 0; i < 32; i++) { 1200 1201 err = mv88e6xxx_port_read(chip, port, i, ®); 1202 if (!err) 1203 p[i] = reg; 1204 } 1205 1206 if (chip->info->ops->serdes_get_regs) 1207 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1208 1209 mv88e6xxx_reg_unlock(chip); 1210 } 1211 1212 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1213 struct ethtool_eee *e) 1214 { 1215 /* Nothing to do on the port's MAC */ 1216 return 0; 1217 } 1218 1219 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1220 struct ethtool_eee *e) 1221 { 1222 /* Nothing to do on the port's MAC */ 1223 return 0; 1224 } 1225 1226 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1227 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1228 { 1229 struct dsa_switch *ds = chip->ds; 1230 struct dsa_switch_tree *dst = ds->dst; 1231 struct net_device *br; 1232 struct dsa_port *dp; 1233 bool found = false; 1234 u16 pvlan; 1235 1236 /* dev is a physical switch */ 1237 if (dev <= dst->last_switch) { 1238 list_for_each_entry(dp, &dst->ports, list) { 1239 if (dp->ds->index == dev && dp->index == port) { 1240 /* dp might be a DSA link or a user port, so it 1241 * might or might not have a bridge_dev 1242 * pointer. Use the "found" variable for both 1243 * cases. 1244 */ 1245 br = dp->bridge_dev; 1246 found = true; 1247 break; 1248 } 1249 } 1250 /* dev is a virtual bridge */ 1251 } else { 1252 list_for_each_entry(dp, &dst->ports, list) { 1253 if (dp->bridge_num < 0) 1254 continue; 1255 1256 if (dp->bridge_num + 1 + dst->last_switch != dev) 1257 continue; 1258 1259 br = dp->bridge_dev; 1260 found = true; 1261 break; 1262 } 1263 } 1264 1265 /* Prevent frames from unknown switch or virtual bridge */ 1266 if (!found) 1267 return 0; 1268 1269 /* Frames from DSA links and CPU ports can egress any local port */ 1270 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1271 return mv88e6xxx_port_mask(chip); 1272 1273 pvlan = 0; 1274 1275 /* Frames from user ports can egress any local DSA links and CPU ports, 1276 * as well as any local member of their bridge group. 1277 */ 1278 list_for_each_entry(dp, &dst->ports, list) 1279 if (dp->ds == ds && 1280 (dp->type == DSA_PORT_TYPE_CPU || 1281 dp->type == DSA_PORT_TYPE_DSA || 1282 (br && dp->bridge_dev == br))) 1283 pvlan |= BIT(dp->index); 1284 1285 return pvlan; 1286 } 1287 1288 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1289 { 1290 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1291 1292 /* prevent frames from going back out of the port they came in on */ 1293 output_ports &= ~BIT(port); 1294 1295 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1296 } 1297 1298 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1299 u8 state) 1300 { 1301 struct mv88e6xxx_chip *chip = ds->priv; 1302 int err; 1303 1304 mv88e6xxx_reg_lock(chip); 1305 err = mv88e6xxx_port_set_state(chip, port, state); 1306 mv88e6xxx_reg_unlock(chip); 1307 1308 if (err) 1309 dev_err(ds->dev, "p%d: failed to update state\n", port); 1310 } 1311 1312 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1313 { 1314 int err; 1315 1316 if (chip->info->ops->ieee_pri_map) { 1317 err = chip->info->ops->ieee_pri_map(chip); 1318 if (err) 1319 return err; 1320 } 1321 1322 if (chip->info->ops->ip_pri_map) { 1323 err = chip->info->ops->ip_pri_map(chip); 1324 if (err) 1325 return err; 1326 } 1327 1328 return 0; 1329 } 1330 1331 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1332 { 1333 struct dsa_switch *ds = chip->ds; 1334 int target, port; 1335 int err; 1336 1337 if (!chip->info->global2_addr) 1338 return 0; 1339 1340 /* Initialize the routing port to the 32 possible target devices */ 1341 for (target = 0; target < 32; target++) { 1342 port = dsa_routing_port(ds, target); 1343 if (port == ds->num_ports) 1344 port = 0x1f; 1345 1346 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1347 if (err) 1348 return err; 1349 } 1350 1351 if (chip->info->ops->set_cascade_port) { 1352 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1353 err = chip->info->ops->set_cascade_port(chip, port); 1354 if (err) 1355 return err; 1356 } 1357 1358 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1359 if (err) 1360 return err; 1361 1362 return 0; 1363 } 1364 1365 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1366 { 1367 /* Clear all trunk masks and mapping */ 1368 if (chip->info->global2_addr) 1369 return mv88e6xxx_g2_trunk_clear(chip); 1370 1371 return 0; 1372 } 1373 1374 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1375 { 1376 if (chip->info->ops->rmu_disable) 1377 return chip->info->ops->rmu_disable(chip); 1378 1379 return 0; 1380 } 1381 1382 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1383 { 1384 if (chip->info->ops->pot_clear) 1385 return chip->info->ops->pot_clear(chip); 1386 1387 return 0; 1388 } 1389 1390 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1391 { 1392 if (chip->info->ops->mgmt_rsvd2cpu) 1393 return chip->info->ops->mgmt_rsvd2cpu(chip); 1394 1395 return 0; 1396 } 1397 1398 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1399 { 1400 int err; 1401 1402 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1403 if (err) 1404 return err; 1405 1406 /* The chips that have a "learn2all" bit in Global1, ATU 1407 * Control are precisely those whose port registers have a 1408 * Message Port bit in Port Control 1 and hence implement 1409 * ->port_setup_message_port. 1410 */ 1411 if (chip->info->ops->port_setup_message_port) { 1412 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1413 if (err) 1414 return err; 1415 } 1416 1417 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1418 } 1419 1420 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1421 { 1422 int port; 1423 int err; 1424 1425 if (!chip->info->ops->irl_init_all) 1426 return 0; 1427 1428 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1429 /* Disable ingress rate limiting by resetting all per port 1430 * ingress rate limit resources to their initial state. 1431 */ 1432 err = chip->info->ops->irl_init_all(chip, port); 1433 if (err) 1434 return err; 1435 } 1436 1437 return 0; 1438 } 1439 1440 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1441 { 1442 if (chip->info->ops->set_switch_mac) { 1443 u8 addr[ETH_ALEN]; 1444 1445 eth_random_addr(addr); 1446 1447 return chip->info->ops->set_switch_mac(chip, addr); 1448 } 1449 1450 return 0; 1451 } 1452 1453 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1454 { 1455 struct dsa_switch_tree *dst = chip->ds->dst; 1456 struct dsa_switch *ds; 1457 struct dsa_port *dp; 1458 u16 pvlan = 0; 1459 1460 if (!mv88e6xxx_has_pvt(chip)) 1461 return 0; 1462 1463 /* Skip the local source device, which uses in-chip port VLAN */ 1464 if (dev != chip->ds->index) { 1465 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1466 1467 ds = dsa_switch_find(dst->index, dev); 1468 dp = ds ? dsa_to_port(ds, port) : NULL; 1469 if (dp && dp->lag_dev) { 1470 /* As the PVT is used to limit flooding of 1471 * FORWARD frames, which use the LAG ID as the 1472 * source port, we must translate dev/port to 1473 * the special "LAG device" in the PVT, using 1474 * the LAG ID as the port number. 1475 */ 1476 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1477 port = dsa_lag_id(dst, dp->lag_dev); 1478 } 1479 } 1480 1481 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1482 } 1483 1484 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1485 { 1486 int dev, port; 1487 int err; 1488 1489 if (!mv88e6xxx_has_pvt(chip)) 1490 return 0; 1491 1492 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1493 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1494 */ 1495 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1496 if (err) 1497 return err; 1498 1499 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1500 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1501 err = mv88e6xxx_pvt_map(chip, dev, port); 1502 if (err) 1503 return err; 1504 } 1505 } 1506 1507 return 0; 1508 } 1509 1510 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1511 { 1512 struct mv88e6xxx_chip *chip = ds->priv; 1513 int err; 1514 1515 if (dsa_to_port(ds, port)->lag_dev) 1516 /* Hardware is incapable of fast-aging a LAG through a 1517 * regular ATU move operation. Until we have something 1518 * more fancy in place this is a no-op. 1519 */ 1520 return; 1521 1522 mv88e6xxx_reg_lock(chip); 1523 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1524 mv88e6xxx_reg_unlock(chip); 1525 1526 if (err) 1527 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1528 } 1529 1530 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1531 { 1532 if (!mv88e6xxx_max_vid(chip)) 1533 return 0; 1534 1535 return mv88e6xxx_g1_vtu_flush(chip); 1536 } 1537 1538 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1539 struct mv88e6xxx_vtu_entry *entry) 1540 { 1541 int err; 1542 1543 if (!chip->info->ops->vtu_getnext) 1544 return -EOPNOTSUPP; 1545 1546 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1547 entry->valid = false; 1548 1549 err = chip->info->ops->vtu_getnext(chip, entry); 1550 1551 if (entry->vid != vid) 1552 entry->valid = false; 1553 1554 return err; 1555 } 1556 1557 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1558 int (*cb)(struct mv88e6xxx_chip *chip, 1559 const struct mv88e6xxx_vtu_entry *entry, 1560 void *priv), 1561 void *priv) 1562 { 1563 struct mv88e6xxx_vtu_entry entry = { 1564 .vid = mv88e6xxx_max_vid(chip), 1565 .valid = false, 1566 }; 1567 int err; 1568 1569 if (!chip->info->ops->vtu_getnext) 1570 return -EOPNOTSUPP; 1571 1572 do { 1573 err = chip->info->ops->vtu_getnext(chip, &entry); 1574 if (err) 1575 return err; 1576 1577 if (!entry.valid) 1578 break; 1579 1580 err = cb(chip, &entry, priv); 1581 if (err) 1582 return err; 1583 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1584 1585 return 0; 1586 } 1587 1588 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1589 struct mv88e6xxx_vtu_entry *entry) 1590 { 1591 if (!chip->info->ops->vtu_loadpurge) 1592 return -EOPNOTSUPP; 1593 1594 return chip->info->ops->vtu_loadpurge(chip, entry); 1595 } 1596 1597 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1598 const struct mv88e6xxx_vtu_entry *entry, 1599 void *_fid_bitmap) 1600 { 1601 unsigned long *fid_bitmap = _fid_bitmap; 1602 1603 set_bit(entry->fid, fid_bitmap); 1604 return 0; 1605 } 1606 1607 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1608 { 1609 int i, err; 1610 u16 fid; 1611 1612 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1613 1614 /* Set every FID bit used by the (un)bridged ports */ 1615 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1616 err = mv88e6xxx_port_get_fid(chip, i, &fid); 1617 if (err) 1618 return err; 1619 1620 set_bit(fid, fid_bitmap); 1621 } 1622 1623 /* Set every FID bit used by the VLAN entries */ 1624 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1625 } 1626 1627 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1628 { 1629 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1630 int err; 1631 1632 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1633 if (err) 1634 return err; 1635 1636 /* The reset value 0x000 is used to indicate that multiple address 1637 * databases are not needed. Return the next positive available. 1638 */ 1639 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1640 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1641 return -ENOSPC; 1642 1643 /* Clear the database */ 1644 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1645 } 1646 1647 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1648 u16 vid) 1649 { 1650 struct mv88e6xxx_chip *chip = ds->priv; 1651 struct mv88e6xxx_vtu_entry vlan; 1652 int i, err; 1653 1654 /* DSA and CPU ports have to be members of multiple vlans */ 1655 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1656 return 0; 1657 1658 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1659 if (err) 1660 return err; 1661 1662 if (!vlan.valid) 1663 return 0; 1664 1665 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1666 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1667 continue; 1668 1669 if (!dsa_to_port(ds, i)->slave) 1670 continue; 1671 1672 if (vlan.member[i] == 1673 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1674 continue; 1675 1676 if (dsa_to_port(ds, i)->bridge_dev == 1677 dsa_to_port(ds, port)->bridge_dev) 1678 break; /* same bridge, check next VLAN */ 1679 1680 if (!dsa_to_port(ds, i)->bridge_dev) 1681 continue; 1682 1683 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1684 port, vlan.vid, i, 1685 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1686 return -EOPNOTSUPP; 1687 } 1688 1689 return 0; 1690 } 1691 1692 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 1693 { 1694 struct dsa_port *dp = dsa_to_port(chip->ds, port); 1695 struct mv88e6xxx_port *p = &chip->ports[port]; 1696 u16 pvid = MV88E6XXX_VID_STANDALONE; 1697 bool drop_untagged = false; 1698 int err; 1699 1700 if (dp->bridge_dev) { 1701 if (br_vlan_enabled(dp->bridge_dev)) { 1702 pvid = p->bridge_pvid.vid; 1703 drop_untagged = !p->bridge_pvid.valid; 1704 } else { 1705 pvid = MV88E6XXX_VID_BRIDGED; 1706 } 1707 } 1708 1709 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 1710 if (err) 1711 return err; 1712 1713 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 1714 } 1715 1716 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1717 bool vlan_filtering, 1718 struct netlink_ext_ack *extack) 1719 { 1720 struct mv88e6xxx_chip *chip = ds->priv; 1721 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1722 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1723 int err; 1724 1725 if (!mv88e6xxx_max_vid(chip)) 1726 return -EOPNOTSUPP; 1727 1728 mv88e6xxx_reg_lock(chip); 1729 1730 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1731 if (err) 1732 goto unlock; 1733 1734 err = mv88e6xxx_port_commit_pvid(chip, port); 1735 if (err) 1736 goto unlock; 1737 1738 unlock: 1739 mv88e6xxx_reg_unlock(chip); 1740 1741 return err; 1742 } 1743 1744 static int 1745 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1746 const struct switchdev_obj_port_vlan *vlan) 1747 { 1748 struct mv88e6xxx_chip *chip = ds->priv; 1749 int err; 1750 1751 if (!mv88e6xxx_max_vid(chip)) 1752 return -EOPNOTSUPP; 1753 1754 /* If the requested port doesn't belong to the same bridge as the VLAN 1755 * members, do not support it (yet) and fallback to software VLAN. 1756 */ 1757 mv88e6xxx_reg_lock(chip); 1758 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 1759 mv88e6xxx_reg_unlock(chip); 1760 1761 return err; 1762 } 1763 1764 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1765 const unsigned char *addr, u16 vid, 1766 u8 state) 1767 { 1768 struct mv88e6xxx_atu_entry entry; 1769 struct mv88e6xxx_vtu_entry vlan; 1770 u16 fid; 1771 int err; 1772 1773 /* Ports have two private address databases: one for when the port is 1774 * standalone and one for when the port is under a bridge and the 1775 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 1776 * address database to remain 100% empty, so we never load an ATU entry 1777 * into a standalone port's database. Therefore, translate the null 1778 * VLAN ID into the port's database used for VLAN-unaware bridging. 1779 */ 1780 if (vid == 0) { 1781 fid = MV88E6XXX_FID_BRIDGED; 1782 } else { 1783 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1784 if (err) 1785 return err; 1786 1787 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1788 if (!vlan.valid) 1789 return -EOPNOTSUPP; 1790 1791 fid = vlan.fid; 1792 } 1793 1794 entry.state = 0; 1795 ether_addr_copy(entry.mac, addr); 1796 eth_addr_dec(entry.mac); 1797 1798 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1799 if (err) 1800 return err; 1801 1802 /* Initialize a fresh ATU entry if it isn't found */ 1803 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1804 memset(&entry, 0, sizeof(entry)); 1805 ether_addr_copy(entry.mac, addr); 1806 } 1807 1808 /* Purge the ATU entry only if no port is using it anymore */ 1809 if (!state) { 1810 entry.portvec &= ~BIT(port); 1811 if (!entry.portvec) 1812 entry.state = 0; 1813 } else { 1814 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 1815 entry.portvec = BIT(port); 1816 else 1817 entry.portvec |= BIT(port); 1818 1819 entry.state = state; 1820 } 1821 1822 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1823 } 1824 1825 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1826 const struct mv88e6xxx_policy *policy) 1827 { 1828 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1829 enum mv88e6xxx_policy_action action = policy->action; 1830 const u8 *addr = policy->addr; 1831 u16 vid = policy->vid; 1832 u8 state; 1833 int err; 1834 int id; 1835 1836 if (!chip->info->ops->port_set_policy) 1837 return -EOPNOTSUPP; 1838 1839 switch (mapping) { 1840 case MV88E6XXX_POLICY_MAPPING_DA: 1841 case MV88E6XXX_POLICY_MAPPING_SA: 1842 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1843 state = 0; /* Dissociate the port and address */ 1844 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1845 is_multicast_ether_addr(addr)) 1846 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1847 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1848 is_unicast_ether_addr(addr)) 1849 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1850 else 1851 return -EOPNOTSUPP; 1852 1853 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1854 state); 1855 if (err) 1856 return err; 1857 break; 1858 default: 1859 return -EOPNOTSUPP; 1860 } 1861 1862 /* Skip the port's policy clearing if the mapping is still in use */ 1863 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1864 idr_for_each_entry(&chip->policies, policy, id) 1865 if (policy->port == port && 1866 policy->mapping == mapping && 1867 policy->action != action) 1868 return 0; 1869 1870 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1871 } 1872 1873 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1874 struct ethtool_rx_flow_spec *fs) 1875 { 1876 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1877 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1878 enum mv88e6xxx_policy_mapping mapping; 1879 enum mv88e6xxx_policy_action action; 1880 struct mv88e6xxx_policy *policy; 1881 u16 vid = 0; 1882 u8 *addr; 1883 int err; 1884 int id; 1885 1886 if (fs->location != RX_CLS_LOC_ANY) 1887 return -EINVAL; 1888 1889 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1890 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1891 else 1892 return -EOPNOTSUPP; 1893 1894 switch (fs->flow_type & ~FLOW_EXT) { 1895 case ETHER_FLOW: 1896 if (!is_zero_ether_addr(mac_mask->h_dest) && 1897 is_zero_ether_addr(mac_mask->h_source)) { 1898 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1899 addr = mac_entry->h_dest; 1900 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1901 !is_zero_ether_addr(mac_mask->h_source)) { 1902 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1903 addr = mac_entry->h_source; 1904 } else { 1905 /* Cannot support DA and SA mapping in the same rule */ 1906 return -EOPNOTSUPP; 1907 } 1908 break; 1909 default: 1910 return -EOPNOTSUPP; 1911 } 1912 1913 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1914 if (fs->m_ext.vlan_tci != htons(0xffff)) 1915 return -EOPNOTSUPP; 1916 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1917 } 1918 1919 idr_for_each_entry(&chip->policies, policy, id) { 1920 if (policy->port == port && policy->mapping == mapping && 1921 policy->action == action && policy->vid == vid && 1922 ether_addr_equal(policy->addr, addr)) 1923 return -EEXIST; 1924 } 1925 1926 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1927 if (!policy) 1928 return -ENOMEM; 1929 1930 fs->location = 0; 1931 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1932 GFP_KERNEL); 1933 if (err) { 1934 devm_kfree(chip->dev, policy); 1935 return err; 1936 } 1937 1938 memcpy(&policy->fs, fs, sizeof(*fs)); 1939 ether_addr_copy(policy->addr, addr); 1940 policy->mapping = mapping; 1941 policy->action = action; 1942 policy->port = port; 1943 policy->vid = vid; 1944 1945 err = mv88e6xxx_policy_apply(chip, port, policy); 1946 if (err) { 1947 idr_remove(&chip->policies, fs->location); 1948 devm_kfree(chip->dev, policy); 1949 return err; 1950 } 1951 1952 return 0; 1953 } 1954 1955 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1956 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1957 { 1958 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1959 struct mv88e6xxx_chip *chip = ds->priv; 1960 struct mv88e6xxx_policy *policy; 1961 int err; 1962 int id; 1963 1964 mv88e6xxx_reg_lock(chip); 1965 1966 switch (rxnfc->cmd) { 1967 case ETHTOOL_GRXCLSRLCNT: 1968 rxnfc->data = 0; 1969 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1970 rxnfc->rule_cnt = 0; 1971 idr_for_each_entry(&chip->policies, policy, id) 1972 if (policy->port == port) 1973 rxnfc->rule_cnt++; 1974 err = 0; 1975 break; 1976 case ETHTOOL_GRXCLSRULE: 1977 err = -ENOENT; 1978 policy = idr_find(&chip->policies, fs->location); 1979 if (policy) { 1980 memcpy(fs, &policy->fs, sizeof(*fs)); 1981 err = 0; 1982 } 1983 break; 1984 case ETHTOOL_GRXCLSRLALL: 1985 rxnfc->data = 0; 1986 rxnfc->rule_cnt = 0; 1987 idr_for_each_entry(&chip->policies, policy, id) 1988 if (policy->port == port) 1989 rule_locs[rxnfc->rule_cnt++] = id; 1990 err = 0; 1991 break; 1992 default: 1993 err = -EOPNOTSUPP; 1994 break; 1995 } 1996 1997 mv88e6xxx_reg_unlock(chip); 1998 1999 return err; 2000 } 2001 2002 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2003 struct ethtool_rxnfc *rxnfc) 2004 { 2005 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2006 struct mv88e6xxx_chip *chip = ds->priv; 2007 struct mv88e6xxx_policy *policy; 2008 int err; 2009 2010 mv88e6xxx_reg_lock(chip); 2011 2012 switch (rxnfc->cmd) { 2013 case ETHTOOL_SRXCLSRLINS: 2014 err = mv88e6xxx_policy_insert(chip, port, fs); 2015 break; 2016 case ETHTOOL_SRXCLSRLDEL: 2017 err = -ENOENT; 2018 policy = idr_remove(&chip->policies, fs->location); 2019 if (policy) { 2020 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2021 err = mv88e6xxx_policy_apply(chip, port, policy); 2022 devm_kfree(chip->dev, policy); 2023 } 2024 break; 2025 default: 2026 err = -EOPNOTSUPP; 2027 break; 2028 } 2029 2030 mv88e6xxx_reg_unlock(chip); 2031 2032 return err; 2033 } 2034 2035 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2036 u16 vid) 2037 { 2038 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2039 u8 broadcast[ETH_ALEN]; 2040 2041 eth_broadcast_addr(broadcast); 2042 2043 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2044 } 2045 2046 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2047 { 2048 int port; 2049 int err; 2050 2051 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2052 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2053 struct net_device *brport; 2054 2055 if (dsa_is_unused_port(chip->ds, port)) 2056 continue; 2057 2058 brport = dsa_port_to_bridge_port(dp); 2059 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2060 /* Skip bridged user ports where broadcast 2061 * flooding is disabled. 2062 */ 2063 continue; 2064 2065 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2066 if (err) 2067 return err; 2068 } 2069 2070 return 0; 2071 } 2072 2073 struct mv88e6xxx_port_broadcast_sync_ctx { 2074 int port; 2075 bool flood; 2076 }; 2077 2078 static int 2079 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2080 const struct mv88e6xxx_vtu_entry *vlan, 2081 void *_ctx) 2082 { 2083 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2084 u8 broadcast[ETH_ALEN]; 2085 u8 state; 2086 2087 if (ctx->flood) 2088 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2089 else 2090 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2091 2092 eth_broadcast_addr(broadcast); 2093 2094 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2095 vlan->vid, state); 2096 } 2097 2098 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2099 bool flood) 2100 { 2101 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2102 .port = port, 2103 .flood = flood, 2104 }; 2105 struct mv88e6xxx_vtu_entry vid0 = { 2106 .vid = 0, 2107 }; 2108 int err; 2109 2110 /* Update the port's private database... */ 2111 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2112 if (err) 2113 return err; 2114 2115 /* ...and the database for all VLANs. */ 2116 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2117 &ctx); 2118 } 2119 2120 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2121 u16 vid, u8 member, bool warn) 2122 { 2123 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2124 struct mv88e6xxx_vtu_entry vlan; 2125 int i, err; 2126 2127 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2128 if (err) 2129 return err; 2130 2131 if (!vlan.valid) { 2132 memset(&vlan, 0, sizeof(vlan)); 2133 2134 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2135 if (err) 2136 return err; 2137 2138 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2139 if (i == port) 2140 vlan.member[i] = member; 2141 else 2142 vlan.member[i] = non_member; 2143 2144 vlan.vid = vid; 2145 vlan.valid = true; 2146 2147 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2148 if (err) 2149 return err; 2150 2151 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2152 if (err) 2153 return err; 2154 } else if (vlan.member[port] != member) { 2155 vlan.member[port] = member; 2156 2157 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2158 if (err) 2159 return err; 2160 } else if (warn) { 2161 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2162 port, vid); 2163 } 2164 2165 return 0; 2166 } 2167 2168 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2169 const struct switchdev_obj_port_vlan *vlan, 2170 struct netlink_ext_ack *extack) 2171 { 2172 struct mv88e6xxx_chip *chip = ds->priv; 2173 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2174 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2175 struct mv88e6xxx_port *p = &chip->ports[port]; 2176 bool warn; 2177 u8 member; 2178 int err; 2179 2180 if (!vlan->vid) 2181 return 0; 2182 2183 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2184 if (err) 2185 return err; 2186 2187 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2188 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2189 else if (untagged) 2190 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2191 else 2192 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2193 2194 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2195 * and then the CPU port. Do not warn for duplicates for the CPU port. 2196 */ 2197 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2198 2199 mv88e6xxx_reg_lock(chip); 2200 2201 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2202 if (err) { 2203 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2204 vlan->vid, untagged ? 'u' : 't'); 2205 goto out; 2206 } 2207 2208 if (pvid) { 2209 p->bridge_pvid.vid = vlan->vid; 2210 p->bridge_pvid.valid = true; 2211 2212 err = mv88e6xxx_port_commit_pvid(chip, port); 2213 if (err) 2214 goto out; 2215 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2216 /* The old pvid was reinstalled as a non-pvid VLAN */ 2217 p->bridge_pvid.valid = false; 2218 2219 err = mv88e6xxx_port_commit_pvid(chip, port); 2220 if (err) 2221 goto out; 2222 } 2223 2224 out: 2225 mv88e6xxx_reg_unlock(chip); 2226 2227 return err; 2228 } 2229 2230 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2231 int port, u16 vid) 2232 { 2233 struct mv88e6xxx_vtu_entry vlan; 2234 int i, err; 2235 2236 if (!vid) 2237 return 0; 2238 2239 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2240 if (err) 2241 return err; 2242 2243 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2244 * tell switchdev that this VLAN is likely handled in software. 2245 */ 2246 if (!vlan.valid || 2247 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2248 return -EOPNOTSUPP; 2249 2250 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2251 2252 /* keep the VLAN unless all ports are excluded */ 2253 vlan.valid = false; 2254 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2255 if (vlan.member[i] != 2256 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2257 vlan.valid = true; 2258 break; 2259 } 2260 } 2261 2262 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2263 if (err) 2264 return err; 2265 2266 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2267 } 2268 2269 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2270 const struct switchdev_obj_port_vlan *vlan) 2271 { 2272 struct mv88e6xxx_chip *chip = ds->priv; 2273 struct mv88e6xxx_port *p = &chip->ports[port]; 2274 int err = 0; 2275 u16 pvid; 2276 2277 if (!mv88e6xxx_max_vid(chip)) 2278 return -EOPNOTSUPP; 2279 2280 mv88e6xxx_reg_lock(chip); 2281 2282 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2283 if (err) 2284 goto unlock; 2285 2286 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2287 if (err) 2288 goto unlock; 2289 2290 if (vlan->vid == pvid) { 2291 p->bridge_pvid.valid = false; 2292 2293 err = mv88e6xxx_port_commit_pvid(chip, port); 2294 if (err) 2295 goto unlock; 2296 } 2297 2298 unlock: 2299 mv88e6xxx_reg_unlock(chip); 2300 2301 return err; 2302 } 2303 2304 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2305 const unsigned char *addr, u16 vid) 2306 { 2307 struct mv88e6xxx_chip *chip = ds->priv; 2308 int err; 2309 2310 mv88e6xxx_reg_lock(chip); 2311 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2312 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2313 mv88e6xxx_reg_unlock(chip); 2314 2315 return err; 2316 } 2317 2318 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2319 const unsigned char *addr, u16 vid) 2320 { 2321 struct mv88e6xxx_chip *chip = ds->priv; 2322 int err; 2323 2324 mv88e6xxx_reg_lock(chip); 2325 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2326 mv88e6xxx_reg_unlock(chip); 2327 2328 return err; 2329 } 2330 2331 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2332 u16 fid, u16 vid, int port, 2333 dsa_fdb_dump_cb_t *cb, void *data) 2334 { 2335 struct mv88e6xxx_atu_entry addr; 2336 bool is_static; 2337 int err; 2338 2339 addr.state = 0; 2340 eth_broadcast_addr(addr.mac); 2341 2342 do { 2343 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2344 if (err) 2345 return err; 2346 2347 if (!addr.state) 2348 break; 2349 2350 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2351 continue; 2352 2353 if (!is_unicast_ether_addr(addr.mac)) 2354 continue; 2355 2356 is_static = (addr.state == 2357 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2358 err = cb(addr.mac, vid, is_static, data); 2359 if (err) 2360 return err; 2361 } while (!is_broadcast_ether_addr(addr.mac)); 2362 2363 return err; 2364 } 2365 2366 struct mv88e6xxx_port_db_dump_vlan_ctx { 2367 int port; 2368 dsa_fdb_dump_cb_t *cb; 2369 void *data; 2370 }; 2371 2372 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2373 const struct mv88e6xxx_vtu_entry *entry, 2374 void *_data) 2375 { 2376 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2377 2378 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2379 ctx->port, ctx->cb, ctx->data); 2380 } 2381 2382 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2383 dsa_fdb_dump_cb_t *cb, void *data) 2384 { 2385 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2386 .port = port, 2387 .cb = cb, 2388 .data = data, 2389 }; 2390 u16 fid; 2391 int err; 2392 2393 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2394 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2395 if (err) 2396 return err; 2397 2398 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2399 if (err) 2400 return err; 2401 2402 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2403 } 2404 2405 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2406 dsa_fdb_dump_cb_t *cb, void *data) 2407 { 2408 struct mv88e6xxx_chip *chip = ds->priv; 2409 int err; 2410 2411 mv88e6xxx_reg_lock(chip); 2412 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2413 mv88e6xxx_reg_unlock(chip); 2414 2415 return err; 2416 } 2417 2418 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2419 struct net_device *br) 2420 { 2421 struct dsa_switch *ds = chip->ds; 2422 struct dsa_switch_tree *dst = ds->dst; 2423 struct dsa_port *dp; 2424 int err; 2425 2426 list_for_each_entry(dp, &dst->ports, list) { 2427 if (dp->bridge_dev == br) { 2428 if (dp->ds == ds) { 2429 /* This is a local bridge group member, 2430 * remap its Port VLAN Map. 2431 */ 2432 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2433 if (err) 2434 return err; 2435 } else { 2436 /* This is an external bridge group member, 2437 * remap its cross-chip Port VLAN Table entry. 2438 */ 2439 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2440 dp->index); 2441 if (err) 2442 return err; 2443 } 2444 } 2445 } 2446 2447 return 0; 2448 } 2449 2450 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2451 struct net_device *br) 2452 { 2453 struct mv88e6xxx_chip *chip = ds->priv; 2454 int err; 2455 2456 mv88e6xxx_reg_lock(chip); 2457 2458 err = mv88e6xxx_bridge_map(chip, br); 2459 if (err) 2460 goto unlock; 2461 2462 err = mv88e6xxx_port_commit_pvid(chip, port); 2463 if (err) 2464 goto unlock; 2465 2466 unlock: 2467 mv88e6xxx_reg_unlock(chip); 2468 2469 return err; 2470 } 2471 2472 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2473 struct net_device *br) 2474 { 2475 struct mv88e6xxx_chip *chip = ds->priv; 2476 int err; 2477 2478 mv88e6xxx_reg_lock(chip); 2479 2480 if (mv88e6xxx_bridge_map(chip, br) || 2481 mv88e6xxx_port_vlan_map(chip, port)) 2482 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2483 2484 err = mv88e6xxx_port_commit_pvid(chip, port); 2485 if (err) 2486 dev_err(ds->dev, 2487 "port %d failed to restore standalone pvid: %pe\n", 2488 port, ERR_PTR(err)); 2489 2490 mv88e6xxx_reg_unlock(chip); 2491 } 2492 2493 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2494 int tree_index, int sw_index, 2495 int port, struct net_device *br) 2496 { 2497 struct mv88e6xxx_chip *chip = ds->priv; 2498 int err; 2499 2500 if (tree_index != ds->dst->index) 2501 return 0; 2502 2503 mv88e6xxx_reg_lock(chip); 2504 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2505 mv88e6xxx_reg_unlock(chip); 2506 2507 return err; 2508 } 2509 2510 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2511 int tree_index, int sw_index, 2512 int port, struct net_device *br) 2513 { 2514 struct mv88e6xxx_chip *chip = ds->priv; 2515 2516 if (tree_index != ds->dst->index) 2517 return; 2518 2519 mv88e6xxx_reg_lock(chip); 2520 if (mv88e6xxx_pvt_map(chip, sw_index, port)) 2521 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2522 mv88e6xxx_reg_unlock(chip); 2523 } 2524 2525 /* Treat the software bridge as a virtual single-port switch behind the 2526 * CPU and map in the PVT. First dst->last_switch elements are taken by 2527 * physical switches, so start from beyond that range. 2528 */ 2529 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2530 int bridge_num) 2531 { 2532 u8 dev = bridge_num + ds->dst->last_switch + 1; 2533 struct mv88e6xxx_chip *chip = ds->priv; 2534 int err; 2535 2536 mv88e6xxx_reg_lock(chip); 2537 err = mv88e6xxx_pvt_map(chip, dev, 0); 2538 mv88e6xxx_reg_unlock(chip); 2539 2540 return err; 2541 } 2542 2543 static int mv88e6xxx_bridge_tx_fwd_offload(struct dsa_switch *ds, int port, 2544 struct net_device *br, 2545 int bridge_num) 2546 { 2547 return mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num); 2548 } 2549 2550 static void mv88e6xxx_bridge_tx_fwd_unoffload(struct dsa_switch *ds, int port, 2551 struct net_device *br, 2552 int bridge_num) 2553 { 2554 int err; 2555 2556 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num); 2557 if (err) { 2558 dev_err(ds->dev, "failed to remap cross-chip Port VLAN: %pe\n", 2559 ERR_PTR(err)); 2560 } 2561 } 2562 2563 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2564 { 2565 if (chip->info->ops->reset) 2566 return chip->info->ops->reset(chip); 2567 2568 return 0; 2569 } 2570 2571 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2572 { 2573 struct gpio_desc *gpiod = chip->reset; 2574 2575 /* If there is a GPIO connected to the reset pin, toggle it */ 2576 if (gpiod) { 2577 gpiod_set_value_cansleep(gpiod, 1); 2578 usleep_range(10000, 20000); 2579 gpiod_set_value_cansleep(gpiod, 0); 2580 usleep_range(10000, 20000); 2581 2582 mv88e6xxx_g1_wait_eeprom_done(chip); 2583 } 2584 } 2585 2586 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2587 { 2588 int i, err; 2589 2590 /* Set all ports to the Disabled state */ 2591 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2592 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2593 if (err) 2594 return err; 2595 } 2596 2597 /* Wait for transmit queues to drain, 2598 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2599 */ 2600 usleep_range(2000, 4000); 2601 2602 return 0; 2603 } 2604 2605 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2606 { 2607 int err; 2608 2609 err = mv88e6xxx_disable_ports(chip); 2610 if (err) 2611 return err; 2612 2613 mv88e6xxx_hardware_reset(chip); 2614 2615 return mv88e6xxx_software_reset(chip); 2616 } 2617 2618 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2619 enum mv88e6xxx_frame_mode frame, 2620 enum mv88e6xxx_egress_mode egress, u16 etype) 2621 { 2622 int err; 2623 2624 if (!chip->info->ops->port_set_frame_mode) 2625 return -EOPNOTSUPP; 2626 2627 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2628 if (err) 2629 return err; 2630 2631 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2632 if (err) 2633 return err; 2634 2635 if (chip->info->ops->port_set_ether_type) 2636 return chip->info->ops->port_set_ether_type(chip, port, etype); 2637 2638 return 0; 2639 } 2640 2641 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2642 { 2643 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2644 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2645 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2646 } 2647 2648 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2649 { 2650 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2651 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2652 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2653 } 2654 2655 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2656 { 2657 return mv88e6xxx_set_port_mode(chip, port, 2658 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2659 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2660 ETH_P_EDSA); 2661 } 2662 2663 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2664 { 2665 if (dsa_is_dsa_port(chip->ds, port)) 2666 return mv88e6xxx_set_port_mode_dsa(chip, port); 2667 2668 if (dsa_is_user_port(chip->ds, port)) 2669 return mv88e6xxx_set_port_mode_normal(chip, port); 2670 2671 /* Setup CPU port mode depending on its supported tag format */ 2672 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 2673 return mv88e6xxx_set_port_mode_dsa(chip, port); 2674 2675 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 2676 return mv88e6xxx_set_port_mode_edsa(chip, port); 2677 2678 return -EINVAL; 2679 } 2680 2681 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2682 { 2683 bool message = dsa_is_dsa_port(chip->ds, port); 2684 2685 return mv88e6xxx_port_set_message_port(chip, port, message); 2686 } 2687 2688 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2689 { 2690 int err; 2691 2692 if (chip->info->ops->port_set_ucast_flood) { 2693 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 2694 if (err) 2695 return err; 2696 } 2697 if (chip->info->ops->port_set_mcast_flood) { 2698 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 2699 if (err) 2700 return err; 2701 } 2702 2703 return 0; 2704 } 2705 2706 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2707 { 2708 struct mv88e6xxx_port *mvp = dev_id; 2709 struct mv88e6xxx_chip *chip = mvp->chip; 2710 irqreturn_t ret = IRQ_NONE; 2711 int port = mvp->port; 2712 int lane; 2713 2714 mv88e6xxx_reg_lock(chip); 2715 lane = mv88e6xxx_serdes_get_lane(chip, port); 2716 if (lane >= 0) 2717 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2718 mv88e6xxx_reg_unlock(chip); 2719 2720 return ret; 2721 } 2722 2723 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2724 int lane) 2725 { 2726 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2727 unsigned int irq; 2728 int err; 2729 2730 /* Nothing to request if this SERDES port has no IRQ */ 2731 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2732 if (!irq) 2733 return 0; 2734 2735 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2736 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2737 2738 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2739 mv88e6xxx_reg_unlock(chip); 2740 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2741 IRQF_ONESHOT, dev_id->serdes_irq_name, 2742 dev_id); 2743 mv88e6xxx_reg_lock(chip); 2744 if (err) 2745 return err; 2746 2747 dev_id->serdes_irq = irq; 2748 2749 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2750 } 2751 2752 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2753 int lane) 2754 { 2755 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2756 unsigned int irq = dev_id->serdes_irq; 2757 int err; 2758 2759 /* Nothing to free if no IRQ has been requested */ 2760 if (!irq) 2761 return 0; 2762 2763 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2764 2765 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2766 mv88e6xxx_reg_unlock(chip); 2767 free_irq(irq, dev_id); 2768 mv88e6xxx_reg_lock(chip); 2769 2770 dev_id->serdes_irq = 0; 2771 2772 return err; 2773 } 2774 2775 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2776 bool on) 2777 { 2778 int lane; 2779 int err; 2780 2781 lane = mv88e6xxx_serdes_get_lane(chip, port); 2782 if (lane < 0) 2783 return 0; 2784 2785 if (on) { 2786 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2787 if (err) 2788 return err; 2789 2790 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2791 } else { 2792 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2793 if (err) 2794 return err; 2795 2796 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2797 } 2798 2799 return err; 2800 } 2801 2802 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 2803 enum mv88e6xxx_egress_direction direction, 2804 int port) 2805 { 2806 int err; 2807 2808 if (!chip->info->ops->set_egress_port) 2809 return -EOPNOTSUPP; 2810 2811 err = chip->info->ops->set_egress_port(chip, direction, port); 2812 if (err) 2813 return err; 2814 2815 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 2816 chip->ingress_dest_port = port; 2817 else 2818 chip->egress_dest_port = port; 2819 2820 return 0; 2821 } 2822 2823 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2824 { 2825 struct dsa_switch *ds = chip->ds; 2826 int upstream_port; 2827 int err; 2828 2829 upstream_port = dsa_upstream_port(ds, port); 2830 if (chip->info->ops->port_set_upstream_port) { 2831 err = chip->info->ops->port_set_upstream_port(chip, port, 2832 upstream_port); 2833 if (err) 2834 return err; 2835 } 2836 2837 if (port == upstream_port) { 2838 if (chip->info->ops->set_cpu_port) { 2839 err = chip->info->ops->set_cpu_port(chip, 2840 upstream_port); 2841 if (err) 2842 return err; 2843 } 2844 2845 err = mv88e6xxx_set_egress_port(chip, 2846 MV88E6XXX_EGRESS_DIR_INGRESS, 2847 upstream_port); 2848 if (err && err != -EOPNOTSUPP) 2849 return err; 2850 2851 err = mv88e6xxx_set_egress_port(chip, 2852 MV88E6XXX_EGRESS_DIR_EGRESS, 2853 upstream_port); 2854 if (err && err != -EOPNOTSUPP) 2855 return err; 2856 } 2857 2858 return 0; 2859 } 2860 2861 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2862 { 2863 struct dsa_switch *ds = chip->ds; 2864 int err; 2865 u16 reg; 2866 2867 chip->ports[port].chip = chip; 2868 chip->ports[port].port = port; 2869 2870 /* MAC Forcing register: don't force link, speed, duplex or flow control 2871 * state to any particular values on physical ports, but force the CPU 2872 * port and all DSA ports to their maximum bandwidth and full duplex. 2873 */ 2874 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2875 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2876 SPEED_MAX, DUPLEX_FULL, 2877 PAUSE_OFF, 2878 PHY_INTERFACE_MODE_NA); 2879 else 2880 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2881 SPEED_UNFORCED, DUPLEX_UNFORCED, 2882 PAUSE_ON, 2883 PHY_INTERFACE_MODE_NA); 2884 if (err) 2885 return err; 2886 2887 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2888 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2889 * tunneling, determine priority by looking at 802.1p and IP 2890 * priority fields (IP prio has precedence), and set STP state 2891 * to Forwarding. 2892 * 2893 * If this is the CPU link, use DSA or EDSA tagging depending 2894 * on which tagging mode was configured. 2895 * 2896 * If this is a link to another switch, use DSA tagging mode. 2897 * 2898 * If this is the upstream port for this switch, enable 2899 * forwarding of unknown unicasts and multicasts. 2900 */ 2901 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2902 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2903 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2904 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2905 if (err) 2906 return err; 2907 2908 err = mv88e6xxx_setup_port_mode(chip, port); 2909 if (err) 2910 return err; 2911 2912 err = mv88e6xxx_setup_egress_floods(chip, port); 2913 if (err) 2914 return err; 2915 2916 /* Port Control 2: don't force a good FCS, set the MTU size to 2917 * 10222 bytes, disable 802.1q tags checking, don't discard tagged or 2918 * untagged frames on this port, do a destination address lookup on all 2919 * received packets as usual, disable ARP mirroring and don't send a 2920 * copy of all transmitted/received frames on this port to the CPU. 2921 */ 2922 err = mv88e6xxx_port_set_map_da(chip, port); 2923 if (err) 2924 return err; 2925 2926 err = mv88e6xxx_setup_upstream_port(chip, port); 2927 if (err) 2928 return err; 2929 2930 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2931 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2932 if (err) 2933 return err; 2934 2935 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 2936 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 2937 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 2938 * as the private PVID on ports under a VLAN-unaware bridge. 2939 * Shared (DSA and CPU) ports must also be members of it, to translate 2940 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 2941 * relying on their port default FID. 2942 */ 2943 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 2944 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED, 2945 false); 2946 if (err) 2947 return err; 2948 2949 if (chip->info->ops->port_set_jumbo_size) { 2950 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 2951 if (err) 2952 return err; 2953 } 2954 2955 /* Port Association Vector: disable automatic address learning 2956 * on all user ports since they start out in standalone 2957 * mode. When joining a bridge, learning will be configured to 2958 * match the bridge port settings. Enable learning on all 2959 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 2960 * learning process. 2961 * 2962 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 2963 * and RefreshLocked. I.e. setup standard automatic learning. 2964 */ 2965 if (dsa_is_user_port(ds, port)) 2966 reg = 0; 2967 else 2968 reg = 1 << port; 2969 2970 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2971 reg); 2972 if (err) 2973 return err; 2974 2975 /* Egress rate control 2: disable egress rate control. */ 2976 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2977 0x0000); 2978 if (err) 2979 return err; 2980 2981 if (chip->info->ops->port_pause_limit) { 2982 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2983 if (err) 2984 return err; 2985 } 2986 2987 if (chip->info->ops->port_disable_learn_limit) { 2988 err = chip->info->ops->port_disable_learn_limit(chip, port); 2989 if (err) 2990 return err; 2991 } 2992 2993 if (chip->info->ops->port_disable_pri_override) { 2994 err = chip->info->ops->port_disable_pri_override(chip, port); 2995 if (err) 2996 return err; 2997 } 2998 2999 if (chip->info->ops->port_tag_remap) { 3000 err = chip->info->ops->port_tag_remap(chip, port); 3001 if (err) 3002 return err; 3003 } 3004 3005 if (chip->info->ops->port_egress_rate_limiting) { 3006 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3007 if (err) 3008 return err; 3009 } 3010 3011 if (chip->info->ops->port_setup_message_port) { 3012 err = chip->info->ops->port_setup_message_port(chip, port); 3013 if (err) 3014 return err; 3015 } 3016 3017 /* Port based VLAN map: give each port the same default address 3018 * database, and allow bidirectional communication between the 3019 * CPU and DSA port(s), and the other ports. 3020 */ 3021 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3022 if (err) 3023 return err; 3024 3025 err = mv88e6xxx_port_vlan_map(chip, port); 3026 if (err) 3027 return err; 3028 3029 /* Default VLAN ID and priority: don't set a default VLAN 3030 * ID, and set the default packet priority to zero. 3031 */ 3032 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3033 } 3034 3035 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3036 { 3037 struct mv88e6xxx_chip *chip = ds->priv; 3038 3039 if (chip->info->ops->port_set_jumbo_size) 3040 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3041 else if (chip->info->ops->set_max_frame_size) 3042 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3043 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3044 } 3045 3046 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3047 { 3048 struct mv88e6xxx_chip *chip = ds->priv; 3049 int ret = 0; 3050 3051 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3052 new_mtu += EDSA_HLEN; 3053 3054 mv88e6xxx_reg_lock(chip); 3055 if (chip->info->ops->port_set_jumbo_size) 3056 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3057 else if (chip->info->ops->set_max_frame_size) 3058 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3059 else 3060 if (new_mtu > 1522) 3061 ret = -EINVAL; 3062 mv88e6xxx_reg_unlock(chip); 3063 3064 return ret; 3065 } 3066 3067 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3068 struct phy_device *phydev) 3069 { 3070 struct mv88e6xxx_chip *chip = ds->priv; 3071 int err; 3072 3073 mv88e6xxx_reg_lock(chip); 3074 err = mv88e6xxx_serdes_power(chip, port, true); 3075 mv88e6xxx_reg_unlock(chip); 3076 3077 return err; 3078 } 3079 3080 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3081 { 3082 struct mv88e6xxx_chip *chip = ds->priv; 3083 3084 mv88e6xxx_reg_lock(chip); 3085 if (mv88e6xxx_serdes_power(chip, port, false)) 3086 dev_err(chip->dev, "failed to power off SERDES\n"); 3087 mv88e6xxx_reg_unlock(chip); 3088 } 3089 3090 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3091 unsigned int ageing_time) 3092 { 3093 struct mv88e6xxx_chip *chip = ds->priv; 3094 int err; 3095 3096 mv88e6xxx_reg_lock(chip); 3097 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3098 mv88e6xxx_reg_unlock(chip); 3099 3100 return err; 3101 } 3102 3103 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3104 { 3105 int err; 3106 3107 /* Initialize the statistics unit */ 3108 if (chip->info->ops->stats_set_histogram) { 3109 err = chip->info->ops->stats_set_histogram(chip); 3110 if (err) 3111 return err; 3112 } 3113 3114 return mv88e6xxx_g1_stats_clear(chip); 3115 } 3116 3117 /* Check if the errata has already been applied. */ 3118 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3119 { 3120 int port; 3121 int err; 3122 u16 val; 3123 3124 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3125 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3126 if (err) { 3127 dev_err(chip->dev, 3128 "Error reading hidden register: %d\n", err); 3129 return false; 3130 } 3131 if (val != 0x01c0) 3132 return false; 3133 } 3134 3135 return true; 3136 } 3137 3138 /* The 6390 copper ports have an errata which require poking magic 3139 * values into undocumented hidden registers and then performing a 3140 * software reset. 3141 */ 3142 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3143 { 3144 int port; 3145 int err; 3146 3147 if (mv88e6390_setup_errata_applied(chip)) 3148 return 0; 3149 3150 /* Set the ports into blocking mode */ 3151 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3152 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3153 if (err) 3154 return err; 3155 } 3156 3157 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3158 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3159 if (err) 3160 return err; 3161 } 3162 3163 return mv88e6xxx_software_reset(chip); 3164 } 3165 3166 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3167 { 3168 mv88e6xxx_teardown_devlink_params(ds); 3169 dsa_devlink_resources_unregister(ds); 3170 mv88e6xxx_teardown_devlink_regions_global(ds); 3171 } 3172 3173 static int mv88e6xxx_setup(struct dsa_switch *ds) 3174 { 3175 struct mv88e6xxx_chip *chip = ds->priv; 3176 u8 cmode; 3177 int err; 3178 int i; 3179 3180 chip->ds = ds; 3181 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3182 3183 /* Since virtual bridges are mapped in the PVT, the number we support 3184 * depends on the physical switch topology. We need to let DSA figure 3185 * that out and therefore we cannot set this at dsa_register_switch() 3186 * time. 3187 */ 3188 if (mv88e6xxx_has_pvt(chip)) 3189 ds->num_fwd_offloading_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3190 ds->dst->last_switch - 1; 3191 3192 mv88e6xxx_reg_lock(chip); 3193 3194 if (chip->info->ops->setup_errata) { 3195 err = chip->info->ops->setup_errata(chip); 3196 if (err) 3197 goto unlock; 3198 } 3199 3200 /* Cache the cmode of each port. */ 3201 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3202 if (chip->info->ops->port_get_cmode) { 3203 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3204 if (err) 3205 goto unlock; 3206 3207 chip->ports[i].cmode = cmode; 3208 } 3209 } 3210 3211 err = mv88e6xxx_vtu_setup(chip); 3212 if (err) 3213 goto unlock; 3214 3215 /* Setup Switch Port Registers */ 3216 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3217 if (dsa_is_unused_port(ds, i)) 3218 continue; 3219 3220 /* Prevent the use of an invalid port. */ 3221 if (mv88e6xxx_is_invalid_port(chip, i)) { 3222 dev_err(chip->dev, "port %d is invalid\n", i); 3223 err = -EINVAL; 3224 goto unlock; 3225 } 3226 3227 err = mv88e6xxx_setup_port(chip, i); 3228 if (err) 3229 goto unlock; 3230 } 3231 3232 err = mv88e6xxx_irl_setup(chip); 3233 if (err) 3234 goto unlock; 3235 3236 err = mv88e6xxx_mac_setup(chip); 3237 if (err) 3238 goto unlock; 3239 3240 err = mv88e6xxx_phy_setup(chip); 3241 if (err) 3242 goto unlock; 3243 3244 err = mv88e6xxx_pvt_setup(chip); 3245 if (err) 3246 goto unlock; 3247 3248 err = mv88e6xxx_atu_setup(chip); 3249 if (err) 3250 goto unlock; 3251 3252 err = mv88e6xxx_broadcast_setup(chip, 0); 3253 if (err) 3254 goto unlock; 3255 3256 err = mv88e6xxx_pot_setup(chip); 3257 if (err) 3258 goto unlock; 3259 3260 err = mv88e6xxx_rmu_setup(chip); 3261 if (err) 3262 goto unlock; 3263 3264 err = mv88e6xxx_rsvd2cpu_setup(chip); 3265 if (err) 3266 goto unlock; 3267 3268 err = mv88e6xxx_trunk_setup(chip); 3269 if (err) 3270 goto unlock; 3271 3272 err = mv88e6xxx_devmap_setup(chip); 3273 if (err) 3274 goto unlock; 3275 3276 err = mv88e6xxx_pri_setup(chip); 3277 if (err) 3278 goto unlock; 3279 3280 /* Setup PTP Hardware Clock and timestamping */ 3281 if (chip->info->ptp_support) { 3282 err = mv88e6xxx_ptp_setup(chip); 3283 if (err) 3284 goto unlock; 3285 3286 err = mv88e6xxx_hwtstamp_setup(chip); 3287 if (err) 3288 goto unlock; 3289 } 3290 3291 err = mv88e6xxx_stats_setup(chip); 3292 if (err) 3293 goto unlock; 3294 3295 unlock: 3296 mv88e6xxx_reg_unlock(chip); 3297 3298 if (err) 3299 return err; 3300 3301 /* Have to be called without holding the register lock, since 3302 * they take the devlink lock, and we later take the locks in 3303 * the reverse order when getting/setting parameters or 3304 * resource occupancy. 3305 */ 3306 err = mv88e6xxx_setup_devlink_resources(ds); 3307 if (err) 3308 return err; 3309 3310 err = mv88e6xxx_setup_devlink_params(ds); 3311 if (err) 3312 goto out_resources; 3313 3314 err = mv88e6xxx_setup_devlink_regions_global(ds); 3315 if (err) 3316 goto out_params; 3317 3318 return 0; 3319 3320 out_params: 3321 mv88e6xxx_teardown_devlink_params(ds); 3322 out_resources: 3323 dsa_devlink_resources_unregister(ds); 3324 3325 return err; 3326 } 3327 3328 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3329 { 3330 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3331 } 3332 3333 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3334 { 3335 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3336 } 3337 3338 /* prod_id for switch families which do not have a PHY model number */ 3339 static const u16 family_prod_id_table[] = { 3340 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3341 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3342 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3343 }; 3344 3345 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3346 { 3347 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3348 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3349 u16 prod_id; 3350 u16 val; 3351 int err; 3352 3353 if (!chip->info->ops->phy_read) 3354 return -EOPNOTSUPP; 3355 3356 mv88e6xxx_reg_lock(chip); 3357 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3358 mv88e6xxx_reg_unlock(chip); 3359 3360 /* Some internal PHYs don't have a model number. */ 3361 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3362 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3363 prod_id = family_prod_id_table[chip->info->family]; 3364 if (prod_id) 3365 val |= prod_id >> 4; 3366 } 3367 3368 return err ? err : val; 3369 } 3370 3371 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3372 { 3373 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3374 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3375 int err; 3376 3377 if (!chip->info->ops->phy_write) 3378 return -EOPNOTSUPP; 3379 3380 mv88e6xxx_reg_lock(chip); 3381 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3382 mv88e6xxx_reg_unlock(chip); 3383 3384 return err; 3385 } 3386 3387 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3388 struct device_node *np, 3389 bool external) 3390 { 3391 static int index; 3392 struct mv88e6xxx_mdio_bus *mdio_bus; 3393 struct mii_bus *bus; 3394 int err; 3395 3396 if (external) { 3397 mv88e6xxx_reg_lock(chip); 3398 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3399 mv88e6xxx_reg_unlock(chip); 3400 3401 if (err) 3402 return err; 3403 } 3404 3405 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3406 if (!bus) 3407 return -ENOMEM; 3408 3409 mdio_bus = bus->priv; 3410 mdio_bus->bus = bus; 3411 mdio_bus->chip = chip; 3412 INIT_LIST_HEAD(&mdio_bus->list); 3413 mdio_bus->external = external; 3414 3415 if (np) { 3416 bus->name = np->full_name; 3417 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3418 } else { 3419 bus->name = "mv88e6xxx SMI"; 3420 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3421 } 3422 3423 bus->read = mv88e6xxx_mdio_read; 3424 bus->write = mv88e6xxx_mdio_write; 3425 bus->parent = chip->dev; 3426 3427 if (!external) { 3428 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3429 if (err) 3430 return err; 3431 } 3432 3433 err = of_mdiobus_register(bus, np); 3434 if (err) { 3435 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3436 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3437 return err; 3438 } 3439 3440 if (external) 3441 list_add_tail(&mdio_bus->list, &chip->mdios); 3442 else 3443 list_add(&mdio_bus->list, &chip->mdios); 3444 3445 return 0; 3446 } 3447 3448 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3449 3450 { 3451 struct mv88e6xxx_mdio_bus *mdio_bus; 3452 struct mii_bus *bus; 3453 3454 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3455 bus = mdio_bus->bus; 3456 3457 if (!mdio_bus->external) 3458 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3459 3460 mdiobus_unregister(bus); 3461 } 3462 } 3463 3464 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3465 struct device_node *np) 3466 { 3467 struct device_node *child; 3468 int err; 3469 3470 /* Always register one mdio bus for the internal/default mdio 3471 * bus. This maybe represented in the device tree, but is 3472 * optional. 3473 */ 3474 child = of_get_child_by_name(np, "mdio"); 3475 err = mv88e6xxx_mdio_register(chip, child, false); 3476 if (err) 3477 return err; 3478 3479 /* Walk the device tree, and see if there are any other nodes 3480 * which say they are compatible with the external mdio 3481 * bus. 3482 */ 3483 for_each_available_child_of_node(np, child) { 3484 if (of_device_is_compatible( 3485 child, "marvell,mv88e6xxx-mdio-external")) { 3486 err = mv88e6xxx_mdio_register(chip, child, true); 3487 if (err) { 3488 mv88e6xxx_mdios_unregister(chip); 3489 of_node_put(child); 3490 return err; 3491 } 3492 } 3493 } 3494 3495 return 0; 3496 } 3497 3498 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3499 { 3500 struct mv88e6xxx_chip *chip = ds->priv; 3501 3502 return chip->eeprom_len; 3503 } 3504 3505 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3506 struct ethtool_eeprom *eeprom, u8 *data) 3507 { 3508 struct mv88e6xxx_chip *chip = ds->priv; 3509 int err; 3510 3511 if (!chip->info->ops->get_eeprom) 3512 return -EOPNOTSUPP; 3513 3514 mv88e6xxx_reg_lock(chip); 3515 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3516 mv88e6xxx_reg_unlock(chip); 3517 3518 if (err) 3519 return err; 3520 3521 eeprom->magic = 0xc3ec4951; 3522 3523 return 0; 3524 } 3525 3526 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3527 struct ethtool_eeprom *eeprom, u8 *data) 3528 { 3529 struct mv88e6xxx_chip *chip = ds->priv; 3530 int err; 3531 3532 if (!chip->info->ops->set_eeprom) 3533 return -EOPNOTSUPP; 3534 3535 if (eeprom->magic != 0xc3ec4951) 3536 return -EINVAL; 3537 3538 mv88e6xxx_reg_lock(chip); 3539 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3540 mv88e6xxx_reg_unlock(chip); 3541 3542 return err; 3543 } 3544 3545 static const struct mv88e6xxx_ops mv88e6085_ops = { 3546 /* MV88E6XXX_FAMILY_6097 */ 3547 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3548 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3549 .irl_init_all = mv88e6352_g2_irl_init_all, 3550 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3551 .phy_read = mv88e6185_phy_ppu_read, 3552 .phy_write = mv88e6185_phy_ppu_write, 3553 .port_set_link = mv88e6xxx_port_set_link, 3554 .port_sync_link = mv88e6xxx_port_sync_link, 3555 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3556 .port_tag_remap = mv88e6095_port_tag_remap, 3557 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3558 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3559 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3560 .port_set_ether_type = mv88e6351_port_set_ether_type, 3561 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3562 .port_pause_limit = mv88e6097_port_pause_limit, 3563 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3564 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3565 .port_get_cmode = mv88e6185_port_get_cmode, 3566 .port_setup_message_port = mv88e6xxx_setup_message_port, 3567 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3568 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3569 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3570 .stats_get_strings = mv88e6095_stats_get_strings, 3571 .stats_get_stats = mv88e6095_stats_get_stats, 3572 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3573 .set_egress_port = mv88e6095_g1_set_egress_port, 3574 .watchdog_ops = &mv88e6097_watchdog_ops, 3575 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3576 .pot_clear = mv88e6xxx_g2_pot_clear, 3577 .ppu_enable = mv88e6185_g1_ppu_enable, 3578 .ppu_disable = mv88e6185_g1_ppu_disable, 3579 .reset = mv88e6185_g1_reset, 3580 .rmu_disable = mv88e6085_g1_rmu_disable, 3581 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3582 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3583 .phylink_validate = mv88e6185_phylink_validate, 3584 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3585 }; 3586 3587 static const struct mv88e6xxx_ops mv88e6095_ops = { 3588 /* MV88E6XXX_FAMILY_6095 */ 3589 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3590 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3591 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3592 .phy_read = mv88e6185_phy_ppu_read, 3593 .phy_write = mv88e6185_phy_ppu_write, 3594 .port_set_link = mv88e6xxx_port_set_link, 3595 .port_sync_link = mv88e6185_port_sync_link, 3596 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3597 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3598 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3599 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3600 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3601 .port_get_cmode = mv88e6185_port_get_cmode, 3602 .port_setup_message_port = mv88e6xxx_setup_message_port, 3603 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3604 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3605 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3606 .stats_get_strings = mv88e6095_stats_get_strings, 3607 .stats_get_stats = mv88e6095_stats_get_stats, 3608 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3609 .serdes_power = mv88e6185_serdes_power, 3610 .serdes_get_lane = mv88e6185_serdes_get_lane, 3611 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3612 .ppu_enable = mv88e6185_g1_ppu_enable, 3613 .ppu_disable = mv88e6185_g1_ppu_disable, 3614 .reset = mv88e6185_g1_reset, 3615 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3616 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3617 .phylink_validate = mv88e6185_phylink_validate, 3618 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3619 }; 3620 3621 static const struct mv88e6xxx_ops mv88e6097_ops = { 3622 /* MV88E6XXX_FAMILY_6097 */ 3623 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3624 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3625 .irl_init_all = mv88e6352_g2_irl_init_all, 3626 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3627 .phy_read = mv88e6xxx_g2_smi_phy_read, 3628 .phy_write = mv88e6xxx_g2_smi_phy_write, 3629 .port_set_link = mv88e6xxx_port_set_link, 3630 .port_sync_link = mv88e6185_port_sync_link, 3631 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3632 .port_tag_remap = mv88e6095_port_tag_remap, 3633 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3634 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3635 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3636 .port_set_ether_type = mv88e6351_port_set_ether_type, 3637 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3638 .port_pause_limit = mv88e6097_port_pause_limit, 3639 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3640 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3641 .port_get_cmode = mv88e6185_port_get_cmode, 3642 .port_setup_message_port = mv88e6xxx_setup_message_port, 3643 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3644 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3645 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3646 .stats_get_strings = mv88e6095_stats_get_strings, 3647 .stats_get_stats = mv88e6095_stats_get_stats, 3648 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3649 .set_egress_port = mv88e6095_g1_set_egress_port, 3650 .watchdog_ops = &mv88e6097_watchdog_ops, 3651 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3652 .serdes_power = mv88e6185_serdes_power, 3653 .serdes_get_lane = mv88e6185_serdes_get_lane, 3654 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3655 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3656 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 3657 .serdes_irq_status = mv88e6097_serdes_irq_status, 3658 .pot_clear = mv88e6xxx_g2_pot_clear, 3659 .reset = mv88e6352_g1_reset, 3660 .rmu_disable = mv88e6085_g1_rmu_disable, 3661 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3662 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3663 .phylink_validate = mv88e6185_phylink_validate, 3664 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3665 }; 3666 3667 static const struct mv88e6xxx_ops mv88e6123_ops = { 3668 /* MV88E6XXX_FAMILY_6165 */ 3669 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3670 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3671 .irl_init_all = mv88e6352_g2_irl_init_all, 3672 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3673 .phy_read = mv88e6xxx_g2_smi_phy_read, 3674 .phy_write = mv88e6xxx_g2_smi_phy_write, 3675 .port_set_link = mv88e6xxx_port_set_link, 3676 .port_sync_link = mv88e6xxx_port_sync_link, 3677 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3678 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3679 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3680 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3681 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3682 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3683 .port_get_cmode = mv88e6185_port_get_cmode, 3684 .port_setup_message_port = mv88e6xxx_setup_message_port, 3685 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3686 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3687 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3688 .stats_get_strings = mv88e6095_stats_get_strings, 3689 .stats_get_stats = mv88e6095_stats_get_stats, 3690 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3691 .set_egress_port = mv88e6095_g1_set_egress_port, 3692 .watchdog_ops = &mv88e6097_watchdog_ops, 3693 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3694 .pot_clear = mv88e6xxx_g2_pot_clear, 3695 .reset = mv88e6352_g1_reset, 3696 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3697 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3698 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3699 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3700 .phylink_validate = mv88e6185_phylink_validate, 3701 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3702 }; 3703 3704 static const struct mv88e6xxx_ops mv88e6131_ops = { 3705 /* MV88E6XXX_FAMILY_6185 */ 3706 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3707 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3708 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3709 .phy_read = mv88e6185_phy_ppu_read, 3710 .phy_write = mv88e6185_phy_ppu_write, 3711 .port_set_link = mv88e6xxx_port_set_link, 3712 .port_sync_link = mv88e6xxx_port_sync_link, 3713 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3714 .port_tag_remap = mv88e6095_port_tag_remap, 3715 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3716 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3717 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3718 .port_set_ether_type = mv88e6351_port_set_ether_type, 3719 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3720 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3721 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3722 .port_pause_limit = mv88e6097_port_pause_limit, 3723 .port_set_pause = mv88e6185_port_set_pause, 3724 .port_get_cmode = mv88e6185_port_get_cmode, 3725 .port_setup_message_port = mv88e6xxx_setup_message_port, 3726 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3727 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3728 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3729 .stats_get_strings = mv88e6095_stats_get_strings, 3730 .stats_get_stats = mv88e6095_stats_get_stats, 3731 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3732 .set_egress_port = mv88e6095_g1_set_egress_port, 3733 .watchdog_ops = &mv88e6097_watchdog_ops, 3734 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3735 .ppu_enable = mv88e6185_g1_ppu_enable, 3736 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3737 .ppu_disable = mv88e6185_g1_ppu_disable, 3738 .reset = mv88e6185_g1_reset, 3739 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3740 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3741 .phylink_validate = mv88e6185_phylink_validate, 3742 }; 3743 3744 static const struct mv88e6xxx_ops mv88e6141_ops = { 3745 /* MV88E6XXX_FAMILY_6341 */ 3746 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3747 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3748 .irl_init_all = mv88e6352_g2_irl_init_all, 3749 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3750 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3751 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3752 .phy_read = mv88e6xxx_g2_smi_phy_read, 3753 .phy_write = mv88e6xxx_g2_smi_phy_write, 3754 .port_set_link = mv88e6xxx_port_set_link, 3755 .port_sync_link = mv88e6xxx_port_sync_link, 3756 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3757 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3758 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3759 .port_tag_remap = mv88e6095_port_tag_remap, 3760 .port_set_policy = mv88e6352_port_set_policy, 3761 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3762 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3763 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3764 .port_set_ether_type = mv88e6351_port_set_ether_type, 3765 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3766 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3767 .port_pause_limit = mv88e6097_port_pause_limit, 3768 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3769 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3770 .port_get_cmode = mv88e6352_port_get_cmode, 3771 .port_set_cmode = mv88e6341_port_set_cmode, 3772 .port_setup_message_port = mv88e6xxx_setup_message_port, 3773 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3774 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3775 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3776 .stats_get_strings = mv88e6320_stats_get_strings, 3777 .stats_get_stats = mv88e6390_stats_get_stats, 3778 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3779 .set_egress_port = mv88e6390_g1_set_egress_port, 3780 .watchdog_ops = &mv88e6390_watchdog_ops, 3781 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3782 .pot_clear = mv88e6xxx_g2_pot_clear, 3783 .reset = mv88e6352_g1_reset, 3784 .rmu_disable = mv88e6390_g1_rmu_disable, 3785 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3786 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3787 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3788 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3789 .serdes_power = mv88e6390_serdes_power, 3790 .serdes_get_lane = mv88e6341_serdes_get_lane, 3791 /* Check status register pause & lpa register */ 3792 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3793 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3794 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3795 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3796 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3797 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3798 .serdes_irq_status = mv88e6390_serdes_irq_status, 3799 .gpio_ops = &mv88e6352_gpio_ops, 3800 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 3801 .serdes_get_strings = mv88e6390_serdes_get_strings, 3802 .serdes_get_stats = mv88e6390_serdes_get_stats, 3803 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3804 .serdes_get_regs = mv88e6390_serdes_get_regs, 3805 .phylink_validate = mv88e6341_phylink_validate, 3806 }; 3807 3808 static const struct mv88e6xxx_ops mv88e6161_ops = { 3809 /* MV88E6XXX_FAMILY_6165 */ 3810 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3811 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3812 .irl_init_all = mv88e6352_g2_irl_init_all, 3813 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3814 .phy_read = mv88e6xxx_g2_smi_phy_read, 3815 .phy_write = mv88e6xxx_g2_smi_phy_write, 3816 .port_set_link = mv88e6xxx_port_set_link, 3817 .port_sync_link = mv88e6xxx_port_sync_link, 3818 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3819 .port_tag_remap = mv88e6095_port_tag_remap, 3820 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3821 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3822 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3823 .port_set_ether_type = mv88e6351_port_set_ether_type, 3824 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3825 .port_pause_limit = mv88e6097_port_pause_limit, 3826 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3827 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3828 .port_get_cmode = mv88e6185_port_get_cmode, 3829 .port_setup_message_port = mv88e6xxx_setup_message_port, 3830 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3831 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3832 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3833 .stats_get_strings = mv88e6095_stats_get_strings, 3834 .stats_get_stats = mv88e6095_stats_get_stats, 3835 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3836 .set_egress_port = mv88e6095_g1_set_egress_port, 3837 .watchdog_ops = &mv88e6097_watchdog_ops, 3838 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3839 .pot_clear = mv88e6xxx_g2_pot_clear, 3840 .reset = mv88e6352_g1_reset, 3841 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3842 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3843 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3844 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3845 .avb_ops = &mv88e6165_avb_ops, 3846 .ptp_ops = &mv88e6165_ptp_ops, 3847 .phylink_validate = mv88e6185_phylink_validate, 3848 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3849 }; 3850 3851 static const struct mv88e6xxx_ops mv88e6165_ops = { 3852 /* MV88E6XXX_FAMILY_6165 */ 3853 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3854 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3855 .irl_init_all = mv88e6352_g2_irl_init_all, 3856 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3857 .phy_read = mv88e6165_phy_read, 3858 .phy_write = mv88e6165_phy_write, 3859 .port_set_link = mv88e6xxx_port_set_link, 3860 .port_sync_link = mv88e6xxx_port_sync_link, 3861 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3862 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3863 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3864 .port_get_cmode = mv88e6185_port_get_cmode, 3865 .port_setup_message_port = mv88e6xxx_setup_message_port, 3866 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3867 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3868 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3869 .stats_get_strings = mv88e6095_stats_get_strings, 3870 .stats_get_stats = mv88e6095_stats_get_stats, 3871 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3872 .set_egress_port = mv88e6095_g1_set_egress_port, 3873 .watchdog_ops = &mv88e6097_watchdog_ops, 3874 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3875 .pot_clear = mv88e6xxx_g2_pot_clear, 3876 .reset = mv88e6352_g1_reset, 3877 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3878 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3879 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3880 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3881 .avb_ops = &mv88e6165_avb_ops, 3882 .ptp_ops = &mv88e6165_ptp_ops, 3883 .phylink_validate = mv88e6185_phylink_validate, 3884 }; 3885 3886 static const struct mv88e6xxx_ops mv88e6171_ops = { 3887 /* MV88E6XXX_FAMILY_6351 */ 3888 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3889 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3890 .irl_init_all = mv88e6352_g2_irl_init_all, 3891 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3892 .phy_read = mv88e6xxx_g2_smi_phy_read, 3893 .phy_write = mv88e6xxx_g2_smi_phy_write, 3894 .port_set_link = mv88e6xxx_port_set_link, 3895 .port_sync_link = mv88e6xxx_port_sync_link, 3896 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3897 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3898 .port_tag_remap = mv88e6095_port_tag_remap, 3899 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3900 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3901 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3902 .port_set_ether_type = mv88e6351_port_set_ether_type, 3903 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3904 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3905 .port_pause_limit = mv88e6097_port_pause_limit, 3906 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3907 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3908 .port_get_cmode = mv88e6352_port_get_cmode, 3909 .port_setup_message_port = mv88e6xxx_setup_message_port, 3910 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3911 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3912 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3913 .stats_get_strings = mv88e6095_stats_get_strings, 3914 .stats_get_stats = mv88e6095_stats_get_stats, 3915 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3916 .set_egress_port = mv88e6095_g1_set_egress_port, 3917 .watchdog_ops = &mv88e6097_watchdog_ops, 3918 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3919 .pot_clear = mv88e6xxx_g2_pot_clear, 3920 .reset = mv88e6352_g1_reset, 3921 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3922 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3923 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3924 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3925 .phylink_validate = mv88e6185_phylink_validate, 3926 }; 3927 3928 static const struct mv88e6xxx_ops mv88e6172_ops = { 3929 /* MV88E6XXX_FAMILY_6352 */ 3930 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3931 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3932 .irl_init_all = mv88e6352_g2_irl_init_all, 3933 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3934 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3935 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3936 .phy_read = mv88e6xxx_g2_smi_phy_read, 3937 .phy_write = mv88e6xxx_g2_smi_phy_write, 3938 .port_set_link = mv88e6xxx_port_set_link, 3939 .port_sync_link = mv88e6xxx_port_sync_link, 3940 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3941 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3942 .port_tag_remap = mv88e6095_port_tag_remap, 3943 .port_set_policy = mv88e6352_port_set_policy, 3944 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3945 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3946 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3947 .port_set_ether_type = mv88e6351_port_set_ether_type, 3948 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3949 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3950 .port_pause_limit = mv88e6097_port_pause_limit, 3951 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3952 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3953 .port_get_cmode = mv88e6352_port_get_cmode, 3954 .port_setup_message_port = mv88e6xxx_setup_message_port, 3955 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3956 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3957 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3958 .stats_get_strings = mv88e6095_stats_get_strings, 3959 .stats_get_stats = mv88e6095_stats_get_stats, 3960 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3961 .set_egress_port = mv88e6095_g1_set_egress_port, 3962 .watchdog_ops = &mv88e6097_watchdog_ops, 3963 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3964 .pot_clear = mv88e6xxx_g2_pot_clear, 3965 .reset = mv88e6352_g1_reset, 3966 .rmu_disable = mv88e6352_g1_rmu_disable, 3967 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3968 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3969 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3970 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3971 .serdes_get_lane = mv88e6352_serdes_get_lane, 3972 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3973 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3974 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3975 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3976 .serdes_power = mv88e6352_serdes_power, 3977 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3978 .serdes_get_regs = mv88e6352_serdes_get_regs, 3979 .gpio_ops = &mv88e6352_gpio_ops, 3980 .phylink_validate = mv88e6352_phylink_validate, 3981 }; 3982 3983 static const struct mv88e6xxx_ops mv88e6175_ops = { 3984 /* MV88E6XXX_FAMILY_6351 */ 3985 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3986 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3987 .irl_init_all = mv88e6352_g2_irl_init_all, 3988 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3989 .phy_read = mv88e6xxx_g2_smi_phy_read, 3990 .phy_write = mv88e6xxx_g2_smi_phy_write, 3991 .port_set_link = mv88e6xxx_port_set_link, 3992 .port_sync_link = mv88e6xxx_port_sync_link, 3993 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3994 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3995 .port_tag_remap = mv88e6095_port_tag_remap, 3996 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3997 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3998 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3999 .port_set_ether_type = mv88e6351_port_set_ether_type, 4000 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4001 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4002 .port_pause_limit = mv88e6097_port_pause_limit, 4003 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4004 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4005 .port_get_cmode = mv88e6352_port_get_cmode, 4006 .port_setup_message_port = mv88e6xxx_setup_message_port, 4007 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4008 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4009 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4010 .stats_get_strings = mv88e6095_stats_get_strings, 4011 .stats_get_stats = mv88e6095_stats_get_stats, 4012 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4013 .set_egress_port = mv88e6095_g1_set_egress_port, 4014 .watchdog_ops = &mv88e6097_watchdog_ops, 4015 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4016 .pot_clear = mv88e6xxx_g2_pot_clear, 4017 .reset = mv88e6352_g1_reset, 4018 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4019 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4020 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4021 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4022 .phylink_validate = mv88e6185_phylink_validate, 4023 }; 4024 4025 static const struct mv88e6xxx_ops mv88e6176_ops = { 4026 /* MV88E6XXX_FAMILY_6352 */ 4027 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4028 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4029 .irl_init_all = mv88e6352_g2_irl_init_all, 4030 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4031 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4032 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4033 .phy_read = mv88e6xxx_g2_smi_phy_read, 4034 .phy_write = mv88e6xxx_g2_smi_phy_write, 4035 .port_set_link = mv88e6xxx_port_set_link, 4036 .port_sync_link = mv88e6xxx_port_sync_link, 4037 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4038 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4039 .port_tag_remap = mv88e6095_port_tag_remap, 4040 .port_set_policy = mv88e6352_port_set_policy, 4041 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4042 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4043 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4044 .port_set_ether_type = mv88e6351_port_set_ether_type, 4045 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4046 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4047 .port_pause_limit = mv88e6097_port_pause_limit, 4048 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4049 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4050 .port_get_cmode = mv88e6352_port_get_cmode, 4051 .port_setup_message_port = mv88e6xxx_setup_message_port, 4052 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4053 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4054 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4055 .stats_get_strings = mv88e6095_stats_get_strings, 4056 .stats_get_stats = mv88e6095_stats_get_stats, 4057 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4058 .set_egress_port = mv88e6095_g1_set_egress_port, 4059 .watchdog_ops = &mv88e6097_watchdog_ops, 4060 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4061 .pot_clear = mv88e6xxx_g2_pot_clear, 4062 .reset = mv88e6352_g1_reset, 4063 .rmu_disable = mv88e6352_g1_rmu_disable, 4064 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4065 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4066 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4067 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4068 .serdes_get_lane = mv88e6352_serdes_get_lane, 4069 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4070 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4071 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4072 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4073 .serdes_power = mv88e6352_serdes_power, 4074 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4075 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4076 .serdes_irq_status = mv88e6352_serdes_irq_status, 4077 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4078 .serdes_get_regs = mv88e6352_serdes_get_regs, 4079 .gpio_ops = &mv88e6352_gpio_ops, 4080 .phylink_validate = mv88e6352_phylink_validate, 4081 }; 4082 4083 static const struct mv88e6xxx_ops mv88e6185_ops = { 4084 /* MV88E6XXX_FAMILY_6185 */ 4085 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4086 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4087 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4088 .phy_read = mv88e6185_phy_ppu_read, 4089 .phy_write = mv88e6185_phy_ppu_write, 4090 .port_set_link = mv88e6xxx_port_set_link, 4091 .port_sync_link = mv88e6185_port_sync_link, 4092 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4093 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4094 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4095 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4096 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4097 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4098 .port_set_pause = mv88e6185_port_set_pause, 4099 .port_get_cmode = mv88e6185_port_get_cmode, 4100 .port_setup_message_port = mv88e6xxx_setup_message_port, 4101 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4102 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4103 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4104 .stats_get_strings = mv88e6095_stats_get_strings, 4105 .stats_get_stats = mv88e6095_stats_get_stats, 4106 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4107 .set_egress_port = mv88e6095_g1_set_egress_port, 4108 .watchdog_ops = &mv88e6097_watchdog_ops, 4109 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4110 .serdes_power = mv88e6185_serdes_power, 4111 .serdes_get_lane = mv88e6185_serdes_get_lane, 4112 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4113 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4114 .ppu_enable = mv88e6185_g1_ppu_enable, 4115 .ppu_disable = mv88e6185_g1_ppu_disable, 4116 .reset = mv88e6185_g1_reset, 4117 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4118 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4119 .phylink_validate = mv88e6185_phylink_validate, 4120 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4121 }; 4122 4123 static const struct mv88e6xxx_ops mv88e6190_ops = { 4124 /* MV88E6XXX_FAMILY_6390 */ 4125 .setup_errata = mv88e6390_setup_errata, 4126 .irl_init_all = mv88e6390_g2_irl_init_all, 4127 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4128 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4129 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4130 .phy_read = mv88e6xxx_g2_smi_phy_read, 4131 .phy_write = mv88e6xxx_g2_smi_phy_write, 4132 .port_set_link = mv88e6xxx_port_set_link, 4133 .port_sync_link = mv88e6xxx_port_sync_link, 4134 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4135 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4136 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4137 .port_tag_remap = mv88e6390_port_tag_remap, 4138 .port_set_policy = mv88e6352_port_set_policy, 4139 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4140 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4141 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4142 .port_set_ether_type = mv88e6351_port_set_ether_type, 4143 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4144 .port_pause_limit = mv88e6390_port_pause_limit, 4145 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4146 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4147 .port_get_cmode = mv88e6352_port_get_cmode, 4148 .port_set_cmode = mv88e6390_port_set_cmode, 4149 .port_setup_message_port = mv88e6xxx_setup_message_port, 4150 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4151 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4152 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4153 .stats_get_strings = mv88e6320_stats_get_strings, 4154 .stats_get_stats = mv88e6390_stats_get_stats, 4155 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4156 .set_egress_port = mv88e6390_g1_set_egress_port, 4157 .watchdog_ops = &mv88e6390_watchdog_ops, 4158 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4159 .pot_clear = mv88e6xxx_g2_pot_clear, 4160 .reset = mv88e6352_g1_reset, 4161 .rmu_disable = mv88e6390_g1_rmu_disable, 4162 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4163 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4164 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4165 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4166 .serdes_power = mv88e6390_serdes_power, 4167 .serdes_get_lane = mv88e6390_serdes_get_lane, 4168 /* Check status register pause & lpa register */ 4169 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4170 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4171 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4172 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4173 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4174 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4175 .serdes_irq_status = mv88e6390_serdes_irq_status, 4176 .serdes_get_strings = mv88e6390_serdes_get_strings, 4177 .serdes_get_stats = mv88e6390_serdes_get_stats, 4178 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4179 .serdes_get_regs = mv88e6390_serdes_get_regs, 4180 .gpio_ops = &mv88e6352_gpio_ops, 4181 .phylink_validate = mv88e6390_phylink_validate, 4182 }; 4183 4184 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4185 /* MV88E6XXX_FAMILY_6390 */ 4186 .setup_errata = mv88e6390_setup_errata, 4187 .irl_init_all = mv88e6390_g2_irl_init_all, 4188 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4189 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4190 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4191 .phy_read = mv88e6xxx_g2_smi_phy_read, 4192 .phy_write = mv88e6xxx_g2_smi_phy_write, 4193 .port_set_link = mv88e6xxx_port_set_link, 4194 .port_sync_link = mv88e6xxx_port_sync_link, 4195 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4196 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4197 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4198 .port_tag_remap = mv88e6390_port_tag_remap, 4199 .port_set_policy = mv88e6352_port_set_policy, 4200 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4201 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4202 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4203 .port_set_ether_type = mv88e6351_port_set_ether_type, 4204 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4205 .port_pause_limit = mv88e6390_port_pause_limit, 4206 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4207 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4208 .port_get_cmode = mv88e6352_port_get_cmode, 4209 .port_set_cmode = mv88e6390x_port_set_cmode, 4210 .port_setup_message_port = mv88e6xxx_setup_message_port, 4211 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4212 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4213 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4214 .stats_get_strings = mv88e6320_stats_get_strings, 4215 .stats_get_stats = mv88e6390_stats_get_stats, 4216 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4217 .set_egress_port = mv88e6390_g1_set_egress_port, 4218 .watchdog_ops = &mv88e6390_watchdog_ops, 4219 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4220 .pot_clear = mv88e6xxx_g2_pot_clear, 4221 .reset = mv88e6352_g1_reset, 4222 .rmu_disable = mv88e6390_g1_rmu_disable, 4223 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4224 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4225 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4226 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4227 .serdes_power = mv88e6390_serdes_power, 4228 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4229 /* Check status register pause & lpa register */ 4230 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4231 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4232 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4233 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4234 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4235 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4236 .serdes_irq_status = mv88e6390_serdes_irq_status, 4237 .serdes_get_strings = mv88e6390_serdes_get_strings, 4238 .serdes_get_stats = mv88e6390_serdes_get_stats, 4239 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4240 .serdes_get_regs = mv88e6390_serdes_get_regs, 4241 .gpio_ops = &mv88e6352_gpio_ops, 4242 .phylink_validate = mv88e6390x_phylink_validate, 4243 }; 4244 4245 static const struct mv88e6xxx_ops mv88e6191_ops = { 4246 /* MV88E6XXX_FAMILY_6390 */ 4247 .setup_errata = mv88e6390_setup_errata, 4248 .irl_init_all = mv88e6390_g2_irl_init_all, 4249 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4250 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4251 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4252 .phy_read = mv88e6xxx_g2_smi_phy_read, 4253 .phy_write = mv88e6xxx_g2_smi_phy_write, 4254 .port_set_link = mv88e6xxx_port_set_link, 4255 .port_sync_link = mv88e6xxx_port_sync_link, 4256 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4257 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4258 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4259 .port_tag_remap = mv88e6390_port_tag_remap, 4260 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4261 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4262 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4263 .port_set_ether_type = mv88e6351_port_set_ether_type, 4264 .port_pause_limit = mv88e6390_port_pause_limit, 4265 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4266 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4267 .port_get_cmode = mv88e6352_port_get_cmode, 4268 .port_set_cmode = mv88e6390_port_set_cmode, 4269 .port_setup_message_port = mv88e6xxx_setup_message_port, 4270 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4271 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4272 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4273 .stats_get_strings = mv88e6320_stats_get_strings, 4274 .stats_get_stats = mv88e6390_stats_get_stats, 4275 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4276 .set_egress_port = mv88e6390_g1_set_egress_port, 4277 .watchdog_ops = &mv88e6390_watchdog_ops, 4278 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4279 .pot_clear = mv88e6xxx_g2_pot_clear, 4280 .reset = mv88e6352_g1_reset, 4281 .rmu_disable = mv88e6390_g1_rmu_disable, 4282 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4283 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4284 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4285 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4286 .serdes_power = mv88e6390_serdes_power, 4287 .serdes_get_lane = mv88e6390_serdes_get_lane, 4288 /* Check status register pause & lpa register */ 4289 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4290 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4291 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4292 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4293 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4294 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4295 .serdes_irq_status = mv88e6390_serdes_irq_status, 4296 .serdes_get_strings = mv88e6390_serdes_get_strings, 4297 .serdes_get_stats = mv88e6390_serdes_get_stats, 4298 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4299 .serdes_get_regs = mv88e6390_serdes_get_regs, 4300 .avb_ops = &mv88e6390_avb_ops, 4301 .ptp_ops = &mv88e6352_ptp_ops, 4302 .phylink_validate = mv88e6390_phylink_validate, 4303 }; 4304 4305 static const struct mv88e6xxx_ops mv88e6240_ops = { 4306 /* MV88E6XXX_FAMILY_6352 */ 4307 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4308 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4309 .irl_init_all = mv88e6352_g2_irl_init_all, 4310 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4311 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4312 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4313 .phy_read = mv88e6xxx_g2_smi_phy_read, 4314 .phy_write = mv88e6xxx_g2_smi_phy_write, 4315 .port_set_link = mv88e6xxx_port_set_link, 4316 .port_sync_link = mv88e6xxx_port_sync_link, 4317 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4318 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4319 .port_tag_remap = mv88e6095_port_tag_remap, 4320 .port_set_policy = mv88e6352_port_set_policy, 4321 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4322 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4323 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4324 .port_set_ether_type = mv88e6351_port_set_ether_type, 4325 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4326 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4327 .port_pause_limit = mv88e6097_port_pause_limit, 4328 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4329 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4330 .port_get_cmode = mv88e6352_port_get_cmode, 4331 .port_setup_message_port = mv88e6xxx_setup_message_port, 4332 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4333 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4334 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4335 .stats_get_strings = mv88e6095_stats_get_strings, 4336 .stats_get_stats = mv88e6095_stats_get_stats, 4337 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4338 .set_egress_port = mv88e6095_g1_set_egress_port, 4339 .watchdog_ops = &mv88e6097_watchdog_ops, 4340 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4341 .pot_clear = mv88e6xxx_g2_pot_clear, 4342 .reset = mv88e6352_g1_reset, 4343 .rmu_disable = mv88e6352_g1_rmu_disable, 4344 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4345 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4346 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4347 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4348 .serdes_get_lane = mv88e6352_serdes_get_lane, 4349 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4350 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4351 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4352 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4353 .serdes_power = mv88e6352_serdes_power, 4354 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4355 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4356 .serdes_irq_status = mv88e6352_serdes_irq_status, 4357 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4358 .serdes_get_regs = mv88e6352_serdes_get_regs, 4359 .gpio_ops = &mv88e6352_gpio_ops, 4360 .avb_ops = &mv88e6352_avb_ops, 4361 .ptp_ops = &mv88e6352_ptp_ops, 4362 .phylink_validate = mv88e6352_phylink_validate, 4363 }; 4364 4365 static const struct mv88e6xxx_ops mv88e6250_ops = { 4366 /* MV88E6XXX_FAMILY_6250 */ 4367 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4368 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4369 .irl_init_all = mv88e6352_g2_irl_init_all, 4370 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4371 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4372 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4373 .phy_read = mv88e6xxx_g2_smi_phy_read, 4374 .phy_write = mv88e6xxx_g2_smi_phy_write, 4375 .port_set_link = mv88e6xxx_port_set_link, 4376 .port_sync_link = mv88e6xxx_port_sync_link, 4377 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4378 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4379 .port_tag_remap = mv88e6095_port_tag_remap, 4380 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4381 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4382 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4383 .port_set_ether_type = mv88e6351_port_set_ether_type, 4384 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4385 .port_pause_limit = mv88e6097_port_pause_limit, 4386 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4387 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4388 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4389 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4390 .stats_get_strings = mv88e6250_stats_get_strings, 4391 .stats_get_stats = mv88e6250_stats_get_stats, 4392 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4393 .set_egress_port = mv88e6095_g1_set_egress_port, 4394 .watchdog_ops = &mv88e6250_watchdog_ops, 4395 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4396 .pot_clear = mv88e6xxx_g2_pot_clear, 4397 .reset = mv88e6250_g1_reset, 4398 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4399 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4400 .avb_ops = &mv88e6352_avb_ops, 4401 .ptp_ops = &mv88e6250_ptp_ops, 4402 .phylink_validate = mv88e6065_phylink_validate, 4403 }; 4404 4405 static const struct mv88e6xxx_ops mv88e6290_ops = { 4406 /* MV88E6XXX_FAMILY_6390 */ 4407 .setup_errata = mv88e6390_setup_errata, 4408 .irl_init_all = mv88e6390_g2_irl_init_all, 4409 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4410 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4411 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4412 .phy_read = mv88e6xxx_g2_smi_phy_read, 4413 .phy_write = mv88e6xxx_g2_smi_phy_write, 4414 .port_set_link = mv88e6xxx_port_set_link, 4415 .port_sync_link = mv88e6xxx_port_sync_link, 4416 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4417 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4418 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4419 .port_tag_remap = mv88e6390_port_tag_remap, 4420 .port_set_policy = mv88e6352_port_set_policy, 4421 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4422 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4423 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4424 .port_set_ether_type = mv88e6351_port_set_ether_type, 4425 .port_pause_limit = mv88e6390_port_pause_limit, 4426 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4427 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4428 .port_get_cmode = mv88e6352_port_get_cmode, 4429 .port_set_cmode = mv88e6390_port_set_cmode, 4430 .port_setup_message_port = mv88e6xxx_setup_message_port, 4431 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4432 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4433 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4434 .stats_get_strings = mv88e6320_stats_get_strings, 4435 .stats_get_stats = mv88e6390_stats_get_stats, 4436 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4437 .set_egress_port = mv88e6390_g1_set_egress_port, 4438 .watchdog_ops = &mv88e6390_watchdog_ops, 4439 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4440 .pot_clear = mv88e6xxx_g2_pot_clear, 4441 .reset = mv88e6352_g1_reset, 4442 .rmu_disable = mv88e6390_g1_rmu_disable, 4443 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4444 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4445 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4446 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4447 .serdes_power = mv88e6390_serdes_power, 4448 .serdes_get_lane = mv88e6390_serdes_get_lane, 4449 /* Check status register pause & lpa register */ 4450 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4451 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4452 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4453 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4454 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4455 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4456 .serdes_irq_status = mv88e6390_serdes_irq_status, 4457 .serdes_get_strings = mv88e6390_serdes_get_strings, 4458 .serdes_get_stats = mv88e6390_serdes_get_stats, 4459 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4460 .serdes_get_regs = mv88e6390_serdes_get_regs, 4461 .gpio_ops = &mv88e6352_gpio_ops, 4462 .avb_ops = &mv88e6390_avb_ops, 4463 .ptp_ops = &mv88e6352_ptp_ops, 4464 .phylink_validate = mv88e6390_phylink_validate, 4465 }; 4466 4467 static const struct mv88e6xxx_ops mv88e6320_ops = { 4468 /* MV88E6XXX_FAMILY_6320 */ 4469 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4470 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4471 .irl_init_all = mv88e6352_g2_irl_init_all, 4472 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4473 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4474 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4475 .phy_read = mv88e6xxx_g2_smi_phy_read, 4476 .phy_write = mv88e6xxx_g2_smi_phy_write, 4477 .port_set_link = mv88e6xxx_port_set_link, 4478 .port_sync_link = mv88e6xxx_port_sync_link, 4479 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4480 .port_tag_remap = mv88e6095_port_tag_remap, 4481 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4482 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4483 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4484 .port_set_ether_type = mv88e6351_port_set_ether_type, 4485 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4486 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4487 .port_pause_limit = mv88e6097_port_pause_limit, 4488 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4489 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4490 .port_get_cmode = mv88e6352_port_get_cmode, 4491 .port_setup_message_port = mv88e6xxx_setup_message_port, 4492 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4493 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4494 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4495 .stats_get_strings = mv88e6320_stats_get_strings, 4496 .stats_get_stats = mv88e6320_stats_get_stats, 4497 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4498 .set_egress_port = mv88e6095_g1_set_egress_port, 4499 .watchdog_ops = &mv88e6390_watchdog_ops, 4500 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4501 .pot_clear = mv88e6xxx_g2_pot_clear, 4502 .reset = mv88e6352_g1_reset, 4503 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4504 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4505 .gpio_ops = &mv88e6352_gpio_ops, 4506 .avb_ops = &mv88e6352_avb_ops, 4507 .ptp_ops = &mv88e6352_ptp_ops, 4508 .phylink_validate = mv88e6185_phylink_validate, 4509 }; 4510 4511 static const struct mv88e6xxx_ops mv88e6321_ops = { 4512 /* MV88E6XXX_FAMILY_6320 */ 4513 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4514 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4515 .irl_init_all = mv88e6352_g2_irl_init_all, 4516 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4517 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4518 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4519 .phy_read = mv88e6xxx_g2_smi_phy_read, 4520 .phy_write = mv88e6xxx_g2_smi_phy_write, 4521 .port_set_link = mv88e6xxx_port_set_link, 4522 .port_sync_link = mv88e6xxx_port_sync_link, 4523 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4524 .port_tag_remap = mv88e6095_port_tag_remap, 4525 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4526 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4527 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4528 .port_set_ether_type = mv88e6351_port_set_ether_type, 4529 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4530 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4531 .port_pause_limit = mv88e6097_port_pause_limit, 4532 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4533 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4534 .port_get_cmode = mv88e6352_port_get_cmode, 4535 .port_setup_message_port = mv88e6xxx_setup_message_port, 4536 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4537 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4538 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4539 .stats_get_strings = mv88e6320_stats_get_strings, 4540 .stats_get_stats = mv88e6320_stats_get_stats, 4541 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4542 .set_egress_port = mv88e6095_g1_set_egress_port, 4543 .watchdog_ops = &mv88e6390_watchdog_ops, 4544 .reset = mv88e6352_g1_reset, 4545 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4546 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4547 .gpio_ops = &mv88e6352_gpio_ops, 4548 .avb_ops = &mv88e6352_avb_ops, 4549 .ptp_ops = &mv88e6352_ptp_ops, 4550 .phylink_validate = mv88e6185_phylink_validate, 4551 }; 4552 4553 static const struct mv88e6xxx_ops mv88e6341_ops = { 4554 /* MV88E6XXX_FAMILY_6341 */ 4555 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4556 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4557 .irl_init_all = mv88e6352_g2_irl_init_all, 4558 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4559 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4560 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4561 .phy_read = mv88e6xxx_g2_smi_phy_read, 4562 .phy_write = mv88e6xxx_g2_smi_phy_write, 4563 .port_set_link = mv88e6xxx_port_set_link, 4564 .port_sync_link = mv88e6xxx_port_sync_link, 4565 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4566 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4567 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4568 .port_tag_remap = mv88e6095_port_tag_remap, 4569 .port_set_policy = mv88e6352_port_set_policy, 4570 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4571 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4572 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4573 .port_set_ether_type = mv88e6351_port_set_ether_type, 4574 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4575 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4576 .port_pause_limit = mv88e6097_port_pause_limit, 4577 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4578 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4579 .port_get_cmode = mv88e6352_port_get_cmode, 4580 .port_set_cmode = mv88e6341_port_set_cmode, 4581 .port_setup_message_port = mv88e6xxx_setup_message_port, 4582 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4583 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4584 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4585 .stats_get_strings = mv88e6320_stats_get_strings, 4586 .stats_get_stats = mv88e6390_stats_get_stats, 4587 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4588 .set_egress_port = mv88e6390_g1_set_egress_port, 4589 .watchdog_ops = &mv88e6390_watchdog_ops, 4590 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4591 .pot_clear = mv88e6xxx_g2_pot_clear, 4592 .reset = mv88e6352_g1_reset, 4593 .rmu_disable = mv88e6390_g1_rmu_disable, 4594 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4595 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4596 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4597 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4598 .serdes_power = mv88e6390_serdes_power, 4599 .serdes_get_lane = mv88e6341_serdes_get_lane, 4600 /* Check status register pause & lpa register */ 4601 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4602 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4603 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4604 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4605 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4606 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4607 .serdes_irq_status = mv88e6390_serdes_irq_status, 4608 .gpio_ops = &mv88e6352_gpio_ops, 4609 .avb_ops = &mv88e6390_avb_ops, 4610 .ptp_ops = &mv88e6352_ptp_ops, 4611 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4612 .serdes_get_strings = mv88e6390_serdes_get_strings, 4613 .serdes_get_stats = mv88e6390_serdes_get_stats, 4614 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4615 .serdes_get_regs = mv88e6390_serdes_get_regs, 4616 .phylink_validate = mv88e6341_phylink_validate, 4617 }; 4618 4619 static const struct mv88e6xxx_ops mv88e6350_ops = { 4620 /* MV88E6XXX_FAMILY_6351 */ 4621 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4622 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4623 .irl_init_all = mv88e6352_g2_irl_init_all, 4624 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4625 .phy_read = mv88e6xxx_g2_smi_phy_read, 4626 .phy_write = mv88e6xxx_g2_smi_phy_write, 4627 .port_set_link = mv88e6xxx_port_set_link, 4628 .port_sync_link = mv88e6xxx_port_sync_link, 4629 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4630 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4631 .port_tag_remap = mv88e6095_port_tag_remap, 4632 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4633 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4634 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4635 .port_set_ether_type = mv88e6351_port_set_ether_type, 4636 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4637 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4638 .port_pause_limit = mv88e6097_port_pause_limit, 4639 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4640 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4641 .port_get_cmode = mv88e6352_port_get_cmode, 4642 .port_setup_message_port = mv88e6xxx_setup_message_port, 4643 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4644 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4645 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4646 .stats_get_strings = mv88e6095_stats_get_strings, 4647 .stats_get_stats = mv88e6095_stats_get_stats, 4648 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4649 .set_egress_port = mv88e6095_g1_set_egress_port, 4650 .watchdog_ops = &mv88e6097_watchdog_ops, 4651 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4652 .pot_clear = mv88e6xxx_g2_pot_clear, 4653 .reset = mv88e6352_g1_reset, 4654 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4655 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4656 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4657 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4658 .phylink_validate = mv88e6185_phylink_validate, 4659 }; 4660 4661 static const struct mv88e6xxx_ops mv88e6351_ops = { 4662 /* MV88E6XXX_FAMILY_6351 */ 4663 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4664 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4665 .irl_init_all = mv88e6352_g2_irl_init_all, 4666 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4667 .phy_read = mv88e6xxx_g2_smi_phy_read, 4668 .phy_write = mv88e6xxx_g2_smi_phy_write, 4669 .port_set_link = mv88e6xxx_port_set_link, 4670 .port_sync_link = mv88e6xxx_port_sync_link, 4671 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4672 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4673 .port_tag_remap = mv88e6095_port_tag_remap, 4674 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4675 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4676 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4677 .port_set_ether_type = mv88e6351_port_set_ether_type, 4678 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4679 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4680 .port_pause_limit = mv88e6097_port_pause_limit, 4681 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4682 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4683 .port_get_cmode = mv88e6352_port_get_cmode, 4684 .port_setup_message_port = mv88e6xxx_setup_message_port, 4685 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4686 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4687 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4688 .stats_get_strings = mv88e6095_stats_get_strings, 4689 .stats_get_stats = mv88e6095_stats_get_stats, 4690 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4691 .set_egress_port = mv88e6095_g1_set_egress_port, 4692 .watchdog_ops = &mv88e6097_watchdog_ops, 4693 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4694 .pot_clear = mv88e6xxx_g2_pot_clear, 4695 .reset = mv88e6352_g1_reset, 4696 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4697 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4698 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4699 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4700 .avb_ops = &mv88e6352_avb_ops, 4701 .ptp_ops = &mv88e6352_ptp_ops, 4702 .phylink_validate = mv88e6185_phylink_validate, 4703 }; 4704 4705 static const struct mv88e6xxx_ops mv88e6352_ops = { 4706 /* MV88E6XXX_FAMILY_6352 */ 4707 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4708 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4709 .irl_init_all = mv88e6352_g2_irl_init_all, 4710 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4711 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4712 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4713 .phy_read = mv88e6xxx_g2_smi_phy_read, 4714 .phy_write = mv88e6xxx_g2_smi_phy_write, 4715 .port_set_link = mv88e6xxx_port_set_link, 4716 .port_sync_link = mv88e6xxx_port_sync_link, 4717 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4718 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4719 .port_tag_remap = mv88e6095_port_tag_remap, 4720 .port_set_policy = mv88e6352_port_set_policy, 4721 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4722 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4723 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4724 .port_set_ether_type = mv88e6351_port_set_ether_type, 4725 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4726 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4727 .port_pause_limit = mv88e6097_port_pause_limit, 4728 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4729 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4730 .port_get_cmode = mv88e6352_port_get_cmode, 4731 .port_setup_message_port = mv88e6xxx_setup_message_port, 4732 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4733 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4734 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4735 .stats_get_strings = mv88e6095_stats_get_strings, 4736 .stats_get_stats = mv88e6095_stats_get_stats, 4737 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4738 .set_egress_port = mv88e6095_g1_set_egress_port, 4739 .watchdog_ops = &mv88e6097_watchdog_ops, 4740 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4741 .pot_clear = mv88e6xxx_g2_pot_clear, 4742 .reset = mv88e6352_g1_reset, 4743 .rmu_disable = mv88e6352_g1_rmu_disable, 4744 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4745 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4746 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4747 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4748 .serdes_get_lane = mv88e6352_serdes_get_lane, 4749 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4750 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4751 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4752 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4753 .serdes_power = mv88e6352_serdes_power, 4754 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4755 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4756 .serdes_irq_status = mv88e6352_serdes_irq_status, 4757 .gpio_ops = &mv88e6352_gpio_ops, 4758 .avb_ops = &mv88e6352_avb_ops, 4759 .ptp_ops = &mv88e6352_ptp_ops, 4760 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4761 .serdes_get_strings = mv88e6352_serdes_get_strings, 4762 .serdes_get_stats = mv88e6352_serdes_get_stats, 4763 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4764 .serdes_get_regs = mv88e6352_serdes_get_regs, 4765 .phylink_validate = mv88e6352_phylink_validate, 4766 }; 4767 4768 static const struct mv88e6xxx_ops mv88e6390_ops = { 4769 /* MV88E6XXX_FAMILY_6390 */ 4770 .setup_errata = mv88e6390_setup_errata, 4771 .irl_init_all = mv88e6390_g2_irl_init_all, 4772 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4773 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4774 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4775 .phy_read = mv88e6xxx_g2_smi_phy_read, 4776 .phy_write = mv88e6xxx_g2_smi_phy_write, 4777 .port_set_link = mv88e6xxx_port_set_link, 4778 .port_sync_link = mv88e6xxx_port_sync_link, 4779 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4780 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4781 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4782 .port_tag_remap = mv88e6390_port_tag_remap, 4783 .port_set_policy = mv88e6352_port_set_policy, 4784 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4785 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4786 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4787 .port_set_ether_type = mv88e6351_port_set_ether_type, 4788 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4789 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4790 .port_pause_limit = mv88e6390_port_pause_limit, 4791 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4792 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4793 .port_get_cmode = mv88e6352_port_get_cmode, 4794 .port_set_cmode = mv88e6390_port_set_cmode, 4795 .port_setup_message_port = mv88e6xxx_setup_message_port, 4796 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4797 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4798 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4799 .stats_get_strings = mv88e6320_stats_get_strings, 4800 .stats_get_stats = mv88e6390_stats_get_stats, 4801 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4802 .set_egress_port = mv88e6390_g1_set_egress_port, 4803 .watchdog_ops = &mv88e6390_watchdog_ops, 4804 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4805 .pot_clear = mv88e6xxx_g2_pot_clear, 4806 .reset = mv88e6352_g1_reset, 4807 .rmu_disable = mv88e6390_g1_rmu_disable, 4808 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4809 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4810 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4811 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4812 .serdes_power = mv88e6390_serdes_power, 4813 .serdes_get_lane = mv88e6390_serdes_get_lane, 4814 /* Check status register pause & lpa register */ 4815 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4816 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4817 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4818 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4819 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4820 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4821 .serdes_irq_status = mv88e6390_serdes_irq_status, 4822 .gpio_ops = &mv88e6352_gpio_ops, 4823 .avb_ops = &mv88e6390_avb_ops, 4824 .ptp_ops = &mv88e6352_ptp_ops, 4825 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4826 .serdes_get_strings = mv88e6390_serdes_get_strings, 4827 .serdes_get_stats = mv88e6390_serdes_get_stats, 4828 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4829 .serdes_get_regs = mv88e6390_serdes_get_regs, 4830 .phylink_validate = mv88e6390_phylink_validate, 4831 }; 4832 4833 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4834 /* MV88E6XXX_FAMILY_6390 */ 4835 .setup_errata = mv88e6390_setup_errata, 4836 .irl_init_all = mv88e6390_g2_irl_init_all, 4837 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4838 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4839 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4840 .phy_read = mv88e6xxx_g2_smi_phy_read, 4841 .phy_write = mv88e6xxx_g2_smi_phy_write, 4842 .port_set_link = mv88e6xxx_port_set_link, 4843 .port_sync_link = mv88e6xxx_port_sync_link, 4844 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4845 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4846 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4847 .port_tag_remap = mv88e6390_port_tag_remap, 4848 .port_set_policy = mv88e6352_port_set_policy, 4849 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4850 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4851 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4852 .port_set_ether_type = mv88e6351_port_set_ether_type, 4853 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4854 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4855 .port_pause_limit = mv88e6390_port_pause_limit, 4856 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4857 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4858 .port_get_cmode = mv88e6352_port_get_cmode, 4859 .port_set_cmode = mv88e6390x_port_set_cmode, 4860 .port_setup_message_port = mv88e6xxx_setup_message_port, 4861 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4862 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4863 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4864 .stats_get_strings = mv88e6320_stats_get_strings, 4865 .stats_get_stats = mv88e6390_stats_get_stats, 4866 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4867 .set_egress_port = mv88e6390_g1_set_egress_port, 4868 .watchdog_ops = &mv88e6390_watchdog_ops, 4869 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4870 .pot_clear = mv88e6xxx_g2_pot_clear, 4871 .reset = mv88e6352_g1_reset, 4872 .rmu_disable = mv88e6390_g1_rmu_disable, 4873 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4874 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4875 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4876 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4877 .serdes_power = mv88e6390_serdes_power, 4878 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4879 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4880 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4881 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4882 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4883 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4884 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4885 .serdes_irq_status = mv88e6390_serdes_irq_status, 4886 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4887 .serdes_get_strings = mv88e6390_serdes_get_strings, 4888 .serdes_get_stats = mv88e6390_serdes_get_stats, 4889 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4890 .serdes_get_regs = mv88e6390_serdes_get_regs, 4891 .gpio_ops = &mv88e6352_gpio_ops, 4892 .avb_ops = &mv88e6390_avb_ops, 4893 .ptp_ops = &mv88e6352_ptp_ops, 4894 .phylink_validate = mv88e6390x_phylink_validate, 4895 }; 4896 4897 static const struct mv88e6xxx_ops mv88e6393x_ops = { 4898 /* MV88E6XXX_FAMILY_6393 */ 4899 .setup_errata = mv88e6393x_serdes_setup_errata, 4900 .irl_init_all = mv88e6390_g2_irl_init_all, 4901 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4902 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4903 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4904 .phy_read = mv88e6xxx_g2_smi_phy_read, 4905 .phy_write = mv88e6xxx_g2_smi_phy_write, 4906 .port_set_link = mv88e6xxx_port_set_link, 4907 .port_sync_link = mv88e6xxx_port_sync_link, 4908 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4909 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 4910 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 4911 .port_tag_remap = mv88e6390_port_tag_remap, 4912 .port_set_policy = mv88e6393x_port_set_policy, 4913 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4914 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4915 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4916 .port_set_ether_type = mv88e6393x_port_set_ether_type, 4917 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4918 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4919 .port_pause_limit = mv88e6390_port_pause_limit, 4920 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4921 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4922 .port_get_cmode = mv88e6352_port_get_cmode, 4923 .port_set_cmode = mv88e6393x_port_set_cmode, 4924 .port_setup_message_port = mv88e6xxx_setup_message_port, 4925 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 4926 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4927 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4928 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4929 .stats_get_strings = mv88e6320_stats_get_strings, 4930 .stats_get_stats = mv88e6390_stats_get_stats, 4931 /* .set_cpu_port is missing because this family does not support a global 4932 * CPU port, only per port CPU port which is set via 4933 * .port_set_upstream_port method. 4934 */ 4935 .set_egress_port = mv88e6393x_set_egress_port, 4936 .watchdog_ops = &mv88e6390_watchdog_ops, 4937 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 4938 .pot_clear = mv88e6xxx_g2_pot_clear, 4939 .reset = mv88e6352_g1_reset, 4940 .rmu_disable = mv88e6390_g1_rmu_disable, 4941 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4942 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4943 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4944 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4945 .serdes_power = mv88e6393x_serdes_power, 4946 .serdes_get_lane = mv88e6393x_serdes_get_lane, 4947 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 4948 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4949 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4950 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4951 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4952 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 4953 .serdes_irq_status = mv88e6393x_serdes_irq_status, 4954 /* TODO: serdes stats */ 4955 .gpio_ops = &mv88e6352_gpio_ops, 4956 .avb_ops = &mv88e6390_avb_ops, 4957 .ptp_ops = &mv88e6352_ptp_ops, 4958 .phylink_validate = mv88e6393x_phylink_validate, 4959 }; 4960 4961 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4962 [MV88E6085] = { 4963 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4964 .family = MV88E6XXX_FAMILY_6097, 4965 .name = "Marvell 88E6085", 4966 .num_databases = 4096, 4967 .num_macs = 8192, 4968 .num_ports = 10, 4969 .num_internal_phys = 5, 4970 .max_vid = 4095, 4971 .port_base_addr = 0x10, 4972 .phy_base_addr = 0x0, 4973 .global1_addr = 0x1b, 4974 .global2_addr = 0x1c, 4975 .age_time_coeff = 15000, 4976 .g1_irqs = 8, 4977 .g2_irqs = 10, 4978 .atu_move_port_mask = 0xf, 4979 .pvt = true, 4980 .multi_chip = true, 4981 .ops = &mv88e6085_ops, 4982 }, 4983 4984 [MV88E6095] = { 4985 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4986 .family = MV88E6XXX_FAMILY_6095, 4987 .name = "Marvell 88E6095/88E6095F", 4988 .num_databases = 256, 4989 .num_macs = 8192, 4990 .num_ports = 11, 4991 .num_internal_phys = 0, 4992 .max_vid = 4095, 4993 .port_base_addr = 0x10, 4994 .phy_base_addr = 0x0, 4995 .global1_addr = 0x1b, 4996 .global2_addr = 0x1c, 4997 .age_time_coeff = 15000, 4998 .g1_irqs = 8, 4999 .atu_move_port_mask = 0xf, 5000 .multi_chip = true, 5001 .ops = &mv88e6095_ops, 5002 }, 5003 5004 [MV88E6097] = { 5005 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5006 .family = MV88E6XXX_FAMILY_6097, 5007 .name = "Marvell 88E6097/88E6097F", 5008 .num_databases = 4096, 5009 .num_macs = 8192, 5010 .num_ports = 11, 5011 .num_internal_phys = 8, 5012 .max_vid = 4095, 5013 .port_base_addr = 0x10, 5014 .phy_base_addr = 0x0, 5015 .global1_addr = 0x1b, 5016 .global2_addr = 0x1c, 5017 .age_time_coeff = 15000, 5018 .g1_irqs = 8, 5019 .g2_irqs = 10, 5020 .atu_move_port_mask = 0xf, 5021 .pvt = true, 5022 .multi_chip = true, 5023 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5024 .ops = &mv88e6097_ops, 5025 }, 5026 5027 [MV88E6123] = { 5028 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5029 .family = MV88E6XXX_FAMILY_6165, 5030 .name = "Marvell 88E6123", 5031 .num_databases = 4096, 5032 .num_macs = 1024, 5033 .num_ports = 3, 5034 .num_internal_phys = 5, 5035 .max_vid = 4095, 5036 .port_base_addr = 0x10, 5037 .phy_base_addr = 0x0, 5038 .global1_addr = 0x1b, 5039 .global2_addr = 0x1c, 5040 .age_time_coeff = 15000, 5041 .g1_irqs = 9, 5042 .g2_irqs = 10, 5043 .atu_move_port_mask = 0xf, 5044 .pvt = true, 5045 .multi_chip = true, 5046 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5047 .ops = &mv88e6123_ops, 5048 }, 5049 5050 [MV88E6131] = { 5051 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5052 .family = MV88E6XXX_FAMILY_6185, 5053 .name = "Marvell 88E6131", 5054 .num_databases = 256, 5055 .num_macs = 8192, 5056 .num_ports = 8, 5057 .num_internal_phys = 0, 5058 .max_vid = 4095, 5059 .port_base_addr = 0x10, 5060 .phy_base_addr = 0x0, 5061 .global1_addr = 0x1b, 5062 .global2_addr = 0x1c, 5063 .age_time_coeff = 15000, 5064 .g1_irqs = 9, 5065 .atu_move_port_mask = 0xf, 5066 .multi_chip = true, 5067 .ops = &mv88e6131_ops, 5068 }, 5069 5070 [MV88E6141] = { 5071 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5072 .family = MV88E6XXX_FAMILY_6341, 5073 .name = "Marvell 88E6141", 5074 .num_databases = 4096, 5075 .num_macs = 2048, 5076 .num_ports = 6, 5077 .num_internal_phys = 5, 5078 .num_gpio = 11, 5079 .max_vid = 4095, 5080 .port_base_addr = 0x10, 5081 .phy_base_addr = 0x10, 5082 .global1_addr = 0x1b, 5083 .global2_addr = 0x1c, 5084 .age_time_coeff = 3750, 5085 .atu_move_port_mask = 0x1f, 5086 .g1_irqs = 9, 5087 .g2_irqs = 10, 5088 .pvt = true, 5089 .multi_chip = true, 5090 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5091 .ops = &mv88e6141_ops, 5092 }, 5093 5094 [MV88E6161] = { 5095 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5096 .family = MV88E6XXX_FAMILY_6165, 5097 .name = "Marvell 88E6161", 5098 .num_databases = 4096, 5099 .num_macs = 1024, 5100 .num_ports = 6, 5101 .num_internal_phys = 5, 5102 .max_vid = 4095, 5103 .port_base_addr = 0x10, 5104 .phy_base_addr = 0x0, 5105 .global1_addr = 0x1b, 5106 .global2_addr = 0x1c, 5107 .age_time_coeff = 15000, 5108 .g1_irqs = 9, 5109 .g2_irqs = 10, 5110 .atu_move_port_mask = 0xf, 5111 .pvt = true, 5112 .multi_chip = true, 5113 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5114 .ptp_support = true, 5115 .ops = &mv88e6161_ops, 5116 }, 5117 5118 [MV88E6165] = { 5119 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5120 .family = MV88E6XXX_FAMILY_6165, 5121 .name = "Marvell 88E6165", 5122 .num_databases = 4096, 5123 .num_macs = 8192, 5124 .num_ports = 6, 5125 .num_internal_phys = 0, 5126 .max_vid = 4095, 5127 .port_base_addr = 0x10, 5128 .phy_base_addr = 0x0, 5129 .global1_addr = 0x1b, 5130 .global2_addr = 0x1c, 5131 .age_time_coeff = 15000, 5132 .g1_irqs = 9, 5133 .g2_irqs = 10, 5134 .atu_move_port_mask = 0xf, 5135 .pvt = true, 5136 .multi_chip = true, 5137 .ptp_support = true, 5138 .ops = &mv88e6165_ops, 5139 }, 5140 5141 [MV88E6171] = { 5142 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5143 .family = MV88E6XXX_FAMILY_6351, 5144 .name = "Marvell 88E6171", 5145 .num_databases = 4096, 5146 .num_macs = 8192, 5147 .num_ports = 7, 5148 .num_internal_phys = 5, 5149 .max_vid = 4095, 5150 .port_base_addr = 0x10, 5151 .phy_base_addr = 0x0, 5152 .global1_addr = 0x1b, 5153 .global2_addr = 0x1c, 5154 .age_time_coeff = 15000, 5155 .g1_irqs = 9, 5156 .g2_irqs = 10, 5157 .atu_move_port_mask = 0xf, 5158 .pvt = true, 5159 .multi_chip = true, 5160 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5161 .ops = &mv88e6171_ops, 5162 }, 5163 5164 [MV88E6172] = { 5165 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5166 .family = MV88E6XXX_FAMILY_6352, 5167 .name = "Marvell 88E6172", 5168 .num_databases = 4096, 5169 .num_macs = 8192, 5170 .num_ports = 7, 5171 .num_internal_phys = 5, 5172 .num_gpio = 15, 5173 .max_vid = 4095, 5174 .port_base_addr = 0x10, 5175 .phy_base_addr = 0x0, 5176 .global1_addr = 0x1b, 5177 .global2_addr = 0x1c, 5178 .age_time_coeff = 15000, 5179 .g1_irqs = 9, 5180 .g2_irqs = 10, 5181 .atu_move_port_mask = 0xf, 5182 .pvt = true, 5183 .multi_chip = true, 5184 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5185 .ops = &mv88e6172_ops, 5186 }, 5187 5188 [MV88E6175] = { 5189 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5190 .family = MV88E6XXX_FAMILY_6351, 5191 .name = "Marvell 88E6175", 5192 .num_databases = 4096, 5193 .num_macs = 8192, 5194 .num_ports = 7, 5195 .num_internal_phys = 5, 5196 .max_vid = 4095, 5197 .port_base_addr = 0x10, 5198 .phy_base_addr = 0x0, 5199 .global1_addr = 0x1b, 5200 .global2_addr = 0x1c, 5201 .age_time_coeff = 15000, 5202 .g1_irqs = 9, 5203 .g2_irqs = 10, 5204 .atu_move_port_mask = 0xf, 5205 .pvt = true, 5206 .multi_chip = true, 5207 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5208 .ops = &mv88e6175_ops, 5209 }, 5210 5211 [MV88E6176] = { 5212 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5213 .family = MV88E6XXX_FAMILY_6352, 5214 .name = "Marvell 88E6176", 5215 .num_databases = 4096, 5216 .num_macs = 8192, 5217 .num_ports = 7, 5218 .num_internal_phys = 5, 5219 .num_gpio = 15, 5220 .max_vid = 4095, 5221 .port_base_addr = 0x10, 5222 .phy_base_addr = 0x0, 5223 .global1_addr = 0x1b, 5224 .global2_addr = 0x1c, 5225 .age_time_coeff = 15000, 5226 .g1_irqs = 9, 5227 .g2_irqs = 10, 5228 .atu_move_port_mask = 0xf, 5229 .pvt = true, 5230 .multi_chip = true, 5231 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5232 .ops = &mv88e6176_ops, 5233 }, 5234 5235 [MV88E6185] = { 5236 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5237 .family = MV88E6XXX_FAMILY_6185, 5238 .name = "Marvell 88E6185", 5239 .num_databases = 256, 5240 .num_macs = 8192, 5241 .num_ports = 10, 5242 .num_internal_phys = 0, 5243 .max_vid = 4095, 5244 .port_base_addr = 0x10, 5245 .phy_base_addr = 0x0, 5246 .global1_addr = 0x1b, 5247 .global2_addr = 0x1c, 5248 .age_time_coeff = 15000, 5249 .g1_irqs = 8, 5250 .atu_move_port_mask = 0xf, 5251 .multi_chip = true, 5252 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5253 .ops = &mv88e6185_ops, 5254 }, 5255 5256 [MV88E6190] = { 5257 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5258 .family = MV88E6XXX_FAMILY_6390, 5259 .name = "Marvell 88E6190", 5260 .num_databases = 4096, 5261 .num_macs = 16384, 5262 .num_ports = 11, /* 10 + Z80 */ 5263 .num_internal_phys = 9, 5264 .num_gpio = 16, 5265 .max_vid = 8191, 5266 .port_base_addr = 0x0, 5267 .phy_base_addr = 0x0, 5268 .global1_addr = 0x1b, 5269 .global2_addr = 0x1c, 5270 .age_time_coeff = 3750, 5271 .g1_irqs = 9, 5272 .g2_irqs = 14, 5273 .pvt = true, 5274 .multi_chip = true, 5275 .atu_move_port_mask = 0x1f, 5276 .ops = &mv88e6190_ops, 5277 }, 5278 5279 [MV88E6190X] = { 5280 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5281 .family = MV88E6XXX_FAMILY_6390, 5282 .name = "Marvell 88E6190X", 5283 .num_databases = 4096, 5284 .num_macs = 16384, 5285 .num_ports = 11, /* 10 + Z80 */ 5286 .num_internal_phys = 9, 5287 .num_gpio = 16, 5288 .max_vid = 8191, 5289 .port_base_addr = 0x0, 5290 .phy_base_addr = 0x0, 5291 .global1_addr = 0x1b, 5292 .global2_addr = 0x1c, 5293 .age_time_coeff = 3750, 5294 .g1_irqs = 9, 5295 .g2_irqs = 14, 5296 .atu_move_port_mask = 0x1f, 5297 .pvt = true, 5298 .multi_chip = true, 5299 .ops = &mv88e6190x_ops, 5300 }, 5301 5302 [MV88E6191] = { 5303 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5304 .family = MV88E6XXX_FAMILY_6390, 5305 .name = "Marvell 88E6191", 5306 .num_databases = 4096, 5307 .num_macs = 16384, 5308 .num_ports = 11, /* 10 + Z80 */ 5309 .num_internal_phys = 9, 5310 .max_vid = 8191, 5311 .port_base_addr = 0x0, 5312 .phy_base_addr = 0x0, 5313 .global1_addr = 0x1b, 5314 .global2_addr = 0x1c, 5315 .age_time_coeff = 3750, 5316 .g1_irqs = 9, 5317 .g2_irqs = 14, 5318 .atu_move_port_mask = 0x1f, 5319 .pvt = true, 5320 .multi_chip = true, 5321 .ptp_support = true, 5322 .ops = &mv88e6191_ops, 5323 }, 5324 5325 [MV88E6191X] = { 5326 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5327 .family = MV88E6XXX_FAMILY_6393, 5328 .name = "Marvell 88E6191X", 5329 .num_databases = 4096, 5330 .num_ports = 11, /* 10 + Z80 */ 5331 .num_internal_phys = 9, 5332 .max_vid = 8191, 5333 .port_base_addr = 0x0, 5334 .phy_base_addr = 0x0, 5335 .global1_addr = 0x1b, 5336 .global2_addr = 0x1c, 5337 .age_time_coeff = 3750, 5338 .g1_irqs = 10, 5339 .g2_irqs = 14, 5340 .atu_move_port_mask = 0x1f, 5341 .pvt = true, 5342 .multi_chip = true, 5343 .ptp_support = true, 5344 .ops = &mv88e6393x_ops, 5345 }, 5346 5347 [MV88E6193X] = { 5348 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5349 .family = MV88E6XXX_FAMILY_6393, 5350 .name = "Marvell 88E6193X", 5351 .num_databases = 4096, 5352 .num_ports = 11, /* 10 + Z80 */ 5353 .num_internal_phys = 9, 5354 .max_vid = 8191, 5355 .port_base_addr = 0x0, 5356 .phy_base_addr = 0x0, 5357 .global1_addr = 0x1b, 5358 .global2_addr = 0x1c, 5359 .age_time_coeff = 3750, 5360 .g1_irqs = 10, 5361 .g2_irqs = 14, 5362 .atu_move_port_mask = 0x1f, 5363 .pvt = true, 5364 .multi_chip = true, 5365 .ptp_support = true, 5366 .ops = &mv88e6393x_ops, 5367 }, 5368 5369 [MV88E6220] = { 5370 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5371 .family = MV88E6XXX_FAMILY_6250, 5372 .name = "Marvell 88E6220", 5373 .num_databases = 64, 5374 5375 /* Ports 2-4 are not routed to pins 5376 * => usable ports 0, 1, 5, 6 5377 */ 5378 .num_ports = 7, 5379 .num_internal_phys = 2, 5380 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5381 .max_vid = 4095, 5382 .port_base_addr = 0x08, 5383 .phy_base_addr = 0x00, 5384 .global1_addr = 0x0f, 5385 .global2_addr = 0x07, 5386 .age_time_coeff = 15000, 5387 .g1_irqs = 9, 5388 .g2_irqs = 10, 5389 .atu_move_port_mask = 0xf, 5390 .dual_chip = true, 5391 .ptp_support = true, 5392 .ops = &mv88e6250_ops, 5393 }, 5394 5395 [MV88E6240] = { 5396 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5397 .family = MV88E6XXX_FAMILY_6352, 5398 .name = "Marvell 88E6240", 5399 .num_databases = 4096, 5400 .num_macs = 8192, 5401 .num_ports = 7, 5402 .num_internal_phys = 5, 5403 .num_gpio = 15, 5404 .max_vid = 4095, 5405 .port_base_addr = 0x10, 5406 .phy_base_addr = 0x0, 5407 .global1_addr = 0x1b, 5408 .global2_addr = 0x1c, 5409 .age_time_coeff = 15000, 5410 .g1_irqs = 9, 5411 .g2_irqs = 10, 5412 .atu_move_port_mask = 0xf, 5413 .pvt = true, 5414 .multi_chip = true, 5415 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5416 .ptp_support = true, 5417 .ops = &mv88e6240_ops, 5418 }, 5419 5420 [MV88E6250] = { 5421 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5422 .family = MV88E6XXX_FAMILY_6250, 5423 .name = "Marvell 88E6250", 5424 .num_databases = 64, 5425 .num_ports = 7, 5426 .num_internal_phys = 5, 5427 .max_vid = 4095, 5428 .port_base_addr = 0x08, 5429 .phy_base_addr = 0x00, 5430 .global1_addr = 0x0f, 5431 .global2_addr = 0x07, 5432 .age_time_coeff = 15000, 5433 .g1_irqs = 9, 5434 .g2_irqs = 10, 5435 .atu_move_port_mask = 0xf, 5436 .dual_chip = true, 5437 .ptp_support = true, 5438 .ops = &mv88e6250_ops, 5439 }, 5440 5441 [MV88E6290] = { 5442 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5443 .family = MV88E6XXX_FAMILY_6390, 5444 .name = "Marvell 88E6290", 5445 .num_databases = 4096, 5446 .num_ports = 11, /* 10 + Z80 */ 5447 .num_internal_phys = 9, 5448 .num_gpio = 16, 5449 .max_vid = 8191, 5450 .port_base_addr = 0x0, 5451 .phy_base_addr = 0x0, 5452 .global1_addr = 0x1b, 5453 .global2_addr = 0x1c, 5454 .age_time_coeff = 3750, 5455 .g1_irqs = 9, 5456 .g2_irqs = 14, 5457 .atu_move_port_mask = 0x1f, 5458 .pvt = true, 5459 .multi_chip = true, 5460 .ptp_support = true, 5461 .ops = &mv88e6290_ops, 5462 }, 5463 5464 [MV88E6320] = { 5465 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5466 .family = MV88E6XXX_FAMILY_6320, 5467 .name = "Marvell 88E6320", 5468 .num_databases = 4096, 5469 .num_macs = 8192, 5470 .num_ports = 7, 5471 .num_internal_phys = 5, 5472 .num_gpio = 15, 5473 .max_vid = 4095, 5474 .port_base_addr = 0x10, 5475 .phy_base_addr = 0x0, 5476 .global1_addr = 0x1b, 5477 .global2_addr = 0x1c, 5478 .age_time_coeff = 15000, 5479 .g1_irqs = 8, 5480 .g2_irqs = 10, 5481 .atu_move_port_mask = 0xf, 5482 .pvt = true, 5483 .multi_chip = true, 5484 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5485 .ptp_support = true, 5486 .ops = &mv88e6320_ops, 5487 }, 5488 5489 [MV88E6321] = { 5490 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5491 .family = MV88E6XXX_FAMILY_6320, 5492 .name = "Marvell 88E6321", 5493 .num_databases = 4096, 5494 .num_macs = 8192, 5495 .num_ports = 7, 5496 .num_internal_phys = 5, 5497 .num_gpio = 15, 5498 .max_vid = 4095, 5499 .port_base_addr = 0x10, 5500 .phy_base_addr = 0x0, 5501 .global1_addr = 0x1b, 5502 .global2_addr = 0x1c, 5503 .age_time_coeff = 15000, 5504 .g1_irqs = 8, 5505 .g2_irqs = 10, 5506 .atu_move_port_mask = 0xf, 5507 .multi_chip = true, 5508 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5509 .ptp_support = true, 5510 .ops = &mv88e6321_ops, 5511 }, 5512 5513 [MV88E6341] = { 5514 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5515 .family = MV88E6XXX_FAMILY_6341, 5516 .name = "Marvell 88E6341", 5517 .num_databases = 4096, 5518 .num_macs = 2048, 5519 .num_internal_phys = 5, 5520 .num_ports = 6, 5521 .num_gpio = 11, 5522 .max_vid = 4095, 5523 .port_base_addr = 0x10, 5524 .phy_base_addr = 0x10, 5525 .global1_addr = 0x1b, 5526 .global2_addr = 0x1c, 5527 .age_time_coeff = 3750, 5528 .atu_move_port_mask = 0x1f, 5529 .g1_irqs = 9, 5530 .g2_irqs = 10, 5531 .pvt = true, 5532 .multi_chip = true, 5533 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5534 .ptp_support = true, 5535 .ops = &mv88e6341_ops, 5536 }, 5537 5538 [MV88E6350] = { 5539 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5540 .family = MV88E6XXX_FAMILY_6351, 5541 .name = "Marvell 88E6350", 5542 .num_databases = 4096, 5543 .num_macs = 8192, 5544 .num_ports = 7, 5545 .num_internal_phys = 5, 5546 .max_vid = 4095, 5547 .port_base_addr = 0x10, 5548 .phy_base_addr = 0x0, 5549 .global1_addr = 0x1b, 5550 .global2_addr = 0x1c, 5551 .age_time_coeff = 15000, 5552 .g1_irqs = 9, 5553 .g2_irqs = 10, 5554 .atu_move_port_mask = 0xf, 5555 .pvt = true, 5556 .multi_chip = true, 5557 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5558 .ops = &mv88e6350_ops, 5559 }, 5560 5561 [MV88E6351] = { 5562 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5563 .family = MV88E6XXX_FAMILY_6351, 5564 .name = "Marvell 88E6351", 5565 .num_databases = 4096, 5566 .num_macs = 8192, 5567 .num_ports = 7, 5568 .num_internal_phys = 5, 5569 .max_vid = 4095, 5570 .port_base_addr = 0x10, 5571 .phy_base_addr = 0x0, 5572 .global1_addr = 0x1b, 5573 .global2_addr = 0x1c, 5574 .age_time_coeff = 15000, 5575 .g1_irqs = 9, 5576 .g2_irqs = 10, 5577 .atu_move_port_mask = 0xf, 5578 .pvt = true, 5579 .multi_chip = true, 5580 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5581 .ops = &mv88e6351_ops, 5582 }, 5583 5584 [MV88E6352] = { 5585 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5586 .family = MV88E6XXX_FAMILY_6352, 5587 .name = "Marvell 88E6352", 5588 .num_databases = 4096, 5589 .num_macs = 8192, 5590 .num_ports = 7, 5591 .num_internal_phys = 5, 5592 .num_gpio = 15, 5593 .max_vid = 4095, 5594 .port_base_addr = 0x10, 5595 .phy_base_addr = 0x0, 5596 .global1_addr = 0x1b, 5597 .global2_addr = 0x1c, 5598 .age_time_coeff = 15000, 5599 .g1_irqs = 9, 5600 .g2_irqs = 10, 5601 .atu_move_port_mask = 0xf, 5602 .pvt = true, 5603 .multi_chip = true, 5604 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5605 .ptp_support = true, 5606 .ops = &mv88e6352_ops, 5607 }, 5608 [MV88E6390] = { 5609 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5610 .family = MV88E6XXX_FAMILY_6390, 5611 .name = "Marvell 88E6390", 5612 .num_databases = 4096, 5613 .num_macs = 16384, 5614 .num_ports = 11, /* 10 + Z80 */ 5615 .num_internal_phys = 9, 5616 .num_gpio = 16, 5617 .max_vid = 8191, 5618 .port_base_addr = 0x0, 5619 .phy_base_addr = 0x0, 5620 .global1_addr = 0x1b, 5621 .global2_addr = 0x1c, 5622 .age_time_coeff = 3750, 5623 .g1_irqs = 9, 5624 .g2_irqs = 14, 5625 .atu_move_port_mask = 0x1f, 5626 .pvt = true, 5627 .multi_chip = true, 5628 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5629 .ptp_support = true, 5630 .ops = &mv88e6390_ops, 5631 }, 5632 [MV88E6390X] = { 5633 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5634 .family = MV88E6XXX_FAMILY_6390, 5635 .name = "Marvell 88E6390X", 5636 .num_databases = 4096, 5637 .num_macs = 16384, 5638 .num_ports = 11, /* 10 + Z80 */ 5639 .num_internal_phys = 9, 5640 .num_gpio = 16, 5641 .max_vid = 8191, 5642 .port_base_addr = 0x0, 5643 .phy_base_addr = 0x0, 5644 .global1_addr = 0x1b, 5645 .global2_addr = 0x1c, 5646 .age_time_coeff = 3750, 5647 .g1_irqs = 9, 5648 .g2_irqs = 14, 5649 .atu_move_port_mask = 0x1f, 5650 .pvt = true, 5651 .multi_chip = true, 5652 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5653 .ptp_support = true, 5654 .ops = &mv88e6390x_ops, 5655 }, 5656 5657 [MV88E6393X] = { 5658 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 5659 .family = MV88E6XXX_FAMILY_6393, 5660 .name = "Marvell 88E6393X", 5661 .num_databases = 4096, 5662 .num_ports = 11, /* 10 + Z80 */ 5663 .num_internal_phys = 9, 5664 .max_vid = 8191, 5665 .port_base_addr = 0x0, 5666 .phy_base_addr = 0x0, 5667 .global1_addr = 0x1b, 5668 .global2_addr = 0x1c, 5669 .age_time_coeff = 3750, 5670 .g1_irqs = 10, 5671 .g2_irqs = 14, 5672 .atu_move_port_mask = 0x1f, 5673 .pvt = true, 5674 .multi_chip = true, 5675 .ptp_support = true, 5676 .ops = &mv88e6393x_ops, 5677 }, 5678 }; 5679 5680 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5681 { 5682 int i; 5683 5684 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5685 if (mv88e6xxx_table[i].prod_num == prod_num) 5686 return &mv88e6xxx_table[i]; 5687 5688 return NULL; 5689 } 5690 5691 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5692 { 5693 const struct mv88e6xxx_info *info; 5694 unsigned int prod_num, rev; 5695 u16 id; 5696 int err; 5697 5698 mv88e6xxx_reg_lock(chip); 5699 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5700 mv88e6xxx_reg_unlock(chip); 5701 if (err) 5702 return err; 5703 5704 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5705 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5706 5707 info = mv88e6xxx_lookup_info(prod_num); 5708 if (!info) 5709 return -ENODEV; 5710 5711 /* Update the compatible info with the probed one */ 5712 chip->info = info; 5713 5714 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5715 chip->info->prod_num, chip->info->name, rev); 5716 5717 return 0; 5718 } 5719 5720 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5721 { 5722 struct mv88e6xxx_chip *chip; 5723 5724 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5725 if (!chip) 5726 return NULL; 5727 5728 chip->dev = dev; 5729 5730 mutex_init(&chip->reg_lock); 5731 INIT_LIST_HEAD(&chip->mdios); 5732 idr_init(&chip->policies); 5733 5734 return chip; 5735 } 5736 5737 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5738 int port, 5739 enum dsa_tag_protocol m) 5740 { 5741 struct mv88e6xxx_chip *chip = ds->priv; 5742 5743 return chip->tag_protocol; 5744 } 5745 5746 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port, 5747 enum dsa_tag_protocol proto) 5748 { 5749 struct mv88e6xxx_chip *chip = ds->priv; 5750 enum dsa_tag_protocol old_protocol; 5751 int err; 5752 5753 switch (proto) { 5754 case DSA_TAG_PROTO_EDSA: 5755 switch (chip->info->edsa_support) { 5756 case MV88E6XXX_EDSA_UNSUPPORTED: 5757 return -EPROTONOSUPPORT; 5758 case MV88E6XXX_EDSA_UNDOCUMENTED: 5759 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 5760 fallthrough; 5761 case MV88E6XXX_EDSA_SUPPORTED: 5762 break; 5763 } 5764 break; 5765 case DSA_TAG_PROTO_DSA: 5766 break; 5767 default: 5768 return -EPROTONOSUPPORT; 5769 } 5770 5771 old_protocol = chip->tag_protocol; 5772 chip->tag_protocol = proto; 5773 5774 mv88e6xxx_reg_lock(chip); 5775 err = mv88e6xxx_setup_port_mode(chip, port); 5776 mv88e6xxx_reg_unlock(chip); 5777 5778 if (err) 5779 chip->tag_protocol = old_protocol; 5780 5781 return err; 5782 } 5783 5784 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5785 const struct switchdev_obj_port_mdb *mdb) 5786 { 5787 struct mv88e6xxx_chip *chip = ds->priv; 5788 int err; 5789 5790 mv88e6xxx_reg_lock(chip); 5791 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5792 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 5793 mv88e6xxx_reg_unlock(chip); 5794 5795 return err; 5796 } 5797 5798 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5799 const struct switchdev_obj_port_mdb *mdb) 5800 { 5801 struct mv88e6xxx_chip *chip = ds->priv; 5802 int err; 5803 5804 mv88e6xxx_reg_lock(chip); 5805 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5806 mv88e6xxx_reg_unlock(chip); 5807 5808 return err; 5809 } 5810 5811 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5812 struct dsa_mall_mirror_tc_entry *mirror, 5813 bool ingress) 5814 { 5815 enum mv88e6xxx_egress_direction direction = ingress ? 5816 MV88E6XXX_EGRESS_DIR_INGRESS : 5817 MV88E6XXX_EGRESS_DIR_EGRESS; 5818 struct mv88e6xxx_chip *chip = ds->priv; 5819 bool other_mirrors = false; 5820 int i; 5821 int err; 5822 5823 mutex_lock(&chip->reg_lock); 5824 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5825 mirror->to_local_port) { 5826 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5827 other_mirrors |= ingress ? 5828 chip->ports[i].mirror_ingress : 5829 chip->ports[i].mirror_egress; 5830 5831 /* Can't change egress port when other mirror is active */ 5832 if (other_mirrors) { 5833 err = -EBUSY; 5834 goto out; 5835 } 5836 5837 err = mv88e6xxx_set_egress_port(chip, direction, 5838 mirror->to_local_port); 5839 if (err) 5840 goto out; 5841 } 5842 5843 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5844 out: 5845 mutex_unlock(&chip->reg_lock); 5846 5847 return err; 5848 } 5849 5850 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5851 struct dsa_mall_mirror_tc_entry *mirror) 5852 { 5853 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5854 MV88E6XXX_EGRESS_DIR_INGRESS : 5855 MV88E6XXX_EGRESS_DIR_EGRESS; 5856 struct mv88e6xxx_chip *chip = ds->priv; 5857 bool other_mirrors = false; 5858 int i; 5859 5860 mutex_lock(&chip->reg_lock); 5861 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5862 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5863 5864 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5865 other_mirrors |= mirror->ingress ? 5866 chip->ports[i].mirror_ingress : 5867 chip->ports[i].mirror_egress; 5868 5869 /* Reset egress port when no other mirror is active */ 5870 if (!other_mirrors) { 5871 if (mv88e6xxx_set_egress_port(chip, direction, 5872 dsa_upstream_port(ds, port))) 5873 dev_err(ds->dev, "failed to set egress port\n"); 5874 } 5875 5876 mutex_unlock(&chip->reg_lock); 5877 } 5878 5879 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 5880 struct switchdev_brport_flags flags, 5881 struct netlink_ext_ack *extack) 5882 { 5883 struct mv88e6xxx_chip *chip = ds->priv; 5884 const struct mv88e6xxx_ops *ops; 5885 5886 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 5887 BR_BCAST_FLOOD)) 5888 return -EINVAL; 5889 5890 ops = chip->info->ops; 5891 5892 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 5893 return -EINVAL; 5894 5895 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 5896 return -EINVAL; 5897 5898 return 0; 5899 } 5900 5901 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 5902 struct switchdev_brport_flags flags, 5903 struct netlink_ext_ack *extack) 5904 { 5905 struct mv88e6xxx_chip *chip = ds->priv; 5906 int err = -EOPNOTSUPP; 5907 5908 mv88e6xxx_reg_lock(chip); 5909 5910 if (flags.mask & BR_LEARNING) { 5911 bool learning = !!(flags.val & BR_LEARNING); 5912 u16 pav = learning ? (1 << port) : 0; 5913 5914 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 5915 if (err) 5916 goto out; 5917 } 5918 5919 if (flags.mask & BR_FLOOD) { 5920 bool unicast = !!(flags.val & BR_FLOOD); 5921 5922 err = chip->info->ops->port_set_ucast_flood(chip, port, 5923 unicast); 5924 if (err) 5925 goto out; 5926 } 5927 5928 if (flags.mask & BR_MCAST_FLOOD) { 5929 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 5930 5931 err = chip->info->ops->port_set_mcast_flood(chip, port, 5932 multicast); 5933 if (err) 5934 goto out; 5935 } 5936 5937 if (flags.mask & BR_BCAST_FLOOD) { 5938 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 5939 5940 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 5941 if (err) 5942 goto out; 5943 } 5944 5945 out: 5946 mv88e6xxx_reg_unlock(chip); 5947 5948 return err; 5949 } 5950 5951 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 5952 struct net_device *lag, 5953 struct netdev_lag_upper_info *info) 5954 { 5955 struct mv88e6xxx_chip *chip = ds->priv; 5956 struct dsa_port *dp; 5957 int id, members = 0; 5958 5959 if (!mv88e6xxx_has_lag(chip)) 5960 return false; 5961 5962 id = dsa_lag_id(ds->dst, lag); 5963 if (id < 0 || id >= ds->num_lag_ids) 5964 return false; 5965 5966 dsa_lag_foreach_port(dp, ds->dst, lag) 5967 /* Includes the port joining the LAG */ 5968 members++; 5969 5970 if (members > 8) 5971 return false; 5972 5973 /* We could potentially relax this to include active 5974 * backup in the future. 5975 */ 5976 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 5977 return false; 5978 5979 /* Ideally we would also validate that the hash type matches 5980 * the hardware. Alas, this is always set to unknown on team 5981 * interfaces. 5982 */ 5983 return true; 5984 } 5985 5986 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag) 5987 { 5988 struct mv88e6xxx_chip *chip = ds->priv; 5989 struct dsa_port *dp; 5990 u16 map = 0; 5991 int id; 5992 5993 id = dsa_lag_id(ds->dst, lag); 5994 5995 /* Build the map of all ports to distribute flows destined for 5996 * this LAG. This can be either a local user port, or a DSA 5997 * port if the LAG port is on a remote chip. 5998 */ 5999 dsa_lag_foreach_port(dp, ds->dst, lag) 6000 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6001 6002 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6003 } 6004 6005 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6006 /* Row number corresponds to the number of active members in a 6007 * LAG. Each column states which of the eight hash buckets are 6008 * mapped to the column:th port in the LAG. 6009 * 6010 * Example: In a LAG with three active ports, the second port 6011 * ([2][1]) would be selected for traffic mapped to buckets 6012 * 3,4,5 (0x38). 6013 */ 6014 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6015 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6016 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6017 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6018 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6019 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6020 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6021 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6022 }; 6023 6024 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6025 int num_tx, int nth) 6026 { 6027 u8 active = 0; 6028 int i; 6029 6030 num_tx = num_tx <= 8 ? num_tx : 8; 6031 if (nth < num_tx) 6032 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6033 6034 for (i = 0; i < 8; i++) { 6035 if (BIT(i) & active) 6036 mask[i] |= BIT(port); 6037 } 6038 } 6039 6040 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6041 { 6042 struct mv88e6xxx_chip *chip = ds->priv; 6043 unsigned int id, num_tx; 6044 struct net_device *lag; 6045 struct dsa_port *dp; 6046 int i, err, nth; 6047 u16 mask[8]; 6048 u16 ivec; 6049 6050 /* Assume no port is a member of any LAG. */ 6051 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6052 6053 /* Disable all masks for ports that _are_ members of a LAG. */ 6054 list_for_each_entry(dp, &ds->dst->ports, list) { 6055 if (!dp->lag_dev || dp->ds != ds) 6056 continue; 6057 6058 ivec &= ~BIT(dp->index); 6059 } 6060 6061 for (i = 0; i < 8; i++) 6062 mask[i] = ivec; 6063 6064 /* Enable the correct subset of masks for all LAG ports that 6065 * are in the Tx set. 6066 */ 6067 dsa_lags_foreach_id(id, ds->dst) { 6068 lag = dsa_lag_dev(ds->dst, id); 6069 if (!lag) 6070 continue; 6071 6072 num_tx = 0; 6073 dsa_lag_foreach_port(dp, ds->dst, lag) { 6074 if (dp->lag_tx_enabled) 6075 num_tx++; 6076 } 6077 6078 if (!num_tx) 6079 continue; 6080 6081 nth = 0; 6082 dsa_lag_foreach_port(dp, ds->dst, lag) { 6083 if (!dp->lag_tx_enabled) 6084 continue; 6085 6086 if (dp->ds == ds) 6087 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6088 num_tx, nth); 6089 6090 nth++; 6091 } 6092 } 6093 6094 for (i = 0; i < 8; i++) { 6095 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6096 if (err) 6097 return err; 6098 } 6099 6100 return 0; 6101 } 6102 6103 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6104 struct net_device *lag) 6105 { 6106 int err; 6107 6108 err = mv88e6xxx_lag_sync_masks(ds); 6109 6110 if (!err) 6111 err = mv88e6xxx_lag_sync_map(ds, lag); 6112 6113 return err; 6114 } 6115 6116 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6117 { 6118 struct mv88e6xxx_chip *chip = ds->priv; 6119 int err; 6120 6121 mv88e6xxx_reg_lock(chip); 6122 err = mv88e6xxx_lag_sync_masks(ds); 6123 mv88e6xxx_reg_unlock(chip); 6124 return err; 6125 } 6126 6127 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6128 struct net_device *lag, 6129 struct netdev_lag_upper_info *info) 6130 { 6131 struct mv88e6xxx_chip *chip = ds->priv; 6132 int err, id; 6133 6134 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6135 return -EOPNOTSUPP; 6136 6137 id = dsa_lag_id(ds->dst, lag); 6138 6139 mv88e6xxx_reg_lock(chip); 6140 6141 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6142 if (err) 6143 goto err_unlock; 6144 6145 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6146 if (err) 6147 goto err_clear_trunk; 6148 6149 mv88e6xxx_reg_unlock(chip); 6150 return 0; 6151 6152 err_clear_trunk: 6153 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6154 err_unlock: 6155 mv88e6xxx_reg_unlock(chip); 6156 return err; 6157 } 6158 6159 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6160 struct net_device *lag) 6161 { 6162 struct mv88e6xxx_chip *chip = ds->priv; 6163 int err_sync, err_trunk; 6164 6165 mv88e6xxx_reg_lock(chip); 6166 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6167 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6168 mv88e6xxx_reg_unlock(chip); 6169 return err_sync ? : err_trunk; 6170 } 6171 6172 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6173 int port) 6174 { 6175 struct mv88e6xxx_chip *chip = ds->priv; 6176 int err; 6177 6178 mv88e6xxx_reg_lock(chip); 6179 err = mv88e6xxx_lag_sync_masks(ds); 6180 mv88e6xxx_reg_unlock(chip); 6181 return err; 6182 } 6183 6184 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6185 int port, struct net_device *lag, 6186 struct netdev_lag_upper_info *info) 6187 { 6188 struct mv88e6xxx_chip *chip = ds->priv; 6189 int err; 6190 6191 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6192 return -EOPNOTSUPP; 6193 6194 mv88e6xxx_reg_lock(chip); 6195 6196 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6197 if (err) 6198 goto unlock; 6199 6200 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6201 6202 unlock: 6203 mv88e6xxx_reg_unlock(chip); 6204 return err; 6205 } 6206 6207 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6208 int port, struct net_device *lag) 6209 { 6210 struct mv88e6xxx_chip *chip = ds->priv; 6211 int err_sync, err_pvt; 6212 6213 mv88e6xxx_reg_lock(chip); 6214 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6215 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6216 mv88e6xxx_reg_unlock(chip); 6217 return err_sync ? : err_pvt; 6218 } 6219 6220 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6221 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6222 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6223 .setup = mv88e6xxx_setup, 6224 .teardown = mv88e6xxx_teardown, 6225 .port_setup = mv88e6xxx_port_setup, 6226 .port_teardown = mv88e6xxx_port_teardown, 6227 .phylink_validate = mv88e6xxx_validate, 6228 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 6229 .phylink_mac_config = mv88e6xxx_mac_config, 6230 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 6231 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6232 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6233 .get_strings = mv88e6xxx_get_strings, 6234 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6235 .get_sset_count = mv88e6xxx_get_sset_count, 6236 .port_enable = mv88e6xxx_port_enable, 6237 .port_disable = mv88e6xxx_port_disable, 6238 .port_max_mtu = mv88e6xxx_get_max_mtu, 6239 .port_change_mtu = mv88e6xxx_change_mtu, 6240 .get_mac_eee = mv88e6xxx_get_mac_eee, 6241 .set_mac_eee = mv88e6xxx_set_mac_eee, 6242 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6243 .get_eeprom = mv88e6xxx_get_eeprom, 6244 .set_eeprom = mv88e6xxx_set_eeprom, 6245 .get_regs_len = mv88e6xxx_get_regs_len, 6246 .get_regs = mv88e6xxx_get_regs, 6247 .get_rxnfc = mv88e6xxx_get_rxnfc, 6248 .set_rxnfc = mv88e6xxx_set_rxnfc, 6249 .set_ageing_time = mv88e6xxx_set_ageing_time, 6250 .port_bridge_join = mv88e6xxx_port_bridge_join, 6251 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6252 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6253 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6254 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6255 .port_fast_age = mv88e6xxx_port_fast_age, 6256 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6257 .port_vlan_add = mv88e6xxx_port_vlan_add, 6258 .port_vlan_del = mv88e6xxx_port_vlan_del, 6259 .port_fdb_add = mv88e6xxx_port_fdb_add, 6260 .port_fdb_del = mv88e6xxx_port_fdb_del, 6261 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6262 .port_mdb_add = mv88e6xxx_port_mdb_add, 6263 .port_mdb_del = mv88e6xxx_port_mdb_del, 6264 .port_mirror_add = mv88e6xxx_port_mirror_add, 6265 .port_mirror_del = mv88e6xxx_port_mirror_del, 6266 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6267 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6268 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6269 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6270 .port_txtstamp = mv88e6xxx_port_txtstamp, 6271 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6272 .get_ts_info = mv88e6xxx_get_ts_info, 6273 .devlink_param_get = mv88e6xxx_devlink_param_get, 6274 .devlink_param_set = mv88e6xxx_devlink_param_set, 6275 .devlink_info_get = mv88e6xxx_devlink_info_get, 6276 .port_lag_change = mv88e6xxx_port_lag_change, 6277 .port_lag_join = mv88e6xxx_port_lag_join, 6278 .port_lag_leave = mv88e6xxx_port_lag_leave, 6279 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6280 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6281 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6282 .port_bridge_tx_fwd_offload = mv88e6xxx_bridge_tx_fwd_offload, 6283 .port_bridge_tx_fwd_unoffload = mv88e6xxx_bridge_tx_fwd_unoffload, 6284 }; 6285 6286 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6287 { 6288 struct device *dev = chip->dev; 6289 struct dsa_switch *ds; 6290 6291 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6292 if (!ds) 6293 return -ENOMEM; 6294 6295 ds->dev = dev; 6296 ds->num_ports = mv88e6xxx_num_ports(chip); 6297 ds->priv = chip; 6298 ds->dev = dev; 6299 ds->ops = &mv88e6xxx_switch_ops; 6300 ds->ageing_time_min = chip->info->age_time_coeff; 6301 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6302 6303 /* Some chips support up to 32, but that requires enabling the 6304 * 5-bit port mode, which we do not support. 640k^W16 ought to 6305 * be enough for anyone. 6306 */ 6307 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6308 6309 dev_set_drvdata(dev, ds); 6310 6311 return dsa_register_switch(ds); 6312 } 6313 6314 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6315 { 6316 dsa_unregister_switch(chip->ds); 6317 } 6318 6319 static const void *pdata_device_get_match_data(struct device *dev) 6320 { 6321 const struct of_device_id *matches = dev->driver->of_match_table; 6322 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6323 6324 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6325 matches++) { 6326 if (!strcmp(pdata->compatible, matches->compatible)) 6327 return matches->data; 6328 } 6329 return NULL; 6330 } 6331 6332 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6333 * would be lost after a power cycle so prevent it to be suspended. 6334 */ 6335 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6336 { 6337 return -EOPNOTSUPP; 6338 } 6339 6340 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6341 { 6342 return 0; 6343 } 6344 6345 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 6346 6347 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 6348 { 6349 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 6350 const struct mv88e6xxx_info *compat_info = NULL; 6351 struct device *dev = &mdiodev->dev; 6352 struct device_node *np = dev->of_node; 6353 struct mv88e6xxx_chip *chip; 6354 int port; 6355 int err; 6356 6357 if (!np && !pdata) 6358 return -EINVAL; 6359 6360 if (np) 6361 compat_info = of_device_get_match_data(dev); 6362 6363 if (pdata) { 6364 compat_info = pdata_device_get_match_data(dev); 6365 6366 if (!pdata->netdev) 6367 return -EINVAL; 6368 6369 for (port = 0; port < DSA_MAX_PORTS; port++) { 6370 if (!(pdata->enabled_ports & (1 << port))) 6371 continue; 6372 if (strcmp(pdata->cd.port_names[port], "cpu")) 6373 continue; 6374 pdata->cd.netdev[port] = &pdata->netdev->dev; 6375 break; 6376 } 6377 } 6378 6379 if (!compat_info) 6380 return -EINVAL; 6381 6382 chip = mv88e6xxx_alloc_chip(dev); 6383 if (!chip) { 6384 err = -ENOMEM; 6385 goto out; 6386 } 6387 6388 chip->info = compat_info; 6389 6390 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 6391 if (err) 6392 goto out; 6393 6394 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 6395 if (IS_ERR(chip->reset)) { 6396 err = PTR_ERR(chip->reset); 6397 goto out; 6398 } 6399 if (chip->reset) 6400 usleep_range(1000, 2000); 6401 6402 err = mv88e6xxx_detect(chip); 6403 if (err) 6404 goto out; 6405 6406 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 6407 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 6408 else 6409 chip->tag_protocol = DSA_TAG_PROTO_DSA; 6410 6411 mv88e6xxx_phy_init(chip); 6412 6413 if (chip->info->ops->get_eeprom) { 6414 if (np) 6415 of_property_read_u32(np, "eeprom-length", 6416 &chip->eeprom_len); 6417 else 6418 chip->eeprom_len = pdata->eeprom_len; 6419 } 6420 6421 mv88e6xxx_reg_lock(chip); 6422 err = mv88e6xxx_switch_reset(chip); 6423 mv88e6xxx_reg_unlock(chip); 6424 if (err) 6425 goto out; 6426 6427 if (np) { 6428 chip->irq = of_irq_get(np, 0); 6429 if (chip->irq == -EPROBE_DEFER) { 6430 err = chip->irq; 6431 goto out; 6432 } 6433 } 6434 6435 if (pdata) 6436 chip->irq = pdata->irq; 6437 6438 /* Has to be performed before the MDIO bus is created, because 6439 * the PHYs will link their interrupts to these interrupt 6440 * controllers 6441 */ 6442 mv88e6xxx_reg_lock(chip); 6443 if (chip->irq > 0) 6444 err = mv88e6xxx_g1_irq_setup(chip); 6445 else 6446 err = mv88e6xxx_irq_poll_setup(chip); 6447 mv88e6xxx_reg_unlock(chip); 6448 6449 if (err) 6450 goto out; 6451 6452 if (chip->info->g2_irqs > 0) { 6453 err = mv88e6xxx_g2_irq_setup(chip); 6454 if (err) 6455 goto out_g1_irq; 6456 } 6457 6458 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 6459 if (err) 6460 goto out_g2_irq; 6461 6462 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 6463 if (err) 6464 goto out_g1_atu_prob_irq; 6465 6466 err = mv88e6xxx_mdios_register(chip, np); 6467 if (err) 6468 goto out_g1_vtu_prob_irq; 6469 6470 err = mv88e6xxx_register_switch(chip); 6471 if (err) 6472 goto out_mdio; 6473 6474 return 0; 6475 6476 out_mdio: 6477 mv88e6xxx_mdios_unregister(chip); 6478 out_g1_vtu_prob_irq: 6479 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6480 out_g1_atu_prob_irq: 6481 mv88e6xxx_g1_atu_prob_irq_free(chip); 6482 out_g2_irq: 6483 if (chip->info->g2_irqs > 0) 6484 mv88e6xxx_g2_irq_free(chip); 6485 out_g1_irq: 6486 if (chip->irq > 0) 6487 mv88e6xxx_g1_irq_free(chip); 6488 else 6489 mv88e6xxx_irq_poll_free(chip); 6490 out: 6491 if (pdata) 6492 dev_put(pdata->netdev); 6493 6494 return err; 6495 } 6496 6497 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 6498 { 6499 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6500 struct mv88e6xxx_chip *chip; 6501 6502 if (!ds) 6503 return; 6504 6505 chip = ds->priv; 6506 6507 if (chip->info->ptp_support) { 6508 mv88e6xxx_hwtstamp_free(chip); 6509 mv88e6xxx_ptp_free(chip); 6510 } 6511 6512 mv88e6xxx_phy_destroy(chip); 6513 mv88e6xxx_unregister_switch(chip); 6514 mv88e6xxx_mdios_unregister(chip); 6515 6516 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6517 mv88e6xxx_g1_atu_prob_irq_free(chip); 6518 6519 if (chip->info->g2_irqs > 0) 6520 mv88e6xxx_g2_irq_free(chip); 6521 6522 if (chip->irq > 0) 6523 mv88e6xxx_g1_irq_free(chip); 6524 else 6525 mv88e6xxx_irq_poll_free(chip); 6526 6527 dev_set_drvdata(&mdiodev->dev, NULL); 6528 } 6529 6530 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 6531 { 6532 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6533 6534 if (!ds) 6535 return; 6536 6537 dsa_switch_shutdown(ds); 6538 6539 dev_set_drvdata(&mdiodev->dev, NULL); 6540 } 6541 6542 static const struct of_device_id mv88e6xxx_of_match[] = { 6543 { 6544 .compatible = "marvell,mv88e6085", 6545 .data = &mv88e6xxx_table[MV88E6085], 6546 }, 6547 { 6548 .compatible = "marvell,mv88e6190", 6549 .data = &mv88e6xxx_table[MV88E6190], 6550 }, 6551 { 6552 .compatible = "marvell,mv88e6250", 6553 .data = &mv88e6xxx_table[MV88E6250], 6554 }, 6555 { /* sentinel */ }, 6556 }; 6557 6558 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 6559 6560 static struct mdio_driver mv88e6xxx_driver = { 6561 .probe = mv88e6xxx_probe, 6562 .remove = mv88e6xxx_remove, 6563 .shutdown = mv88e6xxx_shutdown, 6564 .mdiodrv.driver = { 6565 .name = "mv88e6085", 6566 .of_match_table = mv88e6xxx_of_match, 6567 .pm = &mv88e6xxx_pm_ops, 6568 }, 6569 }; 6570 6571 mdio_module_driver(mv88e6xxx_driver); 6572 6573 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 6574 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 6575 MODULE_LICENSE("GPL"); 6576