1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 dev_err(chip->dev, "Timeout while waiting for switch\n"); 113 return -ETIMEDOUT; 114 } 115 116 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 117 int bit, int val) 118 { 119 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 120 val ? BIT(bit) : 0x0000); 121 } 122 123 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 124 { 125 struct mv88e6xxx_mdio_bus *mdio_bus; 126 127 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 128 list); 129 if (!mdio_bus) 130 return NULL; 131 132 return mdio_bus->bus; 133 } 134 135 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 136 { 137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 138 unsigned int n = d->hwirq; 139 140 chip->g1_irq.masked |= (1 << n); 141 } 142 143 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 144 { 145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 146 unsigned int n = d->hwirq; 147 148 chip->g1_irq.masked &= ~(1 << n); 149 } 150 151 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 152 { 153 unsigned int nhandled = 0; 154 unsigned int sub_irq; 155 unsigned int n; 156 u16 reg; 157 u16 ctl1; 158 int err; 159 160 mv88e6xxx_reg_lock(chip); 161 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 162 mv88e6xxx_reg_unlock(chip); 163 164 if (err) 165 goto out; 166 167 do { 168 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 169 if (reg & (1 << n)) { 170 sub_irq = irq_find_mapping(chip->g1_irq.domain, 171 n); 172 handle_nested_irq(sub_irq); 173 ++nhandled; 174 } 175 } 176 177 mv88e6xxx_reg_lock(chip); 178 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 179 if (err) 180 goto unlock; 181 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 182 unlock: 183 mv88e6xxx_reg_unlock(chip); 184 if (err) 185 goto out; 186 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 187 } while (reg & ctl1); 188 189 out: 190 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 191 } 192 193 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 194 { 195 struct mv88e6xxx_chip *chip = dev_id; 196 197 return mv88e6xxx_g1_irq_thread_work(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 204 mv88e6xxx_reg_lock(chip); 205 } 206 207 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 208 { 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 211 u16 reg; 212 int err; 213 214 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 215 if (err) 216 goto out; 217 218 reg &= ~mask; 219 reg |= (~chip->g1_irq.masked & mask); 220 221 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 222 if (err) 223 goto out; 224 225 out: 226 mv88e6xxx_reg_unlock(chip); 227 } 228 229 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 230 .name = "mv88e6xxx-g1", 231 .irq_mask = mv88e6xxx_g1_irq_mask, 232 .irq_unmask = mv88e6xxx_g1_irq_unmask, 233 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 234 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 235 }; 236 237 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 238 unsigned int irq, 239 irq_hw_number_t hwirq) 240 { 241 struct mv88e6xxx_chip *chip = d->host_data; 242 243 irq_set_chip_data(irq, d->host_data); 244 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 245 irq_set_noprobe(irq); 246 247 return 0; 248 } 249 250 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 251 .map = mv88e6xxx_g1_irq_domain_map, 252 .xlate = irq_domain_xlate_twocell, 253 }; 254 255 /* To be called with reg_lock held */ 256 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 257 { 258 int irq, virq; 259 u16 mask; 260 261 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 262 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 263 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 264 265 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 266 virq = irq_find_mapping(chip->g1_irq.domain, irq); 267 irq_dispose_mapping(virq); 268 } 269 270 irq_domain_remove(chip->g1_irq.domain); 271 } 272 273 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 274 { 275 /* 276 * free_irq must be called without reg_lock taken because the irq 277 * handler takes this lock, too. 278 */ 279 free_irq(chip->irq, chip); 280 281 mv88e6xxx_reg_lock(chip); 282 mv88e6xxx_g1_irq_free_common(chip); 283 mv88e6xxx_reg_unlock(chip); 284 } 285 286 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 287 { 288 int err, irq, virq; 289 u16 reg, mask; 290 291 chip->g1_irq.nirqs = chip->info->g1_irqs; 292 chip->g1_irq.domain = irq_domain_add_simple( 293 NULL, chip->g1_irq.nirqs, 0, 294 &mv88e6xxx_g1_irq_domain_ops, chip); 295 if (!chip->g1_irq.domain) 296 return -ENOMEM; 297 298 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 299 irq_create_mapping(chip->g1_irq.domain, irq); 300 301 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 302 chip->g1_irq.masked = ~0; 303 304 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 305 if (err) 306 goto out_mapping; 307 308 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 309 310 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 311 if (err) 312 goto out_disable; 313 314 /* Reading the interrupt status clears (most of) them */ 315 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 316 if (err) 317 goto out_disable; 318 319 return 0; 320 321 out_disable: 322 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 323 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 324 325 out_mapping: 326 for (irq = 0; irq < 16; irq++) { 327 virq = irq_find_mapping(chip->g1_irq.domain, irq); 328 irq_dispose_mapping(virq); 329 } 330 331 irq_domain_remove(chip->g1_irq.domain); 332 333 return err; 334 } 335 336 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 337 { 338 static struct lock_class_key lock_key; 339 static struct lock_class_key request_key; 340 int err; 341 342 err = mv88e6xxx_g1_irq_setup_common(chip); 343 if (err) 344 return err; 345 346 /* These lock classes tells lockdep that global 1 irqs are in 347 * a different category than their parent GPIO, so it won't 348 * report false recursion. 349 */ 350 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 351 352 snprintf(chip->irq_name, sizeof(chip->irq_name), 353 "mv88e6xxx-%s", dev_name(chip->dev)); 354 355 mv88e6xxx_reg_unlock(chip); 356 err = request_threaded_irq(chip->irq, NULL, 357 mv88e6xxx_g1_irq_thread_fn, 358 IRQF_ONESHOT | IRQF_SHARED, 359 chip->irq_name, chip); 360 mv88e6xxx_reg_lock(chip); 361 if (err) 362 mv88e6xxx_g1_irq_free_common(chip); 363 364 return err; 365 } 366 367 static void mv88e6xxx_irq_poll(struct kthread_work *work) 368 { 369 struct mv88e6xxx_chip *chip = container_of(work, 370 struct mv88e6xxx_chip, 371 irq_poll_work.work); 372 mv88e6xxx_g1_irq_thread_work(chip); 373 374 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 375 msecs_to_jiffies(100)); 376 } 377 378 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 379 { 380 int err; 381 382 err = mv88e6xxx_g1_irq_setup_common(chip); 383 if (err) 384 return err; 385 386 kthread_init_delayed_work(&chip->irq_poll_work, 387 mv88e6xxx_irq_poll); 388 389 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 390 if (IS_ERR(chip->kworker)) 391 return PTR_ERR(chip->kworker); 392 393 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 394 msecs_to_jiffies(100)); 395 396 return 0; 397 } 398 399 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 400 { 401 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 402 kthread_destroy_worker(chip->kworker); 403 404 mv88e6xxx_reg_lock(chip); 405 mv88e6xxx_g1_irq_free_common(chip); 406 mv88e6xxx_reg_unlock(chip); 407 } 408 409 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 410 int port, phy_interface_t interface) 411 { 412 int err; 413 414 if (chip->info->ops->port_set_rgmii_delay) { 415 err = chip->info->ops->port_set_rgmii_delay(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 if (chip->info->ops->port_set_cmode) { 422 err = chip->info->ops->port_set_cmode(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 return 0; 429 } 430 431 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 432 int link, int speed, int duplex, int pause, 433 phy_interface_t mode) 434 { 435 int err; 436 437 if (!chip->info->ops->port_set_link) 438 return 0; 439 440 /* Port's MAC control must not be changed unless the link is down */ 441 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 442 if (err) 443 return err; 444 445 if (chip->info->ops->port_set_speed_duplex) { 446 err = chip->info->ops->port_set_speed_duplex(chip, port, 447 speed, duplex); 448 if (err && err != -EOPNOTSUPP) 449 goto restore_link; 450 } 451 452 if (chip->info->ops->port_set_pause) { 453 err = chip->info->ops->port_set_pause(chip, port, pause); 454 if (err) 455 goto restore_link; 456 } 457 458 err = mv88e6xxx_port_config_interface(chip, port, mode); 459 restore_link: 460 if (chip->info->ops->port_set_link(chip, port, link)) 461 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 462 463 return err; 464 } 465 466 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 467 { 468 struct mv88e6xxx_chip *chip = ds->priv; 469 470 return port < chip->info->num_internal_phys; 471 } 472 473 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 474 { 475 u16 reg; 476 int err; 477 478 /* The 88e6250 family does not have the PHY detect bit. Instead, 479 * report whether the port is internal. 480 */ 481 if (chip->info->family == MV88E6XXX_FAMILY_6250) 482 return port < chip->info->num_internal_phys; 483 484 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 485 if (err) { 486 dev_err(chip->dev, 487 "p%d: %s: failed to read port status\n", 488 port, __func__); 489 return err; 490 } 491 492 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 493 } 494 495 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 496 struct phylink_link_state *state) 497 { 498 struct mv88e6xxx_chip *chip = ds->priv; 499 int lane; 500 int err; 501 502 mv88e6xxx_reg_lock(chip); 503 lane = mv88e6xxx_serdes_get_lane(chip, port); 504 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 505 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 506 state); 507 else 508 err = -EOPNOTSUPP; 509 mv88e6xxx_reg_unlock(chip); 510 511 return err; 512 } 513 514 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 515 unsigned int mode, 516 phy_interface_t interface, 517 const unsigned long *advertise) 518 { 519 const struct mv88e6xxx_ops *ops = chip->info->ops; 520 int lane; 521 522 if (ops->serdes_pcs_config) { 523 lane = mv88e6xxx_serdes_get_lane(chip, port); 524 if (lane >= 0) 525 return ops->serdes_pcs_config(chip, port, lane, mode, 526 interface, advertise); 527 } 528 529 return 0; 530 } 531 532 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 533 { 534 struct mv88e6xxx_chip *chip = ds->priv; 535 const struct mv88e6xxx_ops *ops; 536 int err = 0; 537 int lane; 538 539 ops = chip->info->ops; 540 541 if (ops->serdes_pcs_an_restart) { 542 mv88e6xxx_reg_lock(chip); 543 lane = mv88e6xxx_serdes_get_lane(chip, port); 544 if (lane >= 0) 545 err = ops->serdes_pcs_an_restart(chip, port, lane); 546 mv88e6xxx_reg_unlock(chip); 547 548 if (err) 549 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 550 } 551 } 552 553 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 554 unsigned int mode, 555 int speed, int duplex) 556 { 557 const struct mv88e6xxx_ops *ops = chip->info->ops; 558 int lane; 559 560 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 561 lane = mv88e6xxx_serdes_get_lane(chip, port); 562 if (lane >= 0) 563 return ops->serdes_pcs_link_up(chip, port, lane, 564 speed, duplex); 565 } 566 567 return 0; 568 } 569 570 static const u8 mv88e6185_phy_interface_modes[] = { 571 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 572 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 573 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 574 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 575 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 576 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 577 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 578 }; 579 580 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 581 struct phylink_config *config) 582 { 583 u8 cmode = chip->ports[port].cmode; 584 585 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 586 587 if (mv88e6xxx_phy_is_internal(chip->ds, port)) { 588 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 589 } else { 590 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 591 mv88e6185_phy_interface_modes[cmode]) 592 __set_bit(mv88e6185_phy_interface_modes[cmode], 593 config->supported_interfaces); 594 595 config->mac_capabilities |= MAC_1000FD; 596 } 597 } 598 599 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 600 struct phylink_config *config) 601 { 602 u8 cmode = chip->ports[port].cmode; 603 604 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 605 mv88e6185_phy_interface_modes[cmode]) 606 __set_bit(mv88e6185_phy_interface_modes[cmode], 607 config->supported_interfaces); 608 609 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 610 MAC_1000FD; 611 } 612 613 static const u8 mv88e6xxx_phy_interface_modes[] = { 614 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_MII, 615 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 616 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 617 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_RMII, 618 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 619 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 620 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 621 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 622 /* higher interface modes are not needed here, since ports supporting 623 * them are writable, and so the supported interfaces are filled in the 624 * corresponding .phylink_set_interfaces() implementation below 625 */ 626 }; 627 628 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 629 { 630 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 631 mv88e6xxx_phy_interface_modes[cmode]) 632 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 633 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 634 phy_interface_set_rgmii(supported); 635 } 636 637 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 638 struct phylink_config *config) 639 { 640 unsigned long *supported = config->supported_interfaces; 641 642 /* Translate the default cmode */ 643 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 644 645 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 646 } 647 648 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) 649 { 650 u16 reg, val; 651 int err; 652 653 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®); 654 if (err) 655 return err; 656 657 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 658 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 659 return 0xf; 660 661 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 662 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val); 663 if (err) 664 return err; 665 666 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val); 667 if (err) 668 return err; 669 670 /* Restore PHY_DETECT value */ 671 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg); 672 if (err) 673 return err; 674 675 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 676 } 677 678 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 679 struct phylink_config *config) 680 { 681 unsigned long *supported = config->supported_interfaces; 682 int err, cmode; 683 684 /* Translate the default cmode */ 685 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 686 687 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 688 MAC_1000FD; 689 690 /* Port 4 supports automedia if the serdes is associated with it. */ 691 if (port == 4) { 692 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 693 if (err < 0) 694 dev_err(chip->dev, "p%d: failed to read scratch\n", 695 port); 696 if (err <= 0) 697 return; 698 699 cmode = mv88e6352_get_port4_serdes_cmode(chip); 700 if (cmode < 0) 701 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 702 port); 703 else 704 mv88e6xxx_translate_cmode(cmode, supported); 705 } 706 } 707 708 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 709 struct phylink_config *config) 710 { 711 unsigned long *supported = config->supported_interfaces; 712 713 /* Translate the default cmode */ 714 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 715 716 /* No ethtool bits for 200Mbps */ 717 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 718 MAC_1000FD; 719 720 /* The C_Mode field is programmable on port 5 */ 721 if (port == 5) { 722 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 723 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 724 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 725 726 config->mac_capabilities |= MAC_2500FD; 727 } 728 } 729 730 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 731 struct phylink_config *config) 732 { 733 unsigned long *supported = config->supported_interfaces; 734 735 /* Translate the default cmode */ 736 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 737 738 /* No ethtool bits for 200Mbps */ 739 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 740 MAC_1000FD; 741 742 /* The C_Mode field is programmable on ports 9 and 10 */ 743 if (port == 9 || port == 10) { 744 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 745 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 746 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 747 748 config->mac_capabilities |= MAC_2500FD; 749 } 750 } 751 752 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 753 struct phylink_config *config) 754 { 755 unsigned long *supported = config->supported_interfaces; 756 757 mv88e6390_phylink_get_caps(chip, port, config); 758 759 /* For the 6x90X, ports 2-7 can be in automedia mode. 760 * (Note that 6x90 doesn't support RXAUI nor XAUI). 761 * 762 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 763 * configured for 1000BASE-X, SGMII or 2500BASE-X. 764 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 765 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 766 * 767 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 768 * configured for 1000BASE-X, SGMII or 2500BASE-X. 769 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 770 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 771 * 772 * For now, be permissive (as the old code was) and allow 1000BASE-X 773 * on ports 2..7. 774 */ 775 if (port >= 2 && port <= 7) 776 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 777 778 /* The C_Mode field can also be programmed for 10G speeds */ 779 if (port == 9 || port == 10) { 780 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 781 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 782 783 config->mac_capabilities |= MAC_10000FD; 784 } 785 } 786 787 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 788 struct phylink_config *config) 789 { 790 unsigned long *supported = config->supported_interfaces; 791 bool is_6191x = 792 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 793 794 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 795 796 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 797 MAC_1000FD; 798 799 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 800 if (port == 0 || port == 9 || port == 10) { 801 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 802 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 803 804 /* 6191X supports >1G modes only on port 10 */ 805 if (!is_6191x || port == 10) { 806 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 807 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 808 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 809 /* FIXME: USXGMII is not supported yet */ 810 /* __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); */ 811 812 config->mac_capabilities |= MAC_2500FD | MAC_5000FD | 813 MAC_10000FD; 814 } 815 } 816 817 if (port == 0) { 818 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 819 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 820 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 821 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 822 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 823 } 824 } 825 826 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 827 struct phylink_config *config) 828 { 829 struct mv88e6xxx_chip *chip = ds->priv; 830 831 mv88e6xxx_reg_lock(chip); 832 chip->info->ops->phylink_get_caps(chip, port, config); 833 mv88e6xxx_reg_unlock(chip); 834 835 if (mv88e6xxx_phy_is_internal(ds, port)) { 836 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 837 config->supported_interfaces); 838 /* Internal ports with no phy-mode need GMII for PHYLIB */ 839 __set_bit(PHY_INTERFACE_MODE_GMII, 840 config->supported_interfaces); 841 } 842 } 843 844 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 845 unsigned int mode, 846 const struct phylink_link_state *state) 847 { 848 struct mv88e6xxx_chip *chip = ds->priv; 849 struct mv88e6xxx_port *p; 850 int err = 0; 851 852 p = &chip->ports[port]; 853 854 mv88e6xxx_reg_lock(chip); 855 856 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) { 857 /* In inband mode, the link may come up at any time while the 858 * link is not forced down. Force the link down while we 859 * reconfigure the interface mode. 860 */ 861 if (mode == MLO_AN_INBAND && 862 p->interface != state->interface && 863 chip->info->ops->port_set_link) 864 chip->info->ops->port_set_link(chip, port, 865 LINK_FORCED_DOWN); 866 867 err = mv88e6xxx_port_config_interface(chip, port, 868 state->interface); 869 if (err && err != -EOPNOTSUPP) 870 goto err_unlock; 871 872 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, 873 state->interface, 874 state->advertising); 875 /* FIXME: we should restart negotiation if something changed - 876 * which is something we get if we convert to using phylinks 877 * PCS operations. 878 */ 879 if (err > 0) 880 err = 0; 881 } 882 883 /* Undo the forced down state above after completing configuration 884 * irrespective of its state on entry, which allows the link to come 885 * up in the in-band case where there is no separate SERDES. Also 886 * ensure that the link can come up if the PPU is in use and we are 887 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 888 */ 889 if (chip->info->ops->port_set_link && 890 ((mode == MLO_AN_INBAND && p->interface != state->interface) || 891 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 892 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 893 894 p->interface = state->interface; 895 896 err_unlock: 897 mv88e6xxx_reg_unlock(chip); 898 899 if (err && err != -EOPNOTSUPP) 900 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 901 } 902 903 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 904 unsigned int mode, 905 phy_interface_t interface) 906 { 907 struct mv88e6xxx_chip *chip = ds->priv; 908 const struct mv88e6xxx_ops *ops; 909 int err = 0; 910 911 ops = chip->info->ops; 912 913 mv88e6xxx_reg_lock(chip); 914 /* Force the link down if we know the port may not be automatically 915 * updated by the switch or if we are using fixed-link mode. 916 */ 917 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 918 mode == MLO_AN_FIXED) && ops->port_sync_link) 919 err = ops->port_sync_link(chip, port, mode, false); 920 921 if (!err && ops->port_set_speed_duplex) 922 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 923 DUPLEX_UNFORCED); 924 mv88e6xxx_reg_unlock(chip); 925 926 if (err) 927 dev_err(chip->dev, 928 "p%d: failed to force MAC link down\n", port); 929 } 930 931 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 932 unsigned int mode, phy_interface_t interface, 933 struct phy_device *phydev, 934 int speed, int duplex, 935 bool tx_pause, bool rx_pause) 936 { 937 struct mv88e6xxx_chip *chip = ds->priv; 938 const struct mv88e6xxx_ops *ops; 939 int err = 0; 940 941 ops = chip->info->ops; 942 943 mv88e6xxx_reg_lock(chip); 944 /* Configure and force the link up if we know that the port may not 945 * automatically updated by the switch or if we are using fixed-link 946 * mode. 947 */ 948 if (!mv88e6xxx_port_ppu_updates(chip, port) || 949 mode == MLO_AN_FIXED) { 950 /* FIXME: for an automedia port, should we force the link 951 * down here - what if the link comes up due to "other" media 952 * while we're bringing the port up, how is the exclusivity 953 * handled in the Marvell hardware? E.g. port 2 on 88E6390 954 * shared between internal PHY and Serdes. 955 */ 956 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 957 duplex); 958 if (err) 959 goto error; 960 961 if (ops->port_set_speed_duplex) { 962 err = ops->port_set_speed_duplex(chip, port, 963 speed, duplex); 964 if (err && err != -EOPNOTSUPP) 965 goto error; 966 } 967 968 if (ops->port_sync_link) 969 err = ops->port_sync_link(chip, port, mode, true); 970 } 971 error: 972 mv88e6xxx_reg_unlock(chip); 973 974 if (err && err != -EOPNOTSUPP) 975 dev_err(ds->dev, 976 "p%d: failed to configure MAC link up\n", port); 977 } 978 979 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 980 { 981 if (!chip->info->ops->stats_snapshot) 982 return -EOPNOTSUPP; 983 984 return chip->info->ops->stats_snapshot(chip, port); 985 } 986 987 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 988 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 989 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 990 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 991 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 992 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 993 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 994 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 995 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 996 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 997 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 998 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 999 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 1000 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 1001 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 1002 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 1003 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 1004 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 1005 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 1006 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 1007 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 1008 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 1009 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 1010 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 1011 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 1012 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 1013 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 1014 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 1015 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 1016 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 1017 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 1018 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 1019 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 1020 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 1021 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 1022 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 1023 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 1024 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 1025 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 1026 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 1027 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 1028 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 1029 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 1030 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 1031 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 1032 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 1033 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 1034 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 1035 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 1036 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 1037 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 1038 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 1039 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 1040 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 1041 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 1042 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 1043 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 1044 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 1045 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 1046 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 1047 }; 1048 1049 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1050 struct mv88e6xxx_hw_stat *s, 1051 int port, u16 bank1_select, 1052 u16 histogram) 1053 { 1054 u32 low; 1055 u32 high = 0; 1056 u16 reg = 0; 1057 int err; 1058 u64 value; 1059 1060 switch (s->type) { 1061 case STATS_TYPE_PORT: 1062 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1063 if (err) 1064 return U64_MAX; 1065 1066 low = reg; 1067 if (s->size == 4) { 1068 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1069 if (err) 1070 return U64_MAX; 1071 low |= ((u32)reg) << 16; 1072 } 1073 break; 1074 case STATS_TYPE_BANK1: 1075 reg = bank1_select; 1076 fallthrough; 1077 case STATS_TYPE_BANK0: 1078 reg |= s->reg | histogram; 1079 mv88e6xxx_g1_stats_read(chip, reg, &low); 1080 if (s->size == 8) 1081 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1082 break; 1083 default: 1084 return U64_MAX; 1085 } 1086 value = (((u64)high) << 32) | low; 1087 return value; 1088 } 1089 1090 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1091 uint8_t *data, int types) 1092 { 1093 struct mv88e6xxx_hw_stat *stat; 1094 int i, j; 1095 1096 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1097 stat = &mv88e6xxx_hw_stats[i]; 1098 if (stat->type & types) { 1099 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1100 ETH_GSTRING_LEN); 1101 j++; 1102 } 1103 } 1104 1105 return j; 1106 } 1107 1108 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1109 uint8_t *data) 1110 { 1111 return mv88e6xxx_stats_get_strings(chip, data, 1112 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1113 } 1114 1115 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1116 uint8_t *data) 1117 { 1118 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1119 } 1120 1121 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1122 uint8_t *data) 1123 { 1124 return mv88e6xxx_stats_get_strings(chip, data, 1125 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1126 } 1127 1128 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1129 "atu_member_violation", 1130 "atu_miss_violation", 1131 "atu_full_violation", 1132 "vtu_member_violation", 1133 "vtu_miss_violation", 1134 }; 1135 1136 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1137 { 1138 unsigned int i; 1139 1140 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1141 strscpy(data + i * ETH_GSTRING_LEN, 1142 mv88e6xxx_atu_vtu_stats_strings[i], 1143 ETH_GSTRING_LEN); 1144 } 1145 1146 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1147 u32 stringset, uint8_t *data) 1148 { 1149 struct mv88e6xxx_chip *chip = ds->priv; 1150 int count = 0; 1151 1152 if (stringset != ETH_SS_STATS) 1153 return; 1154 1155 mv88e6xxx_reg_lock(chip); 1156 1157 if (chip->info->ops->stats_get_strings) 1158 count = chip->info->ops->stats_get_strings(chip, data); 1159 1160 if (chip->info->ops->serdes_get_strings) { 1161 data += count * ETH_GSTRING_LEN; 1162 count = chip->info->ops->serdes_get_strings(chip, port, data); 1163 } 1164 1165 data += count * ETH_GSTRING_LEN; 1166 mv88e6xxx_atu_vtu_get_strings(data); 1167 1168 mv88e6xxx_reg_unlock(chip); 1169 } 1170 1171 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1172 int types) 1173 { 1174 struct mv88e6xxx_hw_stat *stat; 1175 int i, j; 1176 1177 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1178 stat = &mv88e6xxx_hw_stats[i]; 1179 if (stat->type & types) 1180 j++; 1181 } 1182 return j; 1183 } 1184 1185 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1186 { 1187 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1188 STATS_TYPE_PORT); 1189 } 1190 1191 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1192 { 1193 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1194 } 1195 1196 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1197 { 1198 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1199 STATS_TYPE_BANK1); 1200 } 1201 1202 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1203 { 1204 struct mv88e6xxx_chip *chip = ds->priv; 1205 int serdes_count = 0; 1206 int count = 0; 1207 1208 if (sset != ETH_SS_STATS) 1209 return 0; 1210 1211 mv88e6xxx_reg_lock(chip); 1212 if (chip->info->ops->stats_get_sset_count) 1213 count = chip->info->ops->stats_get_sset_count(chip); 1214 if (count < 0) 1215 goto out; 1216 1217 if (chip->info->ops->serdes_get_sset_count) 1218 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1219 port); 1220 if (serdes_count < 0) { 1221 count = serdes_count; 1222 goto out; 1223 } 1224 count += serdes_count; 1225 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1226 1227 out: 1228 mv88e6xxx_reg_unlock(chip); 1229 1230 return count; 1231 } 1232 1233 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1234 uint64_t *data, int types, 1235 u16 bank1_select, u16 histogram) 1236 { 1237 struct mv88e6xxx_hw_stat *stat; 1238 int i, j; 1239 1240 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1241 stat = &mv88e6xxx_hw_stats[i]; 1242 if (stat->type & types) { 1243 mv88e6xxx_reg_lock(chip); 1244 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1245 bank1_select, 1246 histogram); 1247 mv88e6xxx_reg_unlock(chip); 1248 1249 j++; 1250 } 1251 } 1252 return j; 1253 } 1254 1255 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1256 uint64_t *data) 1257 { 1258 return mv88e6xxx_stats_get_stats(chip, port, data, 1259 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1260 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1261 } 1262 1263 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1264 uint64_t *data) 1265 { 1266 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1267 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1268 } 1269 1270 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1271 uint64_t *data) 1272 { 1273 return mv88e6xxx_stats_get_stats(chip, port, data, 1274 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1275 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1276 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1277 } 1278 1279 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1280 uint64_t *data) 1281 { 1282 return mv88e6xxx_stats_get_stats(chip, port, data, 1283 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1284 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1285 0); 1286 } 1287 1288 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1289 uint64_t *data) 1290 { 1291 *data++ = chip->ports[port].atu_member_violation; 1292 *data++ = chip->ports[port].atu_miss_violation; 1293 *data++ = chip->ports[port].atu_full_violation; 1294 *data++ = chip->ports[port].vtu_member_violation; 1295 *data++ = chip->ports[port].vtu_miss_violation; 1296 } 1297 1298 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1299 uint64_t *data) 1300 { 1301 int count = 0; 1302 1303 if (chip->info->ops->stats_get_stats) 1304 count = chip->info->ops->stats_get_stats(chip, port, data); 1305 1306 mv88e6xxx_reg_lock(chip); 1307 if (chip->info->ops->serdes_get_stats) { 1308 data += count; 1309 count = chip->info->ops->serdes_get_stats(chip, port, data); 1310 } 1311 data += count; 1312 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1313 mv88e6xxx_reg_unlock(chip); 1314 } 1315 1316 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1317 uint64_t *data) 1318 { 1319 struct mv88e6xxx_chip *chip = ds->priv; 1320 int ret; 1321 1322 mv88e6xxx_reg_lock(chip); 1323 1324 ret = mv88e6xxx_stats_snapshot(chip, port); 1325 mv88e6xxx_reg_unlock(chip); 1326 1327 if (ret < 0) 1328 return; 1329 1330 mv88e6xxx_get_stats(chip, port, data); 1331 1332 } 1333 1334 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1335 { 1336 struct mv88e6xxx_chip *chip = ds->priv; 1337 int len; 1338 1339 len = 32 * sizeof(u16); 1340 if (chip->info->ops->serdes_get_regs_len) 1341 len += chip->info->ops->serdes_get_regs_len(chip, port); 1342 1343 return len; 1344 } 1345 1346 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1347 struct ethtool_regs *regs, void *_p) 1348 { 1349 struct mv88e6xxx_chip *chip = ds->priv; 1350 int err; 1351 u16 reg; 1352 u16 *p = _p; 1353 int i; 1354 1355 regs->version = chip->info->prod_num; 1356 1357 memset(p, 0xff, 32 * sizeof(u16)); 1358 1359 mv88e6xxx_reg_lock(chip); 1360 1361 for (i = 0; i < 32; i++) { 1362 1363 err = mv88e6xxx_port_read(chip, port, i, ®); 1364 if (!err) 1365 p[i] = reg; 1366 } 1367 1368 if (chip->info->ops->serdes_get_regs) 1369 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1370 1371 mv88e6xxx_reg_unlock(chip); 1372 } 1373 1374 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1375 struct ethtool_eee *e) 1376 { 1377 /* Nothing to do on the port's MAC */ 1378 return 0; 1379 } 1380 1381 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1382 struct ethtool_eee *e) 1383 { 1384 /* Nothing to do on the port's MAC */ 1385 return 0; 1386 } 1387 1388 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1389 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1390 { 1391 struct dsa_switch *ds = chip->ds; 1392 struct dsa_switch_tree *dst = ds->dst; 1393 struct dsa_port *dp, *other_dp; 1394 bool found = false; 1395 u16 pvlan; 1396 1397 /* dev is a physical switch */ 1398 if (dev <= dst->last_switch) { 1399 list_for_each_entry(dp, &dst->ports, list) { 1400 if (dp->ds->index == dev && dp->index == port) { 1401 /* dp might be a DSA link or a user port, so it 1402 * might or might not have a bridge. 1403 * Use the "found" variable for both cases. 1404 */ 1405 found = true; 1406 break; 1407 } 1408 } 1409 /* dev is a virtual bridge */ 1410 } else { 1411 list_for_each_entry(dp, &dst->ports, list) { 1412 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1413 1414 if (!bridge_num) 1415 continue; 1416 1417 if (bridge_num + dst->last_switch != dev) 1418 continue; 1419 1420 found = true; 1421 break; 1422 } 1423 } 1424 1425 /* Prevent frames from unknown switch or virtual bridge */ 1426 if (!found) 1427 return 0; 1428 1429 /* Frames from DSA links and CPU ports can egress any local port */ 1430 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1431 return mv88e6xxx_port_mask(chip); 1432 1433 pvlan = 0; 1434 1435 /* Frames from standalone user ports can only egress on the 1436 * upstream port. 1437 */ 1438 if (!dsa_port_bridge_dev_get(dp)) 1439 return BIT(dsa_switch_upstream_port(ds)); 1440 1441 /* Frames from bridged user ports can egress any local DSA 1442 * links and CPU ports, as well as any local member of their 1443 * bridge group. 1444 */ 1445 dsa_switch_for_each_port(other_dp, ds) 1446 if (other_dp->type == DSA_PORT_TYPE_CPU || 1447 other_dp->type == DSA_PORT_TYPE_DSA || 1448 dsa_port_bridge_same(dp, other_dp)) 1449 pvlan |= BIT(other_dp->index); 1450 1451 return pvlan; 1452 } 1453 1454 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1455 { 1456 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1457 1458 /* prevent frames from going back out of the port they came in on */ 1459 output_ports &= ~BIT(port); 1460 1461 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1462 } 1463 1464 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1465 u8 state) 1466 { 1467 struct mv88e6xxx_chip *chip = ds->priv; 1468 int err; 1469 1470 mv88e6xxx_reg_lock(chip); 1471 err = mv88e6xxx_port_set_state(chip, port, state); 1472 mv88e6xxx_reg_unlock(chip); 1473 1474 if (err) 1475 dev_err(ds->dev, "p%d: failed to update state\n", port); 1476 } 1477 1478 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1479 { 1480 int err; 1481 1482 if (chip->info->ops->ieee_pri_map) { 1483 err = chip->info->ops->ieee_pri_map(chip); 1484 if (err) 1485 return err; 1486 } 1487 1488 if (chip->info->ops->ip_pri_map) { 1489 err = chip->info->ops->ip_pri_map(chip); 1490 if (err) 1491 return err; 1492 } 1493 1494 return 0; 1495 } 1496 1497 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1498 { 1499 struct dsa_switch *ds = chip->ds; 1500 int target, port; 1501 int err; 1502 1503 if (!chip->info->global2_addr) 1504 return 0; 1505 1506 /* Initialize the routing port to the 32 possible target devices */ 1507 for (target = 0; target < 32; target++) { 1508 port = dsa_routing_port(ds, target); 1509 if (port == ds->num_ports) 1510 port = 0x1f; 1511 1512 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1513 if (err) 1514 return err; 1515 } 1516 1517 if (chip->info->ops->set_cascade_port) { 1518 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1519 err = chip->info->ops->set_cascade_port(chip, port); 1520 if (err) 1521 return err; 1522 } 1523 1524 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1525 if (err) 1526 return err; 1527 1528 return 0; 1529 } 1530 1531 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1532 { 1533 /* Clear all trunk masks and mapping */ 1534 if (chip->info->global2_addr) 1535 return mv88e6xxx_g2_trunk_clear(chip); 1536 1537 return 0; 1538 } 1539 1540 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1541 { 1542 if (chip->info->ops->rmu_disable) 1543 return chip->info->ops->rmu_disable(chip); 1544 1545 return 0; 1546 } 1547 1548 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1549 { 1550 if (chip->info->ops->pot_clear) 1551 return chip->info->ops->pot_clear(chip); 1552 1553 return 0; 1554 } 1555 1556 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1557 { 1558 if (chip->info->ops->mgmt_rsvd2cpu) 1559 return chip->info->ops->mgmt_rsvd2cpu(chip); 1560 1561 return 0; 1562 } 1563 1564 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1565 { 1566 int err; 1567 1568 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1569 if (err) 1570 return err; 1571 1572 /* The chips that have a "learn2all" bit in Global1, ATU 1573 * Control are precisely those whose port registers have a 1574 * Message Port bit in Port Control 1 and hence implement 1575 * ->port_setup_message_port. 1576 */ 1577 if (chip->info->ops->port_setup_message_port) { 1578 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1579 if (err) 1580 return err; 1581 } 1582 1583 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1584 } 1585 1586 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1587 { 1588 int port; 1589 int err; 1590 1591 if (!chip->info->ops->irl_init_all) 1592 return 0; 1593 1594 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1595 /* Disable ingress rate limiting by resetting all per port 1596 * ingress rate limit resources to their initial state. 1597 */ 1598 err = chip->info->ops->irl_init_all(chip, port); 1599 if (err) 1600 return err; 1601 } 1602 1603 return 0; 1604 } 1605 1606 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1607 { 1608 if (chip->info->ops->set_switch_mac) { 1609 u8 addr[ETH_ALEN]; 1610 1611 eth_random_addr(addr); 1612 1613 return chip->info->ops->set_switch_mac(chip, addr); 1614 } 1615 1616 return 0; 1617 } 1618 1619 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1620 { 1621 struct dsa_switch_tree *dst = chip->ds->dst; 1622 struct dsa_switch *ds; 1623 struct dsa_port *dp; 1624 u16 pvlan = 0; 1625 1626 if (!mv88e6xxx_has_pvt(chip)) 1627 return 0; 1628 1629 /* Skip the local source device, which uses in-chip port VLAN */ 1630 if (dev != chip->ds->index) { 1631 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1632 1633 ds = dsa_switch_find(dst->index, dev); 1634 dp = ds ? dsa_to_port(ds, port) : NULL; 1635 if (dp && dp->lag) { 1636 /* As the PVT is used to limit flooding of 1637 * FORWARD frames, which use the LAG ID as the 1638 * source port, we must translate dev/port to 1639 * the special "LAG device" in the PVT, using 1640 * the LAG ID (one-based) as the port number 1641 * (zero-based). 1642 */ 1643 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1644 port = dsa_port_lag_id_get(dp) - 1; 1645 } 1646 } 1647 1648 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1649 } 1650 1651 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1652 { 1653 int dev, port; 1654 int err; 1655 1656 if (!mv88e6xxx_has_pvt(chip)) 1657 return 0; 1658 1659 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1660 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1661 */ 1662 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1663 if (err) 1664 return err; 1665 1666 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1667 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1668 err = mv88e6xxx_pvt_map(chip, dev, port); 1669 if (err) 1670 return err; 1671 } 1672 } 1673 1674 return 0; 1675 } 1676 1677 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1678 u16 fid) 1679 { 1680 if (dsa_to_port(chip->ds, port)->lag) 1681 /* Hardware is incapable of fast-aging a LAG through a 1682 * regular ATU move operation. Until we have something 1683 * more fancy in place this is a no-op. 1684 */ 1685 return -EOPNOTSUPP; 1686 1687 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1688 } 1689 1690 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1691 { 1692 struct mv88e6xxx_chip *chip = ds->priv; 1693 int err; 1694 1695 mv88e6xxx_reg_lock(chip); 1696 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1697 mv88e6xxx_reg_unlock(chip); 1698 1699 if (err) 1700 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1701 port, err); 1702 } 1703 1704 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1705 { 1706 if (!mv88e6xxx_max_vid(chip)) 1707 return 0; 1708 1709 return mv88e6xxx_g1_vtu_flush(chip); 1710 } 1711 1712 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1713 struct mv88e6xxx_vtu_entry *entry) 1714 { 1715 int err; 1716 1717 if (!chip->info->ops->vtu_getnext) 1718 return -EOPNOTSUPP; 1719 1720 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1721 entry->valid = false; 1722 1723 err = chip->info->ops->vtu_getnext(chip, entry); 1724 1725 if (entry->vid != vid) 1726 entry->valid = false; 1727 1728 return err; 1729 } 1730 1731 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1732 int (*cb)(struct mv88e6xxx_chip *chip, 1733 const struct mv88e6xxx_vtu_entry *entry, 1734 void *priv), 1735 void *priv) 1736 { 1737 struct mv88e6xxx_vtu_entry entry = { 1738 .vid = mv88e6xxx_max_vid(chip), 1739 .valid = false, 1740 }; 1741 int err; 1742 1743 if (!chip->info->ops->vtu_getnext) 1744 return -EOPNOTSUPP; 1745 1746 do { 1747 err = chip->info->ops->vtu_getnext(chip, &entry); 1748 if (err) 1749 return err; 1750 1751 if (!entry.valid) 1752 break; 1753 1754 err = cb(chip, &entry, priv); 1755 if (err) 1756 return err; 1757 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1758 1759 return 0; 1760 } 1761 1762 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1763 struct mv88e6xxx_vtu_entry *entry) 1764 { 1765 if (!chip->info->ops->vtu_loadpurge) 1766 return -EOPNOTSUPP; 1767 1768 return chip->info->ops->vtu_loadpurge(chip, entry); 1769 } 1770 1771 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1772 const struct mv88e6xxx_vtu_entry *entry, 1773 void *_fid_bitmap) 1774 { 1775 unsigned long *fid_bitmap = _fid_bitmap; 1776 1777 set_bit(entry->fid, fid_bitmap); 1778 return 0; 1779 } 1780 1781 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1782 { 1783 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1784 1785 /* Every FID has an associated VID, so walking the VTU 1786 * will discover the full set of FIDs in use. 1787 */ 1788 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1789 } 1790 1791 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1792 { 1793 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1794 int err; 1795 1796 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1797 if (err) 1798 return err; 1799 1800 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID); 1801 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1802 return -ENOSPC; 1803 1804 /* Clear the database */ 1805 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1806 } 1807 1808 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1809 struct mv88e6xxx_stu_entry *entry) 1810 { 1811 if (!chip->info->ops->stu_loadpurge) 1812 return -EOPNOTSUPP; 1813 1814 return chip->info->ops->stu_loadpurge(chip, entry); 1815 } 1816 1817 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1818 { 1819 struct mv88e6xxx_stu_entry stu = { 1820 .valid = true, 1821 .sid = 0 1822 }; 1823 1824 if (!mv88e6xxx_has_stu(chip)) 1825 return 0; 1826 1827 /* Make sure that SID 0 is always valid. This is used by VTU 1828 * entries that do not make use of the STU, e.g. when creating 1829 * a VLAN upper on a port that is also part of a VLAN 1830 * filtering bridge. 1831 */ 1832 return mv88e6xxx_stu_loadpurge(chip, &stu); 1833 } 1834 1835 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1836 { 1837 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1838 struct mv88e6xxx_mst *mst; 1839 1840 __set_bit(0, busy); 1841 1842 list_for_each_entry(mst, &chip->msts, node) 1843 __set_bit(mst->stu.sid, busy); 1844 1845 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1846 1847 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1848 } 1849 1850 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1851 { 1852 struct mv88e6xxx_mst *mst, *tmp; 1853 int err; 1854 1855 if (!sid) 1856 return 0; 1857 1858 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1859 if (mst->stu.sid != sid) 1860 continue; 1861 1862 if (!refcount_dec_and_test(&mst->refcnt)) 1863 return 0; 1864 1865 mst->stu.valid = false; 1866 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1867 if (err) { 1868 refcount_set(&mst->refcnt, 1); 1869 return err; 1870 } 1871 1872 list_del(&mst->node); 1873 kfree(mst); 1874 return 0; 1875 } 1876 1877 return -ENOENT; 1878 } 1879 1880 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1881 u16 msti, u8 *sid) 1882 { 1883 struct mv88e6xxx_mst *mst; 1884 int err, i; 1885 1886 if (!mv88e6xxx_has_stu(chip)) { 1887 err = -EOPNOTSUPP; 1888 goto err; 1889 } 1890 1891 if (!msti) { 1892 *sid = 0; 1893 return 0; 1894 } 1895 1896 list_for_each_entry(mst, &chip->msts, node) { 1897 if (mst->br == br && mst->msti == msti) { 1898 refcount_inc(&mst->refcnt); 1899 *sid = mst->stu.sid; 1900 return 0; 1901 } 1902 } 1903 1904 err = mv88e6xxx_sid_get(chip, sid); 1905 if (err) 1906 goto err; 1907 1908 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 1909 if (!mst) { 1910 err = -ENOMEM; 1911 goto err; 1912 } 1913 1914 INIT_LIST_HEAD(&mst->node); 1915 refcount_set(&mst->refcnt, 1); 1916 mst->br = br; 1917 mst->msti = msti; 1918 mst->stu.valid = true; 1919 mst->stu.sid = *sid; 1920 1921 /* The bridge starts out all ports in the disabled state. But 1922 * a STU state of disabled means to go by the port-global 1923 * state. So we set all user port's initial state to blocking, 1924 * to match the bridge's behavior. 1925 */ 1926 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 1927 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 1928 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 1929 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 1930 1931 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1932 if (err) 1933 goto err_free; 1934 1935 list_add_tail(&mst->node, &chip->msts); 1936 return 0; 1937 1938 err_free: 1939 kfree(mst); 1940 err: 1941 return err; 1942 } 1943 1944 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 1945 const struct switchdev_mst_state *st) 1946 { 1947 struct dsa_port *dp = dsa_to_port(ds, port); 1948 struct mv88e6xxx_chip *chip = ds->priv; 1949 struct mv88e6xxx_mst *mst; 1950 u8 state; 1951 int err; 1952 1953 if (!mv88e6xxx_has_stu(chip)) 1954 return -EOPNOTSUPP; 1955 1956 switch (st->state) { 1957 case BR_STATE_DISABLED: 1958 case BR_STATE_BLOCKING: 1959 case BR_STATE_LISTENING: 1960 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 1961 break; 1962 case BR_STATE_LEARNING: 1963 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 1964 break; 1965 case BR_STATE_FORWARDING: 1966 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1967 break; 1968 default: 1969 return -EINVAL; 1970 } 1971 1972 list_for_each_entry(mst, &chip->msts, node) { 1973 if (mst->br == dsa_port_bridge_dev_get(dp) && 1974 mst->msti == st->msti) { 1975 if (mst->stu.state[port] == state) 1976 return 0; 1977 1978 mst->stu.state[port] = state; 1979 mv88e6xxx_reg_lock(chip); 1980 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1981 mv88e6xxx_reg_unlock(chip); 1982 return err; 1983 } 1984 } 1985 1986 return -ENOENT; 1987 } 1988 1989 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1990 u16 vid) 1991 { 1992 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1993 struct mv88e6xxx_chip *chip = ds->priv; 1994 struct mv88e6xxx_vtu_entry vlan; 1995 int err; 1996 1997 /* DSA and CPU ports have to be members of multiple vlans */ 1998 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 1999 return 0; 2000 2001 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2002 if (err) 2003 return err; 2004 2005 if (!vlan.valid) 2006 return 0; 2007 2008 dsa_switch_for_each_user_port(other_dp, ds) { 2009 struct net_device *other_br; 2010 2011 if (vlan.member[other_dp->index] == 2012 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2013 continue; 2014 2015 if (dsa_port_bridge_same(dp, other_dp)) 2016 break; /* same bridge, check next VLAN */ 2017 2018 other_br = dsa_port_bridge_dev_get(other_dp); 2019 if (!other_br) 2020 continue; 2021 2022 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2023 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2024 return -EOPNOTSUPP; 2025 } 2026 2027 return 0; 2028 } 2029 2030 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2031 { 2032 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2033 struct net_device *br = dsa_port_bridge_dev_get(dp); 2034 struct mv88e6xxx_port *p = &chip->ports[port]; 2035 u16 pvid = MV88E6XXX_VID_STANDALONE; 2036 bool drop_untagged = false; 2037 int err; 2038 2039 if (br) { 2040 if (br_vlan_enabled(br)) { 2041 pvid = p->bridge_pvid.vid; 2042 drop_untagged = !p->bridge_pvid.valid; 2043 } else { 2044 pvid = MV88E6XXX_VID_BRIDGED; 2045 } 2046 } 2047 2048 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2049 if (err) 2050 return err; 2051 2052 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2053 } 2054 2055 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2056 bool vlan_filtering, 2057 struct netlink_ext_ack *extack) 2058 { 2059 struct mv88e6xxx_chip *chip = ds->priv; 2060 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2061 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2062 int err; 2063 2064 if (!mv88e6xxx_max_vid(chip)) 2065 return -EOPNOTSUPP; 2066 2067 mv88e6xxx_reg_lock(chip); 2068 2069 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2070 if (err) 2071 goto unlock; 2072 2073 err = mv88e6xxx_port_commit_pvid(chip, port); 2074 if (err) 2075 goto unlock; 2076 2077 unlock: 2078 mv88e6xxx_reg_unlock(chip); 2079 2080 return err; 2081 } 2082 2083 static int 2084 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2085 const struct switchdev_obj_port_vlan *vlan) 2086 { 2087 struct mv88e6xxx_chip *chip = ds->priv; 2088 int err; 2089 2090 if (!mv88e6xxx_max_vid(chip)) 2091 return -EOPNOTSUPP; 2092 2093 /* If the requested port doesn't belong to the same bridge as the VLAN 2094 * members, do not support it (yet) and fallback to software VLAN. 2095 */ 2096 mv88e6xxx_reg_lock(chip); 2097 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2098 mv88e6xxx_reg_unlock(chip); 2099 2100 return err; 2101 } 2102 2103 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2104 const unsigned char *addr, u16 vid, 2105 u8 state) 2106 { 2107 struct mv88e6xxx_atu_entry entry; 2108 struct mv88e6xxx_vtu_entry vlan; 2109 u16 fid; 2110 int err; 2111 2112 /* Ports have two private address databases: one for when the port is 2113 * standalone and one for when the port is under a bridge and the 2114 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2115 * address database to remain 100% empty, so we never load an ATU entry 2116 * into a standalone port's database. Therefore, translate the null 2117 * VLAN ID into the port's database used for VLAN-unaware bridging. 2118 */ 2119 if (vid == 0) { 2120 fid = MV88E6XXX_FID_BRIDGED; 2121 } else { 2122 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2123 if (err) 2124 return err; 2125 2126 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2127 if (!vlan.valid) 2128 return -EOPNOTSUPP; 2129 2130 fid = vlan.fid; 2131 } 2132 2133 entry.state = 0; 2134 ether_addr_copy(entry.mac, addr); 2135 eth_addr_dec(entry.mac); 2136 2137 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2138 if (err) 2139 return err; 2140 2141 /* Initialize a fresh ATU entry if it isn't found */ 2142 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2143 memset(&entry, 0, sizeof(entry)); 2144 ether_addr_copy(entry.mac, addr); 2145 } 2146 2147 /* Purge the ATU entry only if no port is using it anymore */ 2148 if (!state) { 2149 entry.portvec &= ~BIT(port); 2150 if (!entry.portvec) 2151 entry.state = 0; 2152 } else { 2153 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2154 entry.portvec = BIT(port); 2155 else 2156 entry.portvec |= BIT(port); 2157 2158 entry.state = state; 2159 } 2160 2161 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2162 } 2163 2164 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2165 const struct mv88e6xxx_policy *policy) 2166 { 2167 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2168 enum mv88e6xxx_policy_action action = policy->action; 2169 const u8 *addr = policy->addr; 2170 u16 vid = policy->vid; 2171 u8 state; 2172 int err; 2173 int id; 2174 2175 if (!chip->info->ops->port_set_policy) 2176 return -EOPNOTSUPP; 2177 2178 switch (mapping) { 2179 case MV88E6XXX_POLICY_MAPPING_DA: 2180 case MV88E6XXX_POLICY_MAPPING_SA: 2181 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2182 state = 0; /* Dissociate the port and address */ 2183 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2184 is_multicast_ether_addr(addr)) 2185 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2186 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2187 is_unicast_ether_addr(addr)) 2188 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2189 else 2190 return -EOPNOTSUPP; 2191 2192 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2193 state); 2194 if (err) 2195 return err; 2196 break; 2197 default: 2198 return -EOPNOTSUPP; 2199 } 2200 2201 /* Skip the port's policy clearing if the mapping is still in use */ 2202 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2203 idr_for_each_entry(&chip->policies, policy, id) 2204 if (policy->port == port && 2205 policy->mapping == mapping && 2206 policy->action != action) 2207 return 0; 2208 2209 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2210 } 2211 2212 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2213 struct ethtool_rx_flow_spec *fs) 2214 { 2215 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2216 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2217 enum mv88e6xxx_policy_mapping mapping; 2218 enum mv88e6xxx_policy_action action; 2219 struct mv88e6xxx_policy *policy; 2220 u16 vid = 0; 2221 u8 *addr; 2222 int err; 2223 int id; 2224 2225 if (fs->location != RX_CLS_LOC_ANY) 2226 return -EINVAL; 2227 2228 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2229 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2230 else 2231 return -EOPNOTSUPP; 2232 2233 switch (fs->flow_type & ~FLOW_EXT) { 2234 case ETHER_FLOW: 2235 if (!is_zero_ether_addr(mac_mask->h_dest) && 2236 is_zero_ether_addr(mac_mask->h_source)) { 2237 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2238 addr = mac_entry->h_dest; 2239 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2240 !is_zero_ether_addr(mac_mask->h_source)) { 2241 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2242 addr = mac_entry->h_source; 2243 } else { 2244 /* Cannot support DA and SA mapping in the same rule */ 2245 return -EOPNOTSUPP; 2246 } 2247 break; 2248 default: 2249 return -EOPNOTSUPP; 2250 } 2251 2252 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2253 if (fs->m_ext.vlan_tci != htons(0xffff)) 2254 return -EOPNOTSUPP; 2255 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2256 } 2257 2258 idr_for_each_entry(&chip->policies, policy, id) { 2259 if (policy->port == port && policy->mapping == mapping && 2260 policy->action == action && policy->vid == vid && 2261 ether_addr_equal(policy->addr, addr)) 2262 return -EEXIST; 2263 } 2264 2265 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2266 if (!policy) 2267 return -ENOMEM; 2268 2269 fs->location = 0; 2270 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2271 GFP_KERNEL); 2272 if (err) { 2273 devm_kfree(chip->dev, policy); 2274 return err; 2275 } 2276 2277 memcpy(&policy->fs, fs, sizeof(*fs)); 2278 ether_addr_copy(policy->addr, addr); 2279 policy->mapping = mapping; 2280 policy->action = action; 2281 policy->port = port; 2282 policy->vid = vid; 2283 2284 err = mv88e6xxx_policy_apply(chip, port, policy); 2285 if (err) { 2286 idr_remove(&chip->policies, fs->location); 2287 devm_kfree(chip->dev, policy); 2288 return err; 2289 } 2290 2291 return 0; 2292 } 2293 2294 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2295 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2296 { 2297 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2298 struct mv88e6xxx_chip *chip = ds->priv; 2299 struct mv88e6xxx_policy *policy; 2300 int err; 2301 int id; 2302 2303 mv88e6xxx_reg_lock(chip); 2304 2305 switch (rxnfc->cmd) { 2306 case ETHTOOL_GRXCLSRLCNT: 2307 rxnfc->data = 0; 2308 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2309 rxnfc->rule_cnt = 0; 2310 idr_for_each_entry(&chip->policies, policy, id) 2311 if (policy->port == port) 2312 rxnfc->rule_cnt++; 2313 err = 0; 2314 break; 2315 case ETHTOOL_GRXCLSRULE: 2316 err = -ENOENT; 2317 policy = idr_find(&chip->policies, fs->location); 2318 if (policy) { 2319 memcpy(fs, &policy->fs, sizeof(*fs)); 2320 err = 0; 2321 } 2322 break; 2323 case ETHTOOL_GRXCLSRLALL: 2324 rxnfc->data = 0; 2325 rxnfc->rule_cnt = 0; 2326 idr_for_each_entry(&chip->policies, policy, id) 2327 if (policy->port == port) 2328 rule_locs[rxnfc->rule_cnt++] = id; 2329 err = 0; 2330 break; 2331 default: 2332 err = -EOPNOTSUPP; 2333 break; 2334 } 2335 2336 mv88e6xxx_reg_unlock(chip); 2337 2338 return err; 2339 } 2340 2341 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2342 struct ethtool_rxnfc *rxnfc) 2343 { 2344 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2345 struct mv88e6xxx_chip *chip = ds->priv; 2346 struct mv88e6xxx_policy *policy; 2347 int err; 2348 2349 mv88e6xxx_reg_lock(chip); 2350 2351 switch (rxnfc->cmd) { 2352 case ETHTOOL_SRXCLSRLINS: 2353 err = mv88e6xxx_policy_insert(chip, port, fs); 2354 break; 2355 case ETHTOOL_SRXCLSRLDEL: 2356 err = -ENOENT; 2357 policy = idr_remove(&chip->policies, fs->location); 2358 if (policy) { 2359 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2360 err = mv88e6xxx_policy_apply(chip, port, policy); 2361 devm_kfree(chip->dev, policy); 2362 } 2363 break; 2364 default: 2365 err = -EOPNOTSUPP; 2366 break; 2367 } 2368 2369 mv88e6xxx_reg_unlock(chip); 2370 2371 return err; 2372 } 2373 2374 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2375 u16 vid) 2376 { 2377 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2378 u8 broadcast[ETH_ALEN]; 2379 2380 eth_broadcast_addr(broadcast); 2381 2382 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2383 } 2384 2385 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2386 { 2387 int port; 2388 int err; 2389 2390 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2391 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2392 struct net_device *brport; 2393 2394 if (dsa_is_unused_port(chip->ds, port)) 2395 continue; 2396 2397 brport = dsa_port_to_bridge_port(dp); 2398 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2399 /* Skip bridged user ports where broadcast 2400 * flooding is disabled. 2401 */ 2402 continue; 2403 2404 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2405 if (err) 2406 return err; 2407 } 2408 2409 return 0; 2410 } 2411 2412 struct mv88e6xxx_port_broadcast_sync_ctx { 2413 int port; 2414 bool flood; 2415 }; 2416 2417 static int 2418 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2419 const struct mv88e6xxx_vtu_entry *vlan, 2420 void *_ctx) 2421 { 2422 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2423 u8 broadcast[ETH_ALEN]; 2424 u8 state; 2425 2426 if (ctx->flood) 2427 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2428 else 2429 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2430 2431 eth_broadcast_addr(broadcast); 2432 2433 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2434 vlan->vid, state); 2435 } 2436 2437 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2438 bool flood) 2439 { 2440 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2441 .port = port, 2442 .flood = flood, 2443 }; 2444 struct mv88e6xxx_vtu_entry vid0 = { 2445 .vid = 0, 2446 }; 2447 int err; 2448 2449 /* Update the port's private database... */ 2450 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2451 if (err) 2452 return err; 2453 2454 /* ...and the database for all VLANs. */ 2455 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2456 &ctx); 2457 } 2458 2459 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2460 u16 vid, u8 member, bool warn) 2461 { 2462 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2463 struct mv88e6xxx_vtu_entry vlan; 2464 int i, err; 2465 2466 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2467 if (err) 2468 return err; 2469 2470 if (!vlan.valid) { 2471 memset(&vlan, 0, sizeof(vlan)); 2472 2473 if (vid == MV88E6XXX_VID_STANDALONE) 2474 vlan.policy = true; 2475 2476 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2477 if (err) 2478 return err; 2479 2480 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2481 if (i == port) 2482 vlan.member[i] = member; 2483 else 2484 vlan.member[i] = non_member; 2485 2486 vlan.vid = vid; 2487 vlan.valid = true; 2488 2489 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2490 if (err) 2491 return err; 2492 2493 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2494 if (err) 2495 return err; 2496 } else if (vlan.member[port] != member) { 2497 vlan.member[port] = member; 2498 2499 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2500 if (err) 2501 return err; 2502 } else if (warn) { 2503 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2504 port, vid); 2505 } 2506 2507 return 0; 2508 } 2509 2510 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2511 const struct switchdev_obj_port_vlan *vlan, 2512 struct netlink_ext_ack *extack) 2513 { 2514 struct mv88e6xxx_chip *chip = ds->priv; 2515 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2516 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2517 struct mv88e6xxx_port *p = &chip->ports[port]; 2518 bool warn; 2519 u8 member; 2520 int err; 2521 2522 if (!vlan->vid) 2523 return 0; 2524 2525 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2526 if (err) 2527 return err; 2528 2529 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2530 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2531 else if (untagged) 2532 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2533 else 2534 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2535 2536 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2537 * and then the CPU port. Do not warn for duplicates for the CPU port. 2538 */ 2539 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2540 2541 mv88e6xxx_reg_lock(chip); 2542 2543 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2544 if (err) { 2545 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2546 vlan->vid, untagged ? 'u' : 't'); 2547 goto out; 2548 } 2549 2550 if (pvid) { 2551 p->bridge_pvid.vid = vlan->vid; 2552 p->bridge_pvid.valid = true; 2553 2554 err = mv88e6xxx_port_commit_pvid(chip, port); 2555 if (err) 2556 goto out; 2557 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2558 /* The old pvid was reinstalled as a non-pvid VLAN */ 2559 p->bridge_pvid.valid = false; 2560 2561 err = mv88e6xxx_port_commit_pvid(chip, port); 2562 if (err) 2563 goto out; 2564 } 2565 2566 out: 2567 mv88e6xxx_reg_unlock(chip); 2568 2569 return err; 2570 } 2571 2572 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2573 int port, u16 vid) 2574 { 2575 struct mv88e6xxx_vtu_entry vlan; 2576 int i, err; 2577 2578 if (!vid) 2579 return 0; 2580 2581 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2582 if (err) 2583 return err; 2584 2585 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2586 * tell switchdev that this VLAN is likely handled in software. 2587 */ 2588 if (!vlan.valid || 2589 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2590 return -EOPNOTSUPP; 2591 2592 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2593 2594 /* keep the VLAN unless all ports are excluded */ 2595 vlan.valid = false; 2596 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2597 if (vlan.member[i] != 2598 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2599 vlan.valid = true; 2600 break; 2601 } 2602 } 2603 2604 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2605 if (err) 2606 return err; 2607 2608 if (!vlan.valid) { 2609 err = mv88e6xxx_mst_put(chip, vlan.sid); 2610 if (err) 2611 return err; 2612 } 2613 2614 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2615 } 2616 2617 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2618 const struct switchdev_obj_port_vlan *vlan) 2619 { 2620 struct mv88e6xxx_chip *chip = ds->priv; 2621 struct mv88e6xxx_port *p = &chip->ports[port]; 2622 int err = 0; 2623 u16 pvid; 2624 2625 if (!mv88e6xxx_max_vid(chip)) 2626 return -EOPNOTSUPP; 2627 2628 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2629 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2630 * switchdev workqueue to ensure that all FDB entries are deleted 2631 * before we remove the VLAN. 2632 */ 2633 dsa_flush_workqueue(); 2634 2635 mv88e6xxx_reg_lock(chip); 2636 2637 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2638 if (err) 2639 goto unlock; 2640 2641 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2642 if (err) 2643 goto unlock; 2644 2645 if (vlan->vid == pvid) { 2646 p->bridge_pvid.valid = false; 2647 2648 err = mv88e6xxx_port_commit_pvid(chip, port); 2649 if (err) 2650 goto unlock; 2651 } 2652 2653 unlock: 2654 mv88e6xxx_reg_unlock(chip); 2655 2656 return err; 2657 } 2658 2659 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2660 { 2661 struct mv88e6xxx_chip *chip = ds->priv; 2662 struct mv88e6xxx_vtu_entry vlan; 2663 int err; 2664 2665 mv88e6xxx_reg_lock(chip); 2666 2667 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2668 if (err) 2669 goto unlock; 2670 2671 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2672 2673 unlock: 2674 mv88e6xxx_reg_unlock(chip); 2675 2676 return err; 2677 } 2678 2679 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2680 struct dsa_bridge bridge, 2681 const struct switchdev_vlan_msti *msti) 2682 { 2683 struct mv88e6xxx_chip *chip = ds->priv; 2684 struct mv88e6xxx_vtu_entry vlan; 2685 u8 old_sid, new_sid; 2686 int err; 2687 2688 if (!mv88e6xxx_has_stu(chip)) 2689 return -EOPNOTSUPP; 2690 2691 mv88e6xxx_reg_lock(chip); 2692 2693 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2694 if (err) 2695 goto unlock; 2696 2697 if (!vlan.valid) { 2698 err = -EINVAL; 2699 goto unlock; 2700 } 2701 2702 old_sid = vlan.sid; 2703 2704 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2705 if (err) 2706 goto unlock; 2707 2708 if (new_sid != old_sid) { 2709 vlan.sid = new_sid; 2710 2711 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2712 if (err) { 2713 mv88e6xxx_mst_put(chip, new_sid); 2714 goto unlock; 2715 } 2716 } 2717 2718 err = mv88e6xxx_mst_put(chip, old_sid); 2719 2720 unlock: 2721 mv88e6xxx_reg_unlock(chip); 2722 return err; 2723 } 2724 2725 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2726 const unsigned char *addr, u16 vid, 2727 struct dsa_db db) 2728 { 2729 struct mv88e6xxx_chip *chip = ds->priv; 2730 int err; 2731 2732 mv88e6xxx_reg_lock(chip); 2733 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2734 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2735 mv88e6xxx_reg_unlock(chip); 2736 2737 return err; 2738 } 2739 2740 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2741 const unsigned char *addr, u16 vid, 2742 struct dsa_db db) 2743 { 2744 struct mv88e6xxx_chip *chip = ds->priv; 2745 int err; 2746 2747 mv88e6xxx_reg_lock(chip); 2748 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2749 mv88e6xxx_reg_unlock(chip); 2750 2751 return err; 2752 } 2753 2754 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2755 u16 fid, u16 vid, int port, 2756 dsa_fdb_dump_cb_t *cb, void *data) 2757 { 2758 struct mv88e6xxx_atu_entry addr; 2759 bool is_static; 2760 int err; 2761 2762 addr.state = 0; 2763 eth_broadcast_addr(addr.mac); 2764 2765 do { 2766 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2767 if (err) 2768 return err; 2769 2770 if (!addr.state) 2771 break; 2772 2773 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2774 continue; 2775 2776 if (!is_unicast_ether_addr(addr.mac)) 2777 continue; 2778 2779 is_static = (addr.state == 2780 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2781 err = cb(addr.mac, vid, is_static, data); 2782 if (err) 2783 return err; 2784 } while (!is_broadcast_ether_addr(addr.mac)); 2785 2786 return err; 2787 } 2788 2789 struct mv88e6xxx_port_db_dump_vlan_ctx { 2790 int port; 2791 dsa_fdb_dump_cb_t *cb; 2792 void *data; 2793 }; 2794 2795 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2796 const struct mv88e6xxx_vtu_entry *entry, 2797 void *_data) 2798 { 2799 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2800 2801 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2802 ctx->port, ctx->cb, ctx->data); 2803 } 2804 2805 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2806 dsa_fdb_dump_cb_t *cb, void *data) 2807 { 2808 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2809 .port = port, 2810 .cb = cb, 2811 .data = data, 2812 }; 2813 u16 fid; 2814 int err; 2815 2816 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2817 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2818 if (err) 2819 return err; 2820 2821 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2822 if (err) 2823 return err; 2824 2825 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2826 } 2827 2828 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2829 dsa_fdb_dump_cb_t *cb, void *data) 2830 { 2831 struct mv88e6xxx_chip *chip = ds->priv; 2832 int err; 2833 2834 mv88e6xxx_reg_lock(chip); 2835 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2836 mv88e6xxx_reg_unlock(chip); 2837 2838 return err; 2839 } 2840 2841 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2842 struct dsa_bridge bridge) 2843 { 2844 struct dsa_switch *ds = chip->ds; 2845 struct dsa_switch_tree *dst = ds->dst; 2846 struct dsa_port *dp; 2847 int err; 2848 2849 list_for_each_entry(dp, &dst->ports, list) { 2850 if (dsa_port_offloads_bridge(dp, &bridge)) { 2851 if (dp->ds == ds) { 2852 /* This is a local bridge group member, 2853 * remap its Port VLAN Map. 2854 */ 2855 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2856 if (err) 2857 return err; 2858 } else { 2859 /* This is an external bridge group member, 2860 * remap its cross-chip Port VLAN Table entry. 2861 */ 2862 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2863 dp->index); 2864 if (err) 2865 return err; 2866 } 2867 } 2868 } 2869 2870 return 0; 2871 } 2872 2873 /* Treat the software bridge as a virtual single-port switch behind the 2874 * CPU and map in the PVT. First dst->last_switch elements are taken by 2875 * physical switches, so start from beyond that range. 2876 */ 2877 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2878 unsigned int bridge_num) 2879 { 2880 u8 dev = bridge_num + ds->dst->last_switch; 2881 struct mv88e6xxx_chip *chip = ds->priv; 2882 2883 return mv88e6xxx_pvt_map(chip, dev, 0); 2884 } 2885 2886 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2887 struct dsa_bridge bridge, 2888 bool *tx_fwd_offload, 2889 struct netlink_ext_ack *extack) 2890 { 2891 struct mv88e6xxx_chip *chip = ds->priv; 2892 int err; 2893 2894 mv88e6xxx_reg_lock(chip); 2895 2896 err = mv88e6xxx_bridge_map(chip, bridge); 2897 if (err) 2898 goto unlock; 2899 2900 err = mv88e6xxx_port_set_map_da(chip, port, true); 2901 if (err) 2902 goto unlock; 2903 2904 err = mv88e6xxx_port_commit_pvid(chip, port); 2905 if (err) 2906 goto unlock; 2907 2908 if (mv88e6xxx_has_pvt(chip)) { 2909 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2910 if (err) 2911 goto unlock; 2912 2913 *tx_fwd_offload = true; 2914 } 2915 2916 unlock: 2917 mv88e6xxx_reg_unlock(chip); 2918 2919 return err; 2920 } 2921 2922 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2923 struct dsa_bridge bridge) 2924 { 2925 struct mv88e6xxx_chip *chip = ds->priv; 2926 int err; 2927 2928 mv88e6xxx_reg_lock(chip); 2929 2930 if (bridge.tx_fwd_offload && 2931 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2932 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2933 2934 if (mv88e6xxx_bridge_map(chip, bridge) || 2935 mv88e6xxx_port_vlan_map(chip, port)) 2936 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2937 2938 err = mv88e6xxx_port_set_map_da(chip, port, false); 2939 if (err) 2940 dev_err(ds->dev, 2941 "port %d failed to restore map-DA: %pe\n", 2942 port, ERR_PTR(err)); 2943 2944 err = mv88e6xxx_port_commit_pvid(chip, port); 2945 if (err) 2946 dev_err(ds->dev, 2947 "port %d failed to restore standalone pvid: %pe\n", 2948 port, ERR_PTR(err)); 2949 2950 mv88e6xxx_reg_unlock(chip); 2951 } 2952 2953 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2954 int tree_index, int sw_index, 2955 int port, struct dsa_bridge bridge, 2956 struct netlink_ext_ack *extack) 2957 { 2958 struct mv88e6xxx_chip *chip = ds->priv; 2959 int err; 2960 2961 if (tree_index != ds->dst->index) 2962 return 0; 2963 2964 mv88e6xxx_reg_lock(chip); 2965 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2966 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2967 mv88e6xxx_reg_unlock(chip); 2968 2969 return err; 2970 } 2971 2972 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2973 int tree_index, int sw_index, 2974 int port, struct dsa_bridge bridge) 2975 { 2976 struct mv88e6xxx_chip *chip = ds->priv; 2977 2978 if (tree_index != ds->dst->index) 2979 return; 2980 2981 mv88e6xxx_reg_lock(chip); 2982 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 2983 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2984 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2985 mv88e6xxx_reg_unlock(chip); 2986 } 2987 2988 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2989 { 2990 if (chip->info->ops->reset) 2991 return chip->info->ops->reset(chip); 2992 2993 return 0; 2994 } 2995 2996 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2997 { 2998 struct gpio_desc *gpiod = chip->reset; 2999 3000 /* If there is a GPIO connected to the reset pin, toggle it */ 3001 if (gpiod) { 3002 gpiod_set_value_cansleep(gpiod, 1); 3003 usleep_range(10000, 20000); 3004 gpiod_set_value_cansleep(gpiod, 0); 3005 usleep_range(10000, 20000); 3006 3007 mv88e6xxx_g1_wait_eeprom_done(chip); 3008 } 3009 } 3010 3011 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3012 { 3013 int i, err; 3014 3015 /* Set all ports to the Disabled state */ 3016 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3017 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3018 if (err) 3019 return err; 3020 } 3021 3022 /* Wait for transmit queues to drain, 3023 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3024 */ 3025 usleep_range(2000, 4000); 3026 3027 return 0; 3028 } 3029 3030 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3031 { 3032 int err; 3033 3034 err = mv88e6xxx_disable_ports(chip); 3035 if (err) 3036 return err; 3037 3038 mv88e6xxx_hardware_reset(chip); 3039 3040 return mv88e6xxx_software_reset(chip); 3041 } 3042 3043 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3044 enum mv88e6xxx_frame_mode frame, 3045 enum mv88e6xxx_egress_mode egress, u16 etype) 3046 { 3047 int err; 3048 3049 if (!chip->info->ops->port_set_frame_mode) 3050 return -EOPNOTSUPP; 3051 3052 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3053 if (err) 3054 return err; 3055 3056 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3057 if (err) 3058 return err; 3059 3060 if (chip->info->ops->port_set_ether_type) 3061 return chip->info->ops->port_set_ether_type(chip, port, etype); 3062 3063 return 0; 3064 } 3065 3066 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3067 { 3068 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3069 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3070 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3071 } 3072 3073 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3074 { 3075 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3076 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3077 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3078 } 3079 3080 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3081 { 3082 return mv88e6xxx_set_port_mode(chip, port, 3083 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3084 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3085 ETH_P_EDSA); 3086 } 3087 3088 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3089 { 3090 if (dsa_is_dsa_port(chip->ds, port)) 3091 return mv88e6xxx_set_port_mode_dsa(chip, port); 3092 3093 if (dsa_is_user_port(chip->ds, port)) 3094 return mv88e6xxx_set_port_mode_normal(chip, port); 3095 3096 /* Setup CPU port mode depending on its supported tag format */ 3097 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3098 return mv88e6xxx_set_port_mode_dsa(chip, port); 3099 3100 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3101 return mv88e6xxx_set_port_mode_edsa(chip, port); 3102 3103 return -EINVAL; 3104 } 3105 3106 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3107 { 3108 bool message = dsa_is_dsa_port(chip->ds, port); 3109 3110 return mv88e6xxx_port_set_message_port(chip, port, message); 3111 } 3112 3113 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3114 { 3115 int err; 3116 3117 if (chip->info->ops->port_set_ucast_flood) { 3118 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3119 if (err) 3120 return err; 3121 } 3122 if (chip->info->ops->port_set_mcast_flood) { 3123 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3124 if (err) 3125 return err; 3126 } 3127 3128 return 0; 3129 } 3130 3131 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 3132 { 3133 struct mv88e6xxx_port *mvp = dev_id; 3134 struct mv88e6xxx_chip *chip = mvp->chip; 3135 irqreturn_t ret = IRQ_NONE; 3136 int port = mvp->port; 3137 int lane; 3138 3139 mv88e6xxx_reg_lock(chip); 3140 lane = mv88e6xxx_serdes_get_lane(chip, port); 3141 if (lane >= 0) 3142 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 3143 mv88e6xxx_reg_unlock(chip); 3144 3145 return ret; 3146 } 3147 3148 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 3149 int lane) 3150 { 3151 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3152 unsigned int irq; 3153 int err; 3154 3155 /* Nothing to request if this SERDES port has no IRQ */ 3156 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 3157 if (!irq) 3158 return 0; 3159 3160 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 3161 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 3162 3163 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 3164 mv88e6xxx_reg_unlock(chip); 3165 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 3166 IRQF_ONESHOT, dev_id->serdes_irq_name, 3167 dev_id); 3168 mv88e6xxx_reg_lock(chip); 3169 if (err) 3170 return err; 3171 3172 dev_id->serdes_irq = irq; 3173 3174 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 3175 } 3176 3177 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 3178 int lane) 3179 { 3180 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3181 unsigned int irq = dev_id->serdes_irq; 3182 int err; 3183 3184 /* Nothing to free if no IRQ has been requested */ 3185 if (!irq) 3186 return 0; 3187 3188 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 3189 3190 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 3191 mv88e6xxx_reg_unlock(chip); 3192 free_irq(irq, dev_id); 3193 mv88e6xxx_reg_lock(chip); 3194 3195 dev_id->serdes_irq = 0; 3196 3197 return err; 3198 } 3199 3200 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 3201 bool on) 3202 { 3203 int lane; 3204 int err; 3205 3206 lane = mv88e6xxx_serdes_get_lane(chip, port); 3207 if (lane < 0) 3208 return 0; 3209 3210 if (on) { 3211 err = mv88e6xxx_serdes_power_up(chip, port, lane); 3212 if (err) 3213 return err; 3214 3215 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 3216 } else { 3217 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 3218 if (err) 3219 return err; 3220 3221 err = mv88e6xxx_serdes_power_down(chip, port, lane); 3222 } 3223 3224 return err; 3225 } 3226 3227 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3228 enum mv88e6xxx_egress_direction direction, 3229 int port) 3230 { 3231 int err; 3232 3233 if (!chip->info->ops->set_egress_port) 3234 return -EOPNOTSUPP; 3235 3236 err = chip->info->ops->set_egress_port(chip, direction, port); 3237 if (err) 3238 return err; 3239 3240 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3241 chip->ingress_dest_port = port; 3242 else 3243 chip->egress_dest_port = port; 3244 3245 return 0; 3246 } 3247 3248 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3249 { 3250 struct dsa_switch *ds = chip->ds; 3251 int upstream_port; 3252 int err; 3253 3254 upstream_port = dsa_upstream_port(ds, port); 3255 if (chip->info->ops->port_set_upstream_port) { 3256 err = chip->info->ops->port_set_upstream_port(chip, port, 3257 upstream_port); 3258 if (err) 3259 return err; 3260 } 3261 3262 if (port == upstream_port) { 3263 if (chip->info->ops->set_cpu_port) { 3264 err = chip->info->ops->set_cpu_port(chip, 3265 upstream_port); 3266 if (err) 3267 return err; 3268 } 3269 3270 err = mv88e6xxx_set_egress_port(chip, 3271 MV88E6XXX_EGRESS_DIR_INGRESS, 3272 upstream_port); 3273 if (err && err != -EOPNOTSUPP) 3274 return err; 3275 3276 err = mv88e6xxx_set_egress_port(chip, 3277 MV88E6XXX_EGRESS_DIR_EGRESS, 3278 upstream_port); 3279 if (err && err != -EOPNOTSUPP) 3280 return err; 3281 } 3282 3283 return 0; 3284 } 3285 3286 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3287 { 3288 struct device_node *phy_handle = NULL; 3289 struct dsa_switch *ds = chip->ds; 3290 phy_interface_t mode; 3291 struct dsa_port *dp; 3292 int tx_amp, speed; 3293 int err; 3294 u16 reg; 3295 3296 chip->ports[port].chip = chip; 3297 chip->ports[port].port = port; 3298 3299 dp = dsa_to_port(ds, port); 3300 3301 /* MAC Forcing register: don't force link, speed, duplex or flow control 3302 * state to any particular values on physical ports, but force the CPU 3303 * port and all DSA ports to their maximum bandwidth and full duplex. 3304 */ 3305 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 3306 struct phylink_config pl_config = {}; 3307 unsigned long caps; 3308 3309 chip->info->ops->phylink_get_caps(chip, port, &pl_config); 3310 3311 caps = pl_config.mac_capabilities; 3312 3313 if (chip->info->ops->port_max_speed_mode) 3314 mode = chip->info->ops->port_max_speed_mode(port); 3315 else 3316 mode = PHY_INTERFACE_MODE_NA; 3317 3318 if (caps & MAC_10000FD) 3319 speed = SPEED_10000; 3320 else if (caps & MAC_5000FD) 3321 speed = SPEED_5000; 3322 else if (caps & MAC_2500FD) 3323 speed = SPEED_2500; 3324 else if (caps & MAC_1000) 3325 speed = SPEED_1000; 3326 else if (caps & MAC_100) 3327 speed = SPEED_100; 3328 else 3329 speed = SPEED_10; 3330 3331 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 3332 speed, DUPLEX_FULL, 3333 PAUSE_OFF, mode); 3334 } else { 3335 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3336 SPEED_UNFORCED, DUPLEX_UNFORCED, 3337 PAUSE_ON, 3338 PHY_INTERFACE_MODE_NA); 3339 } 3340 if (err) 3341 return err; 3342 3343 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3344 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3345 * tunneling, determine priority by looking at 802.1p and IP 3346 * priority fields (IP prio has precedence), and set STP state 3347 * to Forwarding. 3348 * 3349 * If this is the CPU link, use DSA or EDSA tagging depending 3350 * on which tagging mode was configured. 3351 * 3352 * If this is a link to another switch, use DSA tagging mode. 3353 * 3354 * If this is the upstream port for this switch, enable 3355 * forwarding of unknown unicasts and multicasts. 3356 */ 3357 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 3358 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3359 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3360 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3361 if (err) 3362 return err; 3363 3364 err = mv88e6xxx_setup_port_mode(chip, port); 3365 if (err) 3366 return err; 3367 3368 err = mv88e6xxx_setup_egress_floods(chip, port); 3369 if (err) 3370 return err; 3371 3372 /* Port Control 2: don't force a good FCS, set the MTU size to 3373 * 10222 bytes, disable 802.1q tags checking, don't discard 3374 * tagged or untagged frames on this port, skip destination 3375 * address lookup on user ports, disable ARP mirroring and don't 3376 * send a copy of all transmitted/received frames on this port 3377 * to the CPU. 3378 */ 3379 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3380 if (err) 3381 return err; 3382 3383 err = mv88e6xxx_setup_upstream_port(chip, port); 3384 if (err) 3385 return err; 3386 3387 /* On chips that support it, set all downstream DSA ports' 3388 * VLAN policy to TRAP. In combination with loading 3389 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3390 * provides a better isolation barrier between standalone 3391 * ports, as the ATU is bypassed on any intermediate switches 3392 * between the incoming port and the CPU. 3393 */ 3394 if (dsa_is_downstream_port(ds, port) && 3395 chip->info->ops->port_set_policy) { 3396 err = chip->info->ops->port_set_policy(chip, port, 3397 MV88E6XXX_POLICY_MAPPING_VTU, 3398 MV88E6XXX_POLICY_ACTION_TRAP); 3399 if (err) 3400 return err; 3401 } 3402 3403 /* User ports start out in standalone mode and 802.1Q is 3404 * therefore disabled. On DSA ports, all valid VIDs are always 3405 * loaded in the VTU - therefore, enable 802.1Q in order to take 3406 * advantage of VLAN policy on chips that supports it. 3407 */ 3408 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3409 dsa_is_user_port(ds, port) ? 3410 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3411 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3412 if (err) 3413 return err; 3414 3415 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3416 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3417 * the first free FID. This will be used as the private PVID for 3418 * unbridged ports. Shared (DSA and CPU) ports must also be 3419 * members of this VID, in order to trap all frames assigned to 3420 * it to the CPU. 3421 */ 3422 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3423 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3424 false); 3425 if (err) 3426 return err; 3427 3428 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3429 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3430 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3431 * as the private PVID on ports under a VLAN-unaware bridge. 3432 * Shared (DSA and CPU) ports must also be members of it, to translate 3433 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3434 * relying on their port default FID. 3435 */ 3436 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3437 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3438 false); 3439 if (err) 3440 return err; 3441 3442 if (chip->info->ops->port_set_jumbo_size) { 3443 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3444 if (err) 3445 return err; 3446 } 3447 3448 /* Port Association Vector: disable automatic address learning 3449 * on all user ports since they start out in standalone 3450 * mode. When joining a bridge, learning will be configured to 3451 * match the bridge port settings. Enable learning on all 3452 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3453 * learning process. 3454 * 3455 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3456 * and RefreshLocked. I.e. setup standard automatic learning. 3457 */ 3458 if (dsa_is_user_port(ds, port)) 3459 reg = 0; 3460 else 3461 reg = 1 << port; 3462 3463 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3464 reg); 3465 if (err) 3466 return err; 3467 3468 /* Egress rate control 2: disable egress rate control. */ 3469 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3470 0x0000); 3471 if (err) 3472 return err; 3473 3474 if (chip->info->ops->port_pause_limit) { 3475 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3476 if (err) 3477 return err; 3478 } 3479 3480 if (chip->info->ops->port_disable_learn_limit) { 3481 err = chip->info->ops->port_disable_learn_limit(chip, port); 3482 if (err) 3483 return err; 3484 } 3485 3486 if (chip->info->ops->port_disable_pri_override) { 3487 err = chip->info->ops->port_disable_pri_override(chip, port); 3488 if (err) 3489 return err; 3490 } 3491 3492 if (chip->info->ops->port_tag_remap) { 3493 err = chip->info->ops->port_tag_remap(chip, port); 3494 if (err) 3495 return err; 3496 } 3497 3498 if (chip->info->ops->port_egress_rate_limiting) { 3499 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3500 if (err) 3501 return err; 3502 } 3503 3504 if (chip->info->ops->port_setup_message_port) { 3505 err = chip->info->ops->port_setup_message_port(chip, port); 3506 if (err) 3507 return err; 3508 } 3509 3510 if (chip->info->ops->serdes_set_tx_amplitude) { 3511 if (dp) 3512 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3513 3514 if (phy_handle && !of_property_read_u32(phy_handle, 3515 "tx-p2p-microvolt", 3516 &tx_amp)) 3517 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3518 port, tx_amp); 3519 if (phy_handle) { 3520 of_node_put(phy_handle); 3521 if (err) 3522 return err; 3523 } 3524 } 3525 3526 /* Port based VLAN map: give each port the same default address 3527 * database, and allow bidirectional communication between the 3528 * CPU and DSA port(s), and the other ports. 3529 */ 3530 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3531 if (err) 3532 return err; 3533 3534 err = mv88e6xxx_port_vlan_map(chip, port); 3535 if (err) 3536 return err; 3537 3538 /* Default VLAN ID and priority: don't set a default VLAN 3539 * ID, and set the default packet priority to zero. 3540 */ 3541 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3542 } 3543 3544 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3545 { 3546 struct mv88e6xxx_chip *chip = ds->priv; 3547 3548 if (chip->info->ops->port_set_jumbo_size) 3549 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3550 else if (chip->info->ops->set_max_frame_size) 3551 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3552 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3553 } 3554 3555 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3556 { 3557 struct mv88e6xxx_chip *chip = ds->priv; 3558 int ret = 0; 3559 3560 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3561 new_mtu += EDSA_HLEN; 3562 3563 mv88e6xxx_reg_lock(chip); 3564 if (chip->info->ops->port_set_jumbo_size) 3565 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3566 else if (chip->info->ops->set_max_frame_size) 3567 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3568 else 3569 if (new_mtu > 1522) 3570 ret = -EINVAL; 3571 mv88e6xxx_reg_unlock(chip); 3572 3573 return ret; 3574 } 3575 3576 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3577 struct phy_device *phydev) 3578 { 3579 struct mv88e6xxx_chip *chip = ds->priv; 3580 int err; 3581 3582 mv88e6xxx_reg_lock(chip); 3583 err = mv88e6xxx_serdes_power(chip, port, true); 3584 mv88e6xxx_reg_unlock(chip); 3585 3586 return err; 3587 } 3588 3589 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3590 { 3591 struct mv88e6xxx_chip *chip = ds->priv; 3592 3593 mv88e6xxx_reg_lock(chip); 3594 if (mv88e6xxx_serdes_power(chip, port, false)) 3595 dev_err(chip->dev, "failed to power off SERDES\n"); 3596 mv88e6xxx_reg_unlock(chip); 3597 } 3598 3599 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3600 unsigned int ageing_time) 3601 { 3602 struct mv88e6xxx_chip *chip = ds->priv; 3603 int err; 3604 3605 mv88e6xxx_reg_lock(chip); 3606 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3607 mv88e6xxx_reg_unlock(chip); 3608 3609 return err; 3610 } 3611 3612 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3613 { 3614 int err; 3615 3616 /* Initialize the statistics unit */ 3617 if (chip->info->ops->stats_set_histogram) { 3618 err = chip->info->ops->stats_set_histogram(chip); 3619 if (err) 3620 return err; 3621 } 3622 3623 return mv88e6xxx_g1_stats_clear(chip); 3624 } 3625 3626 /* Check if the errata has already been applied. */ 3627 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3628 { 3629 int port; 3630 int err; 3631 u16 val; 3632 3633 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3634 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3635 if (err) { 3636 dev_err(chip->dev, 3637 "Error reading hidden register: %d\n", err); 3638 return false; 3639 } 3640 if (val != 0x01c0) 3641 return false; 3642 } 3643 3644 return true; 3645 } 3646 3647 /* The 6390 copper ports have an errata which require poking magic 3648 * values into undocumented hidden registers and then performing a 3649 * software reset. 3650 */ 3651 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3652 { 3653 int port; 3654 int err; 3655 3656 if (mv88e6390_setup_errata_applied(chip)) 3657 return 0; 3658 3659 /* Set the ports into blocking mode */ 3660 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3661 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3662 if (err) 3663 return err; 3664 } 3665 3666 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3667 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3668 if (err) 3669 return err; 3670 } 3671 3672 return mv88e6xxx_software_reset(chip); 3673 } 3674 3675 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3676 { 3677 mv88e6xxx_teardown_devlink_params(ds); 3678 dsa_devlink_resources_unregister(ds); 3679 mv88e6xxx_teardown_devlink_regions_global(ds); 3680 } 3681 3682 static int mv88e6xxx_setup(struct dsa_switch *ds) 3683 { 3684 struct mv88e6xxx_chip *chip = ds->priv; 3685 u8 cmode; 3686 int err; 3687 int i; 3688 3689 chip->ds = ds; 3690 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3691 3692 /* Since virtual bridges are mapped in the PVT, the number we support 3693 * depends on the physical switch topology. We need to let DSA figure 3694 * that out and therefore we cannot set this at dsa_register_switch() 3695 * time. 3696 */ 3697 if (mv88e6xxx_has_pvt(chip)) 3698 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3699 ds->dst->last_switch - 1; 3700 3701 mv88e6xxx_reg_lock(chip); 3702 3703 if (chip->info->ops->setup_errata) { 3704 err = chip->info->ops->setup_errata(chip); 3705 if (err) 3706 goto unlock; 3707 } 3708 3709 /* Cache the cmode of each port. */ 3710 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3711 if (chip->info->ops->port_get_cmode) { 3712 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3713 if (err) 3714 goto unlock; 3715 3716 chip->ports[i].cmode = cmode; 3717 } 3718 } 3719 3720 err = mv88e6xxx_vtu_setup(chip); 3721 if (err) 3722 goto unlock; 3723 3724 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3725 * VTU, thereby also flushing the STU). 3726 */ 3727 err = mv88e6xxx_stu_setup(chip); 3728 if (err) 3729 goto unlock; 3730 3731 /* Setup Switch Port Registers */ 3732 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3733 if (dsa_is_unused_port(ds, i)) 3734 continue; 3735 3736 /* Prevent the use of an invalid port. */ 3737 if (mv88e6xxx_is_invalid_port(chip, i)) { 3738 dev_err(chip->dev, "port %d is invalid\n", i); 3739 err = -EINVAL; 3740 goto unlock; 3741 } 3742 3743 err = mv88e6xxx_setup_port(chip, i); 3744 if (err) 3745 goto unlock; 3746 } 3747 3748 err = mv88e6xxx_irl_setup(chip); 3749 if (err) 3750 goto unlock; 3751 3752 err = mv88e6xxx_mac_setup(chip); 3753 if (err) 3754 goto unlock; 3755 3756 err = mv88e6xxx_phy_setup(chip); 3757 if (err) 3758 goto unlock; 3759 3760 err = mv88e6xxx_pvt_setup(chip); 3761 if (err) 3762 goto unlock; 3763 3764 err = mv88e6xxx_atu_setup(chip); 3765 if (err) 3766 goto unlock; 3767 3768 err = mv88e6xxx_broadcast_setup(chip, 0); 3769 if (err) 3770 goto unlock; 3771 3772 err = mv88e6xxx_pot_setup(chip); 3773 if (err) 3774 goto unlock; 3775 3776 err = mv88e6xxx_rmu_setup(chip); 3777 if (err) 3778 goto unlock; 3779 3780 err = mv88e6xxx_rsvd2cpu_setup(chip); 3781 if (err) 3782 goto unlock; 3783 3784 err = mv88e6xxx_trunk_setup(chip); 3785 if (err) 3786 goto unlock; 3787 3788 err = mv88e6xxx_devmap_setup(chip); 3789 if (err) 3790 goto unlock; 3791 3792 err = mv88e6xxx_pri_setup(chip); 3793 if (err) 3794 goto unlock; 3795 3796 /* Setup PTP Hardware Clock and timestamping */ 3797 if (chip->info->ptp_support) { 3798 err = mv88e6xxx_ptp_setup(chip); 3799 if (err) 3800 goto unlock; 3801 3802 err = mv88e6xxx_hwtstamp_setup(chip); 3803 if (err) 3804 goto unlock; 3805 } 3806 3807 err = mv88e6xxx_stats_setup(chip); 3808 if (err) 3809 goto unlock; 3810 3811 unlock: 3812 mv88e6xxx_reg_unlock(chip); 3813 3814 if (err) 3815 return err; 3816 3817 /* Have to be called without holding the register lock, since 3818 * they take the devlink lock, and we later take the locks in 3819 * the reverse order when getting/setting parameters or 3820 * resource occupancy. 3821 */ 3822 err = mv88e6xxx_setup_devlink_resources(ds); 3823 if (err) 3824 return err; 3825 3826 err = mv88e6xxx_setup_devlink_params(ds); 3827 if (err) 3828 goto out_resources; 3829 3830 err = mv88e6xxx_setup_devlink_regions_global(ds); 3831 if (err) 3832 goto out_params; 3833 3834 return 0; 3835 3836 out_params: 3837 mv88e6xxx_teardown_devlink_params(ds); 3838 out_resources: 3839 dsa_devlink_resources_unregister(ds); 3840 3841 return err; 3842 } 3843 3844 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3845 { 3846 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3847 } 3848 3849 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3850 { 3851 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3852 } 3853 3854 /* prod_id for switch families which do not have a PHY model number */ 3855 static const u16 family_prod_id_table[] = { 3856 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3857 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3858 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3859 }; 3860 3861 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3862 { 3863 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3864 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3865 u16 prod_id; 3866 u16 val; 3867 int err; 3868 3869 if (!chip->info->ops->phy_read) 3870 return -EOPNOTSUPP; 3871 3872 mv88e6xxx_reg_lock(chip); 3873 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3874 mv88e6xxx_reg_unlock(chip); 3875 3876 /* Some internal PHYs don't have a model number. */ 3877 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3878 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3879 prod_id = family_prod_id_table[chip->info->family]; 3880 if (prod_id) 3881 val |= prod_id >> 4; 3882 } 3883 3884 return err ? err : val; 3885 } 3886 3887 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3888 int reg) 3889 { 3890 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3891 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3892 u16 val; 3893 int err; 3894 3895 if (!chip->info->ops->phy_read_c45) 3896 return -EOPNOTSUPP; 3897 3898 mv88e6xxx_reg_lock(chip); 3899 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3900 mv88e6xxx_reg_unlock(chip); 3901 3902 return err ? err : val; 3903 } 3904 3905 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3906 { 3907 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3908 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3909 int err; 3910 3911 if (!chip->info->ops->phy_write) 3912 return -EOPNOTSUPP; 3913 3914 mv88e6xxx_reg_lock(chip); 3915 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3916 mv88e6xxx_reg_unlock(chip); 3917 3918 return err; 3919 } 3920 3921 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3922 int reg, u16 val) 3923 { 3924 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3925 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3926 int err; 3927 3928 if (!chip->info->ops->phy_write_c45) 3929 return -EOPNOTSUPP; 3930 3931 mv88e6xxx_reg_lock(chip); 3932 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3933 mv88e6xxx_reg_unlock(chip); 3934 3935 return err; 3936 } 3937 3938 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3939 struct device_node *np, 3940 bool external) 3941 { 3942 static int index; 3943 struct mv88e6xxx_mdio_bus *mdio_bus; 3944 struct mii_bus *bus; 3945 int err; 3946 3947 if (external) { 3948 mv88e6xxx_reg_lock(chip); 3949 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3950 mv88e6xxx_reg_unlock(chip); 3951 3952 if (err) 3953 return err; 3954 } 3955 3956 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3957 if (!bus) 3958 return -ENOMEM; 3959 3960 mdio_bus = bus->priv; 3961 mdio_bus->bus = bus; 3962 mdio_bus->chip = chip; 3963 INIT_LIST_HEAD(&mdio_bus->list); 3964 mdio_bus->external = external; 3965 3966 if (np) { 3967 bus->name = np->full_name; 3968 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3969 } else { 3970 bus->name = "mv88e6xxx SMI"; 3971 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3972 } 3973 3974 bus->read = mv88e6xxx_mdio_read; 3975 bus->write = mv88e6xxx_mdio_write; 3976 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3977 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3978 bus->parent = chip->dev; 3979 3980 if (!external) { 3981 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3982 if (err) 3983 goto out; 3984 } 3985 3986 err = of_mdiobus_register(bus, np); 3987 if (err) { 3988 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3989 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3990 goto out; 3991 } 3992 3993 if (external) 3994 list_add_tail(&mdio_bus->list, &chip->mdios); 3995 else 3996 list_add(&mdio_bus->list, &chip->mdios); 3997 3998 return 0; 3999 4000 out: 4001 mdiobus_free(bus); 4002 return err; 4003 } 4004 4005 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 4006 4007 { 4008 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 4009 struct mii_bus *bus; 4010 4011 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 4012 bus = mdio_bus->bus; 4013 4014 if (!mdio_bus->external) 4015 mv88e6xxx_g2_irq_mdio_free(chip, bus); 4016 4017 mdiobus_unregister(bus); 4018 mdiobus_free(bus); 4019 } 4020 } 4021 4022 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 4023 struct device_node *np) 4024 { 4025 struct device_node *child; 4026 int err; 4027 4028 /* Always register one mdio bus for the internal/default mdio 4029 * bus. This maybe represented in the device tree, but is 4030 * optional. 4031 */ 4032 child = of_get_child_by_name(np, "mdio"); 4033 err = mv88e6xxx_mdio_register(chip, child, false); 4034 of_node_put(child); 4035 if (err) 4036 return err; 4037 4038 /* Walk the device tree, and see if there are any other nodes 4039 * which say they are compatible with the external mdio 4040 * bus. 4041 */ 4042 for_each_available_child_of_node(np, child) { 4043 if (of_device_is_compatible( 4044 child, "marvell,mv88e6xxx-mdio-external")) { 4045 err = mv88e6xxx_mdio_register(chip, child, true); 4046 if (err) { 4047 mv88e6xxx_mdios_unregister(chip); 4048 of_node_put(child); 4049 return err; 4050 } 4051 } 4052 } 4053 4054 return 0; 4055 } 4056 4057 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4058 { 4059 struct mv88e6xxx_chip *chip = ds->priv; 4060 4061 return chip->eeprom_len; 4062 } 4063 4064 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4065 struct ethtool_eeprom *eeprom, u8 *data) 4066 { 4067 struct mv88e6xxx_chip *chip = ds->priv; 4068 int err; 4069 4070 if (!chip->info->ops->get_eeprom) 4071 return -EOPNOTSUPP; 4072 4073 mv88e6xxx_reg_lock(chip); 4074 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4075 mv88e6xxx_reg_unlock(chip); 4076 4077 if (err) 4078 return err; 4079 4080 eeprom->magic = 0xc3ec4951; 4081 4082 return 0; 4083 } 4084 4085 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4086 struct ethtool_eeprom *eeprom, u8 *data) 4087 { 4088 struct mv88e6xxx_chip *chip = ds->priv; 4089 int err; 4090 4091 if (!chip->info->ops->set_eeprom) 4092 return -EOPNOTSUPP; 4093 4094 if (eeprom->magic != 0xc3ec4951) 4095 return -EINVAL; 4096 4097 mv88e6xxx_reg_lock(chip); 4098 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4099 mv88e6xxx_reg_unlock(chip); 4100 4101 return err; 4102 } 4103 4104 static const struct mv88e6xxx_ops mv88e6085_ops = { 4105 /* MV88E6XXX_FAMILY_6097 */ 4106 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4107 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4108 .irl_init_all = mv88e6352_g2_irl_init_all, 4109 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4110 .phy_read = mv88e6185_phy_ppu_read, 4111 .phy_write = mv88e6185_phy_ppu_write, 4112 .port_set_link = mv88e6xxx_port_set_link, 4113 .port_sync_link = mv88e6xxx_port_sync_link, 4114 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4115 .port_tag_remap = mv88e6095_port_tag_remap, 4116 .port_set_policy = mv88e6352_port_set_policy, 4117 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4118 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4119 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4120 .port_set_ether_type = mv88e6351_port_set_ether_type, 4121 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4122 .port_pause_limit = mv88e6097_port_pause_limit, 4123 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4124 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4125 .port_get_cmode = mv88e6185_port_get_cmode, 4126 .port_setup_message_port = mv88e6xxx_setup_message_port, 4127 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4128 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4129 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4130 .stats_get_strings = mv88e6095_stats_get_strings, 4131 .stats_get_stats = mv88e6095_stats_get_stats, 4132 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4133 .set_egress_port = mv88e6095_g1_set_egress_port, 4134 .watchdog_ops = &mv88e6097_watchdog_ops, 4135 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4136 .pot_clear = mv88e6xxx_g2_pot_clear, 4137 .ppu_enable = mv88e6185_g1_ppu_enable, 4138 .ppu_disable = mv88e6185_g1_ppu_disable, 4139 .reset = mv88e6185_g1_reset, 4140 .rmu_disable = mv88e6085_g1_rmu_disable, 4141 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4142 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4143 .stu_getnext = mv88e6352_g1_stu_getnext, 4144 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4145 .phylink_get_caps = mv88e6185_phylink_get_caps, 4146 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4147 }; 4148 4149 static const struct mv88e6xxx_ops mv88e6095_ops = { 4150 /* MV88E6XXX_FAMILY_6095 */ 4151 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4152 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4153 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4154 .phy_read = mv88e6185_phy_ppu_read, 4155 .phy_write = mv88e6185_phy_ppu_write, 4156 .port_set_link = mv88e6xxx_port_set_link, 4157 .port_sync_link = mv88e6185_port_sync_link, 4158 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4159 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4160 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4161 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4162 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4163 .port_get_cmode = mv88e6185_port_get_cmode, 4164 .port_setup_message_port = mv88e6xxx_setup_message_port, 4165 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4166 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4167 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4168 .stats_get_strings = mv88e6095_stats_get_strings, 4169 .stats_get_stats = mv88e6095_stats_get_stats, 4170 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4171 .serdes_power = mv88e6185_serdes_power, 4172 .serdes_get_lane = mv88e6185_serdes_get_lane, 4173 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4174 .ppu_enable = mv88e6185_g1_ppu_enable, 4175 .ppu_disable = mv88e6185_g1_ppu_disable, 4176 .reset = mv88e6185_g1_reset, 4177 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4178 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4179 .phylink_get_caps = mv88e6095_phylink_get_caps, 4180 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4181 }; 4182 4183 static const struct mv88e6xxx_ops mv88e6097_ops = { 4184 /* MV88E6XXX_FAMILY_6097 */ 4185 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4186 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4187 .irl_init_all = mv88e6352_g2_irl_init_all, 4188 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4189 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4190 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4191 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4192 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4193 .port_set_link = mv88e6xxx_port_set_link, 4194 .port_sync_link = mv88e6185_port_sync_link, 4195 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4196 .port_tag_remap = mv88e6095_port_tag_remap, 4197 .port_set_policy = mv88e6352_port_set_policy, 4198 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4199 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4200 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4201 .port_set_ether_type = mv88e6351_port_set_ether_type, 4202 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4203 .port_pause_limit = mv88e6097_port_pause_limit, 4204 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4205 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4206 .port_get_cmode = mv88e6185_port_get_cmode, 4207 .port_setup_message_port = mv88e6xxx_setup_message_port, 4208 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4209 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4210 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4211 .stats_get_strings = mv88e6095_stats_get_strings, 4212 .stats_get_stats = mv88e6095_stats_get_stats, 4213 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4214 .set_egress_port = mv88e6095_g1_set_egress_port, 4215 .watchdog_ops = &mv88e6097_watchdog_ops, 4216 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4217 .serdes_power = mv88e6185_serdes_power, 4218 .serdes_get_lane = mv88e6185_serdes_get_lane, 4219 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4220 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4221 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 4222 .serdes_irq_status = mv88e6097_serdes_irq_status, 4223 .pot_clear = mv88e6xxx_g2_pot_clear, 4224 .reset = mv88e6352_g1_reset, 4225 .rmu_disable = mv88e6085_g1_rmu_disable, 4226 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4227 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4228 .phylink_get_caps = mv88e6095_phylink_get_caps, 4229 .stu_getnext = mv88e6352_g1_stu_getnext, 4230 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4231 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4232 }; 4233 4234 static const struct mv88e6xxx_ops mv88e6123_ops = { 4235 /* MV88E6XXX_FAMILY_6165 */ 4236 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4237 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4238 .irl_init_all = mv88e6352_g2_irl_init_all, 4239 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4240 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4241 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4242 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4243 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4244 .port_set_link = mv88e6xxx_port_set_link, 4245 .port_sync_link = mv88e6xxx_port_sync_link, 4246 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4247 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4248 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4249 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4250 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4251 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4252 .port_get_cmode = mv88e6185_port_get_cmode, 4253 .port_setup_message_port = mv88e6xxx_setup_message_port, 4254 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4255 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4256 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4257 .stats_get_strings = mv88e6095_stats_get_strings, 4258 .stats_get_stats = mv88e6095_stats_get_stats, 4259 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4260 .set_egress_port = mv88e6095_g1_set_egress_port, 4261 .watchdog_ops = &mv88e6097_watchdog_ops, 4262 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4263 .pot_clear = mv88e6xxx_g2_pot_clear, 4264 .reset = mv88e6352_g1_reset, 4265 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4266 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4267 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4268 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4269 .stu_getnext = mv88e6352_g1_stu_getnext, 4270 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4271 .phylink_get_caps = mv88e6185_phylink_get_caps, 4272 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4273 }; 4274 4275 static const struct mv88e6xxx_ops mv88e6131_ops = { 4276 /* MV88E6XXX_FAMILY_6185 */ 4277 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4278 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4279 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4280 .phy_read = mv88e6185_phy_ppu_read, 4281 .phy_write = mv88e6185_phy_ppu_write, 4282 .port_set_link = mv88e6xxx_port_set_link, 4283 .port_sync_link = mv88e6xxx_port_sync_link, 4284 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4285 .port_tag_remap = mv88e6095_port_tag_remap, 4286 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4287 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4288 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4289 .port_set_ether_type = mv88e6351_port_set_ether_type, 4290 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4291 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4292 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4293 .port_pause_limit = mv88e6097_port_pause_limit, 4294 .port_set_pause = mv88e6185_port_set_pause, 4295 .port_get_cmode = mv88e6185_port_get_cmode, 4296 .port_setup_message_port = mv88e6xxx_setup_message_port, 4297 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4298 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4299 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4300 .stats_get_strings = mv88e6095_stats_get_strings, 4301 .stats_get_stats = mv88e6095_stats_get_stats, 4302 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4303 .set_egress_port = mv88e6095_g1_set_egress_port, 4304 .watchdog_ops = &mv88e6097_watchdog_ops, 4305 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4306 .ppu_enable = mv88e6185_g1_ppu_enable, 4307 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4308 .ppu_disable = mv88e6185_g1_ppu_disable, 4309 .reset = mv88e6185_g1_reset, 4310 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4311 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4312 .phylink_get_caps = mv88e6185_phylink_get_caps, 4313 }; 4314 4315 static const struct mv88e6xxx_ops mv88e6141_ops = { 4316 /* MV88E6XXX_FAMILY_6341 */ 4317 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4318 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4319 .irl_init_all = mv88e6352_g2_irl_init_all, 4320 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4321 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4322 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4323 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4324 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4325 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4326 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4327 .port_set_link = mv88e6xxx_port_set_link, 4328 .port_sync_link = mv88e6xxx_port_sync_link, 4329 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4330 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4331 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4332 .port_tag_remap = mv88e6095_port_tag_remap, 4333 .port_set_policy = mv88e6352_port_set_policy, 4334 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4335 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4336 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4337 .port_set_ether_type = mv88e6351_port_set_ether_type, 4338 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4339 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4340 .port_pause_limit = mv88e6097_port_pause_limit, 4341 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4342 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4343 .port_get_cmode = mv88e6352_port_get_cmode, 4344 .port_set_cmode = mv88e6341_port_set_cmode, 4345 .port_setup_message_port = mv88e6xxx_setup_message_port, 4346 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4347 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4348 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4349 .stats_get_strings = mv88e6320_stats_get_strings, 4350 .stats_get_stats = mv88e6390_stats_get_stats, 4351 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4352 .set_egress_port = mv88e6390_g1_set_egress_port, 4353 .watchdog_ops = &mv88e6390_watchdog_ops, 4354 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4355 .pot_clear = mv88e6xxx_g2_pot_clear, 4356 .reset = mv88e6352_g1_reset, 4357 .rmu_disable = mv88e6390_g1_rmu_disable, 4358 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4359 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4360 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4361 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4362 .stu_getnext = mv88e6352_g1_stu_getnext, 4363 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4364 .serdes_power = mv88e6390_serdes_power, 4365 .serdes_get_lane = mv88e6341_serdes_get_lane, 4366 /* Check status register pause & lpa register */ 4367 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4368 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4369 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4370 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4371 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4372 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4373 .serdes_irq_status = mv88e6390_serdes_irq_status, 4374 .gpio_ops = &mv88e6352_gpio_ops, 4375 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4376 .serdes_get_strings = mv88e6390_serdes_get_strings, 4377 .serdes_get_stats = mv88e6390_serdes_get_stats, 4378 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4379 .serdes_get_regs = mv88e6390_serdes_get_regs, 4380 .phylink_get_caps = mv88e6341_phylink_get_caps, 4381 }; 4382 4383 static const struct mv88e6xxx_ops mv88e6161_ops = { 4384 /* MV88E6XXX_FAMILY_6165 */ 4385 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4386 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4387 .irl_init_all = mv88e6352_g2_irl_init_all, 4388 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4389 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4390 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4391 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4392 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4393 .port_set_link = mv88e6xxx_port_set_link, 4394 .port_sync_link = mv88e6xxx_port_sync_link, 4395 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4396 .port_tag_remap = mv88e6095_port_tag_remap, 4397 .port_set_policy = mv88e6352_port_set_policy, 4398 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4399 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4400 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4401 .port_set_ether_type = mv88e6351_port_set_ether_type, 4402 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4403 .port_pause_limit = mv88e6097_port_pause_limit, 4404 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4405 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4406 .port_get_cmode = mv88e6185_port_get_cmode, 4407 .port_setup_message_port = mv88e6xxx_setup_message_port, 4408 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4409 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4410 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4411 .stats_get_strings = mv88e6095_stats_get_strings, 4412 .stats_get_stats = mv88e6095_stats_get_stats, 4413 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4414 .set_egress_port = mv88e6095_g1_set_egress_port, 4415 .watchdog_ops = &mv88e6097_watchdog_ops, 4416 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4417 .pot_clear = mv88e6xxx_g2_pot_clear, 4418 .reset = mv88e6352_g1_reset, 4419 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4420 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4421 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4422 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4423 .stu_getnext = mv88e6352_g1_stu_getnext, 4424 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4425 .avb_ops = &mv88e6165_avb_ops, 4426 .ptp_ops = &mv88e6165_ptp_ops, 4427 .phylink_get_caps = mv88e6185_phylink_get_caps, 4428 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4429 }; 4430 4431 static const struct mv88e6xxx_ops mv88e6165_ops = { 4432 /* MV88E6XXX_FAMILY_6165 */ 4433 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4434 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4435 .irl_init_all = mv88e6352_g2_irl_init_all, 4436 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4437 .phy_read = mv88e6165_phy_read, 4438 .phy_write = mv88e6165_phy_write, 4439 .port_set_link = mv88e6xxx_port_set_link, 4440 .port_sync_link = mv88e6xxx_port_sync_link, 4441 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4442 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4443 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4444 .port_get_cmode = mv88e6185_port_get_cmode, 4445 .port_setup_message_port = mv88e6xxx_setup_message_port, 4446 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4447 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4448 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4449 .stats_get_strings = mv88e6095_stats_get_strings, 4450 .stats_get_stats = mv88e6095_stats_get_stats, 4451 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4452 .set_egress_port = mv88e6095_g1_set_egress_port, 4453 .watchdog_ops = &mv88e6097_watchdog_ops, 4454 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4455 .pot_clear = mv88e6xxx_g2_pot_clear, 4456 .reset = mv88e6352_g1_reset, 4457 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4458 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4459 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4460 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4461 .stu_getnext = mv88e6352_g1_stu_getnext, 4462 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4463 .avb_ops = &mv88e6165_avb_ops, 4464 .ptp_ops = &mv88e6165_ptp_ops, 4465 .phylink_get_caps = mv88e6185_phylink_get_caps, 4466 }; 4467 4468 static const struct mv88e6xxx_ops mv88e6171_ops = { 4469 /* MV88E6XXX_FAMILY_6351 */ 4470 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4471 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4472 .irl_init_all = mv88e6352_g2_irl_init_all, 4473 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4474 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4475 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4476 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4477 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4478 .port_set_link = mv88e6xxx_port_set_link, 4479 .port_sync_link = mv88e6xxx_port_sync_link, 4480 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4481 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4482 .port_tag_remap = mv88e6095_port_tag_remap, 4483 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4484 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4485 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4486 .port_set_ether_type = mv88e6351_port_set_ether_type, 4487 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4488 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4489 .port_pause_limit = mv88e6097_port_pause_limit, 4490 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4491 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4492 .port_get_cmode = mv88e6352_port_get_cmode, 4493 .port_setup_message_port = mv88e6xxx_setup_message_port, 4494 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4495 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4496 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4497 .stats_get_strings = mv88e6095_stats_get_strings, 4498 .stats_get_stats = mv88e6095_stats_get_stats, 4499 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4500 .set_egress_port = mv88e6095_g1_set_egress_port, 4501 .watchdog_ops = &mv88e6097_watchdog_ops, 4502 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4503 .pot_clear = mv88e6xxx_g2_pot_clear, 4504 .reset = mv88e6352_g1_reset, 4505 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4506 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4507 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4508 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4509 .stu_getnext = mv88e6352_g1_stu_getnext, 4510 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4511 .phylink_get_caps = mv88e6185_phylink_get_caps, 4512 }; 4513 4514 static const struct mv88e6xxx_ops mv88e6172_ops = { 4515 /* MV88E6XXX_FAMILY_6352 */ 4516 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4517 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4518 .irl_init_all = mv88e6352_g2_irl_init_all, 4519 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4520 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4521 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4522 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4523 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4524 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4525 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4526 .port_set_link = mv88e6xxx_port_set_link, 4527 .port_sync_link = mv88e6xxx_port_sync_link, 4528 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4529 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4530 .port_tag_remap = mv88e6095_port_tag_remap, 4531 .port_set_policy = mv88e6352_port_set_policy, 4532 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4533 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4534 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4535 .port_set_ether_type = mv88e6351_port_set_ether_type, 4536 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4537 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4538 .port_pause_limit = mv88e6097_port_pause_limit, 4539 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4540 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4541 .port_get_cmode = mv88e6352_port_get_cmode, 4542 .port_setup_message_port = mv88e6xxx_setup_message_port, 4543 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4544 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4545 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4546 .stats_get_strings = mv88e6095_stats_get_strings, 4547 .stats_get_stats = mv88e6095_stats_get_stats, 4548 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4549 .set_egress_port = mv88e6095_g1_set_egress_port, 4550 .watchdog_ops = &mv88e6097_watchdog_ops, 4551 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4552 .pot_clear = mv88e6xxx_g2_pot_clear, 4553 .reset = mv88e6352_g1_reset, 4554 .rmu_disable = mv88e6352_g1_rmu_disable, 4555 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4556 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4557 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4558 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4559 .stu_getnext = mv88e6352_g1_stu_getnext, 4560 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4561 .serdes_get_lane = mv88e6352_serdes_get_lane, 4562 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4563 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4564 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4565 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4566 .serdes_power = mv88e6352_serdes_power, 4567 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4568 .serdes_get_regs = mv88e6352_serdes_get_regs, 4569 .gpio_ops = &mv88e6352_gpio_ops, 4570 .phylink_get_caps = mv88e6352_phylink_get_caps, 4571 }; 4572 4573 static const struct mv88e6xxx_ops mv88e6175_ops = { 4574 /* MV88E6XXX_FAMILY_6351 */ 4575 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4576 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4577 .irl_init_all = mv88e6352_g2_irl_init_all, 4578 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4579 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4580 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4581 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4582 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4583 .port_set_link = mv88e6xxx_port_set_link, 4584 .port_sync_link = mv88e6xxx_port_sync_link, 4585 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4586 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4587 .port_tag_remap = mv88e6095_port_tag_remap, 4588 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4589 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4590 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4591 .port_set_ether_type = mv88e6351_port_set_ether_type, 4592 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4593 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4594 .port_pause_limit = mv88e6097_port_pause_limit, 4595 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4596 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4597 .port_get_cmode = mv88e6352_port_get_cmode, 4598 .port_setup_message_port = mv88e6xxx_setup_message_port, 4599 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4600 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4601 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4602 .stats_get_strings = mv88e6095_stats_get_strings, 4603 .stats_get_stats = mv88e6095_stats_get_stats, 4604 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4605 .set_egress_port = mv88e6095_g1_set_egress_port, 4606 .watchdog_ops = &mv88e6097_watchdog_ops, 4607 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4608 .pot_clear = mv88e6xxx_g2_pot_clear, 4609 .reset = mv88e6352_g1_reset, 4610 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4611 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4612 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4613 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4614 .stu_getnext = mv88e6352_g1_stu_getnext, 4615 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4616 .phylink_get_caps = mv88e6185_phylink_get_caps, 4617 }; 4618 4619 static const struct mv88e6xxx_ops mv88e6176_ops = { 4620 /* MV88E6XXX_FAMILY_6352 */ 4621 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4622 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4623 .irl_init_all = mv88e6352_g2_irl_init_all, 4624 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4625 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4626 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4627 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4628 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4629 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4630 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4631 .port_set_link = mv88e6xxx_port_set_link, 4632 .port_sync_link = mv88e6xxx_port_sync_link, 4633 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4634 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4635 .port_tag_remap = mv88e6095_port_tag_remap, 4636 .port_set_policy = mv88e6352_port_set_policy, 4637 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4638 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4639 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4640 .port_set_ether_type = mv88e6351_port_set_ether_type, 4641 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4642 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4643 .port_pause_limit = mv88e6097_port_pause_limit, 4644 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4645 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4646 .port_get_cmode = mv88e6352_port_get_cmode, 4647 .port_setup_message_port = mv88e6xxx_setup_message_port, 4648 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4649 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4650 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4651 .stats_get_strings = mv88e6095_stats_get_strings, 4652 .stats_get_stats = mv88e6095_stats_get_stats, 4653 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4654 .set_egress_port = mv88e6095_g1_set_egress_port, 4655 .watchdog_ops = &mv88e6097_watchdog_ops, 4656 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4657 .pot_clear = mv88e6xxx_g2_pot_clear, 4658 .reset = mv88e6352_g1_reset, 4659 .rmu_disable = mv88e6352_g1_rmu_disable, 4660 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4661 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4662 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4663 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4664 .stu_getnext = mv88e6352_g1_stu_getnext, 4665 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4666 .serdes_get_lane = mv88e6352_serdes_get_lane, 4667 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4668 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4669 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4670 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4671 .serdes_power = mv88e6352_serdes_power, 4672 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4673 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4674 .serdes_irq_status = mv88e6352_serdes_irq_status, 4675 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4676 .serdes_get_regs = mv88e6352_serdes_get_regs, 4677 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4678 .gpio_ops = &mv88e6352_gpio_ops, 4679 .phylink_get_caps = mv88e6352_phylink_get_caps, 4680 }; 4681 4682 static const struct mv88e6xxx_ops mv88e6185_ops = { 4683 /* MV88E6XXX_FAMILY_6185 */ 4684 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4685 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4686 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4687 .phy_read = mv88e6185_phy_ppu_read, 4688 .phy_write = mv88e6185_phy_ppu_write, 4689 .port_set_link = mv88e6xxx_port_set_link, 4690 .port_sync_link = mv88e6185_port_sync_link, 4691 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4692 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4693 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4694 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4695 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4696 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4697 .port_set_pause = mv88e6185_port_set_pause, 4698 .port_get_cmode = mv88e6185_port_get_cmode, 4699 .port_setup_message_port = mv88e6xxx_setup_message_port, 4700 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4701 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4702 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4703 .stats_get_strings = mv88e6095_stats_get_strings, 4704 .stats_get_stats = mv88e6095_stats_get_stats, 4705 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4706 .set_egress_port = mv88e6095_g1_set_egress_port, 4707 .watchdog_ops = &mv88e6097_watchdog_ops, 4708 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4709 .serdes_power = mv88e6185_serdes_power, 4710 .serdes_get_lane = mv88e6185_serdes_get_lane, 4711 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4712 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4713 .ppu_enable = mv88e6185_g1_ppu_enable, 4714 .ppu_disable = mv88e6185_g1_ppu_disable, 4715 .reset = mv88e6185_g1_reset, 4716 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4717 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4718 .phylink_get_caps = mv88e6185_phylink_get_caps, 4719 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4720 }; 4721 4722 static const struct mv88e6xxx_ops mv88e6190_ops = { 4723 /* MV88E6XXX_FAMILY_6390 */ 4724 .setup_errata = mv88e6390_setup_errata, 4725 .irl_init_all = mv88e6390_g2_irl_init_all, 4726 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4727 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4728 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4729 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4730 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4731 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4732 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4733 .port_set_link = mv88e6xxx_port_set_link, 4734 .port_sync_link = mv88e6xxx_port_sync_link, 4735 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4736 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4737 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4738 .port_tag_remap = mv88e6390_port_tag_remap, 4739 .port_set_policy = mv88e6352_port_set_policy, 4740 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4741 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4742 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4743 .port_set_ether_type = mv88e6351_port_set_ether_type, 4744 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4745 .port_pause_limit = mv88e6390_port_pause_limit, 4746 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4747 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4748 .port_get_cmode = mv88e6352_port_get_cmode, 4749 .port_set_cmode = mv88e6390_port_set_cmode, 4750 .port_setup_message_port = mv88e6xxx_setup_message_port, 4751 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4752 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4753 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4754 .stats_get_strings = mv88e6320_stats_get_strings, 4755 .stats_get_stats = mv88e6390_stats_get_stats, 4756 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4757 .set_egress_port = mv88e6390_g1_set_egress_port, 4758 .watchdog_ops = &mv88e6390_watchdog_ops, 4759 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4760 .pot_clear = mv88e6xxx_g2_pot_clear, 4761 .reset = mv88e6352_g1_reset, 4762 .rmu_disable = mv88e6390_g1_rmu_disable, 4763 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4764 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4765 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4766 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4767 .stu_getnext = mv88e6390_g1_stu_getnext, 4768 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4769 .serdes_power = mv88e6390_serdes_power, 4770 .serdes_get_lane = mv88e6390_serdes_get_lane, 4771 /* Check status register pause & lpa register */ 4772 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4773 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4774 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4775 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4776 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4777 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4778 .serdes_irq_status = mv88e6390_serdes_irq_status, 4779 .serdes_get_strings = mv88e6390_serdes_get_strings, 4780 .serdes_get_stats = mv88e6390_serdes_get_stats, 4781 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4782 .serdes_get_regs = mv88e6390_serdes_get_regs, 4783 .gpio_ops = &mv88e6352_gpio_ops, 4784 .phylink_get_caps = mv88e6390_phylink_get_caps, 4785 }; 4786 4787 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4788 /* MV88E6XXX_FAMILY_6390 */ 4789 .setup_errata = mv88e6390_setup_errata, 4790 .irl_init_all = mv88e6390_g2_irl_init_all, 4791 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4792 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4793 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4794 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4795 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4796 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4797 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4798 .port_set_link = mv88e6xxx_port_set_link, 4799 .port_sync_link = mv88e6xxx_port_sync_link, 4800 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4801 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4802 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4803 .port_tag_remap = mv88e6390_port_tag_remap, 4804 .port_set_policy = mv88e6352_port_set_policy, 4805 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4806 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4807 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4808 .port_set_ether_type = mv88e6351_port_set_ether_type, 4809 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4810 .port_pause_limit = mv88e6390_port_pause_limit, 4811 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4812 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4813 .port_get_cmode = mv88e6352_port_get_cmode, 4814 .port_set_cmode = mv88e6390x_port_set_cmode, 4815 .port_setup_message_port = mv88e6xxx_setup_message_port, 4816 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4817 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4818 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4819 .stats_get_strings = mv88e6320_stats_get_strings, 4820 .stats_get_stats = mv88e6390_stats_get_stats, 4821 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4822 .set_egress_port = mv88e6390_g1_set_egress_port, 4823 .watchdog_ops = &mv88e6390_watchdog_ops, 4824 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4825 .pot_clear = mv88e6xxx_g2_pot_clear, 4826 .reset = mv88e6352_g1_reset, 4827 .rmu_disable = mv88e6390_g1_rmu_disable, 4828 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4829 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4830 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4831 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4832 .stu_getnext = mv88e6390_g1_stu_getnext, 4833 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4834 .serdes_power = mv88e6390_serdes_power, 4835 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4836 /* Check status register pause & lpa register */ 4837 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4838 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4839 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4840 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4841 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4842 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4843 .serdes_irq_status = mv88e6390_serdes_irq_status, 4844 .serdes_get_strings = mv88e6390_serdes_get_strings, 4845 .serdes_get_stats = mv88e6390_serdes_get_stats, 4846 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4847 .serdes_get_regs = mv88e6390_serdes_get_regs, 4848 .gpio_ops = &mv88e6352_gpio_ops, 4849 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4850 }; 4851 4852 static const struct mv88e6xxx_ops mv88e6191_ops = { 4853 /* MV88E6XXX_FAMILY_6390 */ 4854 .setup_errata = mv88e6390_setup_errata, 4855 .irl_init_all = mv88e6390_g2_irl_init_all, 4856 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4857 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4858 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4859 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4860 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4861 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4862 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4863 .port_set_link = mv88e6xxx_port_set_link, 4864 .port_sync_link = mv88e6xxx_port_sync_link, 4865 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4866 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4867 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4868 .port_tag_remap = mv88e6390_port_tag_remap, 4869 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4870 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4871 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4872 .port_set_ether_type = mv88e6351_port_set_ether_type, 4873 .port_pause_limit = mv88e6390_port_pause_limit, 4874 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4875 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4876 .port_get_cmode = mv88e6352_port_get_cmode, 4877 .port_set_cmode = mv88e6390_port_set_cmode, 4878 .port_setup_message_port = mv88e6xxx_setup_message_port, 4879 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4880 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4881 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4882 .stats_get_strings = mv88e6320_stats_get_strings, 4883 .stats_get_stats = mv88e6390_stats_get_stats, 4884 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4885 .set_egress_port = mv88e6390_g1_set_egress_port, 4886 .watchdog_ops = &mv88e6390_watchdog_ops, 4887 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4888 .pot_clear = mv88e6xxx_g2_pot_clear, 4889 .reset = mv88e6352_g1_reset, 4890 .rmu_disable = mv88e6390_g1_rmu_disable, 4891 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4892 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4893 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4894 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4895 .stu_getnext = mv88e6390_g1_stu_getnext, 4896 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4897 .serdes_power = mv88e6390_serdes_power, 4898 .serdes_get_lane = mv88e6390_serdes_get_lane, 4899 /* Check status register pause & lpa register */ 4900 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4901 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4902 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4903 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4904 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4905 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4906 .serdes_irq_status = mv88e6390_serdes_irq_status, 4907 .serdes_get_strings = mv88e6390_serdes_get_strings, 4908 .serdes_get_stats = mv88e6390_serdes_get_stats, 4909 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4910 .serdes_get_regs = mv88e6390_serdes_get_regs, 4911 .avb_ops = &mv88e6390_avb_ops, 4912 .ptp_ops = &mv88e6352_ptp_ops, 4913 .phylink_get_caps = mv88e6390_phylink_get_caps, 4914 }; 4915 4916 static const struct mv88e6xxx_ops mv88e6240_ops = { 4917 /* MV88E6XXX_FAMILY_6352 */ 4918 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4919 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4920 .irl_init_all = mv88e6352_g2_irl_init_all, 4921 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4922 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4923 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4924 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4925 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4926 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4927 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4928 .port_set_link = mv88e6xxx_port_set_link, 4929 .port_sync_link = mv88e6xxx_port_sync_link, 4930 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4931 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4932 .port_tag_remap = mv88e6095_port_tag_remap, 4933 .port_set_policy = mv88e6352_port_set_policy, 4934 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4935 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4936 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4937 .port_set_ether_type = mv88e6351_port_set_ether_type, 4938 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4939 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4940 .port_pause_limit = mv88e6097_port_pause_limit, 4941 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4942 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4943 .port_get_cmode = mv88e6352_port_get_cmode, 4944 .port_setup_message_port = mv88e6xxx_setup_message_port, 4945 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4946 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4947 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4948 .stats_get_strings = mv88e6095_stats_get_strings, 4949 .stats_get_stats = mv88e6095_stats_get_stats, 4950 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4951 .set_egress_port = mv88e6095_g1_set_egress_port, 4952 .watchdog_ops = &mv88e6097_watchdog_ops, 4953 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4954 .pot_clear = mv88e6xxx_g2_pot_clear, 4955 .reset = mv88e6352_g1_reset, 4956 .rmu_disable = mv88e6352_g1_rmu_disable, 4957 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4958 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4959 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4960 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4961 .stu_getnext = mv88e6352_g1_stu_getnext, 4962 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4963 .serdes_get_lane = mv88e6352_serdes_get_lane, 4964 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4965 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4966 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4967 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4968 .serdes_power = mv88e6352_serdes_power, 4969 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4970 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4971 .serdes_irq_status = mv88e6352_serdes_irq_status, 4972 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4973 .serdes_get_regs = mv88e6352_serdes_get_regs, 4974 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4975 .gpio_ops = &mv88e6352_gpio_ops, 4976 .avb_ops = &mv88e6352_avb_ops, 4977 .ptp_ops = &mv88e6352_ptp_ops, 4978 .phylink_get_caps = mv88e6352_phylink_get_caps, 4979 }; 4980 4981 static const struct mv88e6xxx_ops mv88e6250_ops = { 4982 /* MV88E6XXX_FAMILY_6250 */ 4983 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4984 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4985 .irl_init_all = mv88e6352_g2_irl_init_all, 4986 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4987 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4988 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4989 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4990 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4991 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4992 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4993 .port_set_link = mv88e6xxx_port_set_link, 4994 .port_sync_link = mv88e6xxx_port_sync_link, 4995 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4996 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4997 .port_tag_remap = mv88e6095_port_tag_remap, 4998 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4999 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5000 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5001 .port_set_ether_type = mv88e6351_port_set_ether_type, 5002 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5003 .port_pause_limit = mv88e6097_port_pause_limit, 5004 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5005 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5006 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5007 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 5008 .stats_get_strings = mv88e6250_stats_get_strings, 5009 .stats_get_stats = mv88e6250_stats_get_stats, 5010 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5011 .set_egress_port = mv88e6095_g1_set_egress_port, 5012 .watchdog_ops = &mv88e6250_watchdog_ops, 5013 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5014 .pot_clear = mv88e6xxx_g2_pot_clear, 5015 .reset = mv88e6250_g1_reset, 5016 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5017 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5018 .avb_ops = &mv88e6352_avb_ops, 5019 .ptp_ops = &mv88e6250_ptp_ops, 5020 .phylink_get_caps = mv88e6250_phylink_get_caps, 5021 }; 5022 5023 static const struct mv88e6xxx_ops mv88e6290_ops = { 5024 /* MV88E6XXX_FAMILY_6390 */ 5025 .setup_errata = mv88e6390_setup_errata, 5026 .irl_init_all = mv88e6390_g2_irl_init_all, 5027 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5028 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5029 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5030 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5031 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5032 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5033 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5034 .port_set_link = mv88e6xxx_port_set_link, 5035 .port_sync_link = mv88e6xxx_port_sync_link, 5036 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5037 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5038 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5039 .port_tag_remap = mv88e6390_port_tag_remap, 5040 .port_set_policy = mv88e6352_port_set_policy, 5041 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5042 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5043 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5044 .port_set_ether_type = mv88e6351_port_set_ether_type, 5045 .port_pause_limit = mv88e6390_port_pause_limit, 5046 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5047 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5048 .port_get_cmode = mv88e6352_port_get_cmode, 5049 .port_set_cmode = mv88e6390_port_set_cmode, 5050 .port_setup_message_port = mv88e6xxx_setup_message_port, 5051 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5052 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5053 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5054 .stats_get_strings = mv88e6320_stats_get_strings, 5055 .stats_get_stats = mv88e6390_stats_get_stats, 5056 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5057 .set_egress_port = mv88e6390_g1_set_egress_port, 5058 .watchdog_ops = &mv88e6390_watchdog_ops, 5059 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5060 .pot_clear = mv88e6xxx_g2_pot_clear, 5061 .reset = mv88e6352_g1_reset, 5062 .rmu_disable = mv88e6390_g1_rmu_disable, 5063 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5064 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5065 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5066 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5067 .stu_getnext = mv88e6390_g1_stu_getnext, 5068 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5069 .serdes_power = mv88e6390_serdes_power, 5070 .serdes_get_lane = mv88e6390_serdes_get_lane, 5071 /* Check status register pause & lpa register */ 5072 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5073 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5074 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5075 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5076 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5077 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5078 .serdes_irq_status = mv88e6390_serdes_irq_status, 5079 .serdes_get_strings = mv88e6390_serdes_get_strings, 5080 .serdes_get_stats = mv88e6390_serdes_get_stats, 5081 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5082 .serdes_get_regs = mv88e6390_serdes_get_regs, 5083 .gpio_ops = &mv88e6352_gpio_ops, 5084 .avb_ops = &mv88e6390_avb_ops, 5085 .ptp_ops = &mv88e6390_ptp_ops, 5086 .phylink_get_caps = mv88e6390_phylink_get_caps, 5087 }; 5088 5089 static const struct mv88e6xxx_ops mv88e6320_ops = { 5090 /* MV88E6XXX_FAMILY_6320 */ 5091 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5092 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5093 .irl_init_all = mv88e6352_g2_irl_init_all, 5094 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5095 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5096 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5097 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5098 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5099 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5100 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5101 .port_set_link = mv88e6xxx_port_set_link, 5102 .port_sync_link = mv88e6xxx_port_sync_link, 5103 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5104 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5105 .port_tag_remap = mv88e6095_port_tag_remap, 5106 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5107 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5108 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5109 .port_set_ether_type = mv88e6351_port_set_ether_type, 5110 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5111 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5112 .port_pause_limit = mv88e6097_port_pause_limit, 5113 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5114 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5115 .port_get_cmode = mv88e6352_port_get_cmode, 5116 .port_setup_message_port = mv88e6xxx_setup_message_port, 5117 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5118 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5119 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5120 .stats_get_strings = mv88e6320_stats_get_strings, 5121 .stats_get_stats = mv88e6320_stats_get_stats, 5122 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5123 .set_egress_port = mv88e6095_g1_set_egress_port, 5124 .watchdog_ops = &mv88e6390_watchdog_ops, 5125 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5126 .pot_clear = mv88e6xxx_g2_pot_clear, 5127 .reset = mv88e6352_g1_reset, 5128 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5129 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5130 .gpio_ops = &mv88e6352_gpio_ops, 5131 .avb_ops = &mv88e6352_avb_ops, 5132 .ptp_ops = &mv88e6352_ptp_ops, 5133 .phylink_get_caps = mv88e6185_phylink_get_caps, 5134 }; 5135 5136 static const struct mv88e6xxx_ops mv88e6321_ops = { 5137 /* MV88E6XXX_FAMILY_6320 */ 5138 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5139 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5140 .irl_init_all = mv88e6352_g2_irl_init_all, 5141 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5142 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5143 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5144 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5145 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5146 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5147 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5148 .port_set_link = mv88e6xxx_port_set_link, 5149 .port_sync_link = mv88e6xxx_port_sync_link, 5150 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5151 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5152 .port_tag_remap = mv88e6095_port_tag_remap, 5153 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5154 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5155 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5156 .port_set_ether_type = mv88e6351_port_set_ether_type, 5157 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5158 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5159 .port_pause_limit = mv88e6097_port_pause_limit, 5160 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5161 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5162 .port_get_cmode = mv88e6352_port_get_cmode, 5163 .port_setup_message_port = mv88e6xxx_setup_message_port, 5164 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5165 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5166 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5167 .stats_get_strings = mv88e6320_stats_get_strings, 5168 .stats_get_stats = mv88e6320_stats_get_stats, 5169 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5170 .set_egress_port = mv88e6095_g1_set_egress_port, 5171 .watchdog_ops = &mv88e6390_watchdog_ops, 5172 .reset = mv88e6352_g1_reset, 5173 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5174 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5175 .gpio_ops = &mv88e6352_gpio_ops, 5176 .avb_ops = &mv88e6352_avb_ops, 5177 .ptp_ops = &mv88e6352_ptp_ops, 5178 .phylink_get_caps = mv88e6185_phylink_get_caps, 5179 }; 5180 5181 static const struct mv88e6xxx_ops mv88e6341_ops = { 5182 /* MV88E6XXX_FAMILY_6341 */ 5183 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5184 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5185 .irl_init_all = mv88e6352_g2_irl_init_all, 5186 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5187 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5188 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5189 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5190 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5191 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5192 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5193 .port_set_link = mv88e6xxx_port_set_link, 5194 .port_sync_link = mv88e6xxx_port_sync_link, 5195 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5196 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5197 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5198 .port_tag_remap = mv88e6095_port_tag_remap, 5199 .port_set_policy = mv88e6352_port_set_policy, 5200 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5201 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5202 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5203 .port_set_ether_type = mv88e6351_port_set_ether_type, 5204 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5205 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5206 .port_pause_limit = mv88e6097_port_pause_limit, 5207 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5208 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5209 .port_get_cmode = mv88e6352_port_get_cmode, 5210 .port_set_cmode = mv88e6341_port_set_cmode, 5211 .port_setup_message_port = mv88e6xxx_setup_message_port, 5212 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5213 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5214 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5215 .stats_get_strings = mv88e6320_stats_get_strings, 5216 .stats_get_stats = mv88e6390_stats_get_stats, 5217 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5218 .set_egress_port = mv88e6390_g1_set_egress_port, 5219 .watchdog_ops = &mv88e6390_watchdog_ops, 5220 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5221 .pot_clear = mv88e6xxx_g2_pot_clear, 5222 .reset = mv88e6352_g1_reset, 5223 .rmu_disable = mv88e6390_g1_rmu_disable, 5224 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5225 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5226 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5227 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5228 .stu_getnext = mv88e6352_g1_stu_getnext, 5229 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5230 .serdes_power = mv88e6390_serdes_power, 5231 .serdes_get_lane = mv88e6341_serdes_get_lane, 5232 /* Check status register pause & lpa register */ 5233 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5234 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5235 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5236 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5237 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5238 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5239 .serdes_irq_status = mv88e6390_serdes_irq_status, 5240 .gpio_ops = &mv88e6352_gpio_ops, 5241 .avb_ops = &mv88e6390_avb_ops, 5242 .ptp_ops = &mv88e6352_ptp_ops, 5243 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5244 .serdes_get_strings = mv88e6390_serdes_get_strings, 5245 .serdes_get_stats = mv88e6390_serdes_get_stats, 5246 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5247 .serdes_get_regs = mv88e6390_serdes_get_regs, 5248 .phylink_get_caps = mv88e6341_phylink_get_caps, 5249 }; 5250 5251 static const struct mv88e6xxx_ops mv88e6350_ops = { 5252 /* MV88E6XXX_FAMILY_6351 */ 5253 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5254 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5255 .irl_init_all = mv88e6352_g2_irl_init_all, 5256 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5257 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5258 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5259 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5260 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5261 .port_set_link = mv88e6xxx_port_set_link, 5262 .port_sync_link = mv88e6xxx_port_sync_link, 5263 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5264 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5265 .port_tag_remap = mv88e6095_port_tag_remap, 5266 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5267 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5268 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5269 .port_set_ether_type = mv88e6351_port_set_ether_type, 5270 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5271 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5272 .port_pause_limit = mv88e6097_port_pause_limit, 5273 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5274 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5275 .port_get_cmode = mv88e6352_port_get_cmode, 5276 .port_setup_message_port = mv88e6xxx_setup_message_port, 5277 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5278 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5279 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5280 .stats_get_strings = mv88e6095_stats_get_strings, 5281 .stats_get_stats = mv88e6095_stats_get_stats, 5282 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5283 .set_egress_port = mv88e6095_g1_set_egress_port, 5284 .watchdog_ops = &mv88e6097_watchdog_ops, 5285 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5286 .pot_clear = mv88e6xxx_g2_pot_clear, 5287 .reset = mv88e6352_g1_reset, 5288 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5289 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5290 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5291 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5292 .stu_getnext = mv88e6352_g1_stu_getnext, 5293 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5294 .phylink_get_caps = mv88e6185_phylink_get_caps, 5295 }; 5296 5297 static const struct mv88e6xxx_ops mv88e6351_ops = { 5298 /* MV88E6XXX_FAMILY_6351 */ 5299 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5300 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5301 .irl_init_all = mv88e6352_g2_irl_init_all, 5302 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5303 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5304 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5305 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5306 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5307 .port_set_link = mv88e6xxx_port_set_link, 5308 .port_sync_link = mv88e6xxx_port_sync_link, 5309 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5310 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5311 .port_tag_remap = mv88e6095_port_tag_remap, 5312 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5313 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5314 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5315 .port_set_ether_type = mv88e6351_port_set_ether_type, 5316 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5317 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5318 .port_pause_limit = mv88e6097_port_pause_limit, 5319 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5320 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5321 .port_get_cmode = mv88e6352_port_get_cmode, 5322 .port_setup_message_port = mv88e6xxx_setup_message_port, 5323 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5324 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5325 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5326 .stats_get_strings = mv88e6095_stats_get_strings, 5327 .stats_get_stats = mv88e6095_stats_get_stats, 5328 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5329 .set_egress_port = mv88e6095_g1_set_egress_port, 5330 .watchdog_ops = &mv88e6097_watchdog_ops, 5331 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5332 .pot_clear = mv88e6xxx_g2_pot_clear, 5333 .reset = mv88e6352_g1_reset, 5334 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5335 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5336 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5337 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5338 .stu_getnext = mv88e6352_g1_stu_getnext, 5339 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5340 .avb_ops = &mv88e6352_avb_ops, 5341 .ptp_ops = &mv88e6352_ptp_ops, 5342 .phylink_get_caps = mv88e6185_phylink_get_caps, 5343 }; 5344 5345 static const struct mv88e6xxx_ops mv88e6352_ops = { 5346 /* MV88E6XXX_FAMILY_6352 */ 5347 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5348 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5349 .irl_init_all = mv88e6352_g2_irl_init_all, 5350 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5351 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5352 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5353 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5354 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5355 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5356 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5357 .port_set_link = mv88e6xxx_port_set_link, 5358 .port_sync_link = mv88e6xxx_port_sync_link, 5359 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5360 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5361 .port_tag_remap = mv88e6095_port_tag_remap, 5362 .port_set_policy = mv88e6352_port_set_policy, 5363 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5364 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5365 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5366 .port_set_ether_type = mv88e6351_port_set_ether_type, 5367 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5368 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5369 .port_pause_limit = mv88e6097_port_pause_limit, 5370 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5371 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5372 .port_get_cmode = mv88e6352_port_get_cmode, 5373 .port_setup_message_port = mv88e6xxx_setup_message_port, 5374 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5375 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5376 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5377 .stats_get_strings = mv88e6095_stats_get_strings, 5378 .stats_get_stats = mv88e6095_stats_get_stats, 5379 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5380 .set_egress_port = mv88e6095_g1_set_egress_port, 5381 .watchdog_ops = &mv88e6097_watchdog_ops, 5382 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5383 .pot_clear = mv88e6xxx_g2_pot_clear, 5384 .reset = mv88e6352_g1_reset, 5385 .rmu_disable = mv88e6352_g1_rmu_disable, 5386 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5387 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5388 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5389 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5390 .stu_getnext = mv88e6352_g1_stu_getnext, 5391 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5392 .serdes_get_lane = mv88e6352_serdes_get_lane, 5393 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 5394 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 5395 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 5396 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 5397 .serdes_power = mv88e6352_serdes_power, 5398 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5399 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 5400 .serdes_irq_status = mv88e6352_serdes_irq_status, 5401 .gpio_ops = &mv88e6352_gpio_ops, 5402 .avb_ops = &mv88e6352_avb_ops, 5403 .ptp_ops = &mv88e6352_ptp_ops, 5404 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5405 .serdes_get_strings = mv88e6352_serdes_get_strings, 5406 .serdes_get_stats = mv88e6352_serdes_get_stats, 5407 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5408 .serdes_get_regs = mv88e6352_serdes_get_regs, 5409 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5410 .phylink_get_caps = mv88e6352_phylink_get_caps, 5411 }; 5412 5413 static const struct mv88e6xxx_ops mv88e6390_ops = { 5414 /* MV88E6XXX_FAMILY_6390 */ 5415 .setup_errata = mv88e6390_setup_errata, 5416 .irl_init_all = mv88e6390_g2_irl_init_all, 5417 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5418 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5419 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5420 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5421 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5422 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5423 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5424 .port_set_link = mv88e6xxx_port_set_link, 5425 .port_sync_link = mv88e6xxx_port_sync_link, 5426 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5427 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5428 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5429 .port_tag_remap = mv88e6390_port_tag_remap, 5430 .port_set_policy = mv88e6352_port_set_policy, 5431 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5432 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5433 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5434 .port_set_ether_type = mv88e6351_port_set_ether_type, 5435 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5436 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5437 .port_pause_limit = mv88e6390_port_pause_limit, 5438 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5439 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5440 .port_get_cmode = mv88e6352_port_get_cmode, 5441 .port_set_cmode = mv88e6390_port_set_cmode, 5442 .port_setup_message_port = mv88e6xxx_setup_message_port, 5443 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5444 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5445 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5446 .stats_get_strings = mv88e6320_stats_get_strings, 5447 .stats_get_stats = mv88e6390_stats_get_stats, 5448 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5449 .set_egress_port = mv88e6390_g1_set_egress_port, 5450 .watchdog_ops = &mv88e6390_watchdog_ops, 5451 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5452 .pot_clear = mv88e6xxx_g2_pot_clear, 5453 .reset = mv88e6352_g1_reset, 5454 .rmu_disable = mv88e6390_g1_rmu_disable, 5455 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5456 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5457 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5458 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5459 .stu_getnext = mv88e6390_g1_stu_getnext, 5460 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5461 .serdes_power = mv88e6390_serdes_power, 5462 .serdes_get_lane = mv88e6390_serdes_get_lane, 5463 /* Check status register pause & lpa register */ 5464 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5465 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5466 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5467 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5468 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5469 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5470 .serdes_irq_status = mv88e6390_serdes_irq_status, 5471 .gpio_ops = &mv88e6352_gpio_ops, 5472 .avb_ops = &mv88e6390_avb_ops, 5473 .ptp_ops = &mv88e6390_ptp_ops, 5474 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5475 .serdes_get_strings = mv88e6390_serdes_get_strings, 5476 .serdes_get_stats = mv88e6390_serdes_get_stats, 5477 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5478 .serdes_get_regs = mv88e6390_serdes_get_regs, 5479 .phylink_get_caps = mv88e6390_phylink_get_caps, 5480 }; 5481 5482 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5483 /* MV88E6XXX_FAMILY_6390 */ 5484 .setup_errata = mv88e6390_setup_errata, 5485 .irl_init_all = mv88e6390_g2_irl_init_all, 5486 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5487 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5488 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5489 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5490 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5491 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5492 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5493 .port_set_link = mv88e6xxx_port_set_link, 5494 .port_sync_link = mv88e6xxx_port_sync_link, 5495 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5496 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5497 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5498 .port_tag_remap = mv88e6390_port_tag_remap, 5499 .port_set_policy = mv88e6352_port_set_policy, 5500 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5501 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5502 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5503 .port_set_ether_type = mv88e6351_port_set_ether_type, 5504 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5505 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5506 .port_pause_limit = mv88e6390_port_pause_limit, 5507 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5508 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5509 .port_get_cmode = mv88e6352_port_get_cmode, 5510 .port_set_cmode = mv88e6390x_port_set_cmode, 5511 .port_setup_message_port = mv88e6xxx_setup_message_port, 5512 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5513 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5514 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5515 .stats_get_strings = mv88e6320_stats_get_strings, 5516 .stats_get_stats = mv88e6390_stats_get_stats, 5517 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5518 .set_egress_port = mv88e6390_g1_set_egress_port, 5519 .watchdog_ops = &mv88e6390_watchdog_ops, 5520 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5521 .pot_clear = mv88e6xxx_g2_pot_clear, 5522 .reset = mv88e6352_g1_reset, 5523 .rmu_disable = mv88e6390_g1_rmu_disable, 5524 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5525 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5526 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5527 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5528 .stu_getnext = mv88e6390_g1_stu_getnext, 5529 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5530 .serdes_power = mv88e6390_serdes_power, 5531 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5532 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5533 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5534 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5535 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5536 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5537 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5538 .serdes_irq_status = mv88e6390_serdes_irq_status, 5539 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5540 .serdes_get_strings = mv88e6390_serdes_get_strings, 5541 .serdes_get_stats = mv88e6390_serdes_get_stats, 5542 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5543 .serdes_get_regs = mv88e6390_serdes_get_regs, 5544 .gpio_ops = &mv88e6352_gpio_ops, 5545 .avb_ops = &mv88e6390_avb_ops, 5546 .ptp_ops = &mv88e6390_ptp_ops, 5547 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5548 }; 5549 5550 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5551 /* MV88E6XXX_FAMILY_6393 */ 5552 .setup_errata = mv88e6393x_serdes_setup_errata, 5553 .irl_init_all = mv88e6390_g2_irl_init_all, 5554 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5555 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5556 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5557 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5558 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5559 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5560 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5561 .port_set_link = mv88e6xxx_port_set_link, 5562 .port_sync_link = mv88e6xxx_port_sync_link, 5563 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5564 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5565 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5566 .port_tag_remap = mv88e6390_port_tag_remap, 5567 .port_set_policy = mv88e6393x_port_set_policy, 5568 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5569 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5570 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5571 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5572 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5573 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5574 .port_pause_limit = mv88e6390_port_pause_limit, 5575 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5576 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5577 .port_get_cmode = mv88e6352_port_get_cmode, 5578 .port_set_cmode = mv88e6393x_port_set_cmode, 5579 .port_setup_message_port = mv88e6xxx_setup_message_port, 5580 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5581 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5582 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5583 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5584 .stats_get_strings = mv88e6320_stats_get_strings, 5585 .stats_get_stats = mv88e6390_stats_get_stats, 5586 /* .set_cpu_port is missing because this family does not support a global 5587 * CPU port, only per port CPU port which is set via 5588 * .port_set_upstream_port method. 5589 */ 5590 .set_egress_port = mv88e6393x_set_egress_port, 5591 .watchdog_ops = &mv88e6390_watchdog_ops, 5592 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5593 .pot_clear = mv88e6xxx_g2_pot_clear, 5594 .reset = mv88e6352_g1_reset, 5595 .rmu_disable = mv88e6390_g1_rmu_disable, 5596 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5597 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5598 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5599 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5600 .stu_getnext = mv88e6390_g1_stu_getnext, 5601 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5602 .serdes_power = mv88e6393x_serdes_power, 5603 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5604 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 5605 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5606 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5607 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5608 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5609 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 5610 .serdes_irq_status = mv88e6393x_serdes_irq_status, 5611 /* TODO: serdes stats */ 5612 .gpio_ops = &mv88e6352_gpio_ops, 5613 .avb_ops = &mv88e6390_avb_ops, 5614 .ptp_ops = &mv88e6352_ptp_ops, 5615 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5616 }; 5617 5618 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5619 [MV88E6085] = { 5620 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5621 .family = MV88E6XXX_FAMILY_6097, 5622 .name = "Marvell 88E6085", 5623 .num_databases = 4096, 5624 .num_macs = 8192, 5625 .num_ports = 10, 5626 .num_internal_phys = 5, 5627 .max_vid = 4095, 5628 .max_sid = 63, 5629 .port_base_addr = 0x10, 5630 .phy_base_addr = 0x0, 5631 .global1_addr = 0x1b, 5632 .global2_addr = 0x1c, 5633 .age_time_coeff = 15000, 5634 .g1_irqs = 8, 5635 .g2_irqs = 10, 5636 .atu_move_port_mask = 0xf, 5637 .pvt = true, 5638 .multi_chip = true, 5639 .ops = &mv88e6085_ops, 5640 }, 5641 5642 [MV88E6095] = { 5643 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5644 .family = MV88E6XXX_FAMILY_6095, 5645 .name = "Marvell 88E6095/88E6095F", 5646 .num_databases = 256, 5647 .num_macs = 8192, 5648 .num_ports = 11, 5649 .num_internal_phys = 0, 5650 .max_vid = 4095, 5651 .port_base_addr = 0x10, 5652 .phy_base_addr = 0x0, 5653 .global1_addr = 0x1b, 5654 .global2_addr = 0x1c, 5655 .age_time_coeff = 15000, 5656 .g1_irqs = 8, 5657 .atu_move_port_mask = 0xf, 5658 .multi_chip = true, 5659 .ops = &mv88e6095_ops, 5660 }, 5661 5662 [MV88E6097] = { 5663 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5664 .family = MV88E6XXX_FAMILY_6097, 5665 .name = "Marvell 88E6097/88E6097F", 5666 .num_databases = 4096, 5667 .num_macs = 8192, 5668 .num_ports = 11, 5669 .num_internal_phys = 8, 5670 .max_vid = 4095, 5671 .max_sid = 63, 5672 .port_base_addr = 0x10, 5673 .phy_base_addr = 0x0, 5674 .global1_addr = 0x1b, 5675 .global2_addr = 0x1c, 5676 .age_time_coeff = 15000, 5677 .g1_irqs = 8, 5678 .g2_irqs = 10, 5679 .atu_move_port_mask = 0xf, 5680 .pvt = true, 5681 .multi_chip = true, 5682 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5683 .ops = &mv88e6097_ops, 5684 }, 5685 5686 [MV88E6123] = { 5687 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5688 .family = MV88E6XXX_FAMILY_6165, 5689 .name = "Marvell 88E6123", 5690 .num_databases = 4096, 5691 .num_macs = 1024, 5692 .num_ports = 3, 5693 .num_internal_phys = 5, 5694 .max_vid = 4095, 5695 .max_sid = 63, 5696 .port_base_addr = 0x10, 5697 .phy_base_addr = 0x0, 5698 .global1_addr = 0x1b, 5699 .global2_addr = 0x1c, 5700 .age_time_coeff = 15000, 5701 .g1_irqs = 9, 5702 .g2_irqs = 10, 5703 .atu_move_port_mask = 0xf, 5704 .pvt = true, 5705 .multi_chip = true, 5706 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5707 .ops = &mv88e6123_ops, 5708 }, 5709 5710 [MV88E6131] = { 5711 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5712 .family = MV88E6XXX_FAMILY_6185, 5713 .name = "Marvell 88E6131", 5714 .num_databases = 256, 5715 .num_macs = 8192, 5716 .num_ports = 8, 5717 .num_internal_phys = 0, 5718 .max_vid = 4095, 5719 .port_base_addr = 0x10, 5720 .phy_base_addr = 0x0, 5721 .global1_addr = 0x1b, 5722 .global2_addr = 0x1c, 5723 .age_time_coeff = 15000, 5724 .g1_irqs = 9, 5725 .atu_move_port_mask = 0xf, 5726 .multi_chip = true, 5727 .ops = &mv88e6131_ops, 5728 }, 5729 5730 [MV88E6141] = { 5731 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5732 .family = MV88E6XXX_FAMILY_6341, 5733 .name = "Marvell 88E6141", 5734 .num_databases = 4096, 5735 .num_macs = 2048, 5736 .num_ports = 6, 5737 .num_internal_phys = 5, 5738 .num_gpio = 11, 5739 .max_vid = 4095, 5740 .max_sid = 63, 5741 .port_base_addr = 0x10, 5742 .phy_base_addr = 0x10, 5743 .global1_addr = 0x1b, 5744 .global2_addr = 0x1c, 5745 .age_time_coeff = 3750, 5746 .atu_move_port_mask = 0x1f, 5747 .g1_irqs = 9, 5748 .g2_irqs = 10, 5749 .pvt = true, 5750 .multi_chip = true, 5751 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5752 .ops = &mv88e6141_ops, 5753 }, 5754 5755 [MV88E6161] = { 5756 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5757 .family = MV88E6XXX_FAMILY_6165, 5758 .name = "Marvell 88E6161", 5759 .num_databases = 4096, 5760 .num_macs = 1024, 5761 .num_ports = 6, 5762 .num_internal_phys = 5, 5763 .max_vid = 4095, 5764 .max_sid = 63, 5765 .port_base_addr = 0x10, 5766 .phy_base_addr = 0x0, 5767 .global1_addr = 0x1b, 5768 .global2_addr = 0x1c, 5769 .age_time_coeff = 15000, 5770 .g1_irqs = 9, 5771 .g2_irqs = 10, 5772 .atu_move_port_mask = 0xf, 5773 .pvt = true, 5774 .multi_chip = true, 5775 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5776 .ptp_support = true, 5777 .ops = &mv88e6161_ops, 5778 }, 5779 5780 [MV88E6165] = { 5781 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5782 .family = MV88E6XXX_FAMILY_6165, 5783 .name = "Marvell 88E6165", 5784 .num_databases = 4096, 5785 .num_macs = 8192, 5786 .num_ports = 6, 5787 .num_internal_phys = 0, 5788 .max_vid = 4095, 5789 .max_sid = 63, 5790 .port_base_addr = 0x10, 5791 .phy_base_addr = 0x0, 5792 .global1_addr = 0x1b, 5793 .global2_addr = 0x1c, 5794 .age_time_coeff = 15000, 5795 .g1_irqs = 9, 5796 .g2_irqs = 10, 5797 .atu_move_port_mask = 0xf, 5798 .pvt = true, 5799 .multi_chip = true, 5800 .ptp_support = true, 5801 .ops = &mv88e6165_ops, 5802 }, 5803 5804 [MV88E6171] = { 5805 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5806 .family = MV88E6XXX_FAMILY_6351, 5807 .name = "Marvell 88E6171", 5808 .num_databases = 4096, 5809 .num_macs = 8192, 5810 .num_ports = 7, 5811 .num_internal_phys = 5, 5812 .max_vid = 4095, 5813 .max_sid = 63, 5814 .port_base_addr = 0x10, 5815 .phy_base_addr = 0x0, 5816 .global1_addr = 0x1b, 5817 .global2_addr = 0x1c, 5818 .age_time_coeff = 15000, 5819 .g1_irqs = 9, 5820 .g2_irqs = 10, 5821 .atu_move_port_mask = 0xf, 5822 .pvt = true, 5823 .multi_chip = true, 5824 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5825 .ops = &mv88e6171_ops, 5826 }, 5827 5828 [MV88E6172] = { 5829 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5830 .family = MV88E6XXX_FAMILY_6352, 5831 .name = "Marvell 88E6172", 5832 .num_databases = 4096, 5833 .num_macs = 8192, 5834 .num_ports = 7, 5835 .num_internal_phys = 5, 5836 .num_gpio = 15, 5837 .max_vid = 4095, 5838 .max_sid = 63, 5839 .port_base_addr = 0x10, 5840 .phy_base_addr = 0x0, 5841 .global1_addr = 0x1b, 5842 .global2_addr = 0x1c, 5843 .age_time_coeff = 15000, 5844 .g1_irqs = 9, 5845 .g2_irqs = 10, 5846 .atu_move_port_mask = 0xf, 5847 .pvt = true, 5848 .multi_chip = true, 5849 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5850 .ops = &mv88e6172_ops, 5851 }, 5852 5853 [MV88E6175] = { 5854 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5855 .family = MV88E6XXX_FAMILY_6351, 5856 .name = "Marvell 88E6175", 5857 .num_databases = 4096, 5858 .num_macs = 8192, 5859 .num_ports = 7, 5860 .num_internal_phys = 5, 5861 .max_vid = 4095, 5862 .max_sid = 63, 5863 .port_base_addr = 0x10, 5864 .phy_base_addr = 0x0, 5865 .global1_addr = 0x1b, 5866 .global2_addr = 0x1c, 5867 .age_time_coeff = 15000, 5868 .g1_irqs = 9, 5869 .g2_irqs = 10, 5870 .atu_move_port_mask = 0xf, 5871 .pvt = true, 5872 .multi_chip = true, 5873 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5874 .ops = &mv88e6175_ops, 5875 }, 5876 5877 [MV88E6176] = { 5878 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5879 .family = MV88E6XXX_FAMILY_6352, 5880 .name = "Marvell 88E6176", 5881 .num_databases = 4096, 5882 .num_macs = 8192, 5883 .num_ports = 7, 5884 .num_internal_phys = 5, 5885 .num_gpio = 15, 5886 .max_vid = 4095, 5887 .max_sid = 63, 5888 .port_base_addr = 0x10, 5889 .phy_base_addr = 0x0, 5890 .global1_addr = 0x1b, 5891 .global2_addr = 0x1c, 5892 .age_time_coeff = 15000, 5893 .g1_irqs = 9, 5894 .g2_irqs = 10, 5895 .atu_move_port_mask = 0xf, 5896 .pvt = true, 5897 .multi_chip = true, 5898 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5899 .ops = &mv88e6176_ops, 5900 }, 5901 5902 [MV88E6185] = { 5903 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5904 .family = MV88E6XXX_FAMILY_6185, 5905 .name = "Marvell 88E6185", 5906 .num_databases = 256, 5907 .num_macs = 8192, 5908 .num_ports = 10, 5909 .num_internal_phys = 0, 5910 .max_vid = 4095, 5911 .port_base_addr = 0x10, 5912 .phy_base_addr = 0x0, 5913 .global1_addr = 0x1b, 5914 .global2_addr = 0x1c, 5915 .age_time_coeff = 15000, 5916 .g1_irqs = 8, 5917 .atu_move_port_mask = 0xf, 5918 .multi_chip = true, 5919 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5920 .ops = &mv88e6185_ops, 5921 }, 5922 5923 [MV88E6190] = { 5924 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5925 .family = MV88E6XXX_FAMILY_6390, 5926 .name = "Marvell 88E6190", 5927 .num_databases = 4096, 5928 .num_macs = 16384, 5929 .num_ports = 11, /* 10 + Z80 */ 5930 .num_internal_phys = 9, 5931 .num_gpio = 16, 5932 .max_vid = 8191, 5933 .max_sid = 63, 5934 .port_base_addr = 0x0, 5935 .phy_base_addr = 0x0, 5936 .global1_addr = 0x1b, 5937 .global2_addr = 0x1c, 5938 .age_time_coeff = 3750, 5939 .g1_irqs = 9, 5940 .g2_irqs = 14, 5941 .pvt = true, 5942 .multi_chip = true, 5943 .atu_move_port_mask = 0x1f, 5944 .ops = &mv88e6190_ops, 5945 }, 5946 5947 [MV88E6190X] = { 5948 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5949 .family = MV88E6XXX_FAMILY_6390, 5950 .name = "Marvell 88E6190X", 5951 .num_databases = 4096, 5952 .num_macs = 16384, 5953 .num_ports = 11, /* 10 + Z80 */ 5954 .num_internal_phys = 9, 5955 .num_gpio = 16, 5956 .max_vid = 8191, 5957 .max_sid = 63, 5958 .port_base_addr = 0x0, 5959 .phy_base_addr = 0x0, 5960 .global1_addr = 0x1b, 5961 .global2_addr = 0x1c, 5962 .age_time_coeff = 3750, 5963 .g1_irqs = 9, 5964 .g2_irqs = 14, 5965 .atu_move_port_mask = 0x1f, 5966 .pvt = true, 5967 .multi_chip = true, 5968 .ops = &mv88e6190x_ops, 5969 }, 5970 5971 [MV88E6191] = { 5972 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5973 .family = MV88E6XXX_FAMILY_6390, 5974 .name = "Marvell 88E6191", 5975 .num_databases = 4096, 5976 .num_macs = 16384, 5977 .num_ports = 11, /* 10 + Z80 */ 5978 .num_internal_phys = 9, 5979 .max_vid = 8191, 5980 .max_sid = 63, 5981 .port_base_addr = 0x0, 5982 .phy_base_addr = 0x0, 5983 .global1_addr = 0x1b, 5984 .global2_addr = 0x1c, 5985 .age_time_coeff = 3750, 5986 .g1_irqs = 9, 5987 .g2_irqs = 14, 5988 .atu_move_port_mask = 0x1f, 5989 .pvt = true, 5990 .multi_chip = true, 5991 .ptp_support = true, 5992 .ops = &mv88e6191_ops, 5993 }, 5994 5995 [MV88E6191X] = { 5996 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5997 .family = MV88E6XXX_FAMILY_6393, 5998 .name = "Marvell 88E6191X", 5999 .num_databases = 4096, 6000 .num_ports = 11, /* 10 + Z80 */ 6001 .num_internal_phys = 9, 6002 .max_vid = 8191, 6003 .max_sid = 63, 6004 .port_base_addr = 0x0, 6005 .phy_base_addr = 0x0, 6006 .global1_addr = 0x1b, 6007 .global2_addr = 0x1c, 6008 .age_time_coeff = 3750, 6009 .g1_irqs = 10, 6010 .g2_irqs = 14, 6011 .atu_move_port_mask = 0x1f, 6012 .pvt = true, 6013 .multi_chip = true, 6014 .ptp_support = true, 6015 .ops = &mv88e6393x_ops, 6016 }, 6017 6018 [MV88E6193X] = { 6019 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 6020 .family = MV88E6XXX_FAMILY_6393, 6021 .name = "Marvell 88E6193X", 6022 .num_databases = 4096, 6023 .num_ports = 11, /* 10 + Z80 */ 6024 .num_internal_phys = 9, 6025 .max_vid = 8191, 6026 .max_sid = 63, 6027 .port_base_addr = 0x0, 6028 .phy_base_addr = 0x0, 6029 .global1_addr = 0x1b, 6030 .global2_addr = 0x1c, 6031 .age_time_coeff = 3750, 6032 .g1_irqs = 10, 6033 .g2_irqs = 14, 6034 .atu_move_port_mask = 0x1f, 6035 .pvt = true, 6036 .multi_chip = true, 6037 .ptp_support = true, 6038 .ops = &mv88e6393x_ops, 6039 }, 6040 6041 [MV88E6220] = { 6042 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 6043 .family = MV88E6XXX_FAMILY_6250, 6044 .name = "Marvell 88E6220", 6045 .num_databases = 64, 6046 6047 /* Ports 2-4 are not routed to pins 6048 * => usable ports 0, 1, 5, 6 6049 */ 6050 .num_ports = 7, 6051 .num_internal_phys = 2, 6052 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 6053 .max_vid = 4095, 6054 .port_base_addr = 0x08, 6055 .phy_base_addr = 0x00, 6056 .global1_addr = 0x0f, 6057 .global2_addr = 0x07, 6058 .age_time_coeff = 15000, 6059 .g1_irqs = 9, 6060 .g2_irqs = 10, 6061 .atu_move_port_mask = 0xf, 6062 .dual_chip = true, 6063 .ptp_support = true, 6064 .ops = &mv88e6250_ops, 6065 }, 6066 6067 [MV88E6240] = { 6068 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 6069 .family = MV88E6XXX_FAMILY_6352, 6070 .name = "Marvell 88E6240", 6071 .num_databases = 4096, 6072 .num_macs = 8192, 6073 .num_ports = 7, 6074 .num_internal_phys = 5, 6075 .num_gpio = 15, 6076 .max_vid = 4095, 6077 .max_sid = 63, 6078 .port_base_addr = 0x10, 6079 .phy_base_addr = 0x0, 6080 .global1_addr = 0x1b, 6081 .global2_addr = 0x1c, 6082 .age_time_coeff = 15000, 6083 .g1_irqs = 9, 6084 .g2_irqs = 10, 6085 .atu_move_port_mask = 0xf, 6086 .pvt = true, 6087 .multi_chip = true, 6088 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6089 .ptp_support = true, 6090 .ops = &mv88e6240_ops, 6091 }, 6092 6093 [MV88E6250] = { 6094 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6095 .family = MV88E6XXX_FAMILY_6250, 6096 .name = "Marvell 88E6250", 6097 .num_databases = 64, 6098 .num_ports = 7, 6099 .num_internal_phys = 5, 6100 .max_vid = 4095, 6101 .port_base_addr = 0x08, 6102 .phy_base_addr = 0x00, 6103 .global1_addr = 0x0f, 6104 .global2_addr = 0x07, 6105 .age_time_coeff = 15000, 6106 .g1_irqs = 9, 6107 .g2_irqs = 10, 6108 .atu_move_port_mask = 0xf, 6109 .dual_chip = true, 6110 .ptp_support = true, 6111 .ops = &mv88e6250_ops, 6112 }, 6113 6114 [MV88E6290] = { 6115 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6116 .family = MV88E6XXX_FAMILY_6390, 6117 .name = "Marvell 88E6290", 6118 .num_databases = 4096, 6119 .num_ports = 11, /* 10 + Z80 */ 6120 .num_internal_phys = 9, 6121 .num_gpio = 16, 6122 .max_vid = 8191, 6123 .max_sid = 63, 6124 .port_base_addr = 0x0, 6125 .phy_base_addr = 0x0, 6126 .global1_addr = 0x1b, 6127 .global2_addr = 0x1c, 6128 .age_time_coeff = 3750, 6129 .g1_irqs = 9, 6130 .g2_irqs = 14, 6131 .atu_move_port_mask = 0x1f, 6132 .pvt = true, 6133 .multi_chip = true, 6134 .ptp_support = true, 6135 .ops = &mv88e6290_ops, 6136 }, 6137 6138 [MV88E6320] = { 6139 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6140 .family = MV88E6XXX_FAMILY_6320, 6141 .name = "Marvell 88E6320", 6142 .num_databases = 4096, 6143 .num_macs = 8192, 6144 .num_ports = 7, 6145 .num_internal_phys = 5, 6146 .num_gpio = 15, 6147 .max_vid = 4095, 6148 .port_base_addr = 0x10, 6149 .phy_base_addr = 0x0, 6150 .global1_addr = 0x1b, 6151 .global2_addr = 0x1c, 6152 .age_time_coeff = 15000, 6153 .g1_irqs = 8, 6154 .g2_irqs = 10, 6155 .atu_move_port_mask = 0xf, 6156 .pvt = true, 6157 .multi_chip = true, 6158 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6159 .ptp_support = true, 6160 .ops = &mv88e6320_ops, 6161 }, 6162 6163 [MV88E6321] = { 6164 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6165 .family = MV88E6XXX_FAMILY_6320, 6166 .name = "Marvell 88E6321", 6167 .num_databases = 4096, 6168 .num_macs = 8192, 6169 .num_ports = 7, 6170 .num_internal_phys = 5, 6171 .num_gpio = 15, 6172 .max_vid = 4095, 6173 .port_base_addr = 0x10, 6174 .phy_base_addr = 0x0, 6175 .global1_addr = 0x1b, 6176 .global2_addr = 0x1c, 6177 .age_time_coeff = 15000, 6178 .g1_irqs = 8, 6179 .g2_irqs = 10, 6180 .atu_move_port_mask = 0xf, 6181 .multi_chip = true, 6182 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6183 .ptp_support = true, 6184 .ops = &mv88e6321_ops, 6185 }, 6186 6187 [MV88E6341] = { 6188 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6189 .family = MV88E6XXX_FAMILY_6341, 6190 .name = "Marvell 88E6341", 6191 .num_databases = 4096, 6192 .num_macs = 2048, 6193 .num_internal_phys = 5, 6194 .num_ports = 6, 6195 .num_gpio = 11, 6196 .max_vid = 4095, 6197 .max_sid = 63, 6198 .port_base_addr = 0x10, 6199 .phy_base_addr = 0x10, 6200 .global1_addr = 0x1b, 6201 .global2_addr = 0x1c, 6202 .age_time_coeff = 3750, 6203 .atu_move_port_mask = 0x1f, 6204 .g1_irqs = 9, 6205 .g2_irqs = 10, 6206 .pvt = true, 6207 .multi_chip = true, 6208 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6209 .ptp_support = true, 6210 .ops = &mv88e6341_ops, 6211 }, 6212 6213 [MV88E6350] = { 6214 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6215 .family = MV88E6XXX_FAMILY_6351, 6216 .name = "Marvell 88E6350", 6217 .num_databases = 4096, 6218 .num_macs = 8192, 6219 .num_ports = 7, 6220 .num_internal_phys = 5, 6221 .max_vid = 4095, 6222 .max_sid = 63, 6223 .port_base_addr = 0x10, 6224 .phy_base_addr = 0x0, 6225 .global1_addr = 0x1b, 6226 .global2_addr = 0x1c, 6227 .age_time_coeff = 15000, 6228 .g1_irqs = 9, 6229 .g2_irqs = 10, 6230 .atu_move_port_mask = 0xf, 6231 .pvt = true, 6232 .multi_chip = true, 6233 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6234 .ops = &mv88e6350_ops, 6235 }, 6236 6237 [MV88E6351] = { 6238 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6239 .family = MV88E6XXX_FAMILY_6351, 6240 .name = "Marvell 88E6351", 6241 .num_databases = 4096, 6242 .num_macs = 8192, 6243 .num_ports = 7, 6244 .num_internal_phys = 5, 6245 .max_vid = 4095, 6246 .max_sid = 63, 6247 .port_base_addr = 0x10, 6248 .phy_base_addr = 0x0, 6249 .global1_addr = 0x1b, 6250 .global2_addr = 0x1c, 6251 .age_time_coeff = 15000, 6252 .g1_irqs = 9, 6253 .g2_irqs = 10, 6254 .atu_move_port_mask = 0xf, 6255 .pvt = true, 6256 .multi_chip = true, 6257 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6258 .ops = &mv88e6351_ops, 6259 }, 6260 6261 [MV88E6352] = { 6262 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6263 .family = MV88E6XXX_FAMILY_6352, 6264 .name = "Marvell 88E6352", 6265 .num_databases = 4096, 6266 .num_macs = 8192, 6267 .num_ports = 7, 6268 .num_internal_phys = 5, 6269 .num_gpio = 15, 6270 .max_vid = 4095, 6271 .max_sid = 63, 6272 .port_base_addr = 0x10, 6273 .phy_base_addr = 0x0, 6274 .global1_addr = 0x1b, 6275 .global2_addr = 0x1c, 6276 .age_time_coeff = 15000, 6277 .g1_irqs = 9, 6278 .g2_irqs = 10, 6279 .atu_move_port_mask = 0xf, 6280 .pvt = true, 6281 .multi_chip = true, 6282 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6283 .ptp_support = true, 6284 .ops = &mv88e6352_ops, 6285 }, 6286 [MV88E6390] = { 6287 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6288 .family = MV88E6XXX_FAMILY_6390, 6289 .name = "Marvell 88E6390", 6290 .num_databases = 4096, 6291 .num_macs = 16384, 6292 .num_ports = 11, /* 10 + Z80 */ 6293 .num_internal_phys = 9, 6294 .num_gpio = 16, 6295 .max_vid = 8191, 6296 .max_sid = 63, 6297 .port_base_addr = 0x0, 6298 .phy_base_addr = 0x0, 6299 .global1_addr = 0x1b, 6300 .global2_addr = 0x1c, 6301 .age_time_coeff = 3750, 6302 .g1_irqs = 9, 6303 .g2_irqs = 14, 6304 .atu_move_port_mask = 0x1f, 6305 .pvt = true, 6306 .multi_chip = true, 6307 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6308 .ptp_support = true, 6309 .ops = &mv88e6390_ops, 6310 }, 6311 [MV88E6390X] = { 6312 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6313 .family = MV88E6XXX_FAMILY_6390, 6314 .name = "Marvell 88E6390X", 6315 .num_databases = 4096, 6316 .num_macs = 16384, 6317 .num_ports = 11, /* 10 + Z80 */ 6318 .num_internal_phys = 9, 6319 .num_gpio = 16, 6320 .max_vid = 8191, 6321 .max_sid = 63, 6322 .port_base_addr = 0x0, 6323 .phy_base_addr = 0x0, 6324 .global1_addr = 0x1b, 6325 .global2_addr = 0x1c, 6326 .age_time_coeff = 3750, 6327 .g1_irqs = 9, 6328 .g2_irqs = 14, 6329 .atu_move_port_mask = 0x1f, 6330 .pvt = true, 6331 .multi_chip = true, 6332 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6333 .ptp_support = true, 6334 .ops = &mv88e6390x_ops, 6335 }, 6336 6337 [MV88E6393X] = { 6338 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6339 .family = MV88E6XXX_FAMILY_6393, 6340 .name = "Marvell 88E6393X", 6341 .num_databases = 4096, 6342 .num_ports = 11, /* 10 + Z80 */ 6343 .num_internal_phys = 9, 6344 .max_vid = 8191, 6345 .max_sid = 63, 6346 .port_base_addr = 0x0, 6347 .phy_base_addr = 0x0, 6348 .global1_addr = 0x1b, 6349 .global2_addr = 0x1c, 6350 .age_time_coeff = 3750, 6351 .g1_irqs = 10, 6352 .g2_irqs = 14, 6353 .atu_move_port_mask = 0x1f, 6354 .pvt = true, 6355 .multi_chip = true, 6356 .ptp_support = true, 6357 .ops = &mv88e6393x_ops, 6358 }, 6359 }; 6360 6361 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6362 { 6363 int i; 6364 6365 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6366 if (mv88e6xxx_table[i].prod_num == prod_num) 6367 return &mv88e6xxx_table[i]; 6368 6369 return NULL; 6370 } 6371 6372 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6373 { 6374 const struct mv88e6xxx_info *info; 6375 unsigned int prod_num, rev; 6376 u16 id; 6377 int err; 6378 6379 mv88e6xxx_reg_lock(chip); 6380 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6381 mv88e6xxx_reg_unlock(chip); 6382 if (err) 6383 return err; 6384 6385 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6386 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6387 6388 info = mv88e6xxx_lookup_info(prod_num); 6389 if (!info) 6390 return -ENODEV; 6391 6392 /* Update the compatible info with the probed one */ 6393 chip->info = info; 6394 6395 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6396 chip->info->prod_num, chip->info->name, rev); 6397 6398 return 0; 6399 } 6400 6401 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6402 struct mdio_device *mdiodev) 6403 { 6404 int err; 6405 6406 /* dual_chip takes precedence over single/multi-chip modes */ 6407 if (chip->info->dual_chip) 6408 return -EINVAL; 6409 6410 /* If the mdio addr is 16 indicating the first port address of a switch 6411 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6412 * configured in single chip addressing mode. Setup the smi access as 6413 * single chip addressing mode and attempt to detect the model of the 6414 * switch, if this fails the device is not configured in single chip 6415 * addressing mode. 6416 */ 6417 if (mdiodev->addr != 16) 6418 return -EINVAL; 6419 6420 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6421 if (err) 6422 return err; 6423 6424 return mv88e6xxx_detect(chip); 6425 } 6426 6427 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6428 { 6429 struct mv88e6xxx_chip *chip; 6430 6431 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6432 if (!chip) 6433 return NULL; 6434 6435 chip->dev = dev; 6436 6437 mutex_init(&chip->reg_lock); 6438 INIT_LIST_HEAD(&chip->mdios); 6439 idr_init(&chip->policies); 6440 INIT_LIST_HEAD(&chip->msts); 6441 6442 return chip; 6443 } 6444 6445 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6446 int port, 6447 enum dsa_tag_protocol m) 6448 { 6449 struct mv88e6xxx_chip *chip = ds->priv; 6450 6451 return chip->tag_protocol; 6452 } 6453 6454 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6455 enum dsa_tag_protocol proto) 6456 { 6457 struct mv88e6xxx_chip *chip = ds->priv; 6458 enum dsa_tag_protocol old_protocol; 6459 struct dsa_port *cpu_dp; 6460 int err; 6461 6462 switch (proto) { 6463 case DSA_TAG_PROTO_EDSA: 6464 switch (chip->info->edsa_support) { 6465 case MV88E6XXX_EDSA_UNSUPPORTED: 6466 return -EPROTONOSUPPORT; 6467 case MV88E6XXX_EDSA_UNDOCUMENTED: 6468 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6469 fallthrough; 6470 case MV88E6XXX_EDSA_SUPPORTED: 6471 break; 6472 } 6473 break; 6474 case DSA_TAG_PROTO_DSA: 6475 break; 6476 default: 6477 return -EPROTONOSUPPORT; 6478 } 6479 6480 old_protocol = chip->tag_protocol; 6481 chip->tag_protocol = proto; 6482 6483 mv88e6xxx_reg_lock(chip); 6484 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6485 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6486 if (err) { 6487 mv88e6xxx_reg_unlock(chip); 6488 goto unwind; 6489 } 6490 } 6491 mv88e6xxx_reg_unlock(chip); 6492 6493 return 0; 6494 6495 unwind: 6496 chip->tag_protocol = old_protocol; 6497 6498 mv88e6xxx_reg_lock(chip); 6499 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6500 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6501 mv88e6xxx_reg_unlock(chip); 6502 6503 return err; 6504 } 6505 6506 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6507 const struct switchdev_obj_port_mdb *mdb, 6508 struct dsa_db db) 6509 { 6510 struct mv88e6xxx_chip *chip = ds->priv; 6511 int err; 6512 6513 mv88e6xxx_reg_lock(chip); 6514 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6515 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6516 mv88e6xxx_reg_unlock(chip); 6517 6518 return err; 6519 } 6520 6521 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6522 const struct switchdev_obj_port_mdb *mdb, 6523 struct dsa_db db) 6524 { 6525 struct mv88e6xxx_chip *chip = ds->priv; 6526 int err; 6527 6528 mv88e6xxx_reg_lock(chip); 6529 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6530 mv88e6xxx_reg_unlock(chip); 6531 6532 return err; 6533 } 6534 6535 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6536 struct dsa_mall_mirror_tc_entry *mirror, 6537 bool ingress, 6538 struct netlink_ext_ack *extack) 6539 { 6540 enum mv88e6xxx_egress_direction direction = ingress ? 6541 MV88E6XXX_EGRESS_DIR_INGRESS : 6542 MV88E6XXX_EGRESS_DIR_EGRESS; 6543 struct mv88e6xxx_chip *chip = ds->priv; 6544 bool other_mirrors = false; 6545 int i; 6546 int err; 6547 6548 mutex_lock(&chip->reg_lock); 6549 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6550 mirror->to_local_port) { 6551 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6552 other_mirrors |= ingress ? 6553 chip->ports[i].mirror_ingress : 6554 chip->ports[i].mirror_egress; 6555 6556 /* Can't change egress port when other mirror is active */ 6557 if (other_mirrors) { 6558 err = -EBUSY; 6559 goto out; 6560 } 6561 6562 err = mv88e6xxx_set_egress_port(chip, direction, 6563 mirror->to_local_port); 6564 if (err) 6565 goto out; 6566 } 6567 6568 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6569 out: 6570 mutex_unlock(&chip->reg_lock); 6571 6572 return err; 6573 } 6574 6575 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6576 struct dsa_mall_mirror_tc_entry *mirror) 6577 { 6578 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6579 MV88E6XXX_EGRESS_DIR_INGRESS : 6580 MV88E6XXX_EGRESS_DIR_EGRESS; 6581 struct mv88e6xxx_chip *chip = ds->priv; 6582 bool other_mirrors = false; 6583 int i; 6584 6585 mutex_lock(&chip->reg_lock); 6586 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6587 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6588 6589 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6590 other_mirrors |= mirror->ingress ? 6591 chip->ports[i].mirror_ingress : 6592 chip->ports[i].mirror_egress; 6593 6594 /* Reset egress port when no other mirror is active */ 6595 if (!other_mirrors) { 6596 if (mv88e6xxx_set_egress_port(chip, direction, 6597 dsa_upstream_port(ds, port))) 6598 dev_err(ds->dev, "failed to set egress port\n"); 6599 } 6600 6601 mutex_unlock(&chip->reg_lock); 6602 } 6603 6604 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6605 struct switchdev_brport_flags flags, 6606 struct netlink_ext_ack *extack) 6607 { 6608 struct mv88e6xxx_chip *chip = ds->priv; 6609 const struct mv88e6xxx_ops *ops; 6610 6611 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6612 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6613 return -EINVAL; 6614 6615 ops = chip->info->ops; 6616 6617 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6618 return -EINVAL; 6619 6620 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6621 return -EINVAL; 6622 6623 return 0; 6624 } 6625 6626 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6627 struct switchdev_brport_flags flags, 6628 struct netlink_ext_ack *extack) 6629 { 6630 struct mv88e6xxx_chip *chip = ds->priv; 6631 int err = 0; 6632 6633 mv88e6xxx_reg_lock(chip); 6634 6635 if (flags.mask & BR_LEARNING) { 6636 bool learning = !!(flags.val & BR_LEARNING); 6637 u16 pav = learning ? (1 << port) : 0; 6638 6639 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6640 if (err) 6641 goto out; 6642 } 6643 6644 if (flags.mask & BR_FLOOD) { 6645 bool unicast = !!(flags.val & BR_FLOOD); 6646 6647 err = chip->info->ops->port_set_ucast_flood(chip, port, 6648 unicast); 6649 if (err) 6650 goto out; 6651 } 6652 6653 if (flags.mask & BR_MCAST_FLOOD) { 6654 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6655 6656 err = chip->info->ops->port_set_mcast_flood(chip, port, 6657 multicast); 6658 if (err) 6659 goto out; 6660 } 6661 6662 if (flags.mask & BR_BCAST_FLOOD) { 6663 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6664 6665 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6666 if (err) 6667 goto out; 6668 } 6669 6670 if (flags.mask & BR_PORT_MAB) { 6671 bool mab = !!(flags.val & BR_PORT_MAB); 6672 6673 mv88e6xxx_port_set_mab(chip, port, mab); 6674 } 6675 6676 if (flags.mask & BR_PORT_LOCKED) { 6677 bool locked = !!(flags.val & BR_PORT_LOCKED); 6678 6679 err = mv88e6xxx_port_set_lock(chip, port, locked); 6680 if (err) 6681 goto out; 6682 } 6683 out: 6684 mv88e6xxx_reg_unlock(chip); 6685 6686 return err; 6687 } 6688 6689 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6690 struct dsa_lag lag, 6691 struct netdev_lag_upper_info *info, 6692 struct netlink_ext_ack *extack) 6693 { 6694 struct mv88e6xxx_chip *chip = ds->priv; 6695 struct dsa_port *dp; 6696 int members = 0; 6697 6698 if (!mv88e6xxx_has_lag(chip)) { 6699 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6700 return false; 6701 } 6702 6703 if (!lag.id) 6704 return false; 6705 6706 dsa_lag_foreach_port(dp, ds->dst, &lag) 6707 /* Includes the port joining the LAG */ 6708 members++; 6709 6710 if (members > 8) { 6711 NL_SET_ERR_MSG_MOD(extack, 6712 "Cannot offload more than 8 LAG ports"); 6713 return false; 6714 } 6715 6716 /* We could potentially relax this to include active 6717 * backup in the future. 6718 */ 6719 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6720 NL_SET_ERR_MSG_MOD(extack, 6721 "Can only offload LAG using hash TX type"); 6722 return false; 6723 } 6724 6725 /* Ideally we would also validate that the hash type matches 6726 * the hardware. Alas, this is always set to unknown on team 6727 * interfaces. 6728 */ 6729 return true; 6730 } 6731 6732 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6733 { 6734 struct mv88e6xxx_chip *chip = ds->priv; 6735 struct dsa_port *dp; 6736 u16 map = 0; 6737 int id; 6738 6739 /* DSA LAG IDs are one-based, hardware is zero-based */ 6740 id = lag.id - 1; 6741 6742 /* Build the map of all ports to distribute flows destined for 6743 * this LAG. This can be either a local user port, or a DSA 6744 * port if the LAG port is on a remote chip. 6745 */ 6746 dsa_lag_foreach_port(dp, ds->dst, &lag) 6747 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6748 6749 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6750 } 6751 6752 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6753 /* Row number corresponds to the number of active members in a 6754 * LAG. Each column states which of the eight hash buckets are 6755 * mapped to the column:th port in the LAG. 6756 * 6757 * Example: In a LAG with three active ports, the second port 6758 * ([2][1]) would be selected for traffic mapped to buckets 6759 * 3,4,5 (0x38). 6760 */ 6761 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6762 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6763 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6764 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6765 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6766 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6767 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6768 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6769 }; 6770 6771 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6772 int num_tx, int nth) 6773 { 6774 u8 active = 0; 6775 int i; 6776 6777 num_tx = num_tx <= 8 ? num_tx : 8; 6778 if (nth < num_tx) 6779 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6780 6781 for (i = 0; i < 8; i++) { 6782 if (BIT(i) & active) 6783 mask[i] |= BIT(port); 6784 } 6785 } 6786 6787 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6788 { 6789 struct mv88e6xxx_chip *chip = ds->priv; 6790 unsigned int id, num_tx; 6791 struct dsa_port *dp; 6792 struct dsa_lag *lag; 6793 int i, err, nth; 6794 u16 mask[8]; 6795 u16 ivec; 6796 6797 /* Assume no port is a member of any LAG. */ 6798 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6799 6800 /* Disable all masks for ports that _are_ members of a LAG. */ 6801 dsa_switch_for_each_port(dp, ds) { 6802 if (!dp->lag) 6803 continue; 6804 6805 ivec &= ~BIT(dp->index); 6806 } 6807 6808 for (i = 0; i < 8; i++) 6809 mask[i] = ivec; 6810 6811 /* Enable the correct subset of masks for all LAG ports that 6812 * are in the Tx set. 6813 */ 6814 dsa_lags_foreach_id(id, ds->dst) { 6815 lag = dsa_lag_by_id(ds->dst, id); 6816 if (!lag) 6817 continue; 6818 6819 num_tx = 0; 6820 dsa_lag_foreach_port(dp, ds->dst, lag) { 6821 if (dp->lag_tx_enabled) 6822 num_tx++; 6823 } 6824 6825 if (!num_tx) 6826 continue; 6827 6828 nth = 0; 6829 dsa_lag_foreach_port(dp, ds->dst, lag) { 6830 if (!dp->lag_tx_enabled) 6831 continue; 6832 6833 if (dp->ds == ds) 6834 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6835 num_tx, nth); 6836 6837 nth++; 6838 } 6839 } 6840 6841 for (i = 0; i < 8; i++) { 6842 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6843 if (err) 6844 return err; 6845 } 6846 6847 return 0; 6848 } 6849 6850 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6851 struct dsa_lag lag) 6852 { 6853 int err; 6854 6855 err = mv88e6xxx_lag_sync_masks(ds); 6856 6857 if (!err) 6858 err = mv88e6xxx_lag_sync_map(ds, lag); 6859 6860 return err; 6861 } 6862 6863 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6864 { 6865 struct mv88e6xxx_chip *chip = ds->priv; 6866 int err; 6867 6868 mv88e6xxx_reg_lock(chip); 6869 err = mv88e6xxx_lag_sync_masks(ds); 6870 mv88e6xxx_reg_unlock(chip); 6871 return err; 6872 } 6873 6874 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6875 struct dsa_lag lag, 6876 struct netdev_lag_upper_info *info, 6877 struct netlink_ext_ack *extack) 6878 { 6879 struct mv88e6xxx_chip *chip = ds->priv; 6880 int err, id; 6881 6882 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6883 return -EOPNOTSUPP; 6884 6885 /* DSA LAG IDs are one-based */ 6886 id = lag.id - 1; 6887 6888 mv88e6xxx_reg_lock(chip); 6889 6890 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6891 if (err) 6892 goto err_unlock; 6893 6894 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6895 if (err) 6896 goto err_clear_trunk; 6897 6898 mv88e6xxx_reg_unlock(chip); 6899 return 0; 6900 6901 err_clear_trunk: 6902 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6903 err_unlock: 6904 mv88e6xxx_reg_unlock(chip); 6905 return err; 6906 } 6907 6908 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6909 struct dsa_lag lag) 6910 { 6911 struct mv88e6xxx_chip *chip = ds->priv; 6912 int err_sync, err_trunk; 6913 6914 mv88e6xxx_reg_lock(chip); 6915 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6916 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6917 mv88e6xxx_reg_unlock(chip); 6918 return err_sync ? : err_trunk; 6919 } 6920 6921 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6922 int port) 6923 { 6924 struct mv88e6xxx_chip *chip = ds->priv; 6925 int err; 6926 6927 mv88e6xxx_reg_lock(chip); 6928 err = mv88e6xxx_lag_sync_masks(ds); 6929 mv88e6xxx_reg_unlock(chip); 6930 return err; 6931 } 6932 6933 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6934 int port, struct dsa_lag lag, 6935 struct netdev_lag_upper_info *info, 6936 struct netlink_ext_ack *extack) 6937 { 6938 struct mv88e6xxx_chip *chip = ds->priv; 6939 int err; 6940 6941 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6942 return -EOPNOTSUPP; 6943 6944 mv88e6xxx_reg_lock(chip); 6945 6946 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6947 if (err) 6948 goto unlock; 6949 6950 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6951 6952 unlock: 6953 mv88e6xxx_reg_unlock(chip); 6954 return err; 6955 } 6956 6957 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6958 int port, struct dsa_lag lag) 6959 { 6960 struct mv88e6xxx_chip *chip = ds->priv; 6961 int err_sync, err_pvt; 6962 6963 mv88e6xxx_reg_lock(chip); 6964 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6965 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6966 mv88e6xxx_reg_unlock(chip); 6967 return err_sync ? : err_pvt; 6968 } 6969 6970 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6971 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6972 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6973 .setup = mv88e6xxx_setup, 6974 .teardown = mv88e6xxx_teardown, 6975 .port_setup = mv88e6xxx_port_setup, 6976 .port_teardown = mv88e6xxx_port_teardown, 6977 .phylink_get_caps = mv88e6xxx_get_caps, 6978 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 6979 .phylink_mac_config = mv88e6xxx_mac_config, 6980 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 6981 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6982 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6983 .get_strings = mv88e6xxx_get_strings, 6984 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6985 .get_sset_count = mv88e6xxx_get_sset_count, 6986 .port_enable = mv88e6xxx_port_enable, 6987 .port_disable = mv88e6xxx_port_disable, 6988 .port_max_mtu = mv88e6xxx_get_max_mtu, 6989 .port_change_mtu = mv88e6xxx_change_mtu, 6990 .get_mac_eee = mv88e6xxx_get_mac_eee, 6991 .set_mac_eee = mv88e6xxx_set_mac_eee, 6992 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6993 .get_eeprom = mv88e6xxx_get_eeprom, 6994 .set_eeprom = mv88e6xxx_set_eeprom, 6995 .get_regs_len = mv88e6xxx_get_regs_len, 6996 .get_regs = mv88e6xxx_get_regs, 6997 .get_rxnfc = mv88e6xxx_get_rxnfc, 6998 .set_rxnfc = mv88e6xxx_set_rxnfc, 6999 .set_ageing_time = mv88e6xxx_set_ageing_time, 7000 .port_bridge_join = mv88e6xxx_port_bridge_join, 7001 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 7002 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 7003 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 7004 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 7005 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 7006 .port_fast_age = mv88e6xxx_port_fast_age, 7007 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 7008 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 7009 .port_vlan_add = mv88e6xxx_port_vlan_add, 7010 .port_vlan_del = mv88e6xxx_port_vlan_del, 7011 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 7012 .port_fdb_add = mv88e6xxx_port_fdb_add, 7013 .port_fdb_del = mv88e6xxx_port_fdb_del, 7014 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 7015 .port_mdb_add = mv88e6xxx_port_mdb_add, 7016 .port_mdb_del = mv88e6xxx_port_mdb_del, 7017 .port_mirror_add = mv88e6xxx_port_mirror_add, 7018 .port_mirror_del = mv88e6xxx_port_mirror_del, 7019 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 7020 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 7021 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 7022 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 7023 .port_txtstamp = mv88e6xxx_port_txtstamp, 7024 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 7025 .get_ts_info = mv88e6xxx_get_ts_info, 7026 .devlink_param_get = mv88e6xxx_devlink_param_get, 7027 .devlink_param_set = mv88e6xxx_devlink_param_set, 7028 .devlink_info_get = mv88e6xxx_devlink_info_get, 7029 .port_lag_change = mv88e6xxx_port_lag_change, 7030 .port_lag_join = mv88e6xxx_port_lag_join, 7031 .port_lag_leave = mv88e6xxx_port_lag_leave, 7032 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 7033 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 7034 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 7035 }; 7036 7037 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 7038 { 7039 struct device *dev = chip->dev; 7040 struct dsa_switch *ds; 7041 7042 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 7043 if (!ds) 7044 return -ENOMEM; 7045 7046 ds->dev = dev; 7047 ds->num_ports = mv88e6xxx_num_ports(chip); 7048 ds->priv = chip; 7049 ds->dev = dev; 7050 ds->ops = &mv88e6xxx_switch_ops; 7051 ds->ageing_time_min = chip->info->age_time_coeff; 7052 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 7053 7054 /* Some chips support up to 32, but that requires enabling the 7055 * 5-bit port mode, which we do not support. 640k^W16 ought to 7056 * be enough for anyone. 7057 */ 7058 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 7059 7060 dev_set_drvdata(dev, ds); 7061 7062 return dsa_register_switch(ds); 7063 } 7064 7065 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 7066 { 7067 dsa_unregister_switch(chip->ds); 7068 } 7069 7070 static const void *pdata_device_get_match_data(struct device *dev) 7071 { 7072 const struct of_device_id *matches = dev->driver->of_match_table; 7073 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 7074 7075 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 7076 matches++) { 7077 if (!strcmp(pdata->compatible, matches->compatible)) 7078 return matches->data; 7079 } 7080 return NULL; 7081 } 7082 7083 /* There is no suspend to RAM support at DSA level yet, the switch configuration 7084 * would be lost after a power cycle so prevent it to be suspended. 7085 */ 7086 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 7087 { 7088 return -EOPNOTSUPP; 7089 } 7090 7091 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7092 { 7093 return 0; 7094 } 7095 7096 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7097 7098 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7099 { 7100 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7101 const struct mv88e6xxx_info *compat_info = NULL; 7102 struct device *dev = &mdiodev->dev; 7103 struct device_node *np = dev->of_node; 7104 struct mv88e6xxx_chip *chip; 7105 int port; 7106 int err; 7107 7108 if (!np && !pdata) 7109 return -EINVAL; 7110 7111 if (np) 7112 compat_info = of_device_get_match_data(dev); 7113 7114 if (pdata) { 7115 compat_info = pdata_device_get_match_data(dev); 7116 7117 if (!pdata->netdev) 7118 return -EINVAL; 7119 7120 for (port = 0; port < DSA_MAX_PORTS; port++) { 7121 if (!(pdata->enabled_ports & (1 << port))) 7122 continue; 7123 if (strcmp(pdata->cd.port_names[port], "cpu")) 7124 continue; 7125 pdata->cd.netdev[port] = &pdata->netdev->dev; 7126 break; 7127 } 7128 } 7129 7130 if (!compat_info) 7131 return -EINVAL; 7132 7133 chip = mv88e6xxx_alloc_chip(dev); 7134 if (!chip) { 7135 err = -ENOMEM; 7136 goto out; 7137 } 7138 7139 chip->info = compat_info; 7140 7141 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7142 if (IS_ERR(chip->reset)) { 7143 err = PTR_ERR(chip->reset); 7144 goto out; 7145 } 7146 if (chip->reset) 7147 usleep_range(1000, 2000); 7148 7149 /* Detect if the device is configured in single chip addressing mode, 7150 * otherwise continue with address specific smi init/detection. 7151 */ 7152 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7153 if (err) { 7154 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7155 if (err) 7156 goto out; 7157 7158 err = mv88e6xxx_detect(chip); 7159 if (err) 7160 goto out; 7161 } 7162 7163 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7164 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7165 else 7166 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7167 7168 mv88e6xxx_phy_init(chip); 7169 7170 if (chip->info->ops->get_eeprom) { 7171 if (np) 7172 of_property_read_u32(np, "eeprom-length", 7173 &chip->eeprom_len); 7174 else 7175 chip->eeprom_len = pdata->eeprom_len; 7176 } 7177 7178 mv88e6xxx_reg_lock(chip); 7179 err = mv88e6xxx_switch_reset(chip); 7180 mv88e6xxx_reg_unlock(chip); 7181 if (err) 7182 goto out; 7183 7184 if (np) { 7185 chip->irq = of_irq_get(np, 0); 7186 if (chip->irq == -EPROBE_DEFER) { 7187 err = chip->irq; 7188 goto out; 7189 } 7190 } 7191 7192 if (pdata) 7193 chip->irq = pdata->irq; 7194 7195 /* Has to be performed before the MDIO bus is created, because 7196 * the PHYs will link their interrupts to these interrupt 7197 * controllers 7198 */ 7199 mv88e6xxx_reg_lock(chip); 7200 if (chip->irq > 0) 7201 err = mv88e6xxx_g1_irq_setup(chip); 7202 else 7203 err = mv88e6xxx_irq_poll_setup(chip); 7204 mv88e6xxx_reg_unlock(chip); 7205 7206 if (err) 7207 goto out; 7208 7209 if (chip->info->g2_irqs > 0) { 7210 err = mv88e6xxx_g2_irq_setup(chip); 7211 if (err) 7212 goto out_g1_irq; 7213 } 7214 7215 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7216 if (err) 7217 goto out_g2_irq; 7218 7219 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7220 if (err) 7221 goto out_g1_atu_prob_irq; 7222 7223 err = mv88e6xxx_mdios_register(chip, np); 7224 if (err) 7225 goto out_g1_vtu_prob_irq; 7226 7227 err = mv88e6xxx_register_switch(chip); 7228 if (err) 7229 goto out_mdio; 7230 7231 return 0; 7232 7233 out_mdio: 7234 mv88e6xxx_mdios_unregister(chip); 7235 out_g1_vtu_prob_irq: 7236 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7237 out_g1_atu_prob_irq: 7238 mv88e6xxx_g1_atu_prob_irq_free(chip); 7239 out_g2_irq: 7240 if (chip->info->g2_irqs > 0) 7241 mv88e6xxx_g2_irq_free(chip); 7242 out_g1_irq: 7243 if (chip->irq > 0) 7244 mv88e6xxx_g1_irq_free(chip); 7245 else 7246 mv88e6xxx_irq_poll_free(chip); 7247 out: 7248 if (pdata) 7249 dev_put(pdata->netdev); 7250 7251 return err; 7252 } 7253 7254 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7255 { 7256 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7257 struct mv88e6xxx_chip *chip; 7258 7259 if (!ds) 7260 return; 7261 7262 chip = ds->priv; 7263 7264 if (chip->info->ptp_support) { 7265 mv88e6xxx_hwtstamp_free(chip); 7266 mv88e6xxx_ptp_free(chip); 7267 } 7268 7269 mv88e6xxx_phy_destroy(chip); 7270 mv88e6xxx_unregister_switch(chip); 7271 mv88e6xxx_mdios_unregister(chip); 7272 7273 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7274 mv88e6xxx_g1_atu_prob_irq_free(chip); 7275 7276 if (chip->info->g2_irqs > 0) 7277 mv88e6xxx_g2_irq_free(chip); 7278 7279 if (chip->irq > 0) 7280 mv88e6xxx_g1_irq_free(chip); 7281 else 7282 mv88e6xxx_irq_poll_free(chip); 7283 } 7284 7285 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7286 { 7287 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7288 7289 if (!ds) 7290 return; 7291 7292 dsa_switch_shutdown(ds); 7293 7294 dev_set_drvdata(&mdiodev->dev, NULL); 7295 } 7296 7297 static const struct of_device_id mv88e6xxx_of_match[] = { 7298 { 7299 .compatible = "marvell,mv88e6085", 7300 .data = &mv88e6xxx_table[MV88E6085], 7301 }, 7302 { 7303 .compatible = "marvell,mv88e6190", 7304 .data = &mv88e6xxx_table[MV88E6190], 7305 }, 7306 { 7307 .compatible = "marvell,mv88e6250", 7308 .data = &mv88e6xxx_table[MV88E6250], 7309 }, 7310 { /* sentinel */ }, 7311 }; 7312 7313 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7314 7315 static struct mdio_driver mv88e6xxx_driver = { 7316 .probe = mv88e6xxx_probe, 7317 .remove = mv88e6xxx_remove, 7318 .shutdown = mv88e6xxx_shutdown, 7319 .mdiodrv.driver = { 7320 .name = "mv88e6085", 7321 .of_match_table = mv88e6xxx_of_match, 7322 .pm = &mv88e6xxx_pm_ops, 7323 }, 7324 }; 7325 7326 mdio_module_driver(mv88e6xxx_driver); 7327 7328 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7329 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7330 MODULE_LICENSE("GPL"); 7331