1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 dev_err(chip->dev, "Timeout while waiting for switch\n"); 113 return -ETIMEDOUT; 114 } 115 116 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 117 int bit, int val) 118 { 119 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 120 val ? BIT(bit) : 0x0000); 121 } 122 123 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 124 { 125 struct mv88e6xxx_mdio_bus *mdio_bus; 126 127 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 128 list); 129 if (!mdio_bus) 130 return NULL; 131 132 return mdio_bus->bus; 133 } 134 135 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 136 { 137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 138 unsigned int n = d->hwirq; 139 140 chip->g1_irq.masked |= (1 << n); 141 } 142 143 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 144 { 145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 146 unsigned int n = d->hwirq; 147 148 chip->g1_irq.masked &= ~(1 << n); 149 } 150 151 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 152 { 153 unsigned int nhandled = 0; 154 unsigned int sub_irq; 155 unsigned int n; 156 u16 reg; 157 u16 ctl1; 158 int err; 159 160 mv88e6xxx_reg_lock(chip); 161 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 162 mv88e6xxx_reg_unlock(chip); 163 164 if (err) 165 goto out; 166 167 do { 168 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 169 if (reg & (1 << n)) { 170 sub_irq = irq_find_mapping(chip->g1_irq.domain, 171 n); 172 handle_nested_irq(sub_irq); 173 ++nhandled; 174 } 175 } 176 177 mv88e6xxx_reg_lock(chip); 178 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 179 if (err) 180 goto unlock; 181 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 182 unlock: 183 mv88e6xxx_reg_unlock(chip); 184 if (err) 185 goto out; 186 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 187 } while (reg & ctl1); 188 189 out: 190 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 191 } 192 193 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 194 { 195 struct mv88e6xxx_chip *chip = dev_id; 196 197 return mv88e6xxx_g1_irq_thread_work(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 204 mv88e6xxx_reg_lock(chip); 205 } 206 207 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 208 { 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 211 u16 reg; 212 int err; 213 214 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 215 if (err) 216 goto out; 217 218 reg &= ~mask; 219 reg |= (~chip->g1_irq.masked & mask); 220 221 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 222 if (err) 223 goto out; 224 225 out: 226 mv88e6xxx_reg_unlock(chip); 227 } 228 229 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 230 .name = "mv88e6xxx-g1", 231 .irq_mask = mv88e6xxx_g1_irq_mask, 232 .irq_unmask = mv88e6xxx_g1_irq_unmask, 233 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 234 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 235 }; 236 237 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 238 unsigned int irq, 239 irq_hw_number_t hwirq) 240 { 241 struct mv88e6xxx_chip *chip = d->host_data; 242 243 irq_set_chip_data(irq, d->host_data); 244 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 245 irq_set_noprobe(irq); 246 247 return 0; 248 } 249 250 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 251 .map = mv88e6xxx_g1_irq_domain_map, 252 .xlate = irq_domain_xlate_twocell, 253 }; 254 255 /* To be called with reg_lock held */ 256 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 257 { 258 int irq, virq; 259 u16 mask; 260 261 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 262 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 263 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 264 265 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 266 virq = irq_find_mapping(chip->g1_irq.domain, irq); 267 irq_dispose_mapping(virq); 268 } 269 270 irq_domain_remove(chip->g1_irq.domain); 271 } 272 273 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 274 { 275 /* 276 * free_irq must be called without reg_lock taken because the irq 277 * handler takes this lock, too. 278 */ 279 free_irq(chip->irq, chip); 280 281 mv88e6xxx_reg_lock(chip); 282 mv88e6xxx_g1_irq_free_common(chip); 283 mv88e6xxx_reg_unlock(chip); 284 } 285 286 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 287 { 288 int err, irq, virq; 289 u16 reg, mask; 290 291 chip->g1_irq.nirqs = chip->info->g1_irqs; 292 chip->g1_irq.domain = irq_domain_add_simple( 293 NULL, chip->g1_irq.nirqs, 0, 294 &mv88e6xxx_g1_irq_domain_ops, chip); 295 if (!chip->g1_irq.domain) 296 return -ENOMEM; 297 298 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 299 irq_create_mapping(chip->g1_irq.domain, irq); 300 301 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 302 chip->g1_irq.masked = ~0; 303 304 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 305 if (err) 306 goto out_mapping; 307 308 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 309 310 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 311 if (err) 312 goto out_disable; 313 314 /* Reading the interrupt status clears (most of) them */ 315 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 316 if (err) 317 goto out_disable; 318 319 return 0; 320 321 out_disable: 322 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 323 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 324 325 out_mapping: 326 for (irq = 0; irq < 16; irq++) { 327 virq = irq_find_mapping(chip->g1_irq.domain, irq); 328 irq_dispose_mapping(virq); 329 } 330 331 irq_domain_remove(chip->g1_irq.domain); 332 333 return err; 334 } 335 336 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 337 { 338 static struct lock_class_key lock_key; 339 static struct lock_class_key request_key; 340 int err; 341 342 err = mv88e6xxx_g1_irq_setup_common(chip); 343 if (err) 344 return err; 345 346 /* These lock classes tells lockdep that global 1 irqs are in 347 * a different category than their parent GPIO, so it won't 348 * report false recursion. 349 */ 350 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 351 352 snprintf(chip->irq_name, sizeof(chip->irq_name), 353 "mv88e6xxx-%s", dev_name(chip->dev)); 354 355 mv88e6xxx_reg_unlock(chip); 356 err = request_threaded_irq(chip->irq, NULL, 357 mv88e6xxx_g1_irq_thread_fn, 358 IRQF_ONESHOT | IRQF_SHARED, 359 chip->irq_name, chip); 360 mv88e6xxx_reg_lock(chip); 361 if (err) 362 mv88e6xxx_g1_irq_free_common(chip); 363 364 return err; 365 } 366 367 static void mv88e6xxx_irq_poll(struct kthread_work *work) 368 { 369 struct mv88e6xxx_chip *chip = container_of(work, 370 struct mv88e6xxx_chip, 371 irq_poll_work.work); 372 mv88e6xxx_g1_irq_thread_work(chip); 373 374 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 375 msecs_to_jiffies(100)); 376 } 377 378 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 379 { 380 int err; 381 382 err = mv88e6xxx_g1_irq_setup_common(chip); 383 if (err) 384 return err; 385 386 kthread_init_delayed_work(&chip->irq_poll_work, 387 mv88e6xxx_irq_poll); 388 389 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 390 if (IS_ERR(chip->kworker)) 391 return PTR_ERR(chip->kworker); 392 393 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 394 msecs_to_jiffies(100)); 395 396 return 0; 397 } 398 399 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 400 { 401 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 402 kthread_destroy_worker(chip->kworker); 403 404 mv88e6xxx_reg_lock(chip); 405 mv88e6xxx_g1_irq_free_common(chip); 406 mv88e6xxx_reg_unlock(chip); 407 } 408 409 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 410 int port, phy_interface_t interface) 411 { 412 int err; 413 414 if (chip->info->ops->port_set_rgmii_delay) { 415 err = chip->info->ops->port_set_rgmii_delay(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 if (chip->info->ops->port_set_cmode) { 422 err = chip->info->ops->port_set_cmode(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 return 0; 429 } 430 431 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 432 int link, int speed, int duplex, int pause, 433 phy_interface_t mode) 434 { 435 int err; 436 437 if (!chip->info->ops->port_set_link) 438 return 0; 439 440 /* Port's MAC control must not be changed unless the link is down */ 441 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 442 if (err) 443 return err; 444 445 if (chip->info->ops->port_set_speed_duplex) { 446 err = chip->info->ops->port_set_speed_duplex(chip, port, 447 speed, duplex); 448 if (err && err != -EOPNOTSUPP) 449 goto restore_link; 450 } 451 452 if (chip->info->ops->port_set_pause) { 453 err = chip->info->ops->port_set_pause(chip, port, pause); 454 if (err) 455 goto restore_link; 456 } 457 458 err = mv88e6xxx_port_config_interface(chip, port, mode); 459 restore_link: 460 if (chip->info->ops->port_set_link(chip, port, link)) 461 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 462 463 return err; 464 } 465 466 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 467 { 468 struct mv88e6xxx_chip *chip = ds->priv; 469 470 return port < chip->info->num_internal_phys; 471 } 472 473 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 474 { 475 u16 reg; 476 int err; 477 478 /* The 88e6250 family does not have the PHY detect bit. Instead, 479 * report whether the port is internal. 480 */ 481 if (chip->info->family == MV88E6XXX_FAMILY_6250) 482 return port < chip->info->num_internal_phys; 483 484 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 485 if (err) { 486 dev_err(chip->dev, 487 "p%d: %s: failed to read port status\n", 488 port, __func__); 489 return err; 490 } 491 492 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 493 } 494 495 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 496 struct phylink_link_state *state) 497 { 498 struct mv88e6xxx_chip *chip = ds->priv; 499 int lane; 500 int err; 501 502 mv88e6xxx_reg_lock(chip); 503 lane = mv88e6xxx_serdes_get_lane(chip, port); 504 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 505 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 506 state); 507 else 508 err = -EOPNOTSUPP; 509 mv88e6xxx_reg_unlock(chip); 510 511 return err; 512 } 513 514 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 515 unsigned int mode, 516 phy_interface_t interface, 517 const unsigned long *advertise) 518 { 519 const struct mv88e6xxx_ops *ops = chip->info->ops; 520 int lane; 521 522 if (ops->serdes_pcs_config) { 523 lane = mv88e6xxx_serdes_get_lane(chip, port); 524 if (lane >= 0) 525 return ops->serdes_pcs_config(chip, port, lane, mode, 526 interface, advertise); 527 } 528 529 return 0; 530 } 531 532 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 533 { 534 struct mv88e6xxx_chip *chip = ds->priv; 535 const struct mv88e6xxx_ops *ops; 536 int err = 0; 537 int lane; 538 539 ops = chip->info->ops; 540 541 if (ops->serdes_pcs_an_restart) { 542 mv88e6xxx_reg_lock(chip); 543 lane = mv88e6xxx_serdes_get_lane(chip, port); 544 if (lane >= 0) 545 err = ops->serdes_pcs_an_restart(chip, port, lane); 546 mv88e6xxx_reg_unlock(chip); 547 548 if (err) 549 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 550 } 551 } 552 553 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 554 unsigned int mode, 555 int speed, int duplex) 556 { 557 const struct mv88e6xxx_ops *ops = chip->info->ops; 558 int lane; 559 560 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 561 lane = mv88e6xxx_serdes_get_lane(chip, port); 562 if (lane >= 0) 563 return ops->serdes_pcs_link_up(chip, port, lane, 564 speed, duplex); 565 } 566 567 return 0; 568 } 569 570 static const u8 mv88e6185_phy_interface_modes[] = { 571 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 572 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 573 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 574 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 575 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 576 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 577 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 578 }; 579 580 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 581 struct phylink_config *config) 582 { 583 u8 cmode = chip->ports[port].cmode; 584 585 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 586 587 if (mv88e6xxx_phy_is_internal(chip->ds, port)) { 588 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 589 } else { 590 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 591 mv88e6185_phy_interface_modes[cmode]) 592 __set_bit(mv88e6185_phy_interface_modes[cmode], 593 config->supported_interfaces); 594 595 config->mac_capabilities |= MAC_1000FD; 596 } 597 } 598 599 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 600 struct phylink_config *config) 601 { 602 u8 cmode = chip->ports[port].cmode; 603 604 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 605 mv88e6185_phy_interface_modes[cmode]) 606 __set_bit(mv88e6185_phy_interface_modes[cmode], 607 config->supported_interfaces); 608 609 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 610 MAC_1000FD; 611 } 612 613 static const u8 mv88e6xxx_phy_interface_modes[] = { 614 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 615 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 616 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 617 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 618 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 619 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 620 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 621 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 622 /* higher interface modes are not needed here, since ports supporting 623 * them are writable, and so the supported interfaces are filled in the 624 * corresponding .phylink_set_interfaces() implementation below 625 */ 626 }; 627 628 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 629 { 630 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 631 mv88e6xxx_phy_interface_modes[cmode]) 632 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 633 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 634 phy_interface_set_rgmii(supported); 635 } 636 637 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 638 struct phylink_config *config) 639 { 640 unsigned long *supported = config->supported_interfaces; 641 642 /* Translate the default cmode */ 643 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 644 645 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 646 } 647 648 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) 649 { 650 u16 reg, val; 651 int err; 652 653 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®); 654 if (err) 655 return err; 656 657 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 658 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 659 return 0xf; 660 661 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 662 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val); 663 if (err) 664 return err; 665 666 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val); 667 if (err) 668 return err; 669 670 /* Restore PHY_DETECT value */ 671 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg); 672 if (err) 673 return err; 674 675 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 676 } 677 678 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 679 struct phylink_config *config) 680 { 681 unsigned long *supported = config->supported_interfaces; 682 int err, cmode; 683 684 /* Translate the default cmode */ 685 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 686 687 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 688 MAC_1000FD; 689 690 /* Port 4 supports automedia if the serdes is associated with it. */ 691 if (port == 4) { 692 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 693 if (err < 0) 694 dev_err(chip->dev, "p%d: failed to read scratch\n", 695 port); 696 if (err <= 0) 697 return; 698 699 cmode = mv88e6352_get_port4_serdes_cmode(chip); 700 if (cmode < 0) 701 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 702 port); 703 else 704 mv88e6xxx_translate_cmode(cmode, supported); 705 } 706 } 707 708 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 709 struct phylink_config *config) 710 { 711 unsigned long *supported = config->supported_interfaces; 712 713 /* Translate the default cmode */ 714 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 715 716 /* No ethtool bits for 200Mbps */ 717 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 718 MAC_1000FD; 719 720 /* The C_Mode field is programmable on port 5 */ 721 if (port == 5) { 722 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 723 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 724 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 725 726 config->mac_capabilities |= MAC_2500FD; 727 } 728 } 729 730 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 731 struct phylink_config *config) 732 { 733 unsigned long *supported = config->supported_interfaces; 734 735 /* Translate the default cmode */ 736 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 737 738 /* No ethtool bits for 200Mbps */ 739 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 740 MAC_1000FD; 741 742 /* The C_Mode field is programmable on ports 9 and 10 */ 743 if (port == 9 || port == 10) { 744 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 745 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 746 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 747 748 config->mac_capabilities |= MAC_2500FD; 749 } 750 } 751 752 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 753 struct phylink_config *config) 754 { 755 unsigned long *supported = config->supported_interfaces; 756 757 mv88e6390_phylink_get_caps(chip, port, config); 758 759 /* For the 6x90X, ports 2-7 can be in automedia mode. 760 * (Note that 6x90 doesn't support RXAUI nor XAUI). 761 * 762 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 763 * configured for 1000BASE-X, SGMII or 2500BASE-X. 764 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 765 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 766 * 767 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 768 * configured for 1000BASE-X, SGMII or 2500BASE-X. 769 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 770 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 771 * 772 * For now, be permissive (as the old code was) and allow 1000BASE-X 773 * on ports 2..7. 774 */ 775 if (port >= 2 && port <= 7) 776 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 777 778 /* The C_Mode field can also be programmed for 10G speeds */ 779 if (port == 9 || port == 10) { 780 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 781 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 782 783 config->mac_capabilities |= MAC_10000FD; 784 } 785 } 786 787 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 788 struct phylink_config *config) 789 { 790 unsigned long *supported = config->supported_interfaces; 791 bool is_6191x = 792 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 793 794 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 795 796 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 797 MAC_1000FD; 798 799 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 800 if (port == 0 || port == 9 || port == 10) { 801 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 802 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 803 804 /* 6191X supports >1G modes only on port 10 */ 805 if (!is_6191x || port == 10) { 806 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 807 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 808 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 809 /* FIXME: USXGMII is not supported yet */ 810 /* __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); */ 811 812 config->mac_capabilities |= MAC_2500FD | MAC_5000FD | 813 MAC_10000FD; 814 } 815 } 816 817 if (port == 0) { 818 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 819 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 820 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 821 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 822 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 823 } 824 } 825 826 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 827 struct phylink_config *config) 828 { 829 struct mv88e6xxx_chip *chip = ds->priv; 830 831 mv88e6xxx_reg_lock(chip); 832 chip->info->ops->phylink_get_caps(chip, port, config); 833 mv88e6xxx_reg_unlock(chip); 834 835 if (mv88e6xxx_phy_is_internal(ds, port)) { 836 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 837 config->supported_interfaces); 838 /* Internal ports with no phy-mode need GMII for PHYLIB */ 839 __set_bit(PHY_INTERFACE_MODE_GMII, 840 config->supported_interfaces); 841 } 842 } 843 844 static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port, 845 unsigned int mode, phy_interface_t interface) 846 { 847 struct mv88e6xxx_chip *chip = ds->priv; 848 int err = 0; 849 850 /* In inband mode, the link may come up at any time while the link 851 * is not forced down. Force the link down while we reconfigure the 852 * interface mode. 853 */ 854 if (mode == MLO_AN_INBAND && 855 chip->ports[port].interface != interface && 856 chip->info->ops->port_set_link) { 857 mv88e6xxx_reg_lock(chip); 858 err = chip->info->ops->port_set_link(chip, port, 859 LINK_FORCED_DOWN); 860 mv88e6xxx_reg_unlock(chip); 861 } 862 863 return err; 864 } 865 866 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 867 unsigned int mode, 868 const struct phylink_link_state *state) 869 { 870 struct mv88e6xxx_chip *chip = ds->priv; 871 int err = 0; 872 873 mv88e6xxx_reg_lock(chip); 874 875 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) { 876 err = mv88e6xxx_port_config_interface(chip, port, 877 state->interface); 878 if (err && err != -EOPNOTSUPP) 879 goto err_unlock; 880 881 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, 882 state->interface, 883 state->advertising); 884 /* FIXME: we should restart negotiation if something changed - 885 * which is something we get if we convert to using phylinks 886 * PCS operations. 887 */ 888 if (err > 0) 889 err = 0; 890 } 891 892 err_unlock: 893 mv88e6xxx_reg_unlock(chip); 894 895 if (err && err != -EOPNOTSUPP) 896 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 897 } 898 899 static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port, 900 unsigned int mode, phy_interface_t interface) 901 { 902 struct mv88e6xxx_chip *chip = ds->priv; 903 int err = 0; 904 905 /* Undo the forced down state above after completing configuration 906 * irrespective of its state on entry, which allows the link to come 907 * up in the in-band case where there is no separate SERDES. Also 908 * ensure that the link can come up if the PPU is in use and we are 909 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 910 */ 911 mv88e6xxx_reg_lock(chip); 912 913 if (chip->info->ops->port_set_link && 914 ((mode == MLO_AN_INBAND && 915 chip->ports[port].interface != interface) || 916 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 917 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 918 919 mv88e6xxx_reg_unlock(chip); 920 921 chip->ports[port].interface = interface; 922 923 return err; 924 } 925 926 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 927 unsigned int mode, 928 phy_interface_t interface) 929 { 930 struct mv88e6xxx_chip *chip = ds->priv; 931 const struct mv88e6xxx_ops *ops; 932 int err = 0; 933 934 ops = chip->info->ops; 935 936 mv88e6xxx_reg_lock(chip); 937 /* Force the link down if we know the port may not be automatically 938 * updated by the switch or if we are using fixed-link mode. 939 */ 940 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 941 mode == MLO_AN_FIXED) && ops->port_sync_link) 942 err = ops->port_sync_link(chip, port, mode, false); 943 944 if (!err && ops->port_set_speed_duplex) 945 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 946 DUPLEX_UNFORCED); 947 mv88e6xxx_reg_unlock(chip); 948 949 if (err) 950 dev_err(chip->dev, 951 "p%d: failed to force MAC link down\n", port); 952 } 953 954 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 955 unsigned int mode, phy_interface_t interface, 956 struct phy_device *phydev, 957 int speed, int duplex, 958 bool tx_pause, bool rx_pause) 959 { 960 struct mv88e6xxx_chip *chip = ds->priv; 961 const struct mv88e6xxx_ops *ops; 962 int err = 0; 963 964 ops = chip->info->ops; 965 966 mv88e6xxx_reg_lock(chip); 967 /* Configure and force the link up if we know that the port may not 968 * automatically updated by the switch or if we are using fixed-link 969 * mode. 970 */ 971 if (!mv88e6xxx_port_ppu_updates(chip, port) || 972 mode == MLO_AN_FIXED) { 973 /* FIXME: for an automedia port, should we force the link 974 * down here - what if the link comes up due to "other" media 975 * while we're bringing the port up, how is the exclusivity 976 * handled in the Marvell hardware? E.g. port 2 on 88E6390 977 * shared between internal PHY and Serdes. 978 */ 979 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 980 duplex); 981 if (err) 982 goto error; 983 984 if (ops->port_set_speed_duplex) { 985 err = ops->port_set_speed_duplex(chip, port, 986 speed, duplex); 987 if (err && err != -EOPNOTSUPP) 988 goto error; 989 } 990 991 if (ops->port_sync_link) 992 err = ops->port_sync_link(chip, port, mode, true); 993 } 994 error: 995 mv88e6xxx_reg_unlock(chip); 996 997 if (err && err != -EOPNOTSUPP) 998 dev_err(ds->dev, 999 "p%d: failed to configure MAC link up\n", port); 1000 } 1001 1002 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 1003 { 1004 if (!chip->info->ops->stats_snapshot) 1005 return -EOPNOTSUPP; 1006 1007 return chip->info->ops->stats_snapshot(chip, port); 1008 } 1009 1010 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 1011 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 1012 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 1013 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 1014 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 1015 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 1016 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 1017 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 1018 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 1019 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 1020 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 1021 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 1022 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 1023 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 1024 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 1025 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 1026 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 1027 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 1028 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 1029 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 1030 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 1031 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 1032 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 1033 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 1034 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 1035 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 1036 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 1037 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 1038 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 1039 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 1040 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 1041 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 1042 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 1043 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 1044 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 1045 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 1046 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 1047 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 1048 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 1049 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 1050 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 1051 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 1052 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 1053 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 1054 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 1055 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 1056 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 1057 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 1058 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 1059 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 1060 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 1061 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 1062 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 1063 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 1064 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 1065 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 1066 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 1067 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 1068 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 1069 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 1070 }; 1071 1072 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1073 struct mv88e6xxx_hw_stat *s, 1074 int port, u16 bank1_select, 1075 u16 histogram) 1076 { 1077 u32 low; 1078 u32 high = 0; 1079 u16 reg = 0; 1080 int err; 1081 u64 value; 1082 1083 switch (s->type) { 1084 case STATS_TYPE_PORT: 1085 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1086 if (err) 1087 return U64_MAX; 1088 1089 low = reg; 1090 if (s->size == 4) { 1091 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1092 if (err) 1093 return U64_MAX; 1094 low |= ((u32)reg) << 16; 1095 } 1096 break; 1097 case STATS_TYPE_BANK1: 1098 reg = bank1_select; 1099 fallthrough; 1100 case STATS_TYPE_BANK0: 1101 reg |= s->reg | histogram; 1102 mv88e6xxx_g1_stats_read(chip, reg, &low); 1103 if (s->size == 8) 1104 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1105 break; 1106 default: 1107 return U64_MAX; 1108 } 1109 value = (((u64)high) << 32) | low; 1110 return value; 1111 } 1112 1113 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1114 uint8_t *data, int types) 1115 { 1116 struct mv88e6xxx_hw_stat *stat; 1117 int i, j; 1118 1119 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1120 stat = &mv88e6xxx_hw_stats[i]; 1121 if (stat->type & types) { 1122 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1123 ETH_GSTRING_LEN); 1124 j++; 1125 } 1126 } 1127 1128 return j; 1129 } 1130 1131 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1132 uint8_t *data) 1133 { 1134 return mv88e6xxx_stats_get_strings(chip, data, 1135 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1136 } 1137 1138 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1139 uint8_t *data) 1140 { 1141 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1142 } 1143 1144 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1145 uint8_t *data) 1146 { 1147 return mv88e6xxx_stats_get_strings(chip, data, 1148 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1149 } 1150 1151 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1152 "atu_member_violation", 1153 "atu_miss_violation", 1154 "atu_full_violation", 1155 "vtu_member_violation", 1156 "vtu_miss_violation", 1157 }; 1158 1159 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1160 { 1161 unsigned int i; 1162 1163 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1164 strscpy(data + i * ETH_GSTRING_LEN, 1165 mv88e6xxx_atu_vtu_stats_strings[i], 1166 ETH_GSTRING_LEN); 1167 } 1168 1169 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1170 u32 stringset, uint8_t *data) 1171 { 1172 struct mv88e6xxx_chip *chip = ds->priv; 1173 int count = 0; 1174 1175 if (stringset != ETH_SS_STATS) 1176 return; 1177 1178 mv88e6xxx_reg_lock(chip); 1179 1180 if (chip->info->ops->stats_get_strings) 1181 count = chip->info->ops->stats_get_strings(chip, data); 1182 1183 if (chip->info->ops->serdes_get_strings) { 1184 data += count * ETH_GSTRING_LEN; 1185 count = chip->info->ops->serdes_get_strings(chip, port, data); 1186 } 1187 1188 data += count * ETH_GSTRING_LEN; 1189 mv88e6xxx_atu_vtu_get_strings(data); 1190 1191 mv88e6xxx_reg_unlock(chip); 1192 } 1193 1194 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1195 int types) 1196 { 1197 struct mv88e6xxx_hw_stat *stat; 1198 int i, j; 1199 1200 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1201 stat = &mv88e6xxx_hw_stats[i]; 1202 if (stat->type & types) 1203 j++; 1204 } 1205 return j; 1206 } 1207 1208 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1209 { 1210 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1211 STATS_TYPE_PORT); 1212 } 1213 1214 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1215 { 1216 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1217 } 1218 1219 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1220 { 1221 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1222 STATS_TYPE_BANK1); 1223 } 1224 1225 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1226 { 1227 struct mv88e6xxx_chip *chip = ds->priv; 1228 int serdes_count = 0; 1229 int count = 0; 1230 1231 if (sset != ETH_SS_STATS) 1232 return 0; 1233 1234 mv88e6xxx_reg_lock(chip); 1235 if (chip->info->ops->stats_get_sset_count) 1236 count = chip->info->ops->stats_get_sset_count(chip); 1237 if (count < 0) 1238 goto out; 1239 1240 if (chip->info->ops->serdes_get_sset_count) 1241 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1242 port); 1243 if (serdes_count < 0) { 1244 count = serdes_count; 1245 goto out; 1246 } 1247 count += serdes_count; 1248 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1249 1250 out: 1251 mv88e6xxx_reg_unlock(chip); 1252 1253 return count; 1254 } 1255 1256 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1257 uint64_t *data, int types, 1258 u16 bank1_select, u16 histogram) 1259 { 1260 struct mv88e6xxx_hw_stat *stat; 1261 int i, j; 1262 1263 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1264 stat = &mv88e6xxx_hw_stats[i]; 1265 if (stat->type & types) { 1266 mv88e6xxx_reg_lock(chip); 1267 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1268 bank1_select, 1269 histogram); 1270 mv88e6xxx_reg_unlock(chip); 1271 1272 j++; 1273 } 1274 } 1275 return j; 1276 } 1277 1278 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1279 uint64_t *data) 1280 { 1281 return mv88e6xxx_stats_get_stats(chip, port, data, 1282 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1283 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1284 } 1285 1286 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1287 uint64_t *data) 1288 { 1289 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1290 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1291 } 1292 1293 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1294 uint64_t *data) 1295 { 1296 return mv88e6xxx_stats_get_stats(chip, port, data, 1297 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1298 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1299 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1300 } 1301 1302 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1303 uint64_t *data) 1304 { 1305 return mv88e6xxx_stats_get_stats(chip, port, data, 1306 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1307 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1308 0); 1309 } 1310 1311 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1312 uint64_t *data) 1313 { 1314 *data++ = chip->ports[port].atu_member_violation; 1315 *data++ = chip->ports[port].atu_miss_violation; 1316 *data++ = chip->ports[port].atu_full_violation; 1317 *data++ = chip->ports[port].vtu_member_violation; 1318 *data++ = chip->ports[port].vtu_miss_violation; 1319 } 1320 1321 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1322 uint64_t *data) 1323 { 1324 int count = 0; 1325 1326 if (chip->info->ops->stats_get_stats) 1327 count = chip->info->ops->stats_get_stats(chip, port, data); 1328 1329 mv88e6xxx_reg_lock(chip); 1330 if (chip->info->ops->serdes_get_stats) { 1331 data += count; 1332 count = chip->info->ops->serdes_get_stats(chip, port, data); 1333 } 1334 data += count; 1335 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1336 mv88e6xxx_reg_unlock(chip); 1337 } 1338 1339 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1340 uint64_t *data) 1341 { 1342 struct mv88e6xxx_chip *chip = ds->priv; 1343 int ret; 1344 1345 mv88e6xxx_reg_lock(chip); 1346 1347 ret = mv88e6xxx_stats_snapshot(chip, port); 1348 mv88e6xxx_reg_unlock(chip); 1349 1350 if (ret < 0) 1351 return; 1352 1353 mv88e6xxx_get_stats(chip, port, data); 1354 1355 } 1356 1357 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1358 { 1359 struct mv88e6xxx_chip *chip = ds->priv; 1360 int len; 1361 1362 len = 32 * sizeof(u16); 1363 if (chip->info->ops->serdes_get_regs_len) 1364 len += chip->info->ops->serdes_get_regs_len(chip, port); 1365 1366 return len; 1367 } 1368 1369 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1370 struct ethtool_regs *regs, void *_p) 1371 { 1372 struct mv88e6xxx_chip *chip = ds->priv; 1373 int err; 1374 u16 reg; 1375 u16 *p = _p; 1376 int i; 1377 1378 regs->version = chip->info->prod_num; 1379 1380 memset(p, 0xff, 32 * sizeof(u16)); 1381 1382 mv88e6xxx_reg_lock(chip); 1383 1384 for (i = 0; i < 32; i++) { 1385 1386 err = mv88e6xxx_port_read(chip, port, i, ®); 1387 if (!err) 1388 p[i] = reg; 1389 } 1390 1391 if (chip->info->ops->serdes_get_regs) 1392 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1393 1394 mv88e6xxx_reg_unlock(chip); 1395 } 1396 1397 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1398 struct ethtool_eee *e) 1399 { 1400 /* Nothing to do on the port's MAC */ 1401 return 0; 1402 } 1403 1404 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1405 struct ethtool_eee *e) 1406 { 1407 /* Nothing to do on the port's MAC */ 1408 return 0; 1409 } 1410 1411 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1412 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1413 { 1414 struct dsa_switch *ds = chip->ds; 1415 struct dsa_switch_tree *dst = ds->dst; 1416 struct dsa_port *dp, *other_dp; 1417 bool found = false; 1418 u16 pvlan; 1419 1420 /* dev is a physical switch */ 1421 if (dev <= dst->last_switch) { 1422 list_for_each_entry(dp, &dst->ports, list) { 1423 if (dp->ds->index == dev && dp->index == port) { 1424 /* dp might be a DSA link or a user port, so it 1425 * might or might not have a bridge. 1426 * Use the "found" variable for both cases. 1427 */ 1428 found = true; 1429 break; 1430 } 1431 } 1432 /* dev is a virtual bridge */ 1433 } else { 1434 list_for_each_entry(dp, &dst->ports, list) { 1435 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1436 1437 if (!bridge_num) 1438 continue; 1439 1440 if (bridge_num + dst->last_switch != dev) 1441 continue; 1442 1443 found = true; 1444 break; 1445 } 1446 } 1447 1448 /* Prevent frames from unknown switch or virtual bridge */ 1449 if (!found) 1450 return 0; 1451 1452 /* Frames from DSA links and CPU ports can egress any local port */ 1453 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1454 return mv88e6xxx_port_mask(chip); 1455 1456 pvlan = 0; 1457 1458 /* Frames from standalone user ports can only egress on the 1459 * upstream port. 1460 */ 1461 if (!dsa_port_bridge_dev_get(dp)) 1462 return BIT(dsa_switch_upstream_port(ds)); 1463 1464 /* Frames from bridged user ports can egress any local DSA 1465 * links and CPU ports, as well as any local member of their 1466 * bridge group. 1467 */ 1468 dsa_switch_for_each_port(other_dp, ds) 1469 if (other_dp->type == DSA_PORT_TYPE_CPU || 1470 other_dp->type == DSA_PORT_TYPE_DSA || 1471 dsa_port_bridge_same(dp, other_dp)) 1472 pvlan |= BIT(other_dp->index); 1473 1474 return pvlan; 1475 } 1476 1477 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1478 { 1479 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1480 1481 /* prevent frames from going back out of the port they came in on */ 1482 output_ports &= ~BIT(port); 1483 1484 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1485 } 1486 1487 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1488 u8 state) 1489 { 1490 struct mv88e6xxx_chip *chip = ds->priv; 1491 int err; 1492 1493 mv88e6xxx_reg_lock(chip); 1494 err = mv88e6xxx_port_set_state(chip, port, state); 1495 mv88e6xxx_reg_unlock(chip); 1496 1497 if (err) 1498 dev_err(ds->dev, "p%d: failed to update state\n", port); 1499 } 1500 1501 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1502 { 1503 int err; 1504 1505 if (chip->info->ops->ieee_pri_map) { 1506 err = chip->info->ops->ieee_pri_map(chip); 1507 if (err) 1508 return err; 1509 } 1510 1511 if (chip->info->ops->ip_pri_map) { 1512 err = chip->info->ops->ip_pri_map(chip); 1513 if (err) 1514 return err; 1515 } 1516 1517 return 0; 1518 } 1519 1520 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1521 { 1522 struct dsa_switch *ds = chip->ds; 1523 int target, port; 1524 int err; 1525 1526 if (!chip->info->global2_addr) 1527 return 0; 1528 1529 /* Initialize the routing port to the 32 possible target devices */ 1530 for (target = 0; target < 32; target++) { 1531 port = dsa_routing_port(ds, target); 1532 if (port == ds->num_ports) 1533 port = 0x1f; 1534 1535 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1536 if (err) 1537 return err; 1538 } 1539 1540 if (chip->info->ops->set_cascade_port) { 1541 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1542 err = chip->info->ops->set_cascade_port(chip, port); 1543 if (err) 1544 return err; 1545 } 1546 1547 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1548 if (err) 1549 return err; 1550 1551 return 0; 1552 } 1553 1554 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1555 { 1556 /* Clear all trunk masks and mapping */ 1557 if (chip->info->global2_addr) 1558 return mv88e6xxx_g2_trunk_clear(chip); 1559 1560 return 0; 1561 } 1562 1563 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1564 { 1565 if (chip->info->ops->rmu_disable) 1566 return chip->info->ops->rmu_disable(chip); 1567 1568 return 0; 1569 } 1570 1571 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1572 { 1573 if (chip->info->ops->pot_clear) 1574 return chip->info->ops->pot_clear(chip); 1575 1576 return 0; 1577 } 1578 1579 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1580 { 1581 if (chip->info->ops->mgmt_rsvd2cpu) 1582 return chip->info->ops->mgmt_rsvd2cpu(chip); 1583 1584 return 0; 1585 } 1586 1587 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1588 { 1589 int err; 1590 1591 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1592 if (err) 1593 return err; 1594 1595 /* The chips that have a "learn2all" bit in Global1, ATU 1596 * Control are precisely those whose port registers have a 1597 * Message Port bit in Port Control 1 and hence implement 1598 * ->port_setup_message_port. 1599 */ 1600 if (chip->info->ops->port_setup_message_port) { 1601 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1602 if (err) 1603 return err; 1604 } 1605 1606 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1607 } 1608 1609 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1610 { 1611 int port; 1612 int err; 1613 1614 if (!chip->info->ops->irl_init_all) 1615 return 0; 1616 1617 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1618 /* Disable ingress rate limiting by resetting all per port 1619 * ingress rate limit resources to their initial state. 1620 */ 1621 err = chip->info->ops->irl_init_all(chip, port); 1622 if (err) 1623 return err; 1624 } 1625 1626 return 0; 1627 } 1628 1629 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1630 { 1631 if (chip->info->ops->set_switch_mac) { 1632 u8 addr[ETH_ALEN]; 1633 1634 eth_random_addr(addr); 1635 1636 return chip->info->ops->set_switch_mac(chip, addr); 1637 } 1638 1639 return 0; 1640 } 1641 1642 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1643 { 1644 struct dsa_switch_tree *dst = chip->ds->dst; 1645 struct dsa_switch *ds; 1646 struct dsa_port *dp; 1647 u16 pvlan = 0; 1648 1649 if (!mv88e6xxx_has_pvt(chip)) 1650 return 0; 1651 1652 /* Skip the local source device, which uses in-chip port VLAN */ 1653 if (dev != chip->ds->index) { 1654 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1655 1656 ds = dsa_switch_find(dst->index, dev); 1657 dp = ds ? dsa_to_port(ds, port) : NULL; 1658 if (dp && dp->lag) { 1659 /* As the PVT is used to limit flooding of 1660 * FORWARD frames, which use the LAG ID as the 1661 * source port, we must translate dev/port to 1662 * the special "LAG device" in the PVT, using 1663 * the LAG ID (one-based) as the port number 1664 * (zero-based). 1665 */ 1666 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1667 port = dsa_port_lag_id_get(dp) - 1; 1668 } 1669 } 1670 1671 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1672 } 1673 1674 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1675 { 1676 int dev, port; 1677 int err; 1678 1679 if (!mv88e6xxx_has_pvt(chip)) 1680 return 0; 1681 1682 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1683 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1684 */ 1685 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1686 if (err) 1687 return err; 1688 1689 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1690 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1691 err = mv88e6xxx_pvt_map(chip, dev, port); 1692 if (err) 1693 return err; 1694 } 1695 } 1696 1697 return 0; 1698 } 1699 1700 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1701 u16 fid) 1702 { 1703 if (dsa_to_port(chip->ds, port)->lag) 1704 /* Hardware is incapable of fast-aging a LAG through a 1705 * regular ATU move operation. Until we have something 1706 * more fancy in place this is a no-op. 1707 */ 1708 return -EOPNOTSUPP; 1709 1710 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1711 } 1712 1713 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1714 { 1715 struct mv88e6xxx_chip *chip = ds->priv; 1716 int err; 1717 1718 mv88e6xxx_reg_lock(chip); 1719 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1720 mv88e6xxx_reg_unlock(chip); 1721 1722 if (err) 1723 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1724 port, err); 1725 } 1726 1727 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1728 { 1729 if (!mv88e6xxx_max_vid(chip)) 1730 return 0; 1731 1732 return mv88e6xxx_g1_vtu_flush(chip); 1733 } 1734 1735 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1736 struct mv88e6xxx_vtu_entry *entry) 1737 { 1738 int err; 1739 1740 if (!chip->info->ops->vtu_getnext) 1741 return -EOPNOTSUPP; 1742 1743 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1744 entry->valid = false; 1745 1746 err = chip->info->ops->vtu_getnext(chip, entry); 1747 1748 if (entry->vid != vid) 1749 entry->valid = false; 1750 1751 return err; 1752 } 1753 1754 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1755 int (*cb)(struct mv88e6xxx_chip *chip, 1756 const struct mv88e6xxx_vtu_entry *entry, 1757 void *priv), 1758 void *priv) 1759 { 1760 struct mv88e6xxx_vtu_entry entry = { 1761 .vid = mv88e6xxx_max_vid(chip), 1762 .valid = false, 1763 }; 1764 int err; 1765 1766 if (!chip->info->ops->vtu_getnext) 1767 return -EOPNOTSUPP; 1768 1769 do { 1770 err = chip->info->ops->vtu_getnext(chip, &entry); 1771 if (err) 1772 return err; 1773 1774 if (!entry.valid) 1775 break; 1776 1777 err = cb(chip, &entry, priv); 1778 if (err) 1779 return err; 1780 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1781 1782 return 0; 1783 } 1784 1785 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1786 struct mv88e6xxx_vtu_entry *entry) 1787 { 1788 if (!chip->info->ops->vtu_loadpurge) 1789 return -EOPNOTSUPP; 1790 1791 return chip->info->ops->vtu_loadpurge(chip, entry); 1792 } 1793 1794 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1795 const struct mv88e6xxx_vtu_entry *entry, 1796 void *_fid_bitmap) 1797 { 1798 unsigned long *fid_bitmap = _fid_bitmap; 1799 1800 set_bit(entry->fid, fid_bitmap); 1801 return 0; 1802 } 1803 1804 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1805 { 1806 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1807 1808 /* Every FID has an associated VID, so walking the VTU 1809 * will discover the full set of FIDs in use. 1810 */ 1811 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1812 } 1813 1814 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1815 { 1816 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1817 int err; 1818 1819 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1820 if (err) 1821 return err; 1822 1823 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID); 1824 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1825 return -ENOSPC; 1826 1827 /* Clear the database */ 1828 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1829 } 1830 1831 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1832 struct mv88e6xxx_stu_entry *entry) 1833 { 1834 if (!chip->info->ops->stu_loadpurge) 1835 return -EOPNOTSUPP; 1836 1837 return chip->info->ops->stu_loadpurge(chip, entry); 1838 } 1839 1840 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1841 { 1842 struct mv88e6xxx_stu_entry stu = { 1843 .valid = true, 1844 .sid = 0 1845 }; 1846 1847 if (!mv88e6xxx_has_stu(chip)) 1848 return 0; 1849 1850 /* Make sure that SID 0 is always valid. This is used by VTU 1851 * entries that do not make use of the STU, e.g. when creating 1852 * a VLAN upper on a port that is also part of a VLAN 1853 * filtering bridge. 1854 */ 1855 return mv88e6xxx_stu_loadpurge(chip, &stu); 1856 } 1857 1858 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1859 { 1860 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1861 struct mv88e6xxx_mst *mst; 1862 1863 __set_bit(0, busy); 1864 1865 list_for_each_entry(mst, &chip->msts, node) 1866 __set_bit(mst->stu.sid, busy); 1867 1868 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1869 1870 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1871 } 1872 1873 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1874 { 1875 struct mv88e6xxx_mst *mst, *tmp; 1876 int err; 1877 1878 if (!sid) 1879 return 0; 1880 1881 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1882 if (mst->stu.sid != sid) 1883 continue; 1884 1885 if (!refcount_dec_and_test(&mst->refcnt)) 1886 return 0; 1887 1888 mst->stu.valid = false; 1889 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1890 if (err) { 1891 refcount_set(&mst->refcnt, 1); 1892 return err; 1893 } 1894 1895 list_del(&mst->node); 1896 kfree(mst); 1897 return 0; 1898 } 1899 1900 return -ENOENT; 1901 } 1902 1903 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1904 u16 msti, u8 *sid) 1905 { 1906 struct mv88e6xxx_mst *mst; 1907 int err, i; 1908 1909 if (!mv88e6xxx_has_stu(chip)) { 1910 err = -EOPNOTSUPP; 1911 goto err; 1912 } 1913 1914 if (!msti) { 1915 *sid = 0; 1916 return 0; 1917 } 1918 1919 list_for_each_entry(mst, &chip->msts, node) { 1920 if (mst->br == br && mst->msti == msti) { 1921 refcount_inc(&mst->refcnt); 1922 *sid = mst->stu.sid; 1923 return 0; 1924 } 1925 } 1926 1927 err = mv88e6xxx_sid_get(chip, sid); 1928 if (err) 1929 goto err; 1930 1931 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 1932 if (!mst) { 1933 err = -ENOMEM; 1934 goto err; 1935 } 1936 1937 INIT_LIST_HEAD(&mst->node); 1938 refcount_set(&mst->refcnt, 1); 1939 mst->br = br; 1940 mst->msti = msti; 1941 mst->stu.valid = true; 1942 mst->stu.sid = *sid; 1943 1944 /* The bridge starts out all ports in the disabled state. But 1945 * a STU state of disabled means to go by the port-global 1946 * state. So we set all user port's initial state to blocking, 1947 * to match the bridge's behavior. 1948 */ 1949 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 1950 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 1951 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 1952 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 1953 1954 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1955 if (err) 1956 goto err_free; 1957 1958 list_add_tail(&mst->node, &chip->msts); 1959 return 0; 1960 1961 err_free: 1962 kfree(mst); 1963 err: 1964 return err; 1965 } 1966 1967 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 1968 const struct switchdev_mst_state *st) 1969 { 1970 struct dsa_port *dp = dsa_to_port(ds, port); 1971 struct mv88e6xxx_chip *chip = ds->priv; 1972 struct mv88e6xxx_mst *mst; 1973 u8 state; 1974 int err; 1975 1976 if (!mv88e6xxx_has_stu(chip)) 1977 return -EOPNOTSUPP; 1978 1979 switch (st->state) { 1980 case BR_STATE_DISABLED: 1981 case BR_STATE_BLOCKING: 1982 case BR_STATE_LISTENING: 1983 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 1984 break; 1985 case BR_STATE_LEARNING: 1986 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 1987 break; 1988 case BR_STATE_FORWARDING: 1989 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1990 break; 1991 default: 1992 return -EINVAL; 1993 } 1994 1995 list_for_each_entry(mst, &chip->msts, node) { 1996 if (mst->br == dsa_port_bridge_dev_get(dp) && 1997 mst->msti == st->msti) { 1998 if (mst->stu.state[port] == state) 1999 return 0; 2000 2001 mst->stu.state[port] = state; 2002 mv88e6xxx_reg_lock(chip); 2003 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2004 mv88e6xxx_reg_unlock(chip); 2005 return err; 2006 } 2007 } 2008 2009 return -ENOENT; 2010 } 2011 2012 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2013 u16 vid) 2014 { 2015 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 2016 struct mv88e6xxx_chip *chip = ds->priv; 2017 struct mv88e6xxx_vtu_entry vlan; 2018 int err; 2019 2020 /* DSA and CPU ports have to be members of multiple vlans */ 2021 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2022 return 0; 2023 2024 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2025 if (err) 2026 return err; 2027 2028 if (!vlan.valid) 2029 return 0; 2030 2031 dsa_switch_for_each_user_port(other_dp, ds) { 2032 struct net_device *other_br; 2033 2034 if (vlan.member[other_dp->index] == 2035 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2036 continue; 2037 2038 if (dsa_port_bridge_same(dp, other_dp)) 2039 break; /* same bridge, check next VLAN */ 2040 2041 other_br = dsa_port_bridge_dev_get(other_dp); 2042 if (!other_br) 2043 continue; 2044 2045 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2046 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2047 return -EOPNOTSUPP; 2048 } 2049 2050 return 0; 2051 } 2052 2053 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2054 { 2055 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2056 struct net_device *br = dsa_port_bridge_dev_get(dp); 2057 struct mv88e6xxx_port *p = &chip->ports[port]; 2058 u16 pvid = MV88E6XXX_VID_STANDALONE; 2059 bool drop_untagged = false; 2060 int err; 2061 2062 if (br) { 2063 if (br_vlan_enabled(br)) { 2064 pvid = p->bridge_pvid.vid; 2065 drop_untagged = !p->bridge_pvid.valid; 2066 } else { 2067 pvid = MV88E6XXX_VID_BRIDGED; 2068 } 2069 } 2070 2071 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2072 if (err) 2073 return err; 2074 2075 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2076 } 2077 2078 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2079 bool vlan_filtering, 2080 struct netlink_ext_ack *extack) 2081 { 2082 struct mv88e6xxx_chip *chip = ds->priv; 2083 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2084 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2085 int err; 2086 2087 if (!mv88e6xxx_max_vid(chip)) 2088 return -EOPNOTSUPP; 2089 2090 mv88e6xxx_reg_lock(chip); 2091 2092 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2093 if (err) 2094 goto unlock; 2095 2096 err = mv88e6xxx_port_commit_pvid(chip, port); 2097 if (err) 2098 goto unlock; 2099 2100 unlock: 2101 mv88e6xxx_reg_unlock(chip); 2102 2103 return err; 2104 } 2105 2106 static int 2107 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2108 const struct switchdev_obj_port_vlan *vlan) 2109 { 2110 struct mv88e6xxx_chip *chip = ds->priv; 2111 int err; 2112 2113 if (!mv88e6xxx_max_vid(chip)) 2114 return -EOPNOTSUPP; 2115 2116 /* If the requested port doesn't belong to the same bridge as the VLAN 2117 * members, do not support it (yet) and fallback to software VLAN. 2118 */ 2119 mv88e6xxx_reg_lock(chip); 2120 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2121 mv88e6xxx_reg_unlock(chip); 2122 2123 return err; 2124 } 2125 2126 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2127 const unsigned char *addr, u16 vid, 2128 u8 state) 2129 { 2130 struct mv88e6xxx_atu_entry entry; 2131 struct mv88e6xxx_vtu_entry vlan; 2132 u16 fid; 2133 int err; 2134 2135 /* Ports have two private address databases: one for when the port is 2136 * standalone and one for when the port is under a bridge and the 2137 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2138 * address database to remain 100% empty, so we never load an ATU entry 2139 * into a standalone port's database. Therefore, translate the null 2140 * VLAN ID into the port's database used for VLAN-unaware bridging. 2141 */ 2142 if (vid == 0) { 2143 fid = MV88E6XXX_FID_BRIDGED; 2144 } else { 2145 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2146 if (err) 2147 return err; 2148 2149 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2150 if (!vlan.valid) 2151 return -EOPNOTSUPP; 2152 2153 fid = vlan.fid; 2154 } 2155 2156 entry.state = 0; 2157 ether_addr_copy(entry.mac, addr); 2158 eth_addr_dec(entry.mac); 2159 2160 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2161 if (err) 2162 return err; 2163 2164 /* Initialize a fresh ATU entry if it isn't found */ 2165 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2166 memset(&entry, 0, sizeof(entry)); 2167 ether_addr_copy(entry.mac, addr); 2168 } 2169 2170 /* Purge the ATU entry only if no port is using it anymore */ 2171 if (!state) { 2172 entry.portvec &= ~BIT(port); 2173 if (!entry.portvec) 2174 entry.state = 0; 2175 } else { 2176 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2177 entry.portvec = BIT(port); 2178 else 2179 entry.portvec |= BIT(port); 2180 2181 entry.state = state; 2182 } 2183 2184 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2185 } 2186 2187 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2188 const struct mv88e6xxx_policy *policy) 2189 { 2190 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2191 enum mv88e6xxx_policy_action action = policy->action; 2192 const u8 *addr = policy->addr; 2193 u16 vid = policy->vid; 2194 u8 state; 2195 int err; 2196 int id; 2197 2198 if (!chip->info->ops->port_set_policy) 2199 return -EOPNOTSUPP; 2200 2201 switch (mapping) { 2202 case MV88E6XXX_POLICY_MAPPING_DA: 2203 case MV88E6XXX_POLICY_MAPPING_SA: 2204 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2205 state = 0; /* Dissociate the port and address */ 2206 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2207 is_multicast_ether_addr(addr)) 2208 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2209 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2210 is_unicast_ether_addr(addr)) 2211 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2212 else 2213 return -EOPNOTSUPP; 2214 2215 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2216 state); 2217 if (err) 2218 return err; 2219 break; 2220 default: 2221 return -EOPNOTSUPP; 2222 } 2223 2224 /* Skip the port's policy clearing if the mapping is still in use */ 2225 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2226 idr_for_each_entry(&chip->policies, policy, id) 2227 if (policy->port == port && 2228 policy->mapping == mapping && 2229 policy->action != action) 2230 return 0; 2231 2232 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2233 } 2234 2235 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2236 struct ethtool_rx_flow_spec *fs) 2237 { 2238 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2239 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2240 enum mv88e6xxx_policy_mapping mapping; 2241 enum mv88e6xxx_policy_action action; 2242 struct mv88e6xxx_policy *policy; 2243 u16 vid = 0; 2244 u8 *addr; 2245 int err; 2246 int id; 2247 2248 if (fs->location != RX_CLS_LOC_ANY) 2249 return -EINVAL; 2250 2251 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2252 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2253 else 2254 return -EOPNOTSUPP; 2255 2256 switch (fs->flow_type & ~FLOW_EXT) { 2257 case ETHER_FLOW: 2258 if (!is_zero_ether_addr(mac_mask->h_dest) && 2259 is_zero_ether_addr(mac_mask->h_source)) { 2260 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2261 addr = mac_entry->h_dest; 2262 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2263 !is_zero_ether_addr(mac_mask->h_source)) { 2264 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2265 addr = mac_entry->h_source; 2266 } else { 2267 /* Cannot support DA and SA mapping in the same rule */ 2268 return -EOPNOTSUPP; 2269 } 2270 break; 2271 default: 2272 return -EOPNOTSUPP; 2273 } 2274 2275 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2276 if (fs->m_ext.vlan_tci != htons(0xffff)) 2277 return -EOPNOTSUPP; 2278 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2279 } 2280 2281 idr_for_each_entry(&chip->policies, policy, id) { 2282 if (policy->port == port && policy->mapping == mapping && 2283 policy->action == action && policy->vid == vid && 2284 ether_addr_equal(policy->addr, addr)) 2285 return -EEXIST; 2286 } 2287 2288 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2289 if (!policy) 2290 return -ENOMEM; 2291 2292 fs->location = 0; 2293 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2294 GFP_KERNEL); 2295 if (err) { 2296 devm_kfree(chip->dev, policy); 2297 return err; 2298 } 2299 2300 memcpy(&policy->fs, fs, sizeof(*fs)); 2301 ether_addr_copy(policy->addr, addr); 2302 policy->mapping = mapping; 2303 policy->action = action; 2304 policy->port = port; 2305 policy->vid = vid; 2306 2307 err = mv88e6xxx_policy_apply(chip, port, policy); 2308 if (err) { 2309 idr_remove(&chip->policies, fs->location); 2310 devm_kfree(chip->dev, policy); 2311 return err; 2312 } 2313 2314 return 0; 2315 } 2316 2317 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2318 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2319 { 2320 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2321 struct mv88e6xxx_chip *chip = ds->priv; 2322 struct mv88e6xxx_policy *policy; 2323 int err; 2324 int id; 2325 2326 mv88e6xxx_reg_lock(chip); 2327 2328 switch (rxnfc->cmd) { 2329 case ETHTOOL_GRXCLSRLCNT: 2330 rxnfc->data = 0; 2331 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2332 rxnfc->rule_cnt = 0; 2333 idr_for_each_entry(&chip->policies, policy, id) 2334 if (policy->port == port) 2335 rxnfc->rule_cnt++; 2336 err = 0; 2337 break; 2338 case ETHTOOL_GRXCLSRULE: 2339 err = -ENOENT; 2340 policy = idr_find(&chip->policies, fs->location); 2341 if (policy) { 2342 memcpy(fs, &policy->fs, sizeof(*fs)); 2343 err = 0; 2344 } 2345 break; 2346 case ETHTOOL_GRXCLSRLALL: 2347 rxnfc->data = 0; 2348 rxnfc->rule_cnt = 0; 2349 idr_for_each_entry(&chip->policies, policy, id) 2350 if (policy->port == port) 2351 rule_locs[rxnfc->rule_cnt++] = id; 2352 err = 0; 2353 break; 2354 default: 2355 err = -EOPNOTSUPP; 2356 break; 2357 } 2358 2359 mv88e6xxx_reg_unlock(chip); 2360 2361 return err; 2362 } 2363 2364 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2365 struct ethtool_rxnfc *rxnfc) 2366 { 2367 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2368 struct mv88e6xxx_chip *chip = ds->priv; 2369 struct mv88e6xxx_policy *policy; 2370 int err; 2371 2372 mv88e6xxx_reg_lock(chip); 2373 2374 switch (rxnfc->cmd) { 2375 case ETHTOOL_SRXCLSRLINS: 2376 err = mv88e6xxx_policy_insert(chip, port, fs); 2377 break; 2378 case ETHTOOL_SRXCLSRLDEL: 2379 err = -ENOENT; 2380 policy = idr_remove(&chip->policies, fs->location); 2381 if (policy) { 2382 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2383 err = mv88e6xxx_policy_apply(chip, port, policy); 2384 devm_kfree(chip->dev, policy); 2385 } 2386 break; 2387 default: 2388 err = -EOPNOTSUPP; 2389 break; 2390 } 2391 2392 mv88e6xxx_reg_unlock(chip); 2393 2394 return err; 2395 } 2396 2397 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2398 u16 vid) 2399 { 2400 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2401 u8 broadcast[ETH_ALEN]; 2402 2403 eth_broadcast_addr(broadcast); 2404 2405 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2406 } 2407 2408 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2409 { 2410 int port; 2411 int err; 2412 2413 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2414 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2415 struct net_device *brport; 2416 2417 if (dsa_is_unused_port(chip->ds, port)) 2418 continue; 2419 2420 brport = dsa_port_to_bridge_port(dp); 2421 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2422 /* Skip bridged user ports where broadcast 2423 * flooding is disabled. 2424 */ 2425 continue; 2426 2427 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2428 if (err) 2429 return err; 2430 } 2431 2432 return 0; 2433 } 2434 2435 struct mv88e6xxx_port_broadcast_sync_ctx { 2436 int port; 2437 bool flood; 2438 }; 2439 2440 static int 2441 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2442 const struct mv88e6xxx_vtu_entry *vlan, 2443 void *_ctx) 2444 { 2445 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2446 u8 broadcast[ETH_ALEN]; 2447 u8 state; 2448 2449 if (ctx->flood) 2450 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2451 else 2452 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2453 2454 eth_broadcast_addr(broadcast); 2455 2456 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2457 vlan->vid, state); 2458 } 2459 2460 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2461 bool flood) 2462 { 2463 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2464 .port = port, 2465 .flood = flood, 2466 }; 2467 struct mv88e6xxx_vtu_entry vid0 = { 2468 .vid = 0, 2469 }; 2470 int err; 2471 2472 /* Update the port's private database... */ 2473 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2474 if (err) 2475 return err; 2476 2477 /* ...and the database for all VLANs. */ 2478 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2479 &ctx); 2480 } 2481 2482 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2483 u16 vid, u8 member, bool warn) 2484 { 2485 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2486 struct mv88e6xxx_vtu_entry vlan; 2487 int i, err; 2488 2489 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2490 if (err) 2491 return err; 2492 2493 if (!vlan.valid) { 2494 memset(&vlan, 0, sizeof(vlan)); 2495 2496 if (vid == MV88E6XXX_VID_STANDALONE) 2497 vlan.policy = true; 2498 2499 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2500 if (err) 2501 return err; 2502 2503 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2504 if (i == port) 2505 vlan.member[i] = member; 2506 else 2507 vlan.member[i] = non_member; 2508 2509 vlan.vid = vid; 2510 vlan.valid = true; 2511 2512 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2513 if (err) 2514 return err; 2515 2516 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2517 if (err) 2518 return err; 2519 } else if (vlan.member[port] != member) { 2520 vlan.member[port] = member; 2521 2522 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2523 if (err) 2524 return err; 2525 } else if (warn) { 2526 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2527 port, vid); 2528 } 2529 2530 return 0; 2531 } 2532 2533 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2534 const struct switchdev_obj_port_vlan *vlan, 2535 struct netlink_ext_ack *extack) 2536 { 2537 struct mv88e6xxx_chip *chip = ds->priv; 2538 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2539 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2540 struct mv88e6xxx_port *p = &chip->ports[port]; 2541 bool warn; 2542 u8 member; 2543 int err; 2544 2545 if (!vlan->vid) 2546 return 0; 2547 2548 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2549 if (err) 2550 return err; 2551 2552 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2553 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2554 else if (untagged) 2555 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2556 else 2557 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2558 2559 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2560 * and then the CPU port. Do not warn for duplicates for the CPU port. 2561 */ 2562 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2563 2564 mv88e6xxx_reg_lock(chip); 2565 2566 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2567 if (err) { 2568 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2569 vlan->vid, untagged ? 'u' : 't'); 2570 goto out; 2571 } 2572 2573 if (pvid) { 2574 p->bridge_pvid.vid = vlan->vid; 2575 p->bridge_pvid.valid = true; 2576 2577 err = mv88e6xxx_port_commit_pvid(chip, port); 2578 if (err) 2579 goto out; 2580 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2581 /* The old pvid was reinstalled as a non-pvid VLAN */ 2582 p->bridge_pvid.valid = false; 2583 2584 err = mv88e6xxx_port_commit_pvid(chip, port); 2585 if (err) 2586 goto out; 2587 } 2588 2589 out: 2590 mv88e6xxx_reg_unlock(chip); 2591 2592 return err; 2593 } 2594 2595 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2596 int port, u16 vid) 2597 { 2598 struct mv88e6xxx_vtu_entry vlan; 2599 int i, err; 2600 2601 if (!vid) 2602 return 0; 2603 2604 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2605 if (err) 2606 return err; 2607 2608 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2609 * tell switchdev that this VLAN is likely handled in software. 2610 */ 2611 if (!vlan.valid || 2612 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2613 return -EOPNOTSUPP; 2614 2615 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2616 2617 /* keep the VLAN unless all ports are excluded */ 2618 vlan.valid = false; 2619 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2620 if (vlan.member[i] != 2621 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2622 vlan.valid = true; 2623 break; 2624 } 2625 } 2626 2627 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2628 if (err) 2629 return err; 2630 2631 if (!vlan.valid) { 2632 err = mv88e6xxx_mst_put(chip, vlan.sid); 2633 if (err) 2634 return err; 2635 } 2636 2637 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2638 } 2639 2640 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2641 const struct switchdev_obj_port_vlan *vlan) 2642 { 2643 struct mv88e6xxx_chip *chip = ds->priv; 2644 struct mv88e6xxx_port *p = &chip->ports[port]; 2645 int err = 0; 2646 u16 pvid; 2647 2648 if (!mv88e6xxx_max_vid(chip)) 2649 return -EOPNOTSUPP; 2650 2651 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2652 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2653 * switchdev workqueue to ensure that all FDB entries are deleted 2654 * before we remove the VLAN. 2655 */ 2656 dsa_flush_workqueue(); 2657 2658 mv88e6xxx_reg_lock(chip); 2659 2660 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2661 if (err) 2662 goto unlock; 2663 2664 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2665 if (err) 2666 goto unlock; 2667 2668 if (vlan->vid == pvid) { 2669 p->bridge_pvid.valid = false; 2670 2671 err = mv88e6xxx_port_commit_pvid(chip, port); 2672 if (err) 2673 goto unlock; 2674 } 2675 2676 unlock: 2677 mv88e6xxx_reg_unlock(chip); 2678 2679 return err; 2680 } 2681 2682 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2683 { 2684 struct mv88e6xxx_chip *chip = ds->priv; 2685 struct mv88e6xxx_vtu_entry vlan; 2686 int err; 2687 2688 mv88e6xxx_reg_lock(chip); 2689 2690 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2691 if (err) 2692 goto unlock; 2693 2694 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2695 2696 unlock: 2697 mv88e6xxx_reg_unlock(chip); 2698 2699 return err; 2700 } 2701 2702 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2703 struct dsa_bridge bridge, 2704 const struct switchdev_vlan_msti *msti) 2705 { 2706 struct mv88e6xxx_chip *chip = ds->priv; 2707 struct mv88e6xxx_vtu_entry vlan; 2708 u8 old_sid, new_sid; 2709 int err; 2710 2711 if (!mv88e6xxx_has_stu(chip)) 2712 return -EOPNOTSUPP; 2713 2714 mv88e6xxx_reg_lock(chip); 2715 2716 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2717 if (err) 2718 goto unlock; 2719 2720 if (!vlan.valid) { 2721 err = -EINVAL; 2722 goto unlock; 2723 } 2724 2725 old_sid = vlan.sid; 2726 2727 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2728 if (err) 2729 goto unlock; 2730 2731 if (new_sid != old_sid) { 2732 vlan.sid = new_sid; 2733 2734 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2735 if (err) { 2736 mv88e6xxx_mst_put(chip, new_sid); 2737 goto unlock; 2738 } 2739 } 2740 2741 err = mv88e6xxx_mst_put(chip, old_sid); 2742 2743 unlock: 2744 mv88e6xxx_reg_unlock(chip); 2745 return err; 2746 } 2747 2748 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2749 const unsigned char *addr, u16 vid, 2750 struct dsa_db db) 2751 { 2752 struct mv88e6xxx_chip *chip = ds->priv; 2753 int err; 2754 2755 mv88e6xxx_reg_lock(chip); 2756 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2757 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2758 mv88e6xxx_reg_unlock(chip); 2759 2760 return err; 2761 } 2762 2763 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2764 const unsigned char *addr, u16 vid, 2765 struct dsa_db db) 2766 { 2767 struct mv88e6xxx_chip *chip = ds->priv; 2768 int err; 2769 2770 mv88e6xxx_reg_lock(chip); 2771 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2772 mv88e6xxx_reg_unlock(chip); 2773 2774 return err; 2775 } 2776 2777 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2778 u16 fid, u16 vid, int port, 2779 dsa_fdb_dump_cb_t *cb, void *data) 2780 { 2781 struct mv88e6xxx_atu_entry addr; 2782 bool is_static; 2783 int err; 2784 2785 addr.state = 0; 2786 eth_broadcast_addr(addr.mac); 2787 2788 do { 2789 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2790 if (err) 2791 return err; 2792 2793 if (!addr.state) 2794 break; 2795 2796 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2797 continue; 2798 2799 if (!is_unicast_ether_addr(addr.mac)) 2800 continue; 2801 2802 is_static = (addr.state == 2803 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2804 err = cb(addr.mac, vid, is_static, data); 2805 if (err) 2806 return err; 2807 } while (!is_broadcast_ether_addr(addr.mac)); 2808 2809 return err; 2810 } 2811 2812 struct mv88e6xxx_port_db_dump_vlan_ctx { 2813 int port; 2814 dsa_fdb_dump_cb_t *cb; 2815 void *data; 2816 }; 2817 2818 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2819 const struct mv88e6xxx_vtu_entry *entry, 2820 void *_data) 2821 { 2822 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2823 2824 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2825 ctx->port, ctx->cb, ctx->data); 2826 } 2827 2828 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2829 dsa_fdb_dump_cb_t *cb, void *data) 2830 { 2831 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2832 .port = port, 2833 .cb = cb, 2834 .data = data, 2835 }; 2836 u16 fid; 2837 int err; 2838 2839 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2840 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2841 if (err) 2842 return err; 2843 2844 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2845 if (err) 2846 return err; 2847 2848 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2849 } 2850 2851 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2852 dsa_fdb_dump_cb_t *cb, void *data) 2853 { 2854 struct mv88e6xxx_chip *chip = ds->priv; 2855 int err; 2856 2857 mv88e6xxx_reg_lock(chip); 2858 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2859 mv88e6xxx_reg_unlock(chip); 2860 2861 return err; 2862 } 2863 2864 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2865 struct dsa_bridge bridge) 2866 { 2867 struct dsa_switch *ds = chip->ds; 2868 struct dsa_switch_tree *dst = ds->dst; 2869 struct dsa_port *dp; 2870 int err; 2871 2872 list_for_each_entry(dp, &dst->ports, list) { 2873 if (dsa_port_offloads_bridge(dp, &bridge)) { 2874 if (dp->ds == ds) { 2875 /* This is a local bridge group member, 2876 * remap its Port VLAN Map. 2877 */ 2878 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2879 if (err) 2880 return err; 2881 } else { 2882 /* This is an external bridge group member, 2883 * remap its cross-chip Port VLAN Table entry. 2884 */ 2885 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2886 dp->index); 2887 if (err) 2888 return err; 2889 } 2890 } 2891 } 2892 2893 return 0; 2894 } 2895 2896 /* Treat the software bridge as a virtual single-port switch behind the 2897 * CPU and map in the PVT. First dst->last_switch elements are taken by 2898 * physical switches, so start from beyond that range. 2899 */ 2900 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2901 unsigned int bridge_num) 2902 { 2903 u8 dev = bridge_num + ds->dst->last_switch; 2904 struct mv88e6xxx_chip *chip = ds->priv; 2905 2906 return mv88e6xxx_pvt_map(chip, dev, 0); 2907 } 2908 2909 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2910 struct dsa_bridge bridge, 2911 bool *tx_fwd_offload, 2912 struct netlink_ext_ack *extack) 2913 { 2914 struct mv88e6xxx_chip *chip = ds->priv; 2915 int err; 2916 2917 mv88e6xxx_reg_lock(chip); 2918 2919 err = mv88e6xxx_bridge_map(chip, bridge); 2920 if (err) 2921 goto unlock; 2922 2923 err = mv88e6xxx_port_set_map_da(chip, port, true); 2924 if (err) 2925 goto unlock; 2926 2927 err = mv88e6xxx_port_commit_pvid(chip, port); 2928 if (err) 2929 goto unlock; 2930 2931 if (mv88e6xxx_has_pvt(chip)) { 2932 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2933 if (err) 2934 goto unlock; 2935 2936 *tx_fwd_offload = true; 2937 } 2938 2939 unlock: 2940 mv88e6xxx_reg_unlock(chip); 2941 2942 return err; 2943 } 2944 2945 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2946 struct dsa_bridge bridge) 2947 { 2948 struct mv88e6xxx_chip *chip = ds->priv; 2949 int err; 2950 2951 mv88e6xxx_reg_lock(chip); 2952 2953 if (bridge.tx_fwd_offload && 2954 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2955 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2956 2957 if (mv88e6xxx_bridge_map(chip, bridge) || 2958 mv88e6xxx_port_vlan_map(chip, port)) 2959 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2960 2961 err = mv88e6xxx_port_set_map_da(chip, port, false); 2962 if (err) 2963 dev_err(ds->dev, 2964 "port %d failed to restore map-DA: %pe\n", 2965 port, ERR_PTR(err)); 2966 2967 err = mv88e6xxx_port_commit_pvid(chip, port); 2968 if (err) 2969 dev_err(ds->dev, 2970 "port %d failed to restore standalone pvid: %pe\n", 2971 port, ERR_PTR(err)); 2972 2973 mv88e6xxx_reg_unlock(chip); 2974 } 2975 2976 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2977 int tree_index, int sw_index, 2978 int port, struct dsa_bridge bridge, 2979 struct netlink_ext_ack *extack) 2980 { 2981 struct mv88e6xxx_chip *chip = ds->priv; 2982 int err; 2983 2984 if (tree_index != ds->dst->index) 2985 return 0; 2986 2987 mv88e6xxx_reg_lock(chip); 2988 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2989 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2990 mv88e6xxx_reg_unlock(chip); 2991 2992 return err; 2993 } 2994 2995 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2996 int tree_index, int sw_index, 2997 int port, struct dsa_bridge bridge) 2998 { 2999 struct mv88e6xxx_chip *chip = ds->priv; 3000 3001 if (tree_index != ds->dst->index) 3002 return; 3003 3004 mv88e6xxx_reg_lock(chip); 3005 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 3006 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3007 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3008 mv88e6xxx_reg_unlock(chip); 3009 } 3010 3011 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 3012 { 3013 if (chip->info->ops->reset) 3014 return chip->info->ops->reset(chip); 3015 3016 return 0; 3017 } 3018 3019 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 3020 { 3021 struct gpio_desc *gpiod = chip->reset; 3022 3023 /* If there is a GPIO connected to the reset pin, toggle it */ 3024 if (gpiod) { 3025 gpiod_set_value_cansleep(gpiod, 1); 3026 usleep_range(10000, 20000); 3027 gpiod_set_value_cansleep(gpiod, 0); 3028 usleep_range(10000, 20000); 3029 3030 mv88e6xxx_g1_wait_eeprom_done(chip); 3031 } 3032 } 3033 3034 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3035 { 3036 int i, err; 3037 3038 /* Set all ports to the Disabled state */ 3039 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3040 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3041 if (err) 3042 return err; 3043 } 3044 3045 /* Wait for transmit queues to drain, 3046 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3047 */ 3048 usleep_range(2000, 4000); 3049 3050 return 0; 3051 } 3052 3053 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3054 { 3055 int err; 3056 3057 err = mv88e6xxx_disable_ports(chip); 3058 if (err) 3059 return err; 3060 3061 mv88e6xxx_hardware_reset(chip); 3062 3063 return mv88e6xxx_software_reset(chip); 3064 } 3065 3066 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3067 enum mv88e6xxx_frame_mode frame, 3068 enum mv88e6xxx_egress_mode egress, u16 etype) 3069 { 3070 int err; 3071 3072 if (!chip->info->ops->port_set_frame_mode) 3073 return -EOPNOTSUPP; 3074 3075 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3076 if (err) 3077 return err; 3078 3079 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3080 if (err) 3081 return err; 3082 3083 if (chip->info->ops->port_set_ether_type) 3084 return chip->info->ops->port_set_ether_type(chip, port, etype); 3085 3086 return 0; 3087 } 3088 3089 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3090 { 3091 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3092 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3093 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3094 } 3095 3096 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3097 { 3098 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3099 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3100 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3101 } 3102 3103 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3104 { 3105 return mv88e6xxx_set_port_mode(chip, port, 3106 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3107 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3108 ETH_P_EDSA); 3109 } 3110 3111 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3112 { 3113 if (dsa_is_dsa_port(chip->ds, port)) 3114 return mv88e6xxx_set_port_mode_dsa(chip, port); 3115 3116 if (dsa_is_user_port(chip->ds, port)) 3117 return mv88e6xxx_set_port_mode_normal(chip, port); 3118 3119 /* Setup CPU port mode depending on its supported tag format */ 3120 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3121 return mv88e6xxx_set_port_mode_dsa(chip, port); 3122 3123 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3124 return mv88e6xxx_set_port_mode_edsa(chip, port); 3125 3126 return -EINVAL; 3127 } 3128 3129 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3130 { 3131 bool message = dsa_is_dsa_port(chip->ds, port); 3132 3133 return mv88e6xxx_port_set_message_port(chip, port, message); 3134 } 3135 3136 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3137 { 3138 int err; 3139 3140 if (chip->info->ops->port_set_ucast_flood) { 3141 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3142 if (err) 3143 return err; 3144 } 3145 if (chip->info->ops->port_set_mcast_flood) { 3146 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3147 if (err) 3148 return err; 3149 } 3150 3151 return 0; 3152 } 3153 3154 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 3155 { 3156 struct mv88e6xxx_port *mvp = dev_id; 3157 struct mv88e6xxx_chip *chip = mvp->chip; 3158 irqreturn_t ret = IRQ_NONE; 3159 int port = mvp->port; 3160 int lane; 3161 3162 mv88e6xxx_reg_lock(chip); 3163 lane = mv88e6xxx_serdes_get_lane(chip, port); 3164 if (lane >= 0) 3165 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 3166 mv88e6xxx_reg_unlock(chip); 3167 3168 return ret; 3169 } 3170 3171 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 3172 int lane) 3173 { 3174 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3175 unsigned int irq; 3176 int err; 3177 3178 /* Nothing to request if this SERDES port has no IRQ */ 3179 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 3180 if (!irq) 3181 return 0; 3182 3183 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 3184 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 3185 3186 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 3187 mv88e6xxx_reg_unlock(chip); 3188 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 3189 IRQF_ONESHOT, dev_id->serdes_irq_name, 3190 dev_id); 3191 mv88e6xxx_reg_lock(chip); 3192 if (err) 3193 return err; 3194 3195 dev_id->serdes_irq = irq; 3196 3197 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 3198 } 3199 3200 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 3201 int lane) 3202 { 3203 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3204 unsigned int irq = dev_id->serdes_irq; 3205 int err; 3206 3207 /* Nothing to free if no IRQ has been requested */ 3208 if (!irq) 3209 return 0; 3210 3211 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 3212 3213 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 3214 mv88e6xxx_reg_unlock(chip); 3215 free_irq(irq, dev_id); 3216 mv88e6xxx_reg_lock(chip); 3217 3218 dev_id->serdes_irq = 0; 3219 3220 return err; 3221 } 3222 3223 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 3224 bool on) 3225 { 3226 int lane; 3227 int err; 3228 3229 lane = mv88e6xxx_serdes_get_lane(chip, port); 3230 if (lane < 0) 3231 return 0; 3232 3233 if (on) { 3234 err = mv88e6xxx_serdes_power_up(chip, port, lane); 3235 if (err) 3236 return err; 3237 3238 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 3239 } else { 3240 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 3241 if (err) 3242 return err; 3243 3244 err = mv88e6xxx_serdes_power_down(chip, port, lane); 3245 } 3246 3247 return err; 3248 } 3249 3250 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3251 enum mv88e6xxx_egress_direction direction, 3252 int port) 3253 { 3254 int err; 3255 3256 if (!chip->info->ops->set_egress_port) 3257 return -EOPNOTSUPP; 3258 3259 err = chip->info->ops->set_egress_port(chip, direction, port); 3260 if (err) 3261 return err; 3262 3263 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3264 chip->ingress_dest_port = port; 3265 else 3266 chip->egress_dest_port = port; 3267 3268 return 0; 3269 } 3270 3271 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3272 { 3273 struct dsa_switch *ds = chip->ds; 3274 int upstream_port; 3275 int err; 3276 3277 upstream_port = dsa_upstream_port(ds, port); 3278 if (chip->info->ops->port_set_upstream_port) { 3279 err = chip->info->ops->port_set_upstream_port(chip, port, 3280 upstream_port); 3281 if (err) 3282 return err; 3283 } 3284 3285 if (port == upstream_port) { 3286 if (chip->info->ops->set_cpu_port) { 3287 err = chip->info->ops->set_cpu_port(chip, 3288 upstream_port); 3289 if (err) 3290 return err; 3291 } 3292 3293 err = mv88e6xxx_set_egress_port(chip, 3294 MV88E6XXX_EGRESS_DIR_INGRESS, 3295 upstream_port); 3296 if (err && err != -EOPNOTSUPP) 3297 return err; 3298 3299 err = mv88e6xxx_set_egress_port(chip, 3300 MV88E6XXX_EGRESS_DIR_EGRESS, 3301 upstream_port); 3302 if (err && err != -EOPNOTSUPP) 3303 return err; 3304 } 3305 3306 return 0; 3307 } 3308 3309 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3310 { 3311 struct device_node *phy_handle = NULL; 3312 struct dsa_switch *ds = chip->ds; 3313 phy_interface_t mode; 3314 struct dsa_port *dp; 3315 int tx_amp, speed; 3316 int err; 3317 u16 reg; 3318 3319 chip->ports[port].chip = chip; 3320 chip->ports[port].port = port; 3321 3322 dp = dsa_to_port(ds, port); 3323 3324 /* MAC Forcing register: don't force link, speed, duplex or flow control 3325 * state to any particular values on physical ports, but force the CPU 3326 * port and all DSA ports to their maximum bandwidth and full duplex. 3327 */ 3328 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 3329 struct phylink_config pl_config = {}; 3330 unsigned long caps; 3331 3332 chip->info->ops->phylink_get_caps(chip, port, &pl_config); 3333 3334 caps = pl_config.mac_capabilities; 3335 3336 if (chip->info->ops->port_max_speed_mode) 3337 mode = chip->info->ops->port_max_speed_mode(port); 3338 else 3339 mode = PHY_INTERFACE_MODE_NA; 3340 3341 if (caps & MAC_10000FD) 3342 speed = SPEED_10000; 3343 else if (caps & MAC_5000FD) 3344 speed = SPEED_5000; 3345 else if (caps & MAC_2500FD) 3346 speed = SPEED_2500; 3347 else if (caps & MAC_1000) 3348 speed = SPEED_1000; 3349 else if (caps & MAC_100) 3350 speed = SPEED_100; 3351 else 3352 speed = SPEED_10; 3353 3354 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 3355 speed, DUPLEX_FULL, 3356 PAUSE_OFF, mode); 3357 } else { 3358 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3359 SPEED_UNFORCED, DUPLEX_UNFORCED, 3360 PAUSE_ON, 3361 PHY_INTERFACE_MODE_NA); 3362 } 3363 if (err) 3364 return err; 3365 3366 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3367 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3368 * tunneling, determine priority by looking at 802.1p and IP 3369 * priority fields (IP prio has precedence), and set STP state 3370 * to Forwarding. 3371 * 3372 * If this is the CPU link, use DSA or EDSA tagging depending 3373 * on which tagging mode was configured. 3374 * 3375 * If this is a link to another switch, use DSA tagging mode. 3376 * 3377 * If this is the upstream port for this switch, enable 3378 * forwarding of unknown unicasts and multicasts. 3379 */ 3380 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3381 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3382 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3383 * by a USER port to the CPU port to allow snooping. 3384 */ 3385 if (dsa_is_user_port(ds, port)) 3386 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3387 3388 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3389 if (err) 3390 return err; 3391 3392 err = mv88e6xxx_setup_port_mode(chip, port); 3393 if (err) 3394 return err; 3395 3396 err = mv88e6xxx_setup_egress_floods(chip, port); 3397 if (err) 3398 return err; 3399 3400 /* Port Control 2: don't force a good FCS, set the MTU size to 3401 * 10222 bytes, disable 802.1q tags checking, don't discard 3402 * tagged or untagged frames on this port, skip destination 3403 * address lookup on user ports, disable ARP mirroring and don't 3404 * send a copy of all transmitted/received frames on this port 3405 * to the CPU. 3406 */ 3407 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3408 if (err) 3409 return err; 3410 3411 err = mv88e6xxx_setup_upstream_port(chip, port); 3412 if (err) 3413 return err; 3414 3415 /* On chips that support it, set all downstream DSA ports' 3416 * VLAN policy to TRAP. In combination with loading 3417 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3418 * provides a better isolation barrier between standalone 3419 * ports, as the ATU is bypassed on any intermediate switches 3420 * between the incoming port and the CPU. 3421 */ 3422 if (dsa_is_downstream_port(ds, port) && 3423 chip->info->ops->port_set_policy) { 3424 err = chip->info->ops->port_set_policy(chip, port, 3425 MV88E6XXX_POLICY_MAPPING_VTU, 3426 MV88E6XXX_POLICY_ACTION_TRAP); 3427 if (err) 3428 return err; 3429 } 3430 3431 /* User ports start out in standalone mode and 802.1Q is 3432 * therefore disabled. On DSA ports, all valid VIDs are always 3433 * loaded in the VTU - therefore, enable 802.1Q in order to take 3434 * advantage of VLAN policy on chips that supports it. 3435 */ 3436 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3437 dsa_is_user_port(ds, port) ? 3438 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3439 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3440 if (err) 3441 return err; 3442 3443 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3444 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3445 * the first free FID. This will be used as the private PVID for 3446 * unbridged ports. Shared (DSA and CPU) ports must also be 3447 * members of this VID, in order to trap all frames assigned to 3448 * it to the CPU. 3449 */ 3450 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3451 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3452 false); 3453 if (err) 3454 return err; 3455 3456 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3457 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3458 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3459 * as the private PVID on ports under a VLAN-unaware bridge. 3460 * Shared (DSA and CPU) ports must also be members of it, to translate 3461 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3462 * relying on their port default FID. 3463 */ 3464 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3465 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3466 false); 3467 if (err) 3468 return err; 3469 3470 if (chip->info->ops->port_set_jumbo_size) { 3471 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3472 if (err) 3473 return err; 3474 } 3475 3476 /* Port Association Vector: disable automatic address learning 3477 * on all user ports since they start out in standalone 3478 * mode. When joining a bridge, learning will be configured to 3479 * match the bridge port settings. Enable learning on all 3480 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3481 * learning process. 3482 * 3483 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3484 * and RefreshLocked. I.e. setup standard automatic learning. 3485 */ 3486 if (dsa_is_user_port(ds, port)) 3487 reg = 0; 3488 else 3489 reg = 1 << port; 3490 3491 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3492 reg); 3493 if (err) 3494 return err; 3495 3496 /* Egress rate control 2: disable egress rate control. */ 3497 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3498 0x0000); 3499 if (err) 3500 return err; 3501 3502 if (chip->info->ops->port_pause_limit) { 3503 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3504 if (err) 3505 return err; 3506 } 3507 3508 if (chip->info->ops->port_disable_learn_limit) { 3509 err = chip->info->ops->port_disable_learn_limit(chip, port); 3510 if (err) 3511 return err; 3512 } 3513 3514 if (chip->info->ops->port_disable_pri_override) { 3515 err = chip->info->ops->port_disable_pri_override(chip, port); 3516 if (err) 3517 return err; 3518 } 3519 3520 if (chip->info->ops->port_tag_remap) { 3521 err = chip->info->ops->port_tag_remap(chip, port); 3522 if (err) 3523 return err; 3524 } 3525 3526 if (chip->info->ops->port_egress_rate_limiting) { 3527 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3528 if (err) 3529 return err; 3530 } 3531 3532 if (chip->info->ops->port_setup_message_port) { 3533 err = chip->info->ops->port_setup_message_port(chip, port); 3534 if (err) 3535 return err; 3536 } 3537 3538 if (chip->info->ops->serdes_set_tx_amplitude) { 3539 if (dp) 3540 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3541 3542 if (phy_handle && !of_property_read_u32(phy_handle, 3543 "tx-p2p-microvolt", 3544 &tx_amp)) 3545 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3546 port, tx_amp); 3547 if (phy_handle) { 3548 of_node_put(phy_handle); 3549 if (err) 3550 return err; 3551 } 3552 } 3553 3554 /* Port based VLAN map: give each port the same default address 3555 * database, and allow bidirectional communication between the 3556 * CPU and DSA port(s), and the other ports. 3557 */ 3558 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3559 if (err) 3560 return err; 3561 3562 err = mv88e6xxx_port_vlan_map(chip, port); 3563 if (err) 3564 return err; 3565 3566 /* Default VLAN ID and priority: don't set a default VLAN 3567 * ID, and set the default packet priority to zero. 3568 */ 3569 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3570 } 3571 3572 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3573 { 3574 struct mv88e6xxx_chip *chip = ds->priv; 3575 3576 if (chip->info->ops->port_set_jumbo_size) 3577 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3578 else if (chip->info->ops->set_max_frame_size) 3579 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3580 return ETH_DATA_LEN; 3581 } 3582 3583 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3584 { 3585 struct mv88e6xxx_chip *chip = ds->priv; 3586 int ret = 0; 3587 3588 /* For families where we don't know how to alter the MTU, 3589 * just accept any value up to ETH_DATA_LEN 3590 */ 3591 if (!chip->info->ops->port_set_jumbo_size && 3592 !chip->info->ops->set_max_frame_size) { 3593 if (new_mtu > ETH_DATA_LEN) 3594 return -EINVAL; 3595 3596 return 0; 3597 } 3598 3599 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3600 new_mtu += EDSA_HLEN; 3601 3602 mv88e6xxx_reg_lock(chip); 3603 if (chip->info->ops->port_set_jumbo_size) 3604 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3605 else if (chip->info->ops->set_max_frame_size) 3606 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3607 mv88e6xxx_reg_unlock(chip); 3608 3609 return ret; 3610 } 3611 3612 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3613 struct phy_device *phydev) 3614 { 3615 struct mv88e6xxx_chip *chip = ds->priv; 3616 int err; 3617 3618 mv88e6xxx_reg_lock(chip); 3619 err = mv88e6xxx_serdes_power(chip, port, true); 3620 mv88e6xxx_reg_unlock(chip); 3621 3622 return err; 3623 } 3624 3625 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3626 { 3627 struct mv88e6xxx_chip *chip = ds->priv; 3628 3629 mv88e6xxx_reg_lock(chip); 3630 if (mv88e6xxx_serdes_power(chip, port, false)) 3631 dev_err(chip->dev, "failed to power off SERDES\n"); 3632 mv88e6xxx_reg_unlock(chip); 3633 } 3634 3635 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3636 unsigned int ageing_time) 3637 { 3638 struct mv88e6xxx_chip *chip = ds->priv; 3639 int err; 3640 3641 mv88e6xxx_reg_lock(chip); 3642 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3643 mv88e6xxx_reg_unlock(chip); 3644 3645 return err; 3646 } 3647 3648 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3649 { 3650 int err; 3651 3652 /* Initialize the statistics unit */ 3653 if (chip->info->ops->stats_set_histogram) { 3654 err = chip->info->ops->stats_set_histogram(chip); 3655 if (err) 3656 return err; 3657 } 3658 3659 return mv88e6xxx_g1_stats_clear(chip); 3660 } 3661 3662 /* Check if the errata has already been applied. */ 3663 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3664 { 3665 int port; 3666 int err; 3667 u16 val; 3668 3669 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3670 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3671 if (err) { 3672 dev_err(chip->dev, 3673 "Error reading hidden register: %d\n", err); 3674 return false; 3675 } 3676 if (val != 0x01c0) 3677 return false; 3678 } 3679 3680 return true; 3681 } 3682 3683 /* The 6390 copper ports have an errata which require poking magic 3684 * values into undocumented hidden registers and then performing a 3685 * software reset. 3686 */ 3687 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3688 { 3689 int port; 3690 int err; 3691 3692 if (mv88e6390_setup_errata_applied(chip)) 3693 return 0; 3694 3695 /* Set the ports into blocking mode */ 3696 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3697 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3698 if (err) 3699 return err; 3700 } 3701 3702 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3703 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3704 if (err) 3705 return err; 3706 } 3707 3708 return mv88e6xxx_software_reset(chip); 3709 } 3710 3711 /* prod_id for switch families which do not have a PHY model number */ 3712 static const u16 family_prod_id_table[] = { 3713 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3714 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3715 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3716 }; 3717 3718 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3719 { 3720 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3721 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3722 u16 prod_id; 3723 u16 val; 3724 int err; 3725 3726 if (!chip->info->ops->phy_read) 3727 return -EOPNOTSUPP; 3728 3729 mv88e6xxx_reg_lock(chip); 3730 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3731 mv88e6xxx_reg_unlock(chip); 3732 3733 /* Some internal PHYs don't have a model number. */ 3734 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3735 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3736 prod_id = family_prod_id_table[chip->info->family]; 3737 if (prod_id) 3738 val |= prod_id >> 4; 3739 } 3740 3741 return err ? err : val; 3742 } 3743 3744 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3745 int reg) 3746 { 3747 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3748 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3749 u16 val; 3750 int err; 3751 3752 if (!chip->info->ops->phy_read_c45) 3753 return -EOPNOTSUPP; 3754 3755 mv88e6xxx_reg_lock(chip); 3756 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3757 mv88e6xxx_reg_unlock(chip); 3758 3759 return err ? err : val; 3760 } 3761 3762 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3763 { 3764 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3765 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3766 int err; 3767 3768 if (!chip->info->ops->phy_write) 3769 return -EOPNOTSUPP; 3770 3771 mv88e6xxx_reg_lock(chip); 3772 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3773 mv88e6xxx_reg_unlock(chip); 3774 3775 return err; 3776 } 3777 3778 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3779 int reg, u16 val) 3780 { 3781 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3782 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3783 int err; 3784 3785 if (!chip->info->ops->phy_write_c45) 3786 return -EOPNOTSUPP; 3787 3788 mv88e6xxx_reg_lock(chip); 3789 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3790 mv88e6xxx_reg_unlock(chip); 3791 3792 return err; 3793 } 3794 3795 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3796 struct device_node *np, 3797 bool external) 3798 { 3799 static int index; 3800 struct mv88e6xxx_mdio_bus *mdio_bus; 3801 struct mii_bus *bus; 3802 int err; 3803 3804 if (external) { 3805 mv88e6xxx_reg_lock(chip); 3806 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3807 mv88e6xxx_reg_unlock(chip); 3808 3809 if (err) 3810 return err; 3811 } 3812 3813 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3814 if (!bus) 3815 return -ENOMEM; 3816 3817 mdio_bus = bus->priv; 3818 mdio_bus->bus = bus; 3819 mdio_bus->chip = chip; 3820 INIT_LIST_HEAD(&mdio_bus->list); 3821 mdio_bus->external = external; 3822 3823 if (np) { 3824 bus->name = np->full_name; 3825 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3826 } else { 3827 bus->name = "mv88e6xxx SMI"; 3828 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3829 } 3830 3831 bus->read = mv88e6xxx_mdio_read; 3832 bus->write = mv88e6xxx_mdio_write; 3833 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3834 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3835 bus->parent = chip->dev; 3836 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3837 mv88e6xxx_num_ports(chip) - 1, 3838 chip->info->phy_base_addr); 3839 3840 if (!external) { 3841 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3842 if (err) 3843 goto out; 3844 } 3845 3846 err = of_mdiobus_register(bus, np); 3847 if (err) { 3848 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3849 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3850 goto out; 3851 } 3852 3853 if (external) 3854 list_add_tail(&mdio_bus->list, &chip->mdios); 3855 else 3856 list_add(&mdio_bus->list, &chip->mdios); 3857 3858 return 0; 3859 3860 out: 3861 mdiobus_free(bus); 3862 return err; 3863 } 3864 3865 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3866 3867 { 3868 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3869 struct mii_bus *bus; 3870 3871 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3872 bus = mdio_bus->bus; 3873 3874 if (!mdio_bus->external) 3875 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3876 3877 mdiobus_unregister(bus); 3878 mdiobus_free(bus); 3879 } 3880 } 3881 3882 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3883 { 3884 struct device_node *np = chip->dev->of_node; 3885 struct device_node *child; 3886 int err; 3887 3888 /* Always register one mdio bus for the internal/default mdio 3889 * bus. This maybe represented in the device tree, but is 3890 * optional. 3891 */ 3892 child = of_get_child_by_name(np, "mdio"); 3893 err = mv88e6xxx_mdio_register(chip, child, false); 3894 of_node_put(child); 3895 if (err) 3896 return err; 3897 3898 /* Walk the device tree, and see if there are any other nodes 3899 * which say they are compatible with the external mdio 3900 * bus. 3901 */ 3902 for_each_available_child_of_node(np, child) { 3903 if (of_device_is_compatible( 3904 child, "marvell,mv88e6xxx-mdio-external")) { 3905 err = mv88e6xxx_mdio_register(chip, child, true); 3906 if (err) { 3907 mv88e6xxx_mdios_unregister(chip); 3908 of_node_put(child); 3909 return err; 3910 } 3911 } 3912 } 3913 3914 return 0; 3915 } 3916 3917 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3918 { 3919 struct mv88e6xxx_chip *chip = ds->priv; 3920 3921 mv88e6xxx_teardown_devlink_params(ds); 3922 dsa_devlink_resources_unregister(ds); 3923 mv88e6xxx_teardown_devlink_regions_global(ds); 3924 mv88e6xxx_mdios_unregister(chip); 3925 } 3926 3927 static int mv88e6xxx_setup(struct dsa_switch *ds) 3928 { 3929 struct mv88e6xxx_chip *chip = ds->priv; 3930 u8 cmode; 3931 int err; 3932 int i; 3933 3934 err = mv88e6xxx_mdios_register(chip); 3935 if (err) 3936 return err; 3937 3938 chip->ds = ds; 3939 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3940 3941 /* Since virtual bridges are mapped in the PVT, the number we support 3942 * depends on the physical switch topology. We need to let DSA figure 3943 * that out and therefore we cannot set this at dsa_register_switch() 3944 * time. 3945 */ 3946 if (mv88e6xxx_has_pvt(chip)) 3947 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3948 ds->dst->last_switch - 1; 3949 3950 mv88e6xxx_reg_lock(chip); 3951 3952 if (chip->info->ops->setup_errata) { 3953 err = chip->info->ops->setup_errata(chip); 3954 if (err) 3955 goto unlock; 3956 } 3957 3958 /* Cache the cmode of each port. */ 3959 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3960 if (chip->info->ops->port_get_cmode) { 3961 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3962 if (err) 3963 goto unlock; 3964 3965 chip->ports[i].cmode = cmode; 3966 } 3967 } 3968 3969 err = mv88e6xxx_vtu_setup(chip); 3970 if (err) 3971 goto unlock; 3972 3973 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3974 * VTU, thereby also flushing the STU). 3975 */ 3976 err = mv88e6xxx_stu_setup(chip); 3977 if (err) 3978 goto unlock; 3979 3980 /* Setup Switch Port Registers */ 3981 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3982 if (dsa_is_unused_port(ds, i)) 3983 continue; 3984 3985 /* Prevent the use of an invalid port. */ 3986 if (mv88e6xxx_is_invalid_port(chip, i)) { 3987 dev_err(chip->dev, "port %d is invalid\n", i); 3988 err = -EINVAL; 3989 goto unlock; 3990 } 3991 3992 err = mv88e6xxx_setup_port(chip, i); 3993 if (err) 3994 goto unlock; 3995 } 3996 3997 err = mv88e6xxx_irl_setup(chip); 3998 if (err) 3999 goto unlock; 4000 4001 err = mv88e6xxx_mac_setup(chip); 4002 if (err) 4003 goto unlock; 4004 4005 err = mv88e6xxx_phy_setup(chip); 4006 if (err) 4007 goto unlock; 4008 4009 err = mv88e6xxx_pvt_setup(chip); 4010 if (err) 4011 goto unlock; 4012 4013 err = mv88e6xxx_atu_setup(chip); 4014 if (err) 4015 goto unlock; 4016 4017 err = mv88e6xxx_broadcast_setup(chip, 0); 4018 if (err) 4019 goto unlock; 4020 4021 err = mv88e6xxx_pot_setup(chip); 4022 if (err) 4023 goto unlock; 4024 4025 err = mv88e6xxx_rmu_setup(chip); 4026 if (err) 4027 goto unlock; 4028 4029 err = mv88e6xxx_rsvd2cpu_setup(chip); 4030 if (err) 4031 goto unlock; 4032 4033 err = mv88e6xxx_trunk_setup(chip); 4034 if (err) 4035 goto unlock; 4036 4037 err = mv88e6xxx_devmap_setup(chip); 4038 if (err) 4039 goto unlock; 4040 4041 err = mv88e6xxx_pri_setup(chip); 4042 if (err) 4043 goto unlock; 4044 4045 /* Setup PTP Hardware Clock and timestamping */ 4046 if (chip->info->ptp_support) { 4047 err = mv88e6xxx_ptp_setup(chip); 4048 if (err) 4049 goto unlock; 4050 4051 err = mv88e6xxx_hwtstamp_setup(chip); 4052 if (err) 4053 goto unlock; 4054 } 4055 4056 err = mv88e6xxx_stats_setup(chip); 4057 if (err) 4058 goto unlock; 4059 4060 unlock: 4061 mv88e6xxx_reg_unlock(chip); 4062 4063 if (err) 4064 goto out_mdios; 4065 4066 /* Have to be called without holding the register lock, since 4067 * they take the devlink lock, and we later take the locks in 4068 * the reverse order when getting/setting parameters or 4069 * resource occupancy. 4070 */ 4071 err = mv88e6xxx_setup_devlink_resources(ds); 4072 if (err) 4073 goto out_mdios; 4074 4075 err = mv88e6xxx_setup_devlink_params(ds); 4076 if (err) 4077 goto out_resources; 4078 4079 err = mv88e6xxx_setup_devlink_regions_global(ds); 4080 if (err) 4081 goto out_params; 4082 4083 return 0; 4084 4085 out_params: 4086 mv88e6xxx_teardown_devlink_params(ds); 4087 out_resources: 4088 dsa_devlink_resources_unregister(ds); 4089 out_mdios: 4090 mv88e6xxx_mdios_unregister(chip); 4091 4092 return err; 4093 } 4094 4095 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 4096 { 4097 return mv88e6xxx_setup_devlink_regions_port(ds, port); 4098 } 4099 4100 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 4101 { 4102 mv88e6xxx_teardown_devlink_regions_port(ds, port); 4103 } 4104 4105 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4106 { 4107 struct mv88e6xxx_chip *chip = ds->priv; 4108 4109 return chip->eeprom_len; 4110 } 4111 4112 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4113 struct ethtool_eeprom *eeprom, u8 *data) 4114 { 4115 struct mv88e6xxx_chip *chip = ds->priv; 4116 int err; 4117 4118 if (!chip->info->ops->get_eeprom) 4119 return -EOPNOTSUPP; 4120 4121 mv88e6xxx_reg_lock(chip); 4122 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4123 mv88e6xxx_reg_unlock(chip); 4124 4125 if (err) 4126 return err; 4127 4128 eeprom->magic = 0xc3ec4951; 4129 4130 return 0; 4131 } 4132 4133 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4134 struct ethtool_eeprom *eeprom, u8 *data) 4135 { 4136 struct mv88e6xxx_chip *chip = ds->priv; 4137 int err; 4138 4139 if (!chip->info->ops->set_eeprom) 4140 return -EOPNOTSUPP; 4141 4142 if (eeprom->magic != 0xc3ec4951) 4143 return -EINVAL; 4144 4145 mv88e6xxx_reg_lock(chip); 4146 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4147 mv88e6xxx_reg_unlock(chip); 4148 4149 return err; 4150 } 4151 4152 static const struct mv88e6xxx_ops mv88e6085_ops = { 4153 /* MV88E6XXX_FAMILY_6097 */ 4154 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4155 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4156 .irl_init_all = mv88e6352_g2_irl_init_all, 4157 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4158 .phy_read = mv88e6185_phy_ppu_read, 4159 .phy_write = mv88e6185_phy_ppu_write, 4160 .port_set_link = mv88e6xxx_port_set_link, 4161 .port_sync_link = mv88e6xxx_port_sync_link, 4162 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4163 .port_tag_remap = mv88e6095_port_tag_remap, 4164 .port_set_policy = mv88e6352_port_set_policy, 4165 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4166 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4167 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4168 .port_set_ether_type = mv88e6351_port_set_ether_type, 4169 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4170 .port_pause_limit = mv88e6097_port_pause_limit, 4171 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4172 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4173 .port_get_cmode = mv88e6185_port_get_cmode, 4174 .port_setup_message_port = mv88e6xxx_setup_message_port, 4175 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4176 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4177 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4178 .stats_get_strings = mv88e6095_stats_get_strings, 4179 .stats_get_stats = mv88e6095_stats_get_stats, 4180 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4181 .set_egress_port = mv88e6095_g1_set_egress_port, 4182 .watchdog_ops = &mv88e6097_watchdog_ops, 4183 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4184 .pot_clear = mv88e6xxx_g2_pot_clear, 4185 .ppu_enable = mv88e6185_g1_ppu_enable, 4186 .ppu_disable = mv88e6185_g1_ppu_disable, 4187 .reset = mv88e6185_g1_reset, 4188 .rmu_disable = mv88e6085_g1_rmu_disable, 4189 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4190 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4191 .stu_getnext = mv88e6352_g1_stu_getnext, 4192 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4193 .phylink_get_caps = mv88e6185_phylink_get_caps, 4194 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4195 }; 4196 4197 static const struct mv88e6xxx_ops mv88e6095_ops = { 4198 /* MV88E6XXX_FAMILY_6095 */ 4199 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4200 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4201 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4202 .phy_read = mv88e6185_phy_ppu_read, 4203 .phy_write = mv88e6185_phy_ppu_write, 4204 .port_set_link = mv88e6xxx_port_set_link, 4205 .port_sync_link = mv88e6185_port_sync_link, 4206 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4207 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4208 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4209 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4210 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4211 .port_get_cmode = mv88e6185_port_get_cmode, 4212 .port_setup_message_port = mv88e6xxx_setup_message_port, 4213 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4214 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4215 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4216 .stats_get_strings = mv88e6095_stats_get_strings, 4217 .stats_get_stats = mv88e6095_stats_get_stats, 4218 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4219 .serdes_power = mv88e6185_serdes_power, 4220 .serdes_get_lane = mv88e6185_serdes_get_lane, 4221 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4222 .ppu_enable = mv88e6185_g1_ppu_enable, 4223 .ppu_disable = mv88e6185_g1_ppu_disable, 4224 .reset = mv88e6185_g1_reset, 4225 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4226 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4227 .phylink_get_caps = mv88e6095_phylink_get_caps, 4228 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4229 }; 4230 4231 static const struct mv88e6xxx_ops mv88e6097_ops = { 4232 /* MV88E6XXX_FAMILY_6097 */ 4233 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4234 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4235 .irl_init_all = mv88e6352_g2_irl_init_all, 4236 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4237 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4238 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4239 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4240 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4241 .port_set_link = mv88e6xxx_port_set_link, 4242 .port_sync_link = mv88e6185_port_sync_link, 4243 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4244 .port_tag_remap = mv88e6095_port_tag_remap, 4245 .port_set_policy = mv88e6352_port_set_policy, 4246 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4247 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4248 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4249 .port_set_ether_type = mv88e6351_port_set_ether_type, 4250 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4251 .port_pause_limit = mv88e6097_port_pause_limit, 4252 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4253 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4254 .port_get_cmode = mv88e6185_port_get_cmode, 4255 .port_setup_message_port = mv88e6xxx_setup_message_port, 4256 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4257 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4258 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4259 .stats_get_strings = mv88e6095_stats_get_strings, 4260 .stats_get_stats = mv88e6095_stats_get_stats, 4261 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4262 .set_egress_port = mv88e6095_g1_set_egress_port, 4263 .watchdog_ops = &mv88e6097_watchdog_ops, 4264 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4265 .serdes_power = mv88e6185_serdes_power, 4266 .serdes_get_lane = mv88e6185_serdes_get_lane, 4267 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4268 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4269 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 4270 .serdes_irq_status = mv88e6097_serdes_irq_status, 4271 .pot_clear = mv88e6xxx_g2_pot_clear, 4272 .reset = mv88e6352_g1_reset, 4273 .rmu_disable = mv88e6085_g1_rmu_disable, 4274 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4275 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4276 .phylink_get_caps = mv88e6095_phylink_get_caps, 4277 .stu_getnext = mv88e6352_g1_stu_getnext, 4278 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4279 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4280 }; 4281 4282 static const struct mv88e6xxx_ops mv88e6123_ops = { 4283 /* MV88E6XXX_FAMILY_6165 */ 4284 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4285 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4286 .irl_init_all = mv88e6352_g2_irl_init_all, 4287 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4288 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4289 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4290 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4291 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4292 .port_set_link = mv88e6xxx_port_set_link, 4293 .port_sync_link = mv88e6xxx_port_sync_link, 4294 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4295 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4296 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4297 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4298 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4299 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4300 .port_get_cmode = mv88e6185_port_get_cmode, 4301 .port_setup_message_port = mv88e6xxx_setup_message_port, 4302 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4303 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4304 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4305 .stats_get_strings = mv88e6095_stats_get_strings, 4306 .stats_get_stats = mv88e6095_stats_get_stats, 4307 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4308 .set_egress_port = mv88e6095_g1_set_egress_port, 4309 .watchdog_ops = &mv88e6097_watchdog_ops, 4310 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4311 .pot_clear = mv88e6xxx_g2_pot_clear, 4312 .reset = mv88e6352_g1_reset, 4313 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4314 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4315 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4316 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4317 .stu_getnext = mv88e6352_g1_stu_getnext, 4318 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4319 .phylink_get_caps = mv88e6185_phylink_get_caps, 4320 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4321 }; 4322 4323 static const struct mv88e6xxx_ops mv88e6131_ops = { 4324 /* MV88E6XXX_FAMILY_6185 */ 4325 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4326 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4327 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4328 .phy_read = mv88e6185_phy_ppu_read, 4329 .phy_write = mv88e6185_phy_ppu_write, 4330 .port_set_link = mv88e6xxx_port_set_link, 4331 .port_sync_link = mv88e6xxx_port_sync_link, 4332 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4333 .port_tag_remap = mv88e6095_port_tag_remap, 4334 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4335 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4336 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4337 .port_set_ether_type = mv88e6351_port_set_ether_type, 4338 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4339 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4340 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4341 .port_pause_limit = mv88e6097_port_pause_limit, 4342 .port_set_pause = mv88e6185_port_set_pause, 4343 .port_get_cmode = mv88e6185_port_get_cmode, 4344 .port_setup_message_port = mv88e6xxx_setup_message_port, 4345 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4346 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4347 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4348 .stats_get_strings = mv88e6095_stats_get_strings, 4349 .stats_get_stats = mv88e6095_stats_get_stats, 4350 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4351 .set_egress_port = mv88e6095_g1_set_egress_port, 4352 .watchdog_ops = &mv88e6097_watchdog_ops, 4353 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4354 .ppu_enable = mv88e6185_g1_ppu_enable, 4355 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4356 .ppu_disable = mv88e6185_g1_ppu_disable, 4357 .reset = mv88e6185_g1_reset, 4358 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4359 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4360 .phylink_get_caps = mv88e6185_phylink_get_caps, 4361 }; 4362 4363 static const struct mv88e6xxx_ops mv88e6141_ops = { 4364 /* MV88E6XXX_FAMILY_6341 */ 4365 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4366 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4367 .irl_init_all = mv88e6352_g2_irl_init_all, 4368 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4369 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4370 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4371 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4372 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4373 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4374 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4375 .port_set_link = mv88e6xxx_port_set_link, 4376 .port_sync_link = mv88e6xxx_port_sync_link, 4377 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4378 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4379 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4380 .port_tag_remap = mv88e6095_port_tag_remap, 4381 .port_set_policy = mv88e6352_port_set_policy, 4382 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4383 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4384 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4385 .port_set_ether_type = mv88e6351_port_set_ether_type, 4386 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4387 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4388 .port_pause_limit = mv88e6097_port_pause_limit, 4389 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4390 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4391 .port_get_cmode = mv88e6352_port_get_cmode, 4392 .port_set_cmode = mv88e6341_port_set_cmode, 4393 .port_setup_message_port = mv88e6xxx_setup_message_port, 4394 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4395 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4396 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4397 .stats_get_strings = mv88e6320_stats_get_strings, 4398 .stats_get_stats = mv88e6390_stats_get_stats, 4399 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4400 .set_egress_port = mv88e6390_g1_set_egress_port, 4401 .watchdog_ops = &mv88e6390_watchdog_ops, 4402 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4403 .pot_clear = mv88e6xxx_g2_pot_clear, 4404 .reset = mv88e6352_g1_reset, 4405 .rmu_disable = mv88e6390_g1_rmu_disable, 4406 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4407 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4408 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4409 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4410 .stu_getnext = mv88e6352_g1_stu_getnext, 4411 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4412 .serdes_power = mv88e6390_serdes_power, 4413 .serdes_get_lane = mv88e6341_serdes_get_lane, 4414 /* Check status register pause & lpa register */ 4415 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4416 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4417 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4418 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4419 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4420 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4421 .serdes_irq_status = mv88e6390_serdes_irq_status, 4422 .gpio_ops = &mv88e6352_gpio_ops, 4423 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4424 .serdes_get_strings = mv88e6390_serdes_get_strings, 4425 .serdes_get_stats = mv88e6390_serdes_get_stats, 4426 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4427 .serdes_get_regs = mv88e6390_serdes_get_regs, 4428 .phylink_get_caps = mv88e6341_phylink_get_caps, 4429 }; 4430 4431 static const struct mv88e6xxx_ops mv88e6161_ops = { 4432 /* MV88E6XXX_FAMILY_6165 */ 4433 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4434 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4435 .irl_init_all = mv88e6352_g2_irl_init_all, 4436 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4437 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4438 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4439 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4440 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4441 .port_set_link = mv88e6xxx_port_set_link, 4442 .port_sync_link = mv88e6xxx_port_sync_link, 4443 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4444 .port_tag_remap = mv88e6095_port_tag_remap, 4445 .port_set_policy = mv88e6352_port_set_policy, 4446 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4447 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4448 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4449 .port_set_ether_type = mv88e6351_port_set_ether_type, 4450 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4451 .port_pause_limit = mv88e6097_port_pause_limit, 4452 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4453 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4454 .port_get_cmode = mv88e6185_port_get_cmode, 4455 .port_setup_message_port = mv88e6xxx_setup_message_port, 4456 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4457 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4458 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4459 .stats_get_strings = mv88e6095_stats_get_strings, 4460 .stats_get_stats = mv88e6095_stats_get_stats, 4461 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4462 .set_egress_port = mv88e6095_g1_set_egress_port, 4463 .watchdog_ops = &mv88e6097_watchdog_ops, 4464 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4465 .pot_clear = mv88e6xxx_g2_pot_clear, 4466 .reset = mv88e6352_g1_reset, 4467 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4468 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4469 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4470 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4471 .stu_getnext = mv88e6352_g1_stu_getnext, 4472 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4473 .avb_ops = &mv88e6165_avb_ops, 4474 .ptp_ops = &mv88e6165_ptp_ops, 4475 .phylink_get_caps = mv88e6185_phylink_get_caps, 4476 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4477 }; 4478 4479 static const struct mv88e6xxx_ops mv88e6165_ops = { 4480 /* MV88E6XXX_FAMILY_6165 */ 4481 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4482 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4483 .irl_init_all = mv88e6352_g2_irl_init_all, 4484 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4485 .phy_read = mv88e6165_phy_read, 4486 .phy_write = mv88e6165_phy_write, 4487 .port_set_link = mv88e6xxx_port_set_link, 4488 .port_sync_link = mv88e6xxx_port_sync_link, 4489 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4490 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4491 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4492 .port_get_cmode = mv88e6185_port_get_cmode, 4493 .port_setup_message_port = mv88e6xxx_setup_message_port, 4494 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4495 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4496 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4497 .stats_get_strings = mv88e6095_stats_get_strings, 4498 .stats_get_stats = mv88e6095_stats_get_stats, 4499 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4500 .set_egress_port = mv88e6095_g1_set_egress_port, 4501 .watchdog_ops = &mv88e6097_watchdog_ops, 4502 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4503 .pot_clear = mv88e6xxx_g2_pot_clear, 4504 .reset = mv88e6352_g1_reset, 4505 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4506 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4507 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4508 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4509 .stu_getnext = mv88e6352_g1_stu_getnext, 4510 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4511 .avb_ops = &mv88e6165_avb_ops, 4512 .ptp_ops = &mv88e6165_ptp_ops, 4513 .phylink_get_caps = mv88e6185_phylink_get_caps, 4514 }; 4515 4516 static const struct mv88e6xxx_ops mv88e6171_ops = { 4517 /* MV88E6XXX_FAMILY_6351 */ 4518 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4519 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4520 .irl_init_all = mv88e6352_g2_irl_init_all, 4521 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4522 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4523 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4524 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4525 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4526 .port_set_link = mv88e6xxx_port_set_link, 4527 .port_sync_link = mv88e6xxx_port_sync_link, 4528 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4529 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4530 .port_tag_remap = mv88e6095_port_tag_remap, 4531 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4532 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4533 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4534 .port_set_ether_type = mv88e6351_port_set_ether_type, 4535 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4536 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4537 .port_pause_limit = mv88e6097_port_pause_limit, 4538 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4539 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4540 .port_get_cmode = mv88e6352_port_get_cmode, 4541 .port_setup_message_port = mv88e6xxx_setup_message_port, 4542 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4543 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4544 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4545 .stats_get_strings = mv88e6095_stats_get_strings, 4546 .stats_get_stats = mv88e6095_stats_get_stats, 4547 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4548 .set_egress_port = mv88e6095_g1_set_egress_port, 4549 .watchdog_ops = &mv88e6097_watchdog_ops, 4550 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4551 .pot_clear = mv88e6xxx_g2_pot_clear, 4552 .reset = mv88e6352_g1_reset, 4553 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4554 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4555 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4556 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4557 .stu_getnext = mv88e6352_g1_stu_getnext, 4558 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4559 .phylink_get_caps = mv88e6185_phylink_get_caps, 4560 }; 4561 4562 static const struct mv88e6xxx_ops mv88e6172_ops = { 4563 /* MV88E6XXX_FAMILY_6352 */ 4564 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4565 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4566 .irl_init_all = mv88e6352_g2_irl_init_all, 4567 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4568 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4569 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4570 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4571 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4572 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4573 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4574 .port_set_link = mv88e6xxx_port_set_link, 4575 .port_sync_link = mv88e6xxx_port_sync_link, 4576 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4577 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4578 .port_tag_remap = mv88e6095_port_tag_remap, 4579 .port_set_policy = mv88e6352_port_set_policy, 4580 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4581 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4582 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4583 .port_set_ether_type = mv88e6351_port_set_ether_type, 4584 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4585 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4586 .port_pause_limit = mv88e6097_port_pause_limit, 4587 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4588 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4589 .port_get_cmode = mv88e6352_port_get_cmode, 4590 .port_setup_message_port = mv88e6xxx_setup_message_port, 4591 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4592 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4593 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4594 .stats_get_strings = mv88e6095_stats_get_strings, 4595 .stats_get_stats = mv88e6095_stats_get_stats, 4596 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4597 .set_egress_port = mv88e6095_g1_set_egress_port, 4598 .watchdog_ops = &mv88e6097_watchdog_ops, 4599 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4600 .pot_clear = mv88e6xxx_g2_pot_clear, 4601 .reset = mv88e6352_g1_reset, 4602 .rmu_disable = mv88e6352_g1_rmu_disable, 4603 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4604 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4605 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4606 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4607 .stu_getnext = mv88e6352_g1_stu_getnext, 4608 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4609 .serdes_get_lane = mv88e6352_serdes_get_lane, 4610 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4611 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4612 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4613 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4614 .serdes_power = mv88e6352_serdes_power, 4615 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4616 .serdes_get_regs = mv88e6352_serdes_get_regs, 4617 .gpio_ops = &mv88e6352_gpio_ops, 4618 .phylink_get_caps = mv88e6352_phylink_get_caps, 4619 }; 4620 4621 static const struct mv88e6xxx_ops mv88e6175_ops = { 4622 /* MV88E6XXX_FAMILY_6351 */ 4623 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4624 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4625 .irl_init_all = mv88e6352_g2_irl_init_all, 4626 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4627 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4628 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4629 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4630 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4631 .port_set_link = mv88e6xxx_port_set_link, 4632 .port_sync_link = mv88e6xxx_port_sync_link, 4633 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4634 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4635 .port_tag_remap = mv88e6095_port_tag_remap, 4636 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4637 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4638 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4639 .port_set_ether_type = mv88e6351_port_set_ether_type, 4640 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4641 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4642 .port_pause_limit = mv88e6097_port_pause_limit, 4643 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4644 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4645 .port_get_cmode = mv88e6352_port_get_cmode, 4646 .port_setup_message_port = mv88e6xxx_setup_message_port, 4647 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4648 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4649 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4650 .stats_get_strings = mv88e6095_stats_get_strings, 4651 .stats_get_stats = mv88e6095_stats_get_stats, 4652 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4653 .set_egress_port = mv88e6095_g1_set_egress_port, 4654 .watchdog_ops = &mv88e6097_watchdog_ops, 4655 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4656 .pot_clear = mv88e6xxx_g2_pot_clear, 4657 .reset = mv88e6352_g1_reset, 4658 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4659 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4660 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4661 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4662 .stu_getnext = mv88e6352_g1_stu_getnext, 4663 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4664 .phylink_get_caps = mv88e6185_phylink_get_caps, 4665 }; 4666 4667 static const struct mv88e6xxx_ops mv88e6176_ops = { 4668 /* MV88E6XXX_FAMILY_6352 */ 4669 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4670 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4671 .irl_init_all = mv88e6352_g2_irl_init_all, 4672 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4673 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4674 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4675 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4676 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4677 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4678 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4679 .port_set_link = mv88e6xxx_port_set_link, 4680 .port_sync_link = mv88e6xxx_port_sync_link, 4681 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4682 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4683 .port_tag_remap = mv88e6095_port_tag_remap, 4684 .port_set_policy = mv88e6352_port_set_policy, 4685 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4686 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4687 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4688 .port_set_ether_type = mv88e6351_port_set_ether_type, 4689 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4690 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4691 .port_pause_limit = mv88e6097_port_pause_limit, 4692 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4693 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4694 .port_get_cmode = mv88e6352_port_get_cmode, 4695 .port_setup_message_port = mv88e6xxx_setup_message_port, 4696 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4697 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4698 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4699 .stats_get_strings = mv88e6095_stats_get_strings, 4700 .stats_get_stats = mv88e6095_stats_get_stats, 4701 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4702 .set_egress_port = mv88e6095_g1_set_egress_port, 4703 .watchdog_ops = &mv88e6097_watchdog_ops, 4704 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4705 .pot_clear = mv88e6xxx_g2_pot_clear, 4706 .reset = mv88e6352_g1_reset, 4707 .rmu_disable = mv88e6352_g1_rmu_disable, 4708 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4709 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4710 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4711 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4712 .stu_getnext = mv88e6352_g1_stu_getnext, 4713 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4714 .serdes_get_lane = mv88e6352_serdes_get_lane, 4715 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4716 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4717 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4718 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4719 .serdes_power = mv88e6352_serdes_power, 4720 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4721 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4722 .serdes_irq_status = mv88e6352_serdes_irq_status, 4723 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4724 .serdes_get_regs = mv88e6352_serdes_get_regs, 4725 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4726 .gpio_ops = &mv88e6352_gpio_ops, 4727 .phylink_get_caps = mv88e6352_phylink_get_caps, 4728 }; 4729 4730 static const struct mv88e6xxx_ops mv88e6185_ops = { 4731 /* MV88E6XXX_FAMILY_6185 */ 4732 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4733 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4734 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4735 .phy_read = mv88e6185_phy_ppu_read, 4736 .phy_write = mv88e6185_phy_ppu_write, 4737 .port_set_link = mv88e6xxx_port_set_link, 4738 .port_sync_link = mv88e6185_port_sync_link, 4739 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4740 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4741 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4742 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4743 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4744 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4745 .port_set_pause = mv88e6185_port_set_pause, 4746 .port_get_cmode = mv88e6185_port_get_cmode, 4747 .port_setup_message_port = mv88e6xxx_setup_message_port, 4748 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4749 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4750 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4751 .stats_get_strings = mv88e6095_stats_get_strings, 4752 .stats_get_stats = mv88e6095_stats_get_stats, 4753 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4754 .set_egress_port = mv88e6095_g1_set_egress_port, 4755 .watchdog_ops = &mv88e6097_watchdog_ops, 4756 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4757 .serdes_power = mv88e6185_serdes_power, 4758 .serdes_get_lane = mv88e6185_serdes_get_lane, 4759 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4760 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4761 .ppu_enable = mv88e6185_g1_ppu_enable, 4762 .ppu_disable = mv88e6185_g1_ppu_disable, 4763 .reset = mv88e6185_g1_reset, 4764 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4765 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4766 .phylink_get_caps = mv88e6185_phylink_get_caps, 4767 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4768 }; 4769 4770 static const struct mv88e6xxx_ops mv88e6190_ops = { 4771 /* MV88E6XXX_FAMILY_6390 */ 4772 .setup_errata = mv88e6390_setup_errata, 4773 .irl_init_all = mv88e6390_g2_irl_init_all, 4774 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4775 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4776 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4777 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4778 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4779 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4780 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4781 .port_set_link = mv88e6xxx_port_set_link, 4782 .port_sync_link = mv88e6xxx_port_sync_link, 4783 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4784 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4785 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4786 .port_tag_remap = mv88e6390_port_tag_remap, 4787 .port_set_policy = mv88e6352_port_set_policy, 4788 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4789 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4790 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4791 .port_set_ether_type = mv88e6351_port_set_ether_type, 4792 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4793 .port_pause_limit = mv88e6390_port_pause_limit, 4794 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4795 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4796 .port_get_cmode = mv88e6352_port_get_cmode, 4797 .port_set_cmode = mv88e6390_port_set_cmode, 4798 .port_setup_message_port = mv88e6xxx_setup_message_port, 4799 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4800 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4801 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4802 .stats_get_strings = mv88e6320_stats_get_strings, 4803 .stats_get_stats = mv88e6390_stats_get_stats, 4804 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4805 .set_egress_port = mv88e6390_g1_set_egress_port, 4806 .watchdog_ops = &mv88e6390_watchdog_ops, 4807 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4808 .pot_clear = mv88e6xxx_g2_pot_clear, 4809 .reset = mv88e6352_g1_reset, 4810 .rmu_disable = mv88e6390_g1_rmu_disable, 4811 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4812 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4813 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4814 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4815 .stu_getnext = mv88e6390_g1_stu_getnext, 4816 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4817 .serdes_power = mv88e6390_serdes_power, 4818 .serdes_get_lane = mv88e6390_serdes_get_lane, 4819 /* Check status register pause & lpa register */ 4820 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4821 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4822 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4823 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4824 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4825 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4826 .serdes_irq_status = mv88e6390_serdes_irq_status, 4827 .serdes_get_strings = mv88e6390_serdes_get_strings, 4828 .serdes_get_stats = mv88e6390_serdes_get_stats, 4829 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4830 .serdes_get_regs = mv88e6390_serdes_get_regs, 4831 .gpio_ops = &mv88e6352_gpio_ops, 4832 .phylink_get_caps = mv88e6390_phylink_get_caps, 4833 }; 4834 4835 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4836 /* MV88E6XXX_FAMILY_6390 */ 4837 .setup_errata = mv88e6390_setup_errata, 4838 .irl_init_all = mv88e6390_g2_irl_init_all, 4839 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4840 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4841 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4842 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4843 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4844 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4845 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4846 .port_set_link = mv88e6xxx_port_set_link, 4847 .port_sync_link = mv88e6xxx_port_sync_link, 4848 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4849 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4850 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4851 .port_tag_remap = mv88e6390_port_tag_remap, 4852 .port_set_policy = mv88e6352_port_set_policy, 4853 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4854 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4855 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4856 .port_set_ether_type = mv88e6351_port_set_ether_type, 4857 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4858 .port_pause_limit = mv88e6390_port_pause_limit, 4859 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4860 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4861 .port_get_cmode = mv88e6352_port_get_cmode, 4862 .port_set_cmode = mv88e6390x_port_set_cmode, 4863 .port_setup_message_port = mv88e6xxx_setup_message_port, 4864 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4865 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4866 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4867 .stats_get_strings = mv88e6320_stats_get_strings, 4868 .stats_get_stats = mv88e6390_stats_get_stats, 4869 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4870 .set_egress_port = mv88e6390_g1_set_egress_port, 4871 .watchdog_ops = &mv88e6390_watchdog_ops, 4872 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4873 .pot_clear = mv88e6xxx_g2_pot_clear, 4874 .reset = mv88e6352_g1_reset, 4875 .rmu_disable = mv88e6390_g1_rmu_disable, 4876 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4877 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4878 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4879 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4880 .stu_getnext = mv88e6390_g1_stu_getnext, 4881 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4882 .serdes_power = mv88e6390_serdes_power, 4883 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4884 /* Check status register pause & lpa register */ 4885 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4886 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4887 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4888 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4889 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4890 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4891 .serdes_irq_status = mv88e6390_serdes_irq_status, 4892 .serdes_get_strings = mv88e6390_serdes_get_strings, 4893 .serdes_get_stats = mv88e6390_serdes_get_stats, 4894 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4895 .serdes_get_regs = mv88e6390_serdes_get_regs, 4896 .gpio_ops = &mv88e6352_gpio_ops, 4897 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4898 }; 4899 4900 static const struct mv88e6xxx_ops mv88e6191_ops = { 4901 /* MV88E6XXX_FAMILY_6390 */ 4902 .setup_errata = mv88e6390_setup_errata, 4903 .irl_init_all = mv88e6390_g2_irl_init_all, 4904 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4905 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4906 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4907 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4908 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4909 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4910 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4911 .port_set_link = mv88e6xxx_port_set_link, 4912 .port_sync_link = mv88e6xxx_port_sync_link, 4913 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4914 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4915 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4916 .port_tag_remap = mv88e6390_port_tag_remap, 4917 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4918 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4919 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4920 .port_set_ether_type = mv88e6351_port_set_ether_type, 4921 .port_pause_limit = mv88e6390_port_pause_limit, 4922 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4923 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4924 .port_get_cmode = mv88e6352_port_get_cmode, 4925 .port_set_cmode = mv88e6390_port_set_cmode, 4926 .port_setup_message_port = mv88e6xxx_setup_message_port, 4927 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4928 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4929 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4930 .stats_get_strings = mv88e6320_stats_get_strings, 4931 .stats_get_stats = mv88e6390_stats_get_stats, 4932 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4933 .set_egress_port = mv88e6390_g1_set_egress_port, 4934 .watchdog_ops = &mv88e6390_watchdog_ops, 4935 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4936 .pot_clear = mv88e6xxx_g2_pot_clear, 4937 .reset = mv88e6352_g1_reset, 4938 .rmu_disable = mv88e6390_g1_rmu_disable, 4939 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4940 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4941 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4942 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4943 .stu_getnext = mv88e6390_g1_stu_getnext, 4944 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4945 .serdes_power = mv88e6390_serdes_power, 4946 .serdes_get_lane = mv88e6390_serdes_get_lane, 4947 /* Check status register pause & lpa register */ 4948 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4949 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4950 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4951 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4952 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4953 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4954 .serdes_irq_status = mv88e6390_serdes_irq_status, 4955 .serdes_get_strings = mv88e6390_serdes_get_strings, 4956 .serdes_get_stats = mv88e6390_serdes_get_stats, 4957 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4958 .serdes_get_regs = mv88e6390_serdes_get_regs, 4959 .avb_ops = &mv88e6390_avb_ops, 4960 .ptp_ops = &mv88e6352_ptp_ops, 4961 .phylink_get_caps = mv88e6390_phylink_get_caps, 4962 }; 4963 4964 static const struct mv88e6xxx_ops mv88e6240_ops = { 4965 /* MV88E6XXX_FAMILY_6352 */ 4966 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4967 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4968 .irl_init_all = mv88e6352_g2_irl_init_all, 4969 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4970 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4971 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4972 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4973 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4974 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4975 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4976 .port_set_link = mv88e6xxx_port_set_link, 4977 .port_sync_link = mv88e6xxx_port_sync_link, 4978 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4979 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4980 .port_tag_remap = mv88e6095_port_tag_remap, 4981 .port_set_policy = mv88e6352_port_set_policy, 4982 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4983 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4984 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4985 .port_set_ether_type = mv88e6351_port_set_ether_type, 4986 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4987 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4988 .port_pause_limit = mv88e6097_port_pause_limit, 4989 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4990 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4991 .port_get_cmode = mv88e6352_port_get_cmode, 4992 .port_setup_message_port = mv88e6xxx_setup_message_port, 4993 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4994 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4995 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4996 .stats_get_strings = mv88e6095_stats_get_strings, 4997 .stats_get_stats = mv88e6095_stats_get_stats, 4998 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4999 .set_egress_port = mv88e6095_g1_set_egress_port, 5000 .watchdog_ops = &mv88e6097_watchdog_ops, 5001 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5002 .pot_clear = mv88e6xxx_g2_pot_clear, 5003 .reset = mv88e6352_g1_reset, 5004 .rmu_disable = mv88e6352_g1_rmu_disable, 5005 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5006 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5007 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5008 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5009 .stu_getnext = mv88e6352_g1_stu_getnext, 5010 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5011 .serdes_get_lane = mv88e6352_serdes_get_lane, 5012 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 5013 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 5014 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 5015 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 5016 .serdes_power = mv88e6352_serdes_power, 5017 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5018 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 5019 .serdes_irq_status = mv88e6352_serdes_irq_status, 5020 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5021 .serdes_get_regs = mv88e6352_serdes_get_regs, 5022 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5023 .gpio_ops = &mv88e6352_gpio_ops, 5024 .avb_ops = &mv88e6352_avb_ops, 5025 .ptp_ops = &mv88e6352_ptp_ops, 5026 .phylink_get_caps = mv88e6352_phylink_get_caps, 5027 }; 5028 5029 static const struct mv88e6xxx_ops mv88e6250_ops = { 5030 /* MV88E6XXX_FAMILY_6250 */ 5031 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 5032 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5033 .irl_init_all = mv88e6352_g2_irl_init_all, 5034 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5035 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5036 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5037 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5038 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5039 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5040 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5041 .port_set_link = mv88e6xxx_port_set_link, 5042 .port_sync_link = mv88e6xxx_port_sync_link, 5043 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5044 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 5045 .port_tag_remap = mv88e6095_port_tag_remap, 5046 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5047 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5048 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5049 .port_set_ether_type = mv88e6351_port_set_ether_type, 5050 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5051 .port_pause_limit = mv88e6097_port_pause_limit, 5052 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5053 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5054 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5055 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 5056 .stats_get_strings = mv88e6250_stats_get_strings, 5057 .stats_get_stats = mv88e6250_stats_get_stats, 5058 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5059 .set_egress_port = mv88e6095_g1_set_egress_port, 5060 .watchdog_ops = &mv88e6250_watchdog_ops, 5061 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5062 .pot_clear = mv88e6xxx_g2_pot_clear, 5063 .reset = mv88e6250_g1_reset, 5064 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5065 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5066 .avb_ops = &mv88e6352_avb_ops, 5067 .ptp_ops = &mv88e6250_ptp_ops, 5068 .phylink_get_caps = mv88e6250_phylink_get_caps, 5069 }; 5070 5071 static const struct mv88e6xxx_ops mv88e6290_ops = { 5072 /* MV88E6XXX_FAMILY_6390 */ 5073 .setup_errata = mv88e6390_setup_errata, 5074 .irl_init_all = mv88e6390_g2_irl_init_all, 5075 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5076 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5077 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5078 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5079 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5080 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5081 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5082 .port_set_link = mv88e6xxx_port_set_link, 5083 .port_sync_link = mv88e6xxx_port_sync_link, 5084 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5085 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5086 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5087 .port_tag_remap = mv88e6390_port_tag_remap, 5088 .port_set_policy = mv88e6352_port_set_policy, 5089 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5090 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5091 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5092 .port_set_ether_type = mv88e6351_port_set_ether_type, 5093 .port_pause_limit = mv88e6390_port_pause_limit, 5094 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5095 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5096 .port_get_cmode = mv88e6352_port_get_cmode, 5097 .port_set_cmode = mv88e6390_port_set_cmode, 5098 .port_setup_message_port = mv88e6xxx_setup_message_port, 5099 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5100 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5101 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5102 .stats_get_strings = mv88e6320_stats_get_strings, 5103 .stats_get_stats = mv88e6390_stats_get_stats, 5104 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5105 .set_egress_port = mv88e6390_g1_set_egress_port, 5106 .watchdog_ops = &mv88e6390_watchdog_ops, 5107 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5108 .pot_clear = mv88e6xxx_g2_pot_clear, 5109 .reset = mv88e6352_g1_reset, 5110 .rmu_disable = mv88e6390_g1_rmu_disable, 5111 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5112 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5113 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5114 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5115 .stu_getnext = mv88e6390_g1_stu_getnext, 5116 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5117 .serdes_power = mv88e6390_serdes_power, 5118 .serdes_get_lane = mv88e6390_serdes_get_lane, 5119 /* Check status register pause & lpa register */ 5120 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5121 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5122 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5123 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5124 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5125 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5126 .serdes_irq_status = mv88e6390_serdes_irq_status, 5127 .serdes_get_strings = mv88e6390_serdes_get_strings, 5128 .serdes_get_stats = mv88e6390_serdes_get_stats, 5129 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5130 .serdes_get_regs = mv88e6390_serdes_get_regs, 5131 .gpio_ops = &mv88e6352_gpio_ops, 5132 .avb_ops = &mv88e6390_avb_ops, 5133 .ptp_ops = &mv88e6390_ptp_ops, 5134 .phylink_get_caps = mv88e6390_phylink_get_caps, 5135 }; 5136 5137 static const struct mv88e6xxx_ops mv88e6320_ops = { 5138 /* MV88E6XXX_FAMILY_6320 */ 5139 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5140 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5141 .irl_init_all = mv88e6352_g2_irl_init_all, 5142 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5143 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5144 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5145 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5146 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5147 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5148 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5149 .port_set_link = mv88e6xxx_port_set_link, 5150 .port_sync_link = mv88e6xxx_port_sync_link, 5151 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5152 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5153 .port_tag_remap = mv88e6095_port_tag_remap, 5154 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5155 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5156 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5157 .port_set_ether_type = mv88e6351_port_set_ether_type, 5158 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5159 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5160 .port_pause_limit = mv88e6097_port_pause_limit, 5161 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5162 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5163 .port_get_cmode = mv88e6352_port_get_cmode, 5164 .port_setup_message_port = mv88e6xxx_setup_message_port, 5165 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5166 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5167 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5168 .stats_get_strings = mv88e6320_stats_get_strings, 5169 .stats_get_stats = mv88e6320_stats_get_stats, 5170 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5171 .set_egress_port = mv88e6095_g1_set_egress_port, 5172 .watchdog_ops = &mv88e6390_watchdog_ops, 5173 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5174 .pot_clear = mv88e6xxx_g2_pot_clear, 5175 .reset = mv88e6352_g1_reset, 5176 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5177 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5178 .gpio_ops = &mv88e6352_gpio_ops, 5179 .avb_ops = &mv88e6352_avb_ops, 5180 .ptp_ops = &mv88e6352_ptp_ops, 5181 .phylink_get_caps = mv88e6185_phylink_get_caps, 5182 }; 5183 5184 static const struct mv88e6xxx_ops mv88e6321_ops = { 5185 /* MV88E6XXX_FAMILY_6320 */ 5186 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5187 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5188 .irl_init_all = mv88e6352_g2_irl_init_all, 5189 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5190 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5191 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5192 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5193 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5194 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5195 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5196 .port_set_link = mv88e6xxx_port_set_link, 5197 .port_sync_link = mv88e6xxx_port_sync_link, 5198 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5199 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5200 .port_tag_remap = mv88e6095_port_tag_remap, 5201 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5202 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5203 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5204 .port_set_ether_type = mv88e6351_port_set_ether_type, 5205 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5206 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5207 .port_pause_limit = mv88e6097_port_pause_limit, 5208 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5209 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5210 .port_get_cmode = mv88e6352_port_get_cmode, 5211 .port_setup_message_port = mv88e6xxx_setup_message_port, 5212 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5213 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5214 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5215 .stats_get_strings = mv88e6320_stats_get_strings, 5216 .stats_get_stats = mv88e6320_stats_get_stats, 5217 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5218 .set_egress_port = mv88e6095_g1_set_egress_port, 5219 .watchdog_ops = &mv88e6390_watchdog_ops, 5220 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5221 .reset = mv88e6352_g1_reset, 5222 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5223 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5224 .gpio_ops = &mv88e6352_gpio_ops, 5225 .avb_ops = &mv88e6352_avb_ops, 5226 .ptp_ops = &mv88e6352_ptp_ops, 5227 .phylink_get_caps = mv88e6185_phylink_get_caps, 5228 }; 5229 5230 static const struct mv88e6xxx_ops mv88e6341_ops = { 5231 /* MV88E6XXX_FAMILY_6341 */ 5232 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5233 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5234 .irl_init_all = mv88e6352_g2_irl_init_all, 5235 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5236 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5237 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5238 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5239 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5240 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5241 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5242 .port_set_link = mv88e6xxx_port_set_link, 5243 .port_sync_link = mv88e6xxx_port_sync_link, 5244 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5245 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5246 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5247 .port_tag_remap = mv88e6095_port_tag_remap, 5248 .port_set_policy = mv88e6352_port_set_policy, 5249 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5250 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5251 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5252 .port_set_ether_type = mv88e6351_port_set_ether_type, 5253 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5254 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5255 .port_pause_limit = mv88e6097_port_pause_limit, 5256 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5257 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5258 .port_get_cmode = mv88e6352_port_get_cmode, 5259 .port_set_cmode = mv88e6341_port_set_cmode, 5260 .port_setup_message_port = mv88e6xxx_setup_message_port, 5261 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5262 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5263 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5264 .stats_get_strings = mv88e6320_stats_get_strings, 5265 .stats_get_stats = mv88e6390_stats_get_stats, 5266 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5267 .set_egress_port = mv88e6390_g1_set_egress_port, 5268 .watchdog_ops = &mv88e6390_watchdog_ops, 5269 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5270 .pot_clear = mv88e6xxx_g2_pot_clear, 5271 .reset = mv88e6352_g1_reset, 5272 .rmu_disable = mv88e6390_g1_rmu_disable, 5273 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5274 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5275 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5276 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5277 .stu_getnext = mv88e6352_g1_stu_getnext, 5278 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5279 .serdes_power = mv88e6390_serdes_power, 5280 .serdes_get_lane = mv88e6341_serdes_get_lane, 5281 /* Check status register pause & lpa register */ 5282 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5283 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5284 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5285 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5286 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5287 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5288 .serdes_irq_status = mv88e6390_serdes_irq_status, 5289 .gpio_ops = &mv88e6352_gpio_ops, 5290 .avb_ops = &mv88e6390_avb_ops, 5291 .ptp_ops = &mv88e6352_ptp_ops, 5292 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5293 .serdes_get_strings = mv88e6390_serdes_get_strings, 5294 .serdes_get_stats = mv88e6390_serdes_get_stats, 5295 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5296 .serdes_get_regs = mv88e6390_serdes_get_regs, 5297 .phylink_get_caps = mv88e6341_phylink_get_caps, 5298 }; 5299 5300 static const struct mv88e6xxx_ops mv88e6350_ops = { 5301 /* MV88E6XXX_FAMILY_6351 */ 5302 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5303 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5304 .irl_init_all = mv88e6352_g2_irl_init_all, 5305 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5306 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5307 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5308 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5309 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5310 .port_set_link = mv88e6xxx_port_set_link, 5311 .port_sync_link = mv88e6xxx_port_sync_link, 5312 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5313 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5314 .port_tag_remap = mv88e6095_port_tag_remap, 5315 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5316 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5317 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5318 .port_set_ether_type = mv88e6351_port_set_ether_type, 5319 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5320 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5321 .port_pause_limit = mv88e6097_port_pause_limit, 5322 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5323 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5324 .port_get_cmode = mv88e6352_port_get_cmode, 5325 .port_setup_message_port = mv88e6xxx_setup_message_port, 5326 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5327 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5328 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5329 .stats_get_strings = mv88e6095_stats_get_strings, 5330 .stats_get_stats = mv88e6095_stats_get_stats, 5331 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5332 .set_egress_port = mv88e6095_g1_set_egress_port, 5333 .watchdog_ops = &mv88e6097_watchdog_ops, 5334 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5335 .pot_clear = mv88e6xxx_g2_pot_clear, 5336 .reset = mv88e6352_g1_reset, 5337 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5338 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5339 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5340 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5341 .stu_getnext = mv88e6352_g1_stu_getnext, 5342 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5343 .phylink_get_caps = mv88e6185_phylink_get_caps, 5344 }; 5345 5346 static const struct mv88e6xxx_ops mv88e6351_ops = { 5347 /* MV88E6XXX_FAMILY_6351 */ 5348 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5349 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5350 .irl_init_all = mv88e6352_g2_irl_init_all, 5351 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5352 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5353 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5354 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5355 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5356 .port_set_link = mv88e6xxx_port_set_link, 5357 .port_sync_link = mv88e6xxx_port_sync_link, 5358 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5359 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5360 .port_tag_remap = mv88e6095_port_tag_remap, 5361 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5362 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5363 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5364 .port_set_ether_type = mv88e6351_port_set_ether_type, 5365 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5366 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5367 .port_pause_limit = mv88e6097_port_pause_limit, 5368 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5369 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5370 .port_get_cmode = mv88e6352_port_get_cmode, 5371 .port_setup_message_port = mv88e6xxx_setup_message_port, 5372 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5373 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5374 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5375 .stats_get_strings = mv88e6095_stats_get_strings, 5376 .stats_get_stats = mv88e6095_stats_get_stats, 5377 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5378 .set_egress_port = mv88e6095_g1_set_egress_port, 5379 .watchdog_ops = &mv88e6097_watchdog_ops, 5380 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5381 .pot_clear = mv88e6xxx_g2_pot_clear, 5382 .reset = mv88e6352_g1_reset, 5383 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5384 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5385 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5386 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5387 .stu_getnext = mv88e6352_g1_stu_getnext, 5388 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5389 .avb_ops = &mv88e6352_avb_ops, 5390 .ptp_ops = &mv88e6352_ptp_ops, 5391 .phylink_get_caps = mv88e6185_phylink_get_caps, 5392 }; 5393 5394 static const struct mv88e6xxx_ops mv88e6352_ops = { 5395 /* MV88E6XXX_FAMILY_6352 */ 5396 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5397 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5398 .irl_init_all = mv88e6352_g2_irl_init_all, 5399 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5400 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5401 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5402 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5403 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5404 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5405 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5406 .port_set_link = mv88e6xxx_port_set_link, 5407 .port_sync_link = mv88e6xxx_port_sync_link, 5408 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5409 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5410 .port_tag_remap = mv88e6095_port_tag_remap, 5411 .port_set_policy = mv88e6352_port_set_policy, 5412 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5413 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5414 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5415 .port_set_ether_type = mv88e6351_port_set_ether_type, 5416 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5417 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5418 .port_pause_limit = mv88e6097_port_pause_limit, 5419 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5420 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5421 .port_get_cmode = mv88e6352_port_get_cmode, 5422 .port_setup_message_port = mv88e6xxx_setup_message_port, 5423 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5424 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5425 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5426 .stats_get_strings = mv88e6095_stats_get_strings, 5427 .stats_get_stats = mv88e6095_stats_get_stats, 5428 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5429 .set_egress_port = mv88e6095_g1_set_egress_port, 5430 .watchdog_ops = &mv88e6097_watchdog_ops, 5431 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5432 .pot_clear = mv88e6xxx_g2_pot_clear, 5433 .reset = mv88e6352_g1_reset, 5434 .rmu_disable = mv88e6352_g1_rmu_disable, 5435 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5436 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5437 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5438 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5439 .stu_getnext = mv88e6352_g1_stu_getnext, 5440 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5441 .serdes_get_lane = mv88e6352_serdes_get_lane, 5442 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 5443 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 5444 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 5445 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 5446 .serdes_power = mv88e6352_serdes_power, 5447 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5448 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 5449 .serdes_irq_status = mv88e6352_serdes_irq_status, 5450 .gpio_ops = &mv88e6352_gpio_ops, 5451 .avb_ops = &mv88e6352_avb_ops, 5452 .ptp_ops = &mv88e6352_ptp_ops, 5453 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5454 .serdes_get_strings = mv88e6352_serdes_get_strings, 5455 .serdes_get_stats = mv88e6352_serdes_get_stats, 5456 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5457 .serdes_get_regs = mv88e6352_serdes_get_regs, 5458 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5459 .phylink_get_caps = mv88e6352_phylink_get_caps, 5460 }; 5461 5462 static const struct mv88e6xxx_ops mv88e6390_ops = { 5463 /* MV88E6XXX_FAMILY_6390 */ 5464 .setup_errata = mv88e6390_setup_errata, 5465 .irl_init_all = mv88e6390_g2_irl_init_all, 5466 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5467 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5468 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5469 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5470 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5471 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5472 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5473 .port_set_link = mv88e6xxx_port_set_link, 5474 .port_sync_link = mv88e6xxx_port_sync_link, 5475 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5476 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5477 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5478 .port_tag_remap = mv88e6390_port_tag_remap, 5479 .port_set_policy = mv88e6352_port_set_policy, 5480 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5481 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5482 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5483 .port_set_ether_type = mv88e6351_port_set_ether_type, 5484 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5485 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5486 .port_pause_limit = mv88e6390_port_pause_limit, 5487 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5488 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5489 .port_get_cmode = mv88e6352_port_get_cmode, 5490 .port_set_cmode = mv88e6390_port_set_cmode, 5491 .port_setup_message_port = mv88e6xxx_setup_message_port, 5492 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5493 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5494 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5495 .stats_get_strings = mv88e6320_stats_get_strings, 5496 .stats_get_stats = mv88e6390_stats_get_stats, 5497 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5498 .set_egress_port = mv88e6390_g1_set_egress_port, 5499 .watchdog_ops = &mv88e6390_watchdog_ops, 5500 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5501 .pot_clear = mv88e6xxx_g2_pot_clear, 5502 .reset = mv88e6352_g1_reset, 5503 .rmu_disable = mv88e6390_g1_rmu_disable, 5504 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5505 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5506 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5507 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5508 .stu_getnext = mv88e6390_g1_stu_getnext, 5509 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5510 .serdes_power = mv88e6390_serdes_power, 5511 .serdes_get_lane = mv88e6390_serdes_get_lane, 5512 /* Check status register pause & lpa register */ 5513 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5514 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5515 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5516 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5517 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5518 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5519 .serdes_irq_status = mv88e6390_serdes_irq_status, 5520 .gpio_ops = &mv88e6352_gpio_ops, 5521 .avb_ops = &mv88e6390_avb_ops, 5522 .ptp_ops = &mv88e6390_ptp_ops, 5523 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5524 .serdes_get_strings = mv88e6390_serdes_get_strings, 5525 .serdes_get_stats = mv88e6390_serdes_get_stats, 5526 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5527 .serdes_get_regs = mv88e6390_serdes_get_regs, 5528 .phylink_get_caps = mv88e6390_phylink_get_caps, 5529 }; 5530 5531 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5532 /* MV88E6XXX_FAMILY_6390 */ 5533 .setup_errata = mv88e6390_setup_errata, 5534 .irl_init_all = mv88e6390_g2_irl_init_all, 5535 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5536 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5537 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5538 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5539 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5540 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5541 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5542 .port_set_link = mv88e6xxx_port_set_link, 5543 .port_sync_link = mv88e6xxx_port_sync_link, 5544 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5545 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5546 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5547 .port_tag_remap = mv88e6390_port_tag_remap, 5548 .port_set_policy = mv88e6352_port_set_policy, 5549 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5550 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5551 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5552 .port_set_ether_type = mv88e6351_port_set_ether_type, 5553 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5554 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5555 .port_pause_limit = mv88e6390_port_pause_limit, 5556 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5557 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5558 .port_get_cmode = mv88e6352_port_get_cmode, 5559 .port_set_cmode = mv88e6390x_port_set_cmode, 5560 .port_setup_message_port = mv88e6xxx_setup_message_port, 5561 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5562 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5563 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5564 .stats_get_strings = mv88e6320_stats_get_strings, 5565 .stats_get_stats = mv88e6390_stats_get_stats, 5566 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5567 .set_egress_port = mv88e6390_g1_set_egress_port, 5568 .watchdog_ops = &mv88e6390_watchdog_ops, 5569 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5570 .pot_clear = mv88e6xxx_g2_pot_clear, 5571 .reset = mv88e6352_g1_reset, 5572 .rmu_disable = mv88e6390_g1_rmu_disable, 5573 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5574 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5575 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5576 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5577 .stu_getnext = mv88e6390_g1_stu_getnext, 5578 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5579 .serdes_power = mv88e6390_serdes_power, 5580 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5581 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5582 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5583 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5584 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5585 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5586 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5587 .serdes_irq_status = mv88e6390_serdes_irq_status, 5588 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5589 .serdes_get_strings = mv88e6390_serdes_get_strings, 5590 .serdes_get_stats = mv88e6390_serdes_get_stats, 5591 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5592 .serdes_get_regs = mv88e6390_serdes_get_regs, 5593 .gpio_ops = &mv88e6352_gpio_ops, 5594 .avb_ops = &mv88e6390_avb_ops, 5595 .ptp_ops = &mv88e6390_ptp_ops, 5596 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5597 }; 5598 5599 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5600 /* MV88E6XXX_FAMILY_6393 */ 5601 .setup_errata = mv88e6393x_serdes_setup_errata, 5602 .irl_init_all = mv88e6390_g2_irl_init_all, 5603 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5604 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5605 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5606 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5607 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5608 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5609 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5610 .port_set_link = mv88e6xxx_port_set_link, 5611 .port_sync_link = mv88e6xxx_port_sync_link, 5612 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5613 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5614 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5615 .port_tag_remap = mv88e6390_port_tag_remap, 5616 .port_set_policy = mv88e6393x_port_set_policy, 5617 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5618 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5619 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5620 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5621 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5622 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5623 .port_pause_limit = mv88e6390_port_pause_limit, 5624 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5625 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5626 .port_get_cmode = mv88e6352_port_get_cmode, 5627 .port_set_cmode = mv88e6393x_port_set_cmode, 5628 .port_setup_message_port = mv88e6xxx_setup_message_port, 5629 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5630 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5631 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5632 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5633 .stats_get_strings = mv88e6320_stats_get_strings, 5634 .stats_get_stats = mv88e6390_stats_get_stats, 5635 /* .set_cpu_port is missing because this family does not support a global 5636 * CPU port, only per port CPU port which is set via 5637 * .port_set_upstream_port method. 5638 */ 5639 .set_egress_port = mv88e6393x_set_egress_port, 5640 .watchdog_ops = &mv88e6393x_watchdog_ops, 5641 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5642 .pot_clear = mv88e6xxx_g2_pot_clear, 5643 .reset = mv88e6352_g1_reset, 5644 .rmu_disable = mv88e6390_g1_rmu_disable, 5645 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5646 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5647 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5648 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5649 .stu_getnext = mv88e6390_g1_stu_getnext, 5650 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5651 .serdes_power = mv88e6393x_serdes_power, 5652 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5653 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 5654 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5655 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5656 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5657 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5658 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 5659 .serdes_irq_status = mv88e6393x_serdes_irq_status, 5660 /* TODO: serdes stats */ 5661 .gpio_ops = &mv88e6352_gpio_ops, 5662 .avb_ops = &mv88e6390_avb_ops, 5663 .ptp_ops = &mv88e6352_ptp_ops, 5664 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5665 }; 5666 5667 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5668 [MV88E6085] = { 5669 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5670 .family = MV88E6XXX_FAMILY_6097, 5671 .name = "Marvell 88E6085", 5672 .num_databases = 4096, 5673 .num_macs = 8192, 5674 .num_ports = 10, 5675 .num_internal_phys = 5, 5676 .max_vid = 4095, 5677 .max_sid = 63, 5678 .port_base_addr = 0x10, 5679 .phy_base_addr = 0x0, 5680 .global1_addr = 0x1b, 5681 .global2_addr = 0x1c, 5682 .age_time_coeff = 15000, 5683 .g1_irqs = 8, 5684 .g2_irqs = 10, 5685 .atu_move_port_mask = 0xf, 5686 .pvt = true, 5687 .multi_chip = true, 5688 .ops = &mv88e6085_ops, 5689 }, 5690 5691 [MV88E6095] = { 5692 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5693 .family = MV88E6XXX_FAMILY_6095, 5694 .name = "Marvell 88E6095/88E6095F", 5695 .num_databases = 256, 5696 .num_macs = 8192, 5697 .num_ports = 11, 5698 .num_internal_phys = 0, 5699 .max_vid = 4095, 5700 .port_base_addr = 0x10, 5701 .phy_base_addr = 0x0, 5702 .global1_addr = 0x1b, 5703 .global2_addr = 0x1c, 5704 .age_time_coeff = 15000, 5705 .g1_irqs = 8, 5706 .atu_move_port_mask = 0xf, 5707 .multi_chip = true, 5708 .ops = &mv88e6095_ops, 5709 }, 5710 5711 [MV88E6097] = { 5712 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5713 .family = MV88E6XXX_FAMILY_6097, 5714 .name = "Marvell 88E6097/88E6097F", 5715 .num_databases = 4096, 5716 .num_macs = 8192, 5717 .num_ports = 11, 5718 .num_internal_phys = 8, 5719 .max_vid = 4095, 5720 .max_sid = 63, 5721 .port_base_addr = 0x10, 5722 .phy_base_addr = 0x0, 5723 .global1_addr = 0x1b, 5724 .global2_addr = 0x1c, 5725 .age_time_coeff = 15000, 5726 .g1_irqs = 8, 5727 .g2_irqs = 10, 5728 .atu_move_port_mask = 0xf, 5729 .pvt = true, 5730 .multi_chip = true, 5731 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5732 .ops = &mv88e6097_ops, 5733 }, 5734 5735 [MV88E6123] = { 5736 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5737 .family = MV88E6XXX_FAMILY_6165, 5738 .name = "Marvell 88E6123", 5739 .num_databases = 4096, 5740 .num_macs = 1024, 5741 .num_ports = 3, 5742 .num_internal_phys = 5, 5743 .max_vid = 4095, 5744 .max_sid = 63, 5745 .port_base_addr = 0x10, 5746 .phy_base_addr = 0x0, 5747 .global1_addr = 0x1b, 5748 .global2_addr = 0x1c, 5749 .age_time_coeff = 15000, 5750 .g1_irqs = 9, 5751 .g2_irqs = 10, 5752 .atu_move_port_mask = 0xf, 5753 .pvt = true, 5754 .multi_chip = true, 5755 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5756 .ops = &mv88e6123_ops, 5757 }, 5758 5759 [MV88E6131] = { 5760 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5761 .family = MV88E6XXX_FAMILY_6185, 5762 .name = "Marvell 88E6131", 5763 .num_databases = 256, 5764 .num_macs = 8192, 5765 .num_ports = 8, 5766 .num_internal_phys = 0, 5767 .max_vid = 4095, 5768 .port_base_addr = 0x10, 5769 .phy_base_addr = 0x0, 5770 .global1_addr = 0x1b, 5771 .global2_addr = 0x1c, 5772 .age_time_coeff = 15000, 5773 .g1_irqs = 9, 5774 .atu_move_port_mask = 0xf, 5775 .multi_chip = true, 5776 .ops = &mv88e6131_ops, 5777 }, 5778 5779 [MV88E6141] = { 5780 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5781 .family = MV88E6XXX_FAMILY_6341, 5782 .name = "Marvell 88E6141", 5783 .num_databases = 4096, 5784 .num_macs = 2048, 5785 .num_ports = 6, 5786 .num_internal_phys = 5, 5787 .num_gpio = 11, 5788 .max_vid = 4095, 5789 .max_sid = 63, 5790 .port_base_addr = 0x10, 5791 .phy_base_addr = 0x10, 5792 .global1_addr = 0x1b, 5793 .global2_addr = 0x1c, 5794 .age_time_coeff = 3750, 5795 .atu_move_port_mask = 0x1f, 5796 .g1_irqs = 9, 5797 .g2_irqs = 10, 5798 .pvt = true, 5799 .multi_chip = true, 5800 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5801 .ops = &mv88e6141_ops, 5802 }, 5803 5804 [MV88E6161] = { 5805 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5806 .family = MV88E6XXX_FAMILY_6165, 5807 .name = "Marvell 88E6161", 5808 .num_databases = 4096, 5809 .num_macs = 1024, 5810 .num_ports = 6, 5811 .num_internal_phys = 5, 5812 .max_vid = 4095, 5813 .max_sid = 63, 5814 .port_base_addr = 0x10, 5815 .phy_base_addr = 0x0, 5816 .global1_addr = 0x1b, 5817 .global2_addr = 0x1c, 5818 .age_time_coeff = 15000, 5819 .g1_irqs = 9, 5820 .g2_irqs = 10, 5821 .atu_move_port_mask = 0xf, 5822 .pvt = true, 5823 .multi_chip = true, 5824 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5825 .ptp_support = true, 5826 .ops = &mv88e6161_ops, 5827 }, 5828 5829 [MV88E6165] = { 5830 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5831 .family = MV88E6XXX_FAMILY_6165, 5832 .name = "Marvell 88E6165", 5833 .num_databases = 4096, 5834 .num_macs = 8192, 5835 .num_ports = 6, 5836 .num_internal_phys = 0, 5837 .max_vid = 4095, 5838 .max_sid = 63, 5839 .port_base_addr = 0x10, 5840 .phy_base_addr = 0x0, 5841 .global1_addr = 0x1b, 5842 .global2_addr = 0x1c, 5843 .age_time_coeff = 15000, 5844 .g1_irqs = 9, 5845 .g2_irqs = 10, 5846 .atu_move_port_mask = 0xf, 5847 .pvt = true, 5848 .multi_chip = true, 5849 .ptp_support = true, 5850 .ops = &mv88e6165_ops, 5851 }, 5852 5853 [MV88E6171] = { 5854 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5855 .family = MV88E6XXX_FAMILY_6351, 5856 .name = "Marvell 88E6171", 5857 .num_databases = 4096, 5858 .num_macs = 8192, 5859 .num_ports = 7, 5860 .num_internal_phys = 5, 5861 .max_vid = 4095, 5862 .max_sid = 63, 5863 .port_base_addr = 0x10, 5864 .phy_base_addr = 0x0, 5865 .global1_addr = 0x1b, 5866 .global2_addr = 0x1c, 5867 .age_time_coeff = 15000, 5868 .g1_irqs = 9, 5869 .g2_irqs = 10, 5870 .atu_move_port_mask = 0xf, 5871 .pvt = true, 5872 .multi_chip = true, 5873 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5874 .ops = &mv88e6171_ops, 5875 }, 5876 5877 [MV88E6172] = { 5878 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5879 .family = MV88E6XXX_FAMILY_6352, 5880 .name = "Marvell 88E6172", 5881 .num_databases = 4096, 5882 .num_macs = 8192, 5883 .num_ports = 7, 5884 .num_internal_phys = 5, 5885 .num_gpio = 15, 5886 .max_vid = 4095, 5887 .max_sid = 63, 5888 .port_base_addr = 0x10, 5889 .phy_base_addr = 0x0, 5890 .global1_addr = 0x1b, 5891 .global2_addr = 0x1c, 5892 .age_time_coeff = 15000, 5893 .g1_irqs = 9, 5894 .g2_irqs = 10, 5895 .atu_move_port_mask = 0xf, 5896 .pvt = true, 5897 .multi_chip = true, 5898 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5899 .ops = &mv88e6172_ops, 5900 }, 5901 5902 [MV88E6175] = { 5903 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5904 .family = MV88E6XXX_FAMILY_6351, 5905 .name = "Marvell 88E6175", 5906 .num_databases = 4096, 5907 .num_macs = 8192, 5908 .num_ports = 7, 5909 .num_internal_phys = 5, 5910 .max_vid = 4095, 5911 .max_sid = 63, 5912 .port_base_addr = 0x10, 5913 .phy_base_addr = 0x0, 5914 .global1_addr = 0x1b, 5915 .global2_addr = 0x1c, 5916 .age_time_coeff = 15000, 5917 .g1_irqs = 9, 5918 .g2_irqs = 10, 5919 .atu_move_port_mask = 0xf, 5920 .pvt = true, 5921 .multi_chip = true, 5922 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5923 .ops = &mv88e6175_ops, 5924 }, 5925 5926 [MV88E6176] = { 5927 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5928 .family = MV88E6XXX_FAMILY_6352, 5929 .name = "Marvell 88E6176", 5930 .num_databases = 4096, 5931 .num_macs = 8192, 5932 .num_ports = 7, 5933 .num_internal_phys = 5, 5934 .num_gpio = 15, 5935 .max_vid = 4095, 5936 .max_sid = 63, 5937 .port_base_addr = 0x10, 5938 .phy_base_addr = 0x0, 5939 .global1_addr = 0x1b, 5940 .global2_addr = 0x1c, 5941 .age_time_coeff = 15000, 5942 .g1_irqs = 9, 5943 .g2_irqs = 10, 5944 .atu_move_port_mask = 0xf, 5945 .pvt = true, 5946 .multi_chip = true, 5947 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5948 .ops = &mv88e6176_ops, 5949 }, 5950 5951 [MV88E6185] = { 5952 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5953 .family = MV88E6XXX_FAMILY_6185, 5954 .name = "Marvell 88E6185", 5955 .num_databases = 256, 5956 .num_macs = 8192, 5957 .num_ports = 10, 5958 .num_internal_phys = 0, 5959 .max_vid = 4095, 5960 .port_base_addr = 0x10, 5961 .phy_base_addr = 0x0, 5962 .global1_addr = 0x1b, 5963 .global2_addr = 0x1c, 5964 .age_time_coeff = 15000, 5965 .g1_irqs = 8, 5966 .atu_move_port_mask = 0xf, 5967 .multi_chip = true, 5968 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5969 .ops = &mv88e6185_ops, 5970 }, 5971 5972 [MV88E6190] = { 5973 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5974 .family = MV88E6XXX_FAMILY_6390, 5975 .name = "Marvell 88E6190", 5976 .num_databases = 4096, 5977 .num_macs = 16384, 5978 .num_ports = 11, /* 10 + Z80 */ 5979 .num_internal_phys = 9, 5980 .num_gpio = 16, 5981 .max_vid = 8191, 5982 .max_sid = 63, 5983 .port_base_addr = 0x0, 5984 .phy_base_addr = 0x0, 5985 .global1_addr = 0x1b, 5986 .global2_addr = 0x1c, 5987 .age_time_coeff = 3750, 5988 .g1_irqs = 9, 5989 .g2_irqs = 14, 5990 .pvt = true, 5991 .multi_chip = true, 5992 .atu_move_port_mask = 0x1f, 5993 .ops = &mv88e6190_ops, 5994 }, 5995 5996 [MV88E6190X] = { 5997 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5998 .family = MV88E6XXX_FAMILY_6390, 5999 .name = "Marvell 88E6190X", 6000 .num_databases = 4096, 6001 .num_macs = 16384, 6002 .num_ports = 11, /* 10 + Z80 */ 6003 .num_internal_phys = 9, 6004 .num_gpio = 16, 6005 .max_vid = 8191, 6006 .max_sid = 63, 6007 .port_base_addr = 0x0, 6008 .phy_base_addr = 0x0, 6009 .global1_addr = 0x1b, 6010 .global2_addr = 0x1c, 6011 .age_time_coeff = 3750, 6012 .g1_irqs = 9, 6013 .g2_irqs = 14, 6014 .atu_move_port_mask = 0x1f, 6015 .pvt = true, 6016 .multi_chip = true, 6017 .ops = &mv88e6190x_ops, 6018 }, 6019 6020 [MV88E6191] = { 6021 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 6022 .family = MV88E6XXX_FAMILY_6390, 6023 .name = "Marvell 88E6191", 6024 .num_databases = 4096, 6025 .num_macs = 16384, 6026 .num_ports = 11, /* 10 + Z80 */ 6027 .num_internal_phys = 9, 6028 .max_vid = 8191, 6029 .max_sid = 63, 6030 .port_base_addr = 0x0, 6031 .phy_base_addr = 0x0, 6032 .global1_addr = 0x1b, 6033 .global2_addr = 0x1c, 6034 .age_time_coeff = 3750, 6035 .g1_irqs = 9, 6036 .g2_irqs = 14, 6037 .atu_move_port_mask = 0x1f, 6038 .pvt = true, 6039 .multi_chip = true, 6040 .ptp_support = true, 6041 .ops = &mv88e6191_ops, 6042 }, 6043 6044 [MV88E6191X] = { 6045 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 6046 .family = MV88E6XXX_FAMILY_6393, 6047 .name = "Marvell 88E6191X", 6048 .num_databases = 4096, 6049 .num_ports = 11, /* 10 + Z80 */ 6050 .num_internal_phys = 9, 6051 .max_vid = 8191, 6052 .max_sid = 63, 6053 .port_base_addr = 0x0, 6054 .phy_base_addr = 0x0, 6055 .global1_addr = 0x1b, 6056 .global2_addr = 0x1c, 6057 .age_time_coeff = 3750, 6058 .g1_irqs = 10, 6059 .g2_irqs = 14, 6060 .atu_move_port_mask = 0x1f, 6061 .pvt = true, 6062 .multi_chip = true, 6063 .ptp_support = true, 6064 .ops = &mv88e6393x_ops, 6065 }, 6066 6067 [MV88E6193X] = { 6068 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 6069 .family = MV88E6XXX_FAMILY_6393, 6070 .name = "Marvell 88E6193X", 6071 .num_databases = 4096, 6072 .num_ports = 11, /* 10 + Z80 */ 6073 .num_internal_phys = 9, 6074 .max_vid = 8191, 6075 .max_sid = 63, 6076 .port_base_addr = 0x0, 6077 .phy_base_addr = 0x0, 6078 .global1_addr = 0x1b, 6079 .global2_addr = 0x1c, 6080 .age_time_coeff = 3750, 6081 .g1_irqs = 10, 6082 .g2_irqs = 14, 6083 .atu_move_port_mask = 0x1f, 6084 .pvt = true, 6085 .multi_chip = true, 6086 .ptp_support = true, 6087 .ops = &mv88e6393x_ops, 6088 }, 6089 6090 [MV88E6220] = { 6091 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 6092 .family = MV88E6XXX_FAMILY_6250, 6093 .name = "Marvell 88E6220", 6094 .num_databases = 64, 6095 6096 /* Ports 2-4 are not routed to pins 6097 * => usable ports 0, 1, 5, 6 6098 */ 6099 .num_ports = 7, 6100 .num_internal_phys = 2, 6101 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 6102 .max_vid = 4095, 6103 .port_base_addr = 0x08, 6104 .phy_base_addr = 0x00, 6105 .global1_addr = 0x0f, 6106 .global2_addr = 0x07, 6107 .age_time_coeff = 15000, 6108 .g1_irqs = 9, 6109 .g2_irqs = 10, 6110 .atu_move_port_mask = 0xf, 6111 .dual_chip = true, 6112 .ptp_support = true, 6113 .ops = &mv88e6250_ops, 6114 }, 6115 6116 [MV88E6240] = { 6117 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 6118 .family = MV88E6XXX_FAMILY_6352, 6119 .name = "Marvell 88E6240", 6120 .num_databases = 4096, 6121 .num_macs = 8192, 6122 .num_ports = 7, 6123 .num_internal_phys = 5, 6124 .num_gpio = 15, 6125 .max_vid = 4095, 6126 .max_sid = 63, 6127 .port_base_addr = 0x10, 6128 .phy_base_addr = 0x0, 6129 .global1_addr = 0x1b, 6130 .global2_addr = 0x1c, 6131 .age_time_coeff = 15000, 6132 .g1_irqs = 9, 6133 .g2_irqs = 10, 6134 .atu_move_port_mask = 0xf, 6135 .pvt = true, 6136 .multi_chip = true, 6137 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6138 .ptp_support = true, 6139 .ops = &mv88e6240_ops, 6140 }, 6141 6142 [MV88E6250] = { 6143 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6144 .family = MV88E6XXX_FAMILY_6250, 6145 .name = "Marvell 88E6250", 6146 .num_databases = 64, 6147 .num_ports = 7, 6148 .num_internal_phys = 5, 6149 .max_vid = 4095, 6150 .port_base_addr = 0x08, 6151 .phy_base_addr = 0x00, 6152 .global1_addr = 0x0f, 6153 .global2_addr = 0x07, 6154 .age_time_coeff = 15000, 6155 .g1_irqs = 9, 6156 .g2_irqs = 10, 6157 .atu_move_port_mask = 0xf, 6158 .dual_chip = true, 6159 .ptp_support = true, 6160 .ops = &mv88e6250_ops, 6161 }, 6162 6163 [MV88E6290] = { 6164 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6165 .family = MV88E6XXX_FAMILY_6390, 6166 .name = "Marvell 88E6290", 6167 .num_databases = 4096, 6168 .num_ports = 11, /* 10 + Z80 */ 6169 .num_internal_phys = 9, 6170 .num_gpio = 16, 6171 .max_vid = 8191, 6172 .max_sid = 63, 6173 .port_base_addr = 0x0, 6174 .phy_base_addr = 0x0, 6175 .global1_addr = 0x1b, 6176 .global2_addr = 0x1c, 6177 .age_time_coeff = 3750, 6178 .g1_irqs = 9, 6179 .g2_irqs = 14, 6180 .atu_move_port_mask = 0x1f, 6181 .pvt = true, 6182 .multi_chip = true, 6183 .ptp_support = true, 6184 .ops = &mv88e6290_ops, 6185 }, 6186 6187 [MV88E6320] = { 6188 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6189 .family = MV88E6XXX_FAMILY_6320, 6190 .name = "Marvell 88E6320", 6191 .num_databases = 4096, 6192 .num_macs = 8192, 6193 .num_ports = 7, 6194 .num_internal_phys = 5, 6195 .num_gpio = 15, 6196 .max_vid = 4095, 6197 .port_base_addr = 0x10, 6198 .phy_base_addr = 0x0, 6199 .global1_addr = 0x1b, 6200 .global2_addr = 0x1c, 6201 .age_time_coeff = 15000, 6202 .g1_irqs = 8, 6203 .g2_irqs = 10, 6204 .atu_move_port_mask = 0xf, 6205 .pvt = true, 6206 .multi_chip = true, 6207 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6208 .ptp_support = true, 6209 .ops = &mv88e6320_ops, 6210 }, 6211 6212 [MV88E6321] = { 6213 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6214 .family = MV88E6XXX_FAMILY_6320, 6215 .name = "Marvell 88E6321", 6216 .num_databases = 4096, 6217 .num_macs = 8192, 6218 .num_ports = 7, 6219 .num_internal_phys = 5, 6220 .num_gpio = 15, 6221 .max_vid = 4095, 6222 .port_base_addr = 0x10, 6223 .phy_base_addr = 0x0, 6224 .global1_addr = 0x1b, 6225 .global2_addr = 0x1c, 6226 .age_time_coeff = 15000, 6227 .g1_irqs = 8, 6228 .g2_irqs = 10, 6229 .atu_move_port_mask = 0xf, 6230 .multi_chip = true, 6231 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6232 .ptp_support = true, 6233 .ops = &mv88e6321_ops, 6234 }, 6235 6236 [MV88E6341] = { 6237 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6238 .family = MV88E6XXX_FAMILY_6341, 6239 .name = "Marvell 88E6341", 6240 .num_databases = 4096, 6241 .num_macs = 2048, 6242 .num_internal_phys = 5, 6243 .num_ports = 6, 6244 .num_gpio = 11, 6245 .max_vid = 4095, 6246 .max_sid = 63, 6247 .port_base_addr = 0x10, 6248 .phy_base_addr = 0x10, 6249 .global1_addr = 0x1b, 6250 .global2_addr = 0x1c, 6251 .age_time_coeff = 3750, 6252 .atu_move_port_mask = 0x1f, 6253 .g1_irqs = 9, 6254 .g2_irqs = 10, 6255 .pvt = true, 6256 .multi_chip = true, 6257 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6258 .ptp_support = true, 6259 .ops = &mv88e6341_ops, 6260 }, 6261 6262 [MV88E6350] = { 6263 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6264 .family = MV88E6XXX_FAMILY_6351, 6265 .name = "Marvell 88E6350", 6266 .num_databases = 4096, 6267 .num_macs = 8192, 6268 .num_ports = 7, 6269 .num_internal_phys = 5, 6270 .max_vid = 4095, 6271 .max_sid = 63, 6272 .port_base_addr = 0x10, 6273 .phy_base_addr = 0x0, 6274 .global1_addr = 0x1b, 6275 .global2_addr = 0x1c, 6276 .age_time_coeff = 15000, 6277 .g1_irqs = 9, 6278 .g2_irqs = 10, 6279 .atu_move_port_mask = 0xf, 6280 .pvt = true, 6281 .multi_chip = true, 6282 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6283 .ops = &mv88e6350_ops, 6284 }, 6285 6286 [MV88E6351] = { 6287 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6288 .family = MV88E6XXX_FAMILY_6351, 6289 .name = "Marvell 88E6351", 6290 .num_databases = 4096, 6291 .num_macs = 8192, 6292 .num_ports = 7, 6293 .num_internal_phys = 5, 6294 .max_vid = 4095, 6295 .max_sid = 63, 6296 .port_base_addr = 0x10, 6297 .phy_base_addr = 0x0, 6298 .global1_addr = 0x1b, 6299 .global2_addr = 0x1c, 6300 .age_time_coeff = 15000, 6301 .g1_irqs = 9, 6302 .g2_irqs = 10, 6303 .atu_move_port_mask = 0xf, 6304 .pvt = true, 6305 .multi_chip = true, 6306 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6307 .ops = &mv88e6351_ops, 6308 }, 6309 6310 [MV88E6352] = { 6311 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6312 .family = MV88E6XXX_FAMILY_6352, 6313 .name = "Marvell 88E6352", 6314 .num_databases = 4096, 6315 .num_macs = 8192, 6316 .num_ports = 7, 6317 .num_internal_phys = 5, 6318 .num_gpio = 15, 6319 .max_vid = 4095, 6320 .max_sid = 63, 6321 .port_base_addr = 0x10, 6322 .phy_base_addr = 0x0, 6323 .global1_addr = 0x1b, 6324 .global2_addr = 0x1c, 6325 .age_time_coeff = 15000, 6326 .g1_irqs = 9, 6327 .g2_irqs = 10, 6328 .atu_move_port_mask = 0xf, 6329 .pvt = true, 6330 .multi_chip = true, 6331 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6332 .ptp_support = true, 6333 .ops = &mv88e6352_ops, 6334 }, 6335 [MV88E6390] = { 6336 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6337 .family = MV88E6XXX_FAMILY_6390, 6338 .name = "Marvell 88E6390", 6339 .num_databases = 4096, 6340 .num_macs = 16384, 6341 .num_ports = 11, /* 10 + Z80 */ 6342 .num_internal_phys = 9, 6343 .num_gpio = 16, 6344 .max_vid = 8191, 6345 .max_sid = 63, 6346 .port_base_addr = 0x0, 6347 .phy_base_addr = 0x0, 6348 .global1_addr = 0x1b, 6349 .global2_addr = 0x1c, 6350 .age_time_coeff = 3750, 6351 .g1_irqs = 9, 6352 .g2_irqs = 14, 6353 .atu_move_port_mask = 0x1f, 6354 .pvt = true, 6355 .multi_chip = true, 6356 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6357 .ptp_support = true, 6358 .ops = &mv88e6390_ops, 6359 }, 6360 [MV88E6390X] = { 6361 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6362 .family = MV88E6XXX_FAMILY_6390, 6363 .name = "Marvell 88E6390X", 6364 .num_databases = 4096, 6365 .num_macs = 16384, 6366 .num_ports = 11, /* 10 + Z80 */ 6367 .num_internal_phys = 9, 6368 .num_gpio = 16, 6369 .max_vid = 8191, 6370 .max_sid = 63, 6371 .port_base_addr = 0x0, 6372 .phy_base_addr = 0x0, 6373 .global1_addr = 0x1b, 6374 .global2_addr = 0x1c, 6375 .age_time_coeff = 3750, 6376 .g1_irqs = 9, 6377 .g2_irqs = 14, 6378 .atu_move_port_mask = 0x1f, 6379 .pvt = true, 6380 .multi_chip = true, 6381 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6382 .ptp_support = true, 6383 .ops = &mv88e6390x_ops, 6384 }, 6385 6386 [MV88E6393X] = { 6387 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6388 .family = MV88E6XXX_FAMILY_6393, 6389 .name = "Marvell 88E6393X", 6390 .num_databases = 4096, 6391 .num_ports = 11, /* 10 + Z80 */ 6392 .num_internal_phys = 9, 6393 .max_vid = 8191, 6394 .max_sid = 63, 6395 .port_base_addr = 0x0, 6396 .phy_base_addr = 0x0, 6397 .global1_addr = 0x1b, 6398 .global2_addr = 0x1c, 6399 .age_time_coeff = 3750, 6400 .g1_irqs = 10, 6401 .g2_irqs = 14, 6402 .atu_move_port_mask = 0x1f, 6403 .pvt = true, 6404 .multi_chip = true, 6405 .ptp_support = true, 6406 .ops = &mv88e6393x_ops, 6407 }, 6408 }; 6409 6410 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6411 { 6412 int i; 6413 6414 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6415 if (mv88e6xxx_table[i].prod_num == prod_num) 6416 return &mv88e6xxx_table[i]; 6417 6418 return NULL; 6419 } 6420 6421 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6422 { 6423 const struct mv88e6xxx_info *info; 6424 unsigned int prod_num, rev; 6425 u16 id; 6426 int err; 6427 6428 mv88e6xxx_reg_lock(chip); 6429 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6430 mv88e6xxx_reg_unlock(chip); 6431 if (err) 6432 return err; 6433 6434 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6435 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6436 6437 info = mv88e6xxx_lookup_info(prod_num); 6438 if (!info) 6439 return -ENODEV; 6440 6441 /* Update the compatible info with the probed one */ 6442 chip->info = info; 6443 6444 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6445 chip->info->prod_num, chip->info->name, rev); 6446 6447 return 0; 6448 } 6449 6450 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6451 struct mdio_device *mdiodev) 6452 { 6453 int err; 6454 6455 /* dual_chip takes precedence over single/multi-chip modes */ 6456 if (chip->info->dual_chip) 6457 return -EINVAL; 6458 6459 /* If the mdio addr is 16 indicating the first port address of a switch 6460 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6461 * configured in single chip addressing mode. Setup the smi access as 6462 * single chip addressing mode and attempt to detect the model of the 6463 * switch, if this fails the device is not configured in single chip 6464 * addressing mode. 6465 */ 6466 if (mdiodev->addr != 16) 6467 return -EINVAL; 6468 6469 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6470 if (err) 6471 return err; 6472 6473 return mv88e6xxx_detect(chip); 6474 } 6475 6476 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6477 { 6478 struct mv88e6xxx_chip *chip; 6479 6480 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6481 if (!chip) 6482 return NULL; 6483 6484 chip->dev = dev; 6485 6486 mutex_init(&chip->reg_lock); 6487 INIT_LIST_HEAD(&chip->mdios); 6488 idr_init(&chip->policies); 6489 INIT_LIST_HEAD(&chip->msts); 6490 6491 return chip; 6492 } 6493 6494 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6495 int port, 6496 enum dsa_tag_protocol m) 6497 { 6498 struct mv88e6xxx_chip *chip = ds->priv; 6499 6500 return chip->tag_protocol; 6501 } 6502 6503 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6504 enum dsa_tag_protocol proto) 6505 { 6506 struct mv88e6xxx_chip *chip = ds->priv; 6507 enum dsa_tag_protocol old_protocol; 6508 struct dsa_port *cpu_dp; 6509 int err; 6510 6511 switch (proto) { 6512 case DSA_TAG_PROTO_EDSA: 6513 switch (chip->info->edsa_support) { 6514 case MV88E6XXX_EDSA_UNSUPPORTED: 6515 return -EPROTONOSUPPORT; 6516 case MV88E6XXX_EDSA_UNDOCUMENTED: 6517 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6518 fallthrough; 6519 case MV88E6XXX_EDSA_SUPPORTED: 6520 break; 6521 } 6522 break; 6523 case DSA_TAG_PROTO_DSA: 6524 break; 6525 default: 6526 return -EPROTONOSUPPORT; 6527 } 6528 6529 old_protocol = chip->tag_protocol; 6530 chip->tag_protocol = proto; 6531 6532 mv88e6xxx_reg_lock(chip); 6533 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6534 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6535 if (err) { 6536 mv88e6xxx_reg_unlock(chip); 6537 goto unwind; 6538 } 6539 } 6540 mv88e6xxx_reg_unlock(chip); 6541 6542 return 0; 6543 6544 unwind: 6545 chip->tag_protocol = old_protocol; 6546 6547 mv88e6xxx_reg_lock(chip); 6548 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6549 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6550 mv88e6xxx_reg_unlock(chip); 6551 6552 return err; 6553 } 6554 6555 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6556 const struct switchdev_obj_port_mdb *mdb, 6557 struct dsa_db db) 6558 { 6559 struct mv88e6xxx_chip *chip = ds->priv; 6560 int err; 6561 6562 mv88e6xxx_reg_lock(chip); 6563 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6564 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6565 mv88e6xxx_reg_unlock(chip); 6566 6567 return err; 6568 } 6569 6570 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6571 const struct switchdev_obj_port_mdb *mdb, 6572 struct dsa_db db) 6573 { 6574 struct mv88e6xxx_chip *chip = ds->priv; 6575 int err; 6576 6577 mv88e6xxx_reg_lock(chip); 6578 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6579 mv88e6xxx_reg_unlock(chip); 6580 6581 return err; 6582 } 6583 6584 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6585 struct dsa_mall_mirror_tc_entry *mirror, 6586 bool ingress, 6587 struct netlink_ext_ack *extack) 6588 { 6589 enum mv88e6xxx_egress_direction direction = ingress ? 6590 MV88E6XXX_EGRESS_DIR_INGRESS : 6591 MV88E6XXX_EGRESS_DIR_EGRESS; 6592 struct mv88e6xxx_chip *chip = ds->priv; 6593 bool other_mirrors = false; 6594 int i; 6595 int err; 6596 6597 mutex_lock(&chip->reg_lock); 6598 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6599 mirror->to_local_port) { 6600 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6601 other_mirrors |= ingress ? 6602 chip->ports[i].mirror_ingress : 6603 chip->ports[i].mirror_egress; 6604 6605 /* Can't change egress port when other mirror is active */ 6606 if (other_mirrors) { 6607 err = -EBUSY; 6608 goto out; 6609 } 6610 6611 err = mv88e6xxx_set_egress_port(chip, direction, 6612 mirror->to_local_port); 6613 if (err) 6614 goto out; 6615 } 6616 6617 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6618 out: 6619 mutex_unlock(&chip->reg_lock); 6620 6621 return err; 6622 } 6623 6624 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6625 struct dsa_mall_mirror_tc_entry *mirror) 6626 { 6627 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6628 MV88E6XXX_EGRESS_DIR_INGRESS : 6629 MV88E6XXX_EGRESS_DIR_EGRESS; 6630 struct mv88e6xxx_chip *chip = ds->priv; 6631 bool other_mirrors = false; 6632 int i; 6633 6634 mutex_lock(&chip->reg_lock); 6635 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6636 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6637 6638 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6639 other_mirrors |= mirror->ingress ? 6640 chip->ports[i].mirror_ingress : 6641 chip->ports[i].mirror_egress; 6642 6643 /* Reset egress port when no other mirror is active */ 6644 if (!other_mirrors) { 6645 if (mv88e6xxx_set_egress_port(chip, direction, 6646 dsa_upstream_port(ds, port))) 6647 dev_err(ds->dev, "failed to set egress port\n"); 6648 } 6649 6650 mutex_unlock(&chip->reg_lock); 6651 } 6652 6653 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6654 struct switchdev_brport_flags flags, 6655 struct netlink_ext_ack *extack) 6656 { 6657 struct mv88e6xxx_chip *chip = ds->priv; 6658 const struct mv88e6xxx_ops *ops; 6659 6660 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6661 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6662 return -EINVAL; 6663 6664 ops = chip->info->ops; 6665 6666 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6667 return -EINVAL; 6668 6669 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6670 return -EINVAL; 6671 6672 return 0; 6673 } 6674 6675 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6676 struct switchdev_brport_flags flags, 6677 struct netlink_ext_ack *extack) 6678 { 6679 struct mv88e6xxx_chip *chip = ds->priv; 6680 int err = 0; 6681 6682 mv88e6xxx_reg_lock(chip); 6683 6684 if (flags.mask & BR_LEARNING) { 6685 bool learning = !!(flags.val & BR_LEARNING); 6686 u16 pav = learning ? (1 << port) : 0; 6687 6688 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6689 if (err) 6690 goto out; 6691 } 6692 6693 if (flags.mask & BR_FLOOD) { 6694 bool unicast = !!(flags.val & BR_FLOOD); 6695 6696 err = chip->info->ops->port_set_ucast_flood(chip, port, 6697 unicast); 6698 if (err) 6699 goto out; 6700 } 6701 6702 if (flags.mask & BR_MCAST_FLOOD) { 6703 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6704 6705 err = chip->info->ops->port_set_mcast_flood(chip, port, 6706 multicast); 6707 if (err) 6708 goto out; 6709 } 6710 6711 if (flags.mask & BR_BCAST_FLOOD) { 6712 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6713 6714 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6715 if (err) 6716 goto out; 6717 } 6718 6719 if (flags.mask & BR_PORT_MAB) { 6720 bool mab = !!(flags.val & BR_PORT_MAB); 6721 6722 mv88e6xxx_port_set_mab(chip, port, mab); 6723 } 6724 6725 if (flags.mask & BR_PORT_LOCKED) { 6726 bool locked = !!(flags.val & BR_PORT_LOCKED); 6727 6728 err = mv88e6xxx_port_set_lock(chip, port, locked); 6729 if (err) 6730 goto out; 6731 } 6732 out: 6733 mv88e6xxx_reg_unlock(chip); 6734 6735 return err; 6736 } 6737 6738 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6739 struct dsa_lag lag, 6740 struct netdev_lag_upper_info *info, 6741 struct netlink_ext_ack *extack) 6742 { 6743 struct mv88e6xxx_chip *chip = ds->priv; 6744 struct dsa_port *dp; 6745 int members = 0; 6746 6747 if (!mv88e6xxx_has_lag(chip)) { 6748 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6749 return false; 6750 } 6751 6752 if (!lag.id) 6753 return false; 6754 6755 dsa_lag_foreach_port(dp, ds->dst, &lag) 6756 /* Includes the port joining the LAG */ 6757 members++; 6758 6759 if (members > 8) { 6760 NL_SET_ERR_MSG_MOD(extack, 6761 "Cannot offload more than 8 LAG ports"); 6762 return false; 6763 } 6764 6765 /* We could potentially relax this to include active 6766 * backup in the future. 6767 */ 6768 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6769 NL_SET_ERR_MSG_MOD(extack, 6770 "Can only offload LAG using hash TX type"); 6771 return false; 6772 } 6773 6774 /* Ideally we would also validate that the hash type matches 6775 * the hardware. Alas, this is always set to unknown on team 6776 * interfaces. 6777 */ 6778 return true; 6779 } 6780 6781 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6782 { 6783 struct mv88e6xxx_chip *chip = ds->priv; 6784 struct dsa_port *dp; 6785 u16 map = 0; 6786 int id; 6787 6788 /* DSA LAG IDs are one-based, hardware is zero-based */ 6789 id = lag.id - 1; 6790 6791 /* Build the map of all ports to distribute flows destined for 6792 * this LAG. This can be either a local user port, or a DSA 6793 * port if the LAG port is on a remote chip. 6794 */ 6795 dsa_lag_foreach_port(dp, ds->dst, &lag) 6796 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6797 6798 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6799 } 6800 6801 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6802 /* Row number corresponds to the number of active members in a 6803 * LAG. Each column states which of the eight hash buckets are 6804 * mapped to the column:th port in the LAG. 6805 * 6806 * Example: In a LAG with three active ports, the second port 6807 * ([2][1]) would be selected for traffic mapped to buckets 6808 * 3,4,5 (0x38). 6809 */ 6810 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6811 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6812 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6813 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6814 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6815 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6816 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6817 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6818 }; 6819 6820 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6821 int num_tx, int nth) 6822 { 6823 u8 active = 0; 6824 int i; 6825 6826 num_tx = num_tx <= 8 ? num_tx : 8; 6827 if (nth < num_tx) 6828 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6829 6830 for (i = 0; i < 8; i++) { 6831 if (BIT(i) & active) 6832 mask[i] |= BIT(port); 6833 } 6834 } 6835 6836 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6837 { 6838 struct mv88e6xxx_chip *chip = ds->priv; 6839 unsigned int id, num_tx; 6840 struct dsa_port *dp; 6841 struct dsa_lag *lag; 6842 int i, err, nth; 6843 u16 mask[8]; 6844 u16 ivec; 6845 6846 /* Assume no port is a member of any LAG. */ 6847 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6848 6849 /* Disable all masks for ports that _are_ members of a LAG. */ 6850 dsa_switch_for_each_port(dp, ds) { 6851 if (!dp->lag) 6852 continue; 6853 6854 ivec &= ~BIT(dp->index); 6855 } 6856 6857 for (i = 0; i < 8; i++) 6858 mask[i] = ivec; 6859 6860 /* Enable the correct subset of masks for all LAG ports that 6861 * are in the Tx set. 6862 */ 6863 dsa_lags_foreach_id(id, ds->dst) { 6864 lag = dsa_lag_by_id(ds->dst, id); 6865 if (!lag) 6866 continue; 6867 6868 num_tx = 0; 6869 dsa_lag_foreach_port(dp, ds->dst, lag) { 6870 if (dp->lag_tx_enabled) 6871 num_tx++; 6872 } 6873 6874 if (!num_tx) 6875 continue; 6876 6877 nth = 0; 6878 dsa_lag_foreach_port(dp, ds->dst, lag) { 6879 if (!dp->lag_tx_enabled) 6880 continue; 6881 6882 if (dp->ds == ds) 6883 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6884 num_tx, nth); 6885 6886 nth++; 6887 } 6888 } 6889 6890 for (i = 0; i < 8; i++) { 6891 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6892 if (err) 6893 return err; 6894 } 6895 6896 return 0; 6897 } 6898 6899 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6900 struct dsa_lag lag) 6901 { 6902 int err; 6903 6904 err = mv88e6xxx_lag_sync_masks(ds); 6905 6906 if (!err) 6907 err = mv88e6xxx_lag_sync_map(ds, lag); 6908 6909 return err; 6910 } 6911 6912 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6913 { 6914 struct mv88e6xxx_chip *chip = ds->priv; 6915 int err; 6916 6917 mv88e6xxx_reg_lock(chip); 6918 err = mv88e6xxx_lag_sync_masks(ds); 6919 mv88e6xxx_reg_unlock(chip); 6920 return err; 6921 } 6922 6923 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6924 struct dsa_lag lag, 6925 struct netdev_lag_upper_info *info, 6926 struct netlink_ext_ack *extack) 6927 { 6928 struct mv88e6xxx_chip *chip = ds->priv; 6929 int err, id; 6930 6931 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6932 return -EOPNOTSUPP; 6933 6934 /* DSA LAG IDs are one-based */ 6935 id = lag.id - 1; 6936 6937 mv88e6xxx_reg_lock(chip); 6938 6939 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6940 if (err) 6941 goto err_unlock; 6942 6943 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6944 if (err) 6945 goto err_clear_trunk; 6946 6947 mv88e6xxx_reg_unlock(chip); 6948 return 0; 6949 6950 err_clear_trunk: 6951 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6952 err_unlock: 6953 mv88e6xxx_reg_unlock(chip); 6954 return err; 6955 } 6956 6957 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6958 struct dsa_lag lag) 6959 { 6960 struct mv88e6xxx_chip *chip = ds->priv; 6961 int err_sync, err_trunk; 6962 6963 mv88e6xxx_reg_lock(chip); 6964 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6965 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6966 mv88e6xxx_reg_unlock(chip); 6967 return err_sync ? : err_trunk; 6968 } 6969 6970 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6971 int port) 6972 { 6973 struct mv88e6xxx_chip *chip = ds->priv; 6974 int err; 6975 6976 mv88e6xxx_reg_lock(chip); 6977 err = mv88e6xxx_lag_sync_masks(ds); 6978 mv88e6xxx_reg_unlock(chip); 6979 return err; 6980 } 6981 6982 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6983 int port, struct dsa_lag lag, 6984 struct netdev_lag_upper_info *info, 6985 struct netlink_ext_ack *extack) 6986 { 6987 struct mv88e6xxx_chip *chip = ds->priv; 6988 int err; 6989 6990 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6991 return -EOPNOTSUPP; 6992 6993 mv88e6xxx_reg_lock(chip); 6994 6995 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6996 if (err) 6997 goto unlock; 6998 6999 err = mv88e6xxx_pvt_map(chip, sw_index, port); 7000 7001 unlock: 7002 mv88e6xxx_reg_unlock(chip); 7003 return err; 7004 } 7005 7006 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 7007 int port, struct dsa_lag lag) 7008 { 7009 struct mv88e6xxx_chip *chip = ds->priv; 7010 int err_sync, err_pvt; 7011 7012 mv88e6xxx_reg_lock(chip); 7013 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7014 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 7015 mv88e6xxx_reg_unlock(chip); 7016 return err_sync ? : err_pvt; 7017 } 7018 7019 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 7020 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 7021 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 7022 .setup = mv88e6xxx_setup, 7023 .teardown = mv88e6xxx_teardown, 7024 .port_setup = mv88e6xxx_port_setup, 7025 .port_teardown = mv88e6xxx_port_teardown, 7026 .phylink_get_caps = mv88e6xxx_get_caps, 7027 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 7028 .phylink_mac_prepare = mv88e6xxx_mac_prepare, 7029 .phylink_mac_config = mv88e6xxx_mac_config, 7030 .phylink_mac_finish = mv88e6xxx_mac_finish, 7031 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 7032 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 7033 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 7034 .get_strings = mv88e6xxx_get_strings, 7035 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 7036 .get_sset_count = mv88e6xxx_get_sset_count, 7037 .port_enable = mv88e6xxx_port_enable, 7038 .port_disable = mv88e6xxx_port_disable, 7039 .port_max_mtu = mv88e6xxx_get_max_mtu, 7040 .port_change_mtu = mv88e6xxx_change_mtu, 7041 .get_mac_eee = mv88e6xxx_get_mac_eee, 7042 .set_mac_eee = mv88e6xxx_set_mac_eee, 7043 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 7044 .get_eeprom = mv88e6xxx_get_eeprom, 7045 .set_eeprom = mv88e6xxx_set_eeprom, 7046 .get_regs_len = mv88e6xxx_get_regs_len, 7047 .get_regs = mv88e6xxx_get_regs, 7048 .get_rxnfc = mv88e6xxx_get_rxnfc, 7049 .set_rxnfc = mv88e6xxx_set_rxnfc, 7050 .set_ageing_time = mv88e6xxx_set_ageing_time, 7051 .port_bridge_join = mv88e6xxx_port_bridge_join, 7052 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 7053 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 7054 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 7055 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 7056 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 7057 .port_fast_age = mv88e6xxx_port_fast_age, 7058 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 7059 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 7060 .port_vlan_add = mv88e6xxx_port_vlan_add, 7061 .port_vlan_del = mv88e6xxx_port_vlan_del, 7062 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 7063 .port_fdb_add = mv88e6xxx_port_fdb_add, 7064 .port_fdb_del = mv88e6xxx_port_fdb_del, 7065 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 7066 .port_mdb_add = mv88e6xxx_port_mdb_add, 7067 .port_mdb_del = mv88e6xxx_port_mdb_del, 7068 .port_mirror_add = mv88e6xxx_port_mirror_add, 7069 .port_mirror_del = mv88e6xxx_port_mirror_del, 7070 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 7071 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 7072 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 7073 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 7074 .port_txtstamp = mv88e6xxx_port_txtstamp, 7075 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 7076 .get_ts_info = mv88e6xxx_get_ts_info, 7077 .devlink_param_get = mv88e6xxx_devlink_param_get, 7078 .devlink_param_set = mv88e6xxx_devlink_param_set, 7079 .devlink_info_get = mv88e6xxx_devlink_info_get, 7080 .port_lag_change = mv88e6xxx_port_lag_change, 7081 .port_lag_join = mv88e6xxx_port_lag_join, 7082 .port_lag_leave = mv88e6xxx_port_lag_leave, 7083 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 7084 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 7085 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 7086 }; 7087 7088 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 7089 { 7090 struct device *dev = chip->dev; 7091 struct dsa_switch *ds; 7092 7093 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 7094 if (!ds) 7095 return -ENOMEM; 7096 7097 ds->dev = dev; 7098 ds->num_ports = mv88e6xxx_num_ports(chip); 7099 ds->priv = chip; 7100 ds->dev = dev; 7101 ds->ops = &mv88e6xxx_switch_ops; 7102 ds->ageing_time_min = chip->info->age_time_coeff; 7103 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 7104 7105 /* Some chips support up to 32, but that requires enabling the 7106 * 5-bit port mode, which we do not support. 640k^W16 ought to 7107 * be enough for anyone. 7108 */ 7109 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 7110 7111 dev_set_drvdata(dev, ds); 7112 7113 return dsa_register_switch(ds); 7114 } 7115 7116 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 7117 { 7118 dsa_unregister_switch(chip->ds); 7119 } 7120 7121 static const void *pdata_device_get_match_data(struct device *dev) 7122 { 7123 const struct of_device_id *matches = dev->driver->of_match_table; 7124 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 7125 7126 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 7127 matches++) { 7128 if (!strcmp(pdata->compatible, matches->compatible)) 7129 return matches->data; 7130 } 7131 return NULL; 7132 } 7133 7134 /* There is no suspend to RAM support at DSA level yet, the switch configuration 7135 * would be lost after a power cycle so prevent it to be suspended. 7136 */ 7137 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 7138 { 7139 return -EOPNOTSUPP; 7140 } 7141 7142 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7143 { 7144 return 0; 7145 } 7146 7147 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7148 7149 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7150 { 7151 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7152 const struct mv88e6xxx_info *compat_info = NULL; 7153 struct device *dev = &mdiodev->dev; 7154 struct device_node *np = dev->of_node; 7155 struct mv88e6xxx_chip *chip; 7156 int port; 7157 int err; 7158 7159 if (!np && !pdata) 7160 return -EINVAL; 7161 7162 if (np) 7163 compat_info = of_device_get_match_data(dev); 7164 7165 if (pdata) { 7166 compat_info = pdata_device_get_match_data(dev); 7167 7168 if (!pdata->netdev) 7169 return -EINVAL; 7170 7171 for (port = 0; port < DSA_MAX_PORTS; port++) { 7172 if (!(pdata->enabled_ports & (1 << port))) 7173 continue; 7174 if (strcmp(pdata->cd.port_names[port], "cpu")) 7175 continue; 7176 pdata->cd.netdev[port] = &pdata->netdev->dev; 7177 break; 7178 } 7179 } 7180 7181 if (!compat_info) 7182 return -EINVAL; 7183 7184 chip = mv88e6xxx_alloc_chip(dev); 7185 if (!chip) { 7186 err = -ENOMEM; 7187 goto out; 7188 } 7189 7190 chip->info = compat_info; 7191 7192 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7193 if (IS_ERR(chip->reset)) { 7194 err = PTR_ERR(chip->reset); 7195 goto out; 7196 } 7197 if (chip->reset) 7198 usleep_range(1000, 2000); 7199 7200 /* Detect if the device is configured in single chip addressing mode, 7201 * otherwise continue with address specific smi init/detection. 7202 */ 7203 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7204 if (err) { 7205 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7206 if (err) 7207 goto out; 7208 7209 err = mv88e6xxx_detect(chip); 7210 if (err) 7211 goto out; 7212 } 7213 7214 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7215 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7216 else 7217 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7218 7219 mv88e6xxx_phy_init(chip); 7220 7221 if (chip->info->ops->get_eeprom) { 7222 if (np) 7223 of_property_read_u32(np, "eeprom-length", 7224 &chip->eeprom_len); 7225 else 7226 chip->eeprom_len = pdata->eeprom_len; 7227 } 7228 7229 mv88e6xxx_reg_lock(chip); 7230 err = mv88e6xxx_switch_reset(chip); 7231 mv88e6xxx_reg_unlock(chip); 7232 if (err) 7233 goto out; 7234 7235 if (np) { 7236 chip->irq = of_irq_get(np, 0); 7237 if (chip->irq == -EPROBE_DEFER) { 7238 err = chip->irq; 7239 goto out; 7240 } 7241 } 7242 7243 if (pdata) 7244 chip->irq = pdata->irq; 7245 7246 /* Has to be performed before the MDIO bus is created, because 7247 * the PHYs will link their interrupts to these interrupt 7248 * controllers 7249 */ 7250 mv88e6xxx_reg_lock(chip); 7251 if (chip->irq > 0) 7252 err = mv88e6xxx_g1_irq_setup(chip); 7253 else 7254 err = mv88e6xxx_irq_poll_setup(chip); 7255 mv88e6xxx_reg_unlock(chip); 7256 7257 if (err) 7258 goto out; 7259 7260 if (chip->info->g2_irqs > 0) { 7261 err = mv88e6xxx_g2_irq_setup(chip); 7262 if (err) 7263 goto out_g1_irq; 7264 } 7265 7266 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7267 if (err) 7268 goto out_g2_irq; 7269 7270 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7271 if (err) 7272 goto out_g1_atu_prob_irq; 7273 7274 err = mv88e6xxx_register_switch(chip); 7275 if (err) 7276 goto out_g1_vtu_prob_irq; 7277 7278 return 0; 7279 7280 out_g1_vtu_prob_irq: 7281 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7282 out_g1_atu_prob_irq: 7283 mv88e6xxx_g1_atu_prob_irq_free(chip); 7284 out_g2_irq: 7285 if (chip->info->g2_irqs > 0) 7286 mv88e6xxx_g2_irq_free(chip); 7287 out_g1_irq: 7288 if (chip->irq > 0) 7289 mv88e6xxx_g1_irq_free(chip); 7290 else 7291 mv88e6xxx_irq_poll_free(chip); 7292 out: 7293 if (pdata) 7294 dev_put(pdata->netdev); 7295 7296 return err; 7297 } 7298 7299 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7300 { 7301 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7302 struct mv88e6xxx_chip *chip; 7303 7304 if (!ds) 7305 return; 7306 7307 chip = ds->priv; 7308 7309 if (chip->info->ptp_support) { 7310 mv88e6xxx_hwtstamp_free(chip); 7311 mv88e6xxx_ptp_free(chip); 7312 } 7313 7314 mv88e6xxx_phy_destroy(chip); 7315 mv88e6xxx_unregister_switch(chip); 7316 7317 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7318 mv88e6xxx_g1_atu_prob_irq_free(chip); 7319 7320 if (chip->info->g2_irqs > 0) 7321 mv88e6xxx_g2_irq_free(chip); 7322 7323 if (chip->irq > 0) 7324 mv88e6xxx_g1_irq_free(chip); 7325 else 7326 mv88e6xxx_irq_poll_free(chip); 7327 } 7328 7329 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7330 { 7331 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7332 7333 if (!ds) 7334 return; 7335 7336 dsa_switch_shutdown(ds); 7337 7338 dev_set_drvdata(&mdiodev->dev, NULL); 7339 } 7340 7341 static const struct of_device_id mv88e6xxx_of_match[] = { 7342 { 7343 .compatible = "marvell,mv88e6085", 7344 .data = &mv88e6xxx_table[MV88E6085], 7345 }, 7346 { 7347 .compatible = "marvell,mv88e6190", 7348 .data = &mv88e6xxx_table[MV88E6190], 7349 }, 7350 { 7351 .compatible = "marvell,mv88e6250", 7352 .data = &mv88e6xxx_table[MV88E6250], 7353 }, 7354 { /* sentinel */ }, 7355 }; 7356 7357 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7358 7359 static struct mdio_driver mv88e6xxx_driver = { 7360 .probe = mv88e6xxx_probe, 7361 .remove = mv88e6xxx_remove, 7362 .shutdown = mv88e6xxx_shutdown, 7363 .mdiodrv.driver = { 7364 .name = "mv88e6085", 7365 .of_match_table = mv88e6xxx_of_match, 7366 .pm = &mv88e6xxx_pm_ops, 7367 }, 7368 }; 7369 7370 mdio_module_driver(mv88e6xxx_driver); 7371 7372 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7373 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7374 MODULE_LICENSE("GPL"); 7375