1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 7 * 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/platform_data/mv88e6xxx.h> 32 #include <linux/netdevice.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/phy.h> 35 #include <linux/phylink.h> 36 #include <net/dsa.h> 37 38 #include "chip.h" 39 #include "global1.h" 40 #include "global2.h" 41 #include "hwtstamp.h" 42 #include "phy.h" 43 #include "port.h" 44 #include "ptp.h" 45 #include "serdes.h" 46 47 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 48 { 49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 50 dev_err(chip->dev, "Switch registers lock not held!\n"); 51 dump_stack(); 52 } 53 } 54 55 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 56 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 57 * 58 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 59 * is the only device connected to the SMI master. In this mode it responds to 60 * all 32 possible SMI addresses, and thus maps directly the internal devices. 61 * 62 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 63 * multiple devices to share the SMI interface. In this mode it responds to only 64 * 2 registers, used to indirectly access the internal SMI devices. 65 */ 66 67 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 68 int addr, int reg, u16 *val) 69 { 70 if (!chip->smi_ops) 71 return -EOPNOTSUPP; 72 73 return chip->smi_ops->read(chip, addr, reg, val); 74 } 75 76 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 77 int addr, int reg, u16 val) 78 { 79 if (!chip->smi_ops) 80 return -EOPNOTSUPP; 81 82 return chip->smi_ops->write(chip, addr, reg, val); 83 } 84 85 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 86 int addr, int reg, u16 *val) 87 { 88 int ret; 89 90 ret = mdiobus_read_nested(chip->bus, addr, reg); 91 if (ret < 0) 92 return ret; 93 94 *val = ret & 0xffff; 95 96 return 0; 97 } 98 99 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 100 int addr, int reg, u16 val) 101 { 102 int ret; 103 104 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 105 if (ret < 0) 106 return ret; 107 108 return 0; 109 } 110 111 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 112 .read = mv88e6xxx_smi_single_chip_read, 113 .write = mv88e6xxx_smi_single_chip_write, 114 }; 115 116 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 117 { 118 int ret; 119 int i; 120 121 for (i = 0; i < 16; i++) { 122 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 123 if (ret < 0) 124 return ret; 125 126 if ((ret & SMI_CMD_BUSY) == 0) 127 return 0; 128 } 129 130 return -ETIMEDOUT; 131 } 132 133 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 134 int addr, int reg, u16 *val) 135 { 136 int ret; 137 138 /* Wait for the bus to become free. */ 139 ret = mv88e6xxx_smi_multi_chip_wait(chip); 140 if (ret < 0) 141 return ret; 142 143 /* Transmit the read command. */ 144 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 145 SMI_CMD_OP_22_READ | (addr << 5) | reg); 146 if (ret < 0) 147 return ret; 148 149 /* Wait for the read command to complete. */ 150 ret = mv88e6xxx_smi_multi_chip_wait(chip); 151 if (ret < 0) 152 return ret; 153 154 /* Read the data. */ 155 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 156 if (ret < 0) 157 return ret; 158 159 *val = ret & 0xffff; 160 161 return 0; 162 } 163 164 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 165 int addr, int reg, u16 val) 166 { 167 int ret; 168 169 /* Wait for the bus to become free. */ 170 ret = mv88e6xxx_smi_multi_chip_wait(chip); 171 if (ret < 0) 172 return ret; 173 174 /* Transmit the data to write. */ 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 176 if (ret < 0) 177 return ret; 178 179 /* Transmit the write command. */ 180 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 181 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 182 if (ret < 0) 183 return ret; 184 185 /* Wait for the write command to complete. */ 186 ret = mv88e6xxx_smi_multi_chip_wait(chip); 187 if (ret < 0) 188 return ret; 189 190 return 0; 191 } 192 193 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 194 .read = mv88e6xxx_smi_multi_chip_read, 195 .write = mv88e6xxx_smi_multi_chip_write, 196 }; 197 198 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 199 { 200 int err; 201 202 assert_reg_lock(chip); 203 204 err = mv88e6xxx_smi_read(chip, addr, reg, val); 205 if (err) 206 return err; 207 208 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 209 addr, reg, *val); 210 211 return 0; 212 } 213 214 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 215 { 216 int err; 217 218 assert_reg_lock(chip); 219 220 err = mv88e6xxx_smi_write(chip, addr, reg, val); 221 if (err) 222 return err; 223 224 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 225 addr, reg, val); 226 227 return 0; 228 } 229 230 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 231 { 232 struct mv88e6xxx_mdio_bus *mdio_bus; 233 234 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 235 list); 236 if (!mdio_bus) 237 return NULL; 238 239 return mdio_bus->bus; 240 } 241 242 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 243 { 244 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 245 unsigned int n = d->hwirq; 246 247 chip->g1_irq.masked |= (1 << n); 248 } 249 250 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 251 { 252 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 253 unsigned int n = d->hwirq; 254 255 chip->g1_irq.masked &= ~(1 << n); 256 } 257 258 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 259 { 260 unsigned int nhandled = 0; 261 unsigned int sub_irq; 262 unsigned int n; 263 u16 reg; 264 int err; 265 266 mutex_lock(&chip->reg_lock); 267 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 268 mutex_unlock(&chip->reg_lock); 269 270 if (err) 271 goto out; 272 273 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 274 if (reg & (1 << n)) { 275 sub_irq = irq_find_mapping(chip->g1_irq.domain, n); 276 handle_nested_irq(sub_irq); 277 ++nhandled; 278 } 279 } 280 out: 281 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 282 } 283 284 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 285 { 286 struct mv88e6xxx_chip *chip = dev_id; 287 288 return mv88e6xxx_g1_irq_thread_work(chip); 289 } 290 291 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 292 { 293 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 294 295 mutex_lock(&chip->reg_lock); 296 } 297 298 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 299 { 300 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 301 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 302 u16 reg; 303 int err; 304 305 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 306 if (err) 307 goto out; 308 309 reg &= ~mask; 310 reg |= (~chip->g1_irq.masked & mask); 311 312 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 313 if (err) 314 goto out; 315 316 out: 317 mutex_unlock(&chip->reg_lock); 318 } 319 320 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 321 .name = "mv88e6xxx-g1", 322 .irq_mask = mv88e6xxx_g1_irq_mask, 323 .irq_unmask = mv88e6xxx_g1_irq_unmask, 324 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 325 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 326 }; 327 328 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 329 unsigned int irq, 330 irq_hw_number_t hwirq) 331 { 332 struct mv88e6xxx_chip *chip = d->host_data; 333 334 irq_set_chip_data(irq, d->host_data); 335 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 336 irq_set_noprobe(irq); 337 338 return 0; 339 } 340 341 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 342 .map = mv88e6xxx_g1_irq_domain_map, 343 .xlate = irq_domain_xlate_twocell, 344 }; 345 346 /* To be called with reg_lock held */ 347 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 348 { 349 int irq, virq; 350 u16 mask; 351 352 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 353 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 354 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 355 356 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 357 virq = irq_find_mapping(chip->g1_irq.domain, irq); 358 irq_dispose_mapping(virq); 359 } 360 361 irq_domain_remove(chip->g1_irq.domain); 362 } 363 364 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 365 { 366 /* 367 * free_irq must be called without reg_lock taken because the irq 368 * handler takes this lock, too. 369 */ 370 free_irq(chip->irq, chip); 371 372 mutex_lock(&chip->reg_lock); 373 mv88e6xxx_g1_irq_free_common(chip); 374 mutex_unlock(&chip->reg_lock); 375 } 376 377 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 378 { 379 int err, irq, virq; 380 u16 reg, mask; 381 382 chip->g1_irq.nirqs = chip->info->g1_irqs; 383 chip->g1_irq.domain = irq_domain_add_simple( 384 NULL, chip->g1_irq.nirqs, 0, 385 &mv88e6xxx_g1_irq_domain_ops, chip); 386 if (!chip->g1_irq.domain) 387 return -ENOMEM; 388 389 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 390 irq_create_mapping(chip->g1_irq.domain, irq); 391 392 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 393 chip->g1_irq.masked = ~0; 394 395 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 396 if (err) 397 goto out_mapping; 398 399 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 400 401 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 402 if (err) 403 goto out_disable; 404 405 /* Reading the interrupt status clears (most of) them */ 406 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 407 if (err) 408 goto out_disable; 409 410 return 0; 411 412 out_disable: 413 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 414 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 415 416 out_mapping: 417 for (irq = 0; irq < 16; irq++) { 418 virq = irq_find_mapping(chip->g1_irq.domain, irq); 419 irq_dispose_mapping(virq); 420 } 421 422 irq_domain_remove(chip->g1_irq.domain); 423 424 return err; 425 } 426 427 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 428 { 429 int err; 430 431 err = mv88e6xxx_g1_irq_setup_common(chip); 432 if (err) 433 return err; 434 435 err = request_threaded_irq(chip->irq, NULL, 436 mv88e6xxx_g1_irq_thread_fn, 437 IRQF_ONESHOT, 438 dev_name(chip->dev), chip); 439 if (err) 440 mv88e6xxx_g1_irq_free_common(chip); 441 442 return err; 443 } 444 445 static void mv88e6xxx_irq_poll(struct kthread_work *work) 446 { 447 struct mv88e6xxx_chip *chip = container_of(work, 448 struct mv88e6xxx_chip, 449 irq_poll_work.work); 450 mv88e6xxx_g1_irq_thread_work(chip); 451 452 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 453 msecs_to_jiffies(100)); 454 } 455 456 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 457 { 458 int err; 459 460 err = mv88e6xxx_g1_irq_setup_common(chip); 461 if (err) 462 return err; 463 464 kthread_init_delayed_work(&chip->irq_poll_work, 465 mv88e6xxx_irq_poll); 466 467 chip->kworker = kthread_create_worker(0, dev_name(chip->dev)); 468 if (IS_ERR(chip->kworker)) 469 return PTR_ERR(chip->kworker); 470 471 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 472 msecs_to_jiffies(100)); 473 474 return 0; 475 } 476 477 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 478 { 479 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 480 kthread_destroy_worker(chip->kworker); 481 482 mutex_lock(&chip->reg_lock); 483 mv88e6xxx_g1_irq_free_common(chip); 484 mutex_unlock(&chip->reg_lock); 485 } 486 487 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 488 { 489 int i; 490 491 for (i = 0; i < 16; i++) { 492 u16 val; 493 int err; 494 495 err = mv88e6xxx_read(chip, addr, reg, &val); 496 if (err) 497 return err; 498 499 if (!(val & mask)) 500 return 0; 501 502 usleep_range(1000, 2000); 503 } 504 505 dev_err(chip->dev, "Timeout while waiting for switch\n"); 506 return -ETIMEDOUT; 507 } 508 509 /* Indirect write to single pointer-data register with an Update bit */ 510 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 511 { 512 u16 val; 513 int err; 514 515 /* Wait until the previous operation is completed */ 516 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 517 if (err) 518 return err; 519 520 /* Set the Update bit to trigger a write operation */ 521 val = BIT(15) | update; 522 523 return mv88e6xxx_write(chip, addr, reg, val); 524 } 525 526 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 527 int link, int speed, int duplex, int pause, 528 phy_interface_t mode) 529 { 530 int err; 531 532 if (!chip->info->ops->port_set_link) 533 return 0; 534 535 /* Port's MAC control must not be changed unless the link is down */ 536 err = chip->info->ops->port_set_link(chip, port, 0); 537 if (err) 538 return err; 539 540 if (chip->info->ops->port_set_speed) { 541 err = chip->info->ops->port_set_speed(chip, port, speed); 542 if (err && err != -EOPNOTSUPP) 543 goto restore_link; 544 } 545 546 if (chip->info->ops->port_set_pause) { 547 err = chip->info->ops->port_set_pause(chip, port, pause); 548 if (err) 549 goto restore_link; 550 } 551 552 if (chip->info->ops->port_set_duplex) { 553 err = chip->info->ops->port_set_duplex(chip, port, duplex); 554 if (err && err != -EOPNOTSUPP) 555 goto restore_link; 556 } 557 558 if (chip->info->ops->port_set_rgmii_delay) { 559 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 560 if (err && err != -EOPNOTSUPP) 561 goto restore_link; 562 } 563 564 if (chip->info->ops->port_set_cmode) { 565 err = chip->info->ops->port_set_cmode(chip, port, mode); 566 if (err && err != -EOPNOTSUPP) 567 goto restore_link; 568 } 569 570 err = 0; 571 restore_link: 572 if (chip->info->ops->port_set_link(chip, port, link)) 573 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 574 575 return err; 576 } 577 578 /* We expect the switch to perform auto negotiation if there is a real 579 * phy. However, in the case of a fixed link phy, we force the port 580 * settings from the fixed link settings. 581 */ 582 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 583 struct phy_device *phydev) 584 { 585 struct mv88e6xxx_chip *chip = ds->priv; 586 int err; 587 588 if (!phy_is_pseudo_fixed_link(phydev)) 589 return; 590 591 mutex_lock(&chip->reg_lock); 592 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 593 phydev->duplex, phydev->pause, 594 phydev->interface); 595 mutex_unlock(&chip->reg_lock); 596 597 if (err && err != -EOPNOTSUPP) 598 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 599 } 600 601 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 602 unsigned long *mask, 603 struct phylink_link_state *state) 604 { 605 if (!phy_interface_mode_is_8023z(state->interface)) { 606 /* 10M and 100M are only supported in non-802.3z mode */ 607 phylink_set(mask, 10baseT_Half); 608 phylink_set(mask, 10baseT_Full); 609 phylink_set(mask, 100baseT_Half); 610 phylink_set(mask, 100baseT_Full); 611 } 612 } 613 614 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 615 unsigned long *mask, 616 struct phylink_link_state *state) 617 { 618 /* FIXME: if the port is in 1000Base-X mode, then it only supports 619 * 1000M FD speeds. In this case, CMODE will indicate 5. 620 */ 621 phylink_set(mask, 1000baseT_Full); 622 phylink_set(mask, 1000baseX_Full); 623 624 mv88e6065_phylink_validate(chip, port, mask, state); 625 } 626 627 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 628 unsigned long *mask, 629 struct phylink_link_state *state) 630 { 631 /* No ethtool bits for 200Mbps */ 632 phylink_set(mask, 1000baseT_Full); 633 phylink_set(mask, 1000baseX_Full); 634 635 mv88e6065_phylink_validate(chip, port, mask, state); 636 } 637 638 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 639 unsigned long *mask, 640 struct phylink_link_state *state) 641 { 642 if (port >= 9) 643 phylink_set(mask, 2500baseX_Full); 644 645 /* No ethtool bits for 200Mbps */ 646 phylink_set(mask, 1000baseT_Full); 647 phylink_set(mask, 1000baseX_Full); 648 649 mv88e6065_phylink_validate(chip, port, mask, state); 650 } 651 652 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 653 unsigned long *mask, 654 struct phylink_link_state *state) 655 { 656 if (port >= 9) { 657 phylink_set(mask, 10000baseT_Full); 658 phylink_set(mask, 10000baseKR_Full); 659 } 660 661 mv88e6390_phylink_validate(chip, port, mask, state); 662 } 663 664 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 665 unsigned long *supported, 666 struct phylink_link_state *state) 667 { 668 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 669 struct mv88e6xxx_chip *chip = ds->priv; 670 671 /* Allow all the expected bits */ 672 phylink_set(mask, Autoneg); 673 phylink_set(mask, Pause); 674 phylink_set_port_modes(mask); 675 676 if (chip->info->ops->phylink_validate) 677 chip->info->ops->phylink_validate(chip, port, mask, state); 678 679 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 680 bitmap_and(state->advertising, state->advertising, mask, 681 __ETHTOOL_LINK_MODE_MASK_NBITS); 682 683 /* We can only operate at 2500BaseX or 1000BaseX. If requested 684 * to advertise both, only report advertising at 2500BaseX. 685 */ 686 phylink_helper_basex_speed(state); 687 } 688 689 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port, 690 struct phylink_link_state *state) 691 { 692 struct mv88e6xxx_chip *chip = ds->priv; 693 int err; 694 695 mutex_lock(&chip->reg_lock); 696 if (chip->info->ops->port_link_state) 697 err = chip->info->ops->port_link_state(chip, port, state); 698 else 699 err = -EOPNOTSUPP; 700 mutex_unlock(&chip->reg_lock); 701 702 return err; 703 } 704 705 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 706 unsigned int mode, 707 const struct phylink_link_state *state) 708 { 709 struct mv88e6xxx_chip *chip = ds->priv; 710 int speed, duplex, link, pause, err; 711 712 if (mode == MLO_AN_PHY) 713 return; 714 715 if (mode == MLO_AN_FIXED) { 716 link = LINK_FORCED_UP; 717 speed = state->speed; 718 duplex = state->duplex; 719 } else { 720 speed = SPEED_UNFORCED; 721 duplex = DUPLEX_UNFORCED; 722 link = LINK_UNFORCED; 723 } 724 pause = !!phylink_test(state->advertising, Pause); 725 726 mutex_lock(&chip->reg_lock); 727 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause, 728 state->interface); 729 mutex_unlock(&chip->reg_lock); 730 731 if (err && err != -EOPNOTSUPP) 732 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 733 } 734 735 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link) 736 { 737 struct mv88e6xxx_chip *chip = ds->priv; 738 int err; 739 740 mutex_lock(&chip->reg_lock); 741 err = chip->info->ops->port_set_link(chip, port, link); 742 mutex_unlock(&chip->reg_lock); 743 744 if (err) 745 dev_err(chip->dev, "p%d: failed to force MAC link\n", port); 746 } 747 748 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 749 unsigned int mode, 750 phy_interface_t interface) 751 { 752 if (mode == MLO_AN_FIXED) 753 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN); 754 } 755 756 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 757 unsigned int mode, phy_interface_t interface, 758 struct phy_device *phydev) 759 { 760 if (mode == MLO_AN_FIXED) 761 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP); 762 } 763 764 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 765 { 766 if (!chip->info->ops->stats_snapshot) 767 return -EOPNOTSUPP; 768 769 return chip->info->ops->stats_snapshot(chip, port); 770 } 771 772 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 773 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 774 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 775 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 776 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 777 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 778 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 779 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 780 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 781 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 782 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 783 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 784 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 785 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 786 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 787 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 788 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 789 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 790 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 791 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 792 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 793 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 794 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 795 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 796 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 797 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 798 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 799 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 800 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 801 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 802 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 803 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 804 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 805 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 806 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 807 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 808 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 809 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 810 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 811 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 812 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 813 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 814 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 815 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 816 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 817 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 818 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 819 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 820 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 821 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 822 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 823 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 824 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 825 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 826 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 827 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 828 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 829 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 830 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 831 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 832 }; 833 834 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 835 struct mv88e6xxx_hw_stat *s, 836 int port, u16 bank1_select, 837 u16 histogram) 838 { 839 u32 low; 840 u32 high = 0; 841 u16 reg = 0; 842 int err; 843 u64 value; 844 845 switch (s->type) { 846 case STATS_TYPE_PORT: 847 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 848 if (err) 849 return U64_MAX; 850 851 low = reg; 852 if (s->size == 4) { 853 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 854 if (err) 855 return U64_MAX; 856 high = reg; 857 } 858 break; 859 case STATS_TYPE_BANK1: 860 reg = bank1_select; 861 /* fall through */ 862 case STATS_TYPE_BANK0: 863 reg |= s->reg | histogram; 864 mv88e6xxx_g1_stats_read(chip, reg, &low); 865 if (s->size == 8) 866 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 867 break; 868 default: 869 return U64_MAX; 870 } 871 value = (((u64)high) << 16) | low; 872 return value; 873 } 874 875 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 876 uint8_t *data, int types) 877 { 878 struct mv88e6xxx_hw_stat *stat; 879 int i, j; 880 881 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 882 stat = &mv88e6xxx_hw_stats[i]; 883 if (stat->type & types) { 884 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 885 ETH_GSTRING_LEN); 886 j++; 887 } 888 } 889 890 return j; 891 } 892 893 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 894 uint8_t *data) 895 { 896 return mv88e6xxx_stats_get_strings(chip, data, 897 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 898 } 899 900 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 901 uint8_t *data) 902 { 903 return mv88e6xxx_stats_get_strings(chip, data, 904 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 905 } 906 907 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 908 "atu_member_violation", 909 "atu_miss_violation", 910 "atu_full_violation", 911 "vtu_member_violation", 912 "vtu_miss_violation", 913 }; 914 915 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 916 { 917 unsigned int i; 918 919 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 920 strlcpy(data + i * ETH_GSTRING_LEN, 921 mv88e6xxx_atu_vtu_stats_strings[i], 922 ETH_GSTRING_LEN); 923 } 924 925 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 926 u32 stringset, uint8_t *data) 927 { 928 struct mv88e6xxx_chip *chip = ds->priv; 929 int count = 0; 930 931 if (stringset != ETH_SS_STATS) 932 return; 933 934 mutex_lock(&chip->reg_lock); 935 936 if (chip->info->ops->stats_get_strings) 937 count = chip->info->ops->stats_get_strings(chip, data); 938 939 if (chip->info->ops->serdes_get_strings) { 940 data += count * ETH_GSTRING_LEN; 941 count = chip->info->ops->serdes_get_strings(chip, port, data); 942 } 943 944 data += count * ETH_GSTRING_LEN; 945 mv88e6xxx_atu_vtu_get_strings(data); 946 947 mutex_unlock(&chip->reg_lock); 948 } 949 950 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 951 int types) 952 { 953 struct mv88e6xxx_hw_stat *stat; 954 int i, j; 955 956 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 957 stat = &mv88e6xxx_hw_stats[i]; 958 if (stat->type & types) 959 j++; 960 } 961 return j; 962 } 963 964 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 965 { 966 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 967 STATS_TYPE_PORT); 968 } 969 970 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 971 { 972 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 973 STATS_TYPE_BANK1); 974 } 975 976 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 977 { 978 struct mv88e6xxx_chip *chip = ds->priv; 979 int serdes_count = 0; 980 int count = 0; 981 982 if (sset != ETH_SS_STATS) 983 return 0; 984 985 mutex_lock(&chip->reg_lock); 986 if (chip->info->ops->stats_get_sset_count) 987 count = chip->info->ops->stats_get_sset_count(chip); 988 if (count < 0) 989 goto out; 990 991 if (chip->info->ops->serdes_get_sset_count) 992 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 993 port); 994 if (serdes_count < 0) { 995 count = serdes_count; 996 goto out; 997 } 998 count += serdes_count; 999 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1000 1001 out: 1002 mutex_unlock(&chip->reg_lock); 1003 1004 return count; 1005 } 1006 1007 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1008 uint64_t *data, int types, 1009 u16 bank1_select, u16 histogram) 1010 { 1011 struct mv88e6xxx_hw_stat *stat; 1012 int i, j; 1013 1014 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1015 stat = &mv88e6xxx_hw_stats[i]; 1016 if (stat->type & types) { 1017 mutex_lock(&chip->reg_lock); 1018 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1019 bank1_select, 1020 histogram); 1021 mutex_unlock(&chip->reg_lock); 1022 1023 j++; 1024 } 1025 } 1026 return j; 1027 } 1028 1029 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1030 uint64_t *data) 1031 { 1032 return mv88e6xxx_stats_get_stats(chip, port, data, 1033 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1034 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1035 } 1036 1037 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1038 uint64_t *data) 1039 { 1040 return mv88e6xxx_stats_get_stats(chip, port, data, 1041 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1042 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1043 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1044 } 1045 1046 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1047 uint64_t *data) 1048 { 1049 return mv88e6xxx_stats_get_stats(chip, port, data, 1050 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1051 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1052 0); 1053 } 1054 1055 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1056 uint64_t *data) 1057 { 1058 *data++ = chip->ports[port].atu_member_violation; 1059 *data++ = chip->ports[port].atu_miss_violation; 1060 *data++ = chip->ports[port].atu_full_violation; 1061 *data++ = chip->ports[port].vtu_member_violation; 1062 *data++ = chip->ports[port].vtu_miss_violation; 1063 } 1064 1065 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1066 uint64_t *data) 1067 { 1068 int count = 0; 1069 1070 if (chip->info->ops->stats_get_stats) 1071 count = chip->info->ops->stats_get_stats(chip, port, data); 1072 1073 mutex_lock(&chip->reg_lock); 1074 if (chip->info->ops->serdes_get_stats) { 1075 data += count; 1076 count = chip->info->ops->serdes_get_stats(chip, port, data); 1077 } 1078 data += count; 1079 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1080 mutex_unlock(&chip->reg_lock); 1081 } 1082 1083 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1084 uint64_t *data) 1085 { 1086 struct mv88e6xxx_chip *chip = ds->priv; 1087 int ret; 1088 1089 mutex_lock(&chip->reg_lock); 1090 1091 ret = mv88e6xxx_stats_snapshot(chip, port); 1092 mutex_unlock(&chip->reg_lock); 1093 1094 if (ret < 0) 1095 return; 1096 1097 mv88e6xxx_get_stats(chip, port, data); 1098 1099 } 1100 1101 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1102 { 1103 return 32 * sizeof(u16); 1104 } 1105 1106 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1107 struct ethtool_regs *regs, void *_p) 1108 { 1109 struct mv88e6xxx_chip *chip = ds->priv; 1110 int err; 1111 u16 reg; 1112 u16 *p = _p; 1113 int i; 1114 1115 regs->version = 0; 1116 1117 memset(p, 0xff, 32 * sizeof(u16)); 1118 1119 mutex_lock(&chip->reg_lock); 1120 1121 for (i = 0; i < 32; i++) { 1122 1123 err = mv88e6xxx_port_read(chip, port, i, ®); 1124 if (!err) 1125 p[i] = reg; 1126 } 1127 1128 mutex_unlock(&chip->reg_lock); 1129 } 1130 1131 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1132 struct ethtool_eee *e) 1133 { 1134 /* Nothing to do on the port's MAC */ 1135 return 0; 1136 } 1137 1138 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1139 struct ethtool_eee *e) 1140 { 1141 /* Nothing to do on the port's MAC */ 1142 return 0; 1143 } 1144 1145 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1146 { 1147 struct dsa_switch *ds = NULL; 1148 struct net_device *br; 1149 u16 pvlan; 1150 int i; 1151 1152 if (dev < DSA_MAX_SWITCHES) 1153 ds = chip->ds->dst->ds[dev]; 1154 1155 /* Prevent frames from unknown switch or port */ 1156 if (!ds || port >= ds->num_ports) 1157 return 0; 1158 1159 /* Frames from DSA links and CPU ports can egress any local port */ 1160 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1161 return mv88e6xxx_port_mask(chip); 1162 1163 br = ds->ports[port].bridge_dev; 1164 pvlan = 0; 1165 1166 /* Frames from user ports can egress any local DSA links and CPU ports, 1167 * as well as any local member of their bridge group. 1168 */ 1169 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1170 if (dsa_is_cpu_port(chip->ds, i) || 1171 dsa_is_dsa_port(chip->ds, i) || 1172 (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) 1173 pvlan |= BIT(i); 1174 1175 return pvlan; 1176 } 1177 1178 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1179 { 1180 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1181 1182 /* prevent frames from going back out of the port they came in on */ 1183 output_ports &= ~BIT(port); 1184 1185 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1186 } 1187 1188 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1189 u8 state) 1190 { 1191 struct mv88e6xxx_chip *chip = ds->priv; 1192 int err; 1193 1194 mutex_lock(&chip->reg_lock); 1195 err = mv88e6xxx_port_set_state(chip, port, state); 1196 mutex_unlock(&chip->reg_lock); 1197 1198 if (err) 1199 dev_err(ds->dev, "p%d: failed to update state\n", port); 1200 } 1201 1202 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1203 { 1204 int err; 1205 1206 if (chip->info->ops->ieee_pri_map) { 1207 err = chip->info->ops->ieee_pri_map(chip); 1208 if (err) 1209 return err; 1210 } 1211 1212 if (chip->info->ops->ip_pri_map) { 1213 err = chip->info->ops->ip_pri_map(chip); 1214 if (err) 1215 return err; 1216 } 1217 1218 return 0; 1219 } 1220 1221 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1222 { 1223 int target, port; 1224 int err; 1225 1226 if (!chip->info->global2_addr) 1227 return 0; 1228 1229 /* Initialize the routing port to the 32 possible target devices */ 1230 for (target = 0; target < 32; target++) { 1231 port = 0x1f; 1232 if (target < DSA_MAX_SWITCHES) 1233 if (chip->ds->rtable[target] != DSA_RTABLE_NONE) 1234 port = chip->ds->rtable[target]; 1235 1236 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1237 if (err) 1238 return err; 1239 } 1240 1241 if (chip->info->ops->set_cascade_port) { 1242 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1243 err = chip->info->ops->set_cascade_port(chip, port); 1244 if (err) 1245 return err; 1246 } 1247 1248 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1249 if (err) 1250 return err; 1251 1252 return 0; 1253 } 1254 1255 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1256 { 1257 /* Clear all trunk masks and mapping */ 1258 if (chip->info->global2_addr) 1259 return mv88e6xxx_g2_trunk_clear(chip); 1260 1261 return 0; 1262 } 1263 1264 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1265 { 1266 if (chip->info->ops->rmu_disable) 1267 return chip->info->ops->rmu_disable(chip); 1268 1269 return 0; 1270 } 1271 1272 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1273 { 1274 if (chip->info->ops->pot_clear) 1275 return chip->info->ops->pot_clear(chip); 1276 1277 return 0; 1278 } 1279 1280 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1281 { 1282 if (chip->info->ops->mgmt_rsvd2cpu) 1283 return chip->info->ops->mgmt_rsvd2cpu(chip); 1284 1285 return 0; 1286 } 1287 1288 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1289 { 1290 int err; 1291 1292 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1293 if (err) 1294 return err; 1295 1296 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1297 if (err) 1298 return err; 1299 1300 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1301 } 1302 1303 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1304 { 1305 int port; 1306 int err; 1307 1308 if (!chip->info->ops->irl_init_all) 1309 return 0; 1310 1311 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1312 /* Disable ingress rate limiting by resetting all per port 1313 * ingress rate limit resources to their initial state. 1314 */ 1315 err = chip->info->ops->irl_init_all(chip, port); 1316 if (err) 1317 return err; 1318 } 1319 1320 return 0; 1321 } 1322 1323 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1324 { 1325 if (chip->info->ops->set_switch_mac) { 1326 u8 addr[ETH_ALEN]; 1327 1328 eth_random_addr(addr); 1329 1330 return chip->info->ops->set_switch_mac(chip, addr); 1331 } 1332 1333 return 0; 1334 } 1335 1336 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1337 { 1338 u16 pvlan = 0; 1339 1340 if (!mv88e6xxx_has_pvt(chip)) 1341 return -EOPNOTSUPP; 1342 1343 /* Skip the local source device, which uses in-chip port VLAN */ 1344 if (dev != chip->ds->index) 1345 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1346 1347 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1348 } 1349 1350 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1351 { 1352 int dev, port; 1353 int err; 1354 1355 if (!mv88e6xxx_has_pvt(chip)) 1356 return 0; 1357 1358 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1359 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1360 */ 1361 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1362 if (err) 1363 return err; 1364 1365 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1366 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1367 err = mv88e6xxx_pvt_map(chip, dev, port); 1368 if (err) 1369 return err; 1370 } 1371 } 1372 1373 return 0; 1374 } 1375 1376 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1377 { 1378 struct mv88e6xxx_chip *chip = ds->priv; 1379 int err; 1380 1381 mutex_lock(&chip->reg_lock); 1382 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1383 mutex_unlock(&chip->reg_lock); 1384 1385 if (err) 1386 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1387 } 1388 1389 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1390 { 1391 if (!chip->info->max_vid) 1392 return 0; 1393 1394 return mv88e6xxx_g1_vtu_flush(chip); 1395 } 1396 1397 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1398 struct mv88e6xxx_vtu_entry *entry) 1399 { 1400 if (!chip->info->ops->vtu_getnext) 1401 return -EOPNOTSUPP; 1402 1403 return chip->info->ops->vtu_getnext(chip, entry); 1404 } 1405 1406 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1407 struct mv88e6xxx_vtu_entry *entry) 1408 { 1409 if (!chip->info->ops->vtu_loadpurge) 1410 return -EOPNOTSUPP; 1411 1412 return chip->info->ops->vtu_loadpurge(chip, entry); 1413 } 1414 1415 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1416 { 1417 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1418 struct mv88e6xxx_vtu_entry vlan = { 1419 .vid = chip->info->max_vid, 1420 }; 1421 int i, err; 1422 1423 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1424 1425 /* Set every FID bit used by the (un)bridged ports */ 1426 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1427 err = mv88e6xxx_port_get_fid(chip, i, fid); 1428 if (err) 1429 return err; 1430 1431 set_bit(*fid, fid_bitmap); 1432 } 1433 1434 /* Set every FID bit used by the VLAN entries */ 1435 do { 1436 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1437 if (err) 1438 return err; 1439 1440 if (!vlan.valid) 1441 break; 1442 1443 set_bit(vlan.fid, fid_bitmap); 1444 } while (vlan.vid < chip->info->max_vid); 1445 1446 /* The reset value 0x000 is used to indicate that multiple address 1447 * databases are not needed. Return the next positive available. 1448 */ 1449 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1450 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1451 return -ENOSPC; 1452 1453 /* Clear the database */ 1454 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1455 } 1456 1457 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1458 struct mv88e6xxx_vtu_entry *entry, bool new) 1459 { 1460 int err; 1461 1462 if (!vid) 1463 return -EINVAL; 1464 1465 entry->vid = vid - 1; 1466 entry->valid = false; 1467 1468 err = mv88e6xxx_vtu_getnext(chip, entry); 1469 if (err) 1470 return err; 1471 1472 if (entry->vid == vid && entry->valid) 1473 return 0; 1474 1475 if (new) { 1476 int i; 1477 1478 /* Initialize a fresh VLAN entry */ 1479 memset(entry, 0, sizeof(*entry)); 1480 entry->valid = true; 1481 entry->vid = vid; 1482 1483 /* Exclude all ports */ 1484 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1485 entry->member[i] = 1486 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1487 1488 return mv88e6xxx_atu_new(chip, &entry->fid); 1489 } 1490 1491 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1492 return -EOPNOTSUPP; 1493 } 1494 1495 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1496 u16 vid_begin, u16 vid_end) 1497 { 1498 struct mv88e6xxx_chip *chip = ds->priv; 1499 struct mv88e6xxx_vtu_entry vlan = { 1500 .vid = vid_begin - 1, 1501 }; 1502 int i, err; 1503 1504 /* DSA and CPU ports have to be members of multiple vlans */ 1505 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1506 return 0; 1507 1508 if (!vid_begin) 1509 return -EOPNOTSUPP; 1510 1511 mutex_lock(&chip->reg_lock); 1512 1513 do { 1514 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1515 if (err) 1516 goto unlock; 1517 1518 if (!vlan.valid) 1519 break; 1520 1521 if (vlan.vid > vid_end) 1522 break; 1523 1524 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1525 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1526 continue; 1527 1528 if (!ds->ports[i].slave) 1529 continue; 1530 1531 if (vlan.member[i] == 1532 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1533 continue; 1534 1535 if (dsa_to_port(ds, i)->bridge_dev == 1536 ds->ports[port].bridge_dev) 1537 break; /* same bridge, check next VLAN */ 1538 1539 if (!dsa_to_port(ds, i)->bridge_dev) 1540 continue; 1541 1542 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1543 port, vlan.vid, i, 1544 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1545 err = -EOPNOTSUPP; 1546 goto unlock; 1547 } 1548 } while (vlan.vid < vid_end); 1549 1550 unlock: 1551 mutex_unlock(&chip->reg_lock); 1552 1553 return err; 1554 } 1555 1556 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1557 bool vlan_filtering) 1558 { 1559 struct mv88e6xxx_chip *chip = ds->priv; 1560 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1561 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1562 int err; 1563 1564 if (!chip->info->max_vid) 1565 return -EOPNOTSUPP; 1566 1567 mutex_lock(&chip->reg_lock); 1568 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1569 mutex_unlock(&chip->reg_lock); 1570 1571 return err; 1572 } 1573 1574 static int 1575 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1576 const struct switchdev_obj_port_vlan *vlan) 1577 { 1578 struct mv88e6xxx_chip *chip = ds->priv; 1579 int err; 1580 1581 if (!chip->info->max_vid) 1582 return -EOPNOTSUPP; 1583 1584 /* If the requested port doesn't belong to the same bridge as the VLAN 1585 * members, do not support it (yet) and fallback to software VLAN. 1586 */ 1587 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1588 vlan->vid_end); 1589 if (err) 1590 return err; 1591 1592 /* We don't need any dynamic resource from the kernel (yet), 1593 * so skip the prepare phase. 1594 */ 1595 return 0; 1596 } 1597 1598 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1599 const unsigned char *addr, u16 vid, 1600 u8 state) 1601 { 1602 struct mv88e6xxx_vtu_entry vlan; 1603 struct mv88e6xxx_atu_entry entry; 1604 int err; 1605 1606 /* Null VLAN ID corresponds to the port private database */ 1607 if (vid == 0) 1608 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 1609 else 1610 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1611 if (err) 1612 return err; 1613 1614 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1615 ether_addr_copy(entry.mac, addr); 1616 eth_addr_dec(entry.mac); 1617 1618 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); 1619 if (err) 1620 return err; 1621 1622 /* Initialize a fresh ATU entry if it isn't found */ 1623 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1624 !ether_addr_equal(entry.mac, addr)) { 1625 memset(&entry, 0, sizeof(entry)); 1626 ether_addr_copy(entry.mac, addr); 1627 } 1628 1629 /* Purge the ATU entry only if no port is using it anymore */ 1630 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1631 entry.portvec &= ~BIT(port); 1632 if (!entry.portvec) 1633 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1634 } else { 1635 entry.portvec |= BIT(port); 1636 entry.state = state; 1637 } 1638 1639 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); 1640 } 1641 1642 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1643 u16 vid) 1644 { 1645 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1646 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1647 1648 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1649 } 1650 1651 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1652 { 1653 int port; 1654 int err; 1655 1656 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1657 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1658 if (err) 1659 return err; 1660 } 1661 1662 return 0; 1663 } 1664 1665 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1666 u16 vid, u8 member) 1667 { 1668 struct mv88e6xxx_vtu_entry vlan; 1669 int err; 1670 1671 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1672 if (err) 1673 return err; 1674 1675 vlan.member[port] = member; 1676 1677 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1678 if (err) 1679 return err; 1680 1681 return mv88e6xxx_broadcast_setup(chip, vid); 1682 } 1683 1684 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1685 const struct switchdev_obj_port_vlan *vlan) 1686 { 1687 struct mv88e6xxx_chip *chip = ds->priv; 1688 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1689 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1690 u8 member; 1691 u16 vid; 1692 1693 if (!chip->info->max_vid) 1694 return; 1695 1696 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1697 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1698 else if (untagged) 1699 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1700 else 1701 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1702 1703 mutex_lock(&chip->reg_lock); 1704 1705 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1706 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) 1707 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1708 vid, untagged ? 'u' : 't'); 1709 1710 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1711 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1712 vlan->vid_end); 1713 1714 mutex_unlock(&chip->reg_lock); 1715 } 1716 1717 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1718 int port, u16 vid) 1719 { 1720 struct mv88e6xxx_vtu_entry vlan; 1721 int i, err; 1722 1723 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1724 if (err) 1725 return err; 1726 1727 /* Tell switchdev if this VLAN is handled in software */ 1728 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1729 return -EOPNOTSUPP; 1730 1731 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1732 1733 /* keep the VLAN unless all ports are excluded */ 1734 vlan.valid = false; 1735 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1736 if (vlan.member[i] != 1737 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1738 vlan.valid = true; 1739 break; 1740 } 1741 } 1742 1743 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1744 if (err) 1745 return err; 1746 1747 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1748 } 1749 1750 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1751 const struct switchdev_obj_port_vlan *vlan) 1752 { 1753 struct mv88e6xxx_chip *chip = ds->priv; 1754 u16 pvid, vid; 1755 int err = 0; 1756 1757 if (!chip->info->max_vid) 1758 return -EOPNOTSUPP; 1759 1760 mutex_lock(&chip->reg_lock); 1761 1762 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1763 if (err) 1764 goto unlock; 1765 1766 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1767 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1768 if (err) 1769 goto unlock; 1770 1771 if (vid == pvid) { 1772 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1773 if (err) 1774 goto unlock; 1775 } 1776 } 1777 1778 unlock: 1779 mutex_unlock(&chip->reg_lock); 1780 1781 return err; 1782 } 1783 1784 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1785 const unsigned char *addr, u16 vid) 1786 { 1787 struct mv88e6xxx_chip *chip = ds->priv; 1788 int err; 1789 1790 mutex_lock(&chip->reg_lock); 1791 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1792 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1793 mutex_unlock(&chip->reg_lock); 1794 1795 return err; 1796 } 1797 1798 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1799 const unsigned char *addr, u16 vid) 1800 { 1801 struct mv88e6xxx_chip *chip = ds->priv; 1802 int err; 1803 1804 mutex_lock(&chip->reg_lock); 1805 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1806 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1807 mutex_unlock(&chip->reg_lock); 1808 1809 return err; 1810 } 1811 1812 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1813 u16 fid, u16 vid, int port, 1814 dsa_fdb_dump_cb_t *cb, void *data) 1815 { 1816 struct mv88e6xxx_atu_entry addr; 1817 bool is_static; 1818 int err; 1819 1820 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1821 eth_broadcast_addr(addr.mac); 1822 1823 do { 1824 mutex_lock(&chip->reg_lock); 1825 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1826 mutex_unlock(&chip->reg_lock); 1827 if (err) 1828 return err; 1829 1830 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1831 break; 1832 1833 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1834 continue; 1835 1836 if (!is_unicast_ether_addr(addr.mac)) 1837 continue; 1838 1839 is_static = (addr.state == 1840 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1841 err = cb(addr.mac, vid, is_static, data); 1842 if (err) 1843 return err; 1844 } while (!is_broadcast_ether_addr(addr.mac)); 1845 1846 return err; 1847 } 1848 1849 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1850 dsa_fdb_dump_cb_t *cb, void *data) 1851 { 1852 struct mv88e6xxx_vtu_entry vlan = { 1853 .vid = chip->info->max_vid, 1854 }; 1855 u16 fid; 1856 int err; 1857 1858 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1859 mutex_lock(&chip->reg_lock); 1860 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1861 mutex_unlock(&chip->reg_lock); 1862 1863 if (err) 1864 return err; 1865 1866 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1867 if (err) 1868 return err; 1869 1870 /* Dump VLANs' Filtering Information Databases */ 1871 do { 1872 mutex_lock(&chip->reg_lock); 1873 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1874 mutex_unlock(&chip->reg_lock); 1875 if (err) 1876 return err; 1877 1878 if (!vlan.valid) 1879 break; 1880 1881 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1882 cb, data); 1883 if (err) 1884 return err; 1885 } while (vlan.vid < chip->info->max_vid); 1886 1887 return err; 1888 } 1889 1890 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1891 dsa_fdb_dump_cb_t *cb, void *data) 1892 { 1893 struct mv88e6xxx_chip *chip = ds->priv; 1894 1895 return mv88e6xxx_port_db_dump(chip, port, cb, data); 1896 } 1897 1898 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1899 struct net_device *br) 1900 { 1901 struct dsa_switch *ds; 1902 int port; 1903 int dev; 1904 int err; 1905 1906 /* Remap the Port VLAN of each local bridge group member */ 1907 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1908 if (chip->ds->ports[port].bridge_dev == br) { 1909 err = mv88e6xxx_port_vlan_map(chip, port); 1910 if (err) 1911 return err; 1912 } 1913 } 1914 1915 if (!mv88e6xxx_has_pvt(chip)) 1916 return 0; 1917 1918 /* Remap the Port VLAN of each cross-chip bridge group member */ 1919 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1920 ds = chip->ds->dst->ds[dev]; 1921 if (!ds) 1922 break; 1923 1924 for (port = 0; port < ds->num_ports; ++port) { 1925 if (ds->ports[port].bridge_dev == br) { 1926 err = mv88e6xxx_pvt_map(chip, dev, port); 1927 if (err) 1928 return err; 1929 } 1930 } 1931 } 1932 1933 return 0; 1934 } 1935 1936 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1937 struct net_device *br) 1938 { 1939 struct mv88e6xxx_chip *chip = ds->priv; 1940 int err; 1941 1942 mutex_lock(&chip->reg_lock); 1943 err = mv88e6xxx_bridge_map(chip, br); 1944 mutex_unlock(&chip->reg_lock); 1945 1946 return err; 1947 } 1948 1949 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 1950 struct net_device *br) 1951 { 1952 struct mv88e6xxx_chip *chip = ds->priv; 1953 1954 mutex_lock(&chip->reg_lock); 1955 if (mv88e6xxx_bridge_map(chip, br) || 1956 mv88e6xxx_port_vlan_map(chip, port)) 1957 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 1958 mutex_unlock(&chip->reg_lock); 1959 } 1960 1961 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 1962 int port, struct net_device *br) 1963 { 1964 struct mv88e6xxx_chip *chip = ds->priv; 1965 int err; 1966 1967 if (!mv88e6xxx_has_pvt(chip)) 1968 return 0; 1969 1970 mutex_lock(&chip->reg_lock); 1971 err = mv88e6xxx_pvt_map(chip, dev, port); 1972 mutex_unlock(&chip->reg_lock); 1973 1974 return err; 1975 } 1976 1977 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 1978 int port, struct net_device *br) 1979 { 1980 struct mv88e6xxx_chip *chip = ds->priv; 1981 1982 if (!mv88e6xxx_has_pvt(chip)) 1983 return; 1984 1985 mutex_lock(&chip->reg_lock); 1986 if (mv88e6xxx_pvt_map(chip, dev, port)) 1987 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 1988 mutex_unlock(&chip->reg_lock); 1989 } 1990 1991 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 1992 { 1993 if (chip->info->ops->reset) 1994 return chip->info->ops->reset(chip); 1995 1996 return 0; 1997 } 1998 1999 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2000 { 2001 struct gpio_desc *gpiod = chip->reset; 2002 2003 /* If there is a GPIO connected to the reset pin, toggle it */ 2004 if (gpiod) { 2005 gpiod_set_value_cansleep(gpiod, 1); 2006 usleep_range(10000, 20000); 2007 gpiod_set_value_cansleep(gpiod, 0); 2008 usleep_range(10000, 20000); 2009 } 2010 } 2011 2012 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2013 { 2014 int i, err; 2015 2016 /* Set all ports to the Disabled state */ 2017 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2018 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2019 if (err) 2020 return err; 2021 } 2022 2023 /* Wait for transmit queues to drain, 2024 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2025 */ 2026 usleep_range(2000, 4000); 2027 2028 return 0; 2029 } 2030 2031 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2032 { 2033 int err; 2034 2035 err = mv88e6xxx_disable_ports(chip); 2036 if (err) 2037 return err; 2038 2039 mv88e6xxx_hardware_reset(chip); 2040 2041 return mv88e6xxx_software_reset(chip); 2042 } 2043 2044 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2045 enum mv88e6xxx_frame_mode frame, 2046 enum mv88e6xxx_egress_mode egress, u16 etype) 2047 { 2048 int err; 2049 2050 if (!chip->info->ops->port_set_frame_mode) 2051 return -EOPNOTSUPP; 2052 2053 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2054 if (err) 2055 return err; 2056 2057 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2058 if (err) 2059 return err; 2060 2061 if (chip->info->ops->port_set_ether_type) 2062 return chip->info->ops->port_set_ether_type(chip, port, etype); 2063 2064 return 0; 2065 } 2066 2067 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2068 { 2069 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2070 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2071 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2072 } 2073 2074 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2075 { 2076 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2077 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2078 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2079 } 2080 2081 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2082 { 2083 return mv88e6xxx_set_port_mode(chip, port, 2084 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2085 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2086 ETH_P_EDSA); 2087 } 2088 2089 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2090 { 2091 if (dsa_is_dsa_port(chip->ds, port)) 2092 return mv88e6xxx_set_port_mode_dsa(chip, port); 2093 2094 if (dsa_is_user_port(chip->ds, port)) 2095 return mv88e6xxx_set_port_mode_normal(chip, port); 2096 2097 /* Setup CPU port mode depending on its supported tag format */ 2098 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2099 return mv88e6xxx_set_port_mode_dsa(chip, port); 2100 2101 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2102 return mv88e6xxx_set_port_mode_edsa(chip, port); 2103 2104 return -EINVAL; 2105 } 2106 2107 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2108 { 2109 bool message = dsa_is_dsa_port(chip->ds, port); 2110 2111 return mv88e6xxx_port_set_message_port(chip, port, message); 2112 } 2113 2114 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2115 { 2116 struct dsa_switch *ds = chip->ds; 2117 bool flood; 2118 2119 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2120 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2121 if (chip->info->ops->port_set_egress_floods) 2122 return chip->info->ops->port_set_egress_floods(chip, port, 2123 flood, flood); 2124 2125 return 0; 2126 } 2127 2128 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2129 bool on) 2130 { 2131 if (chip->info->ops->serdes_power) 2132 return chip->info->ops->serdes_power(chip, port, on); 2133 2134 return 0; 2135 } 2136 2137 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2138 { 2139 struct dsa_switch *ds = chip->ds; 2140 int upstream_port; 2141 int err; 2142 2143 upstream_port = dsa_upstream_port(ds, port); 2144 if (chip->info->ops->port_set_upstream_port) { 2145 err = chip->info->ops->port_set_upstream_port(chip, port, 2146 upstream_port); 2147 if (err) 2148 return err; 2149 } 2150 2151 if (port == upstream_port) { 2152 if (chip->info->ops->set_cpu_port) { 2153 err = chip->info->ops->set_cpu_port(chip, 2154 upstream_port); 2155 if (err) 2156 return err; 2157 } 2158 2159 if (chip->info->ops->set_egress_port) { 2160 err = chip->info->ops->set_egress_port(chip, 2161 upstream_port); 2162 if (err) 2163 return err; 2164 } 2165 } 2166 2167 return 0; 2168 } 2169 2170 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2171 { 2172 struct dsa_switch *ds = chip->ds; 2173 int err; 2174 u16 reg; 2175 2176 chip->ports[port].chip = chip; 2177 chip->ports[port].port = port; 2178 2179 /* MAC Forcing register: don't force link, speed, duplex or flow control 2180 * state to any particular values on physical ports, but force the CPU 2181 * port and all DSA ports to their maximum bandwidth and full duplex. 2182 */ 2183 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2184 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2185 SPEED_MAX, DUPLEX_FULL, 2186 PAUSE_OFF, 2187 PHY_INTERFACE_MODE_NA); 2188 else 2189 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2190 SPEED_UNFORCED, DUPLEX_UNFORCED, 2191 PAUSE_ON, 2192 PHY_INTERFACE_MODE_NA); 2193 if (err) 2194 return err; 2195 2196 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2197 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2198 * tunneling, determine priority by looking at 802.1p and IP 2199 * priority fields (IP prio has precedence), and set STP state 2200 * to Forwarding. 2201 * 2202 * If this is the CPU link, use DSA or EDSA tagging depending 2203 * on which tagging mode was configured. 2204 * 2205 * If this is a link to another switch, use DSA tagging mode. 2206 * 2207 * If this is the upstream port for this switch, enable 2208 * forwarding of unknown unicasts and multicasts. 2209 */ 2210 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2211 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2212 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2213 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2214 if (err) 2215 return err; 2216 2217 err = mv88e6xxx_setup_port_mode(chip, port); 2218 if (err) 2219 return err; 2220 2221 err = mv88e6xxx_setup_egress_floods(chip, port); 2222 if (err) 2223 return err; 2224 2225 /* Enable the SERDES interface for DSA and CPU ports. Normal 2226 * ports SERDES are enabled when the port is enabled, thus 2227 * saving a bit of power. 2228 */ 2229 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 2230 err = mv88e6xxx_serdes_power(chip, port, true); 2231 if (err) 2232 return err; 2233 } 2234 2235 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2236 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2237 * untagged frames on this port, do a destination address lookup on all 2238 * received packets as usual, disable ARP mirroring and don't send a 2239 * copy of all transmitted/received frames on this port to the CPU. 2240 */ 2241 err = mv88e6xxx_port_set_map_da(chip, port); 2242 if (err) 2243 return err; 2244 2245 err = mv88e6xxx_setup_upstream_port(chip, port); 2246 if (err) 2247 return err; 2248 2249 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2250 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2251 if (err) 2252 return err; 2253 2254 if (chip->info->ops->port_set_jumbo_size) { 2255 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2256 if (err) 2257 return err; 2258 } 2259 2260 /* Port Association Vector: when learning source addresses 2261 * of packets, add the address to the address database using 2262 * a port bitmap that has only the bit for this port set and 2263 * the other bits clear. 2264 */ 2265 reg = 1 << port; 2266 /* Disable learning for CPU port */ 2267 if (dsa_is_cpu_port(ds, port)) 2268 reg = 0; 2269 2270 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2271 reg); 2272 if (err) 2273 return err; 2274 2275 /* Egress rate control 2: disable egress rate control. */ 2276 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2277 0x0000); 2278 if (err) 2279 return err; 2280 2281 if (chip->info->ops->port_pause_limit) { 2282 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2283 if (err) 2284 return err; 2285 } 2286 2287 if (chip->info->ops->port_disable_learn_limit) { 2288 err = chip->info->ops->port_disable_learn_limit(chip, port); 2289 if (err) 2290 return err; 2291 } 2292 2293 if (chip->info->ops->port_disable_pri_override) { 2294 err = chip->info->ops->port_disable_pri_override(chip, port); 2295 if (err) 2296 return err; 2297 } 2298 2299 if (chip->info->ops->port_tag_remap) { 2300 err = chip->info->ops->port_tag_remap(chip, port); 2301 if (err) 2302 return err; 2303 } 2304 2305 if (chip->info->ops->port_egress_rate_limiting) { 2306 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2307 if (err) 2308 return err; 2309 } 2310 2311 err = mv88e6xxx_setup_message_port(chip, port); 2312 if (err) 2313 return err; 2314 2315 /* Port based VLAN map: give each port the same default address 2316 * database, and allow bidirectional communication between the 2317 * CPU and DSA port(s), and the other ports. 2318 */ 2319 err = mv88e6xxx_port_set_fid(chip, port, 0); 2320 if (err) 2321 return err; 2322 2323 err = mv88e6xxx_port_vlan_map(chip, port); 2324 if (err) 2325 return err; 2326 2327 /* Default VLAN ID and priority: don't set a default VLAN 2328 * ID, and set the default packet priority to zero. 2329 */ 2330 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2331 } 2332 2333 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2334 struct phy_device *phydev) 2335 { 2336 struct mv88e6xxx_chip *chip = ds->priv; 2337 int err; 2338 2339 mutex_lock(&chip->reg_lock); 2340 2341 err = mv88e6xxx_serdes_power(chip, port, true); 2342 2343 if (!err && chip->info->ops->serdes_irq_setup) 2344 err = chip->info->ops->serdes_irq_setup(chip, port); 2345 2346 mutex_unlock(&chip->reg_lock); 2347 2348 return err; 2349 } 2350 2351 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port, 2352 struct phy_device *phydev) 2353 { 2354 struct mv88e6xxx_chip *chip = ds->priv; 2355 2356 mutex_lock(&chip->reg_lock); 2357 2358 if (chip->info->ops->serdes_irq_free) 2359 chip->info->ops->serdes_irq_free(chip, port); 2360 2361 if (mv88e6xxx_serdes_power(chip, port, false)) 2362 dev_err(chip->dev, "failed to power off SERDES\n"); 2363 2364 mutex_unlock(&chip->reg_lock); 2365 } 2366 2367 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2368 unsigned int ageing_time) 2369 { 2370 struct mv88e6xxx_chip *chip = ds->priv; 2371 int err; 2372 2373 mutex_lock(&chip->reg_lock); 2374 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2375 mutex_unlock(&chip->reg_lock); 2376 2377 return err; 2378 } 2379 2380 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2381 { 2382 int err; 2383 2384 /* Initialize the statistics unit */ 2385 if (chip->info->ops->stats_set_histogram) { 2386 err = chip->info->ops->stats_set_histogram(chip); 2387 if (err) 2388 return err; 2389 } 2390 2391 return mv88e6xxx_g1_stats_clear(chip); 2392 } 2393 2394 static int mv88e6xxx_setup(struct dsa_switch *ds) 2395 { 2396 struct mv88e6xxx_chip *chip = ds->priv; 2397 u8 cmode; 2398 int err; 2399 int i; 2400 2401 chip->ds = ds; 2402 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2403 2404 mutex_lock(&chip->reg_lock); 2405 2406 /* Cache the cmode of each port. */ 2407 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2408 if (chip->info->ops->port_get_cmode) { 2409 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 2410 if (err) 2411 goto unlock; 2412 2413 chip->ports[i].cmode = cmode; 2414 } 2415 } 2416 2417 /* Setup Switch Port Registers */ 2418 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2419 if (dsa_is_unused_port(ds, i)) 2420 continue; 2421 2422 err = mv88e6xxx_setup_port(chip, i); 2423 if (err) 2424 goto unlock; 2425 } 2426 2427 err = mv88e6xxx_irl_setup(chip); 2428 if (err) 2429 goto unlock; 2430 2431 err = mv88e6xxx_mac_setup(chip); 2432 if (err) 2433 goto unlock; 2434 2435 err = mv88e6xxx_phy_setup(chip); 2436 if (err) 2437 goto unlock; 2438 2439 err = mv88e6xxx_vtu_setup(chip); 2440 if (err) 2441 goto unlock; 2442 2443 err = mv88e6xxx_pvt_setup(chip); 2444 if (err) 2445 goto unlock; 2446 2447 err = mv88e6xxx_atu_setup(chip); 2448 if (err) 2449 goto unlock; 2450 2451 err = mv88e6xxx_broadcast_setup(chip, 0); 2452 if (err) 2453 goto unlock; 2454 2455 err = mv88e6xxx_pot_setup(chip); 2456 if (err) 2457 goto unlock; 2458 2459 err = mv88e6xxx_rmu_setup(chip); 2460 if (err) 2461 goto unlock; 2462 2463 err = mv88e6xxx_rsvd2cpu_setup(chip); 2464 if (err) 2465 goto unlock; 2466 2467 err = mv88e6xxx_trunk_setup(chip); 2468 if (err) 2469 goto unlock; 2470 2471 err = mv88e6xxx_devmap_setup(chip); 2472 if (err) 2473 goto unlock; 2474 2475 err = mv88e6xxx_pri_setup(chip); 2476 if (err) 2477 goto unlock; 2478 2479 /* Setup PTP Hardware Clock and timestamping */ 2480 if (chip->info->ptp_support) { 2481 err = mv88e6xxx_ptp_setup(chip); 2482 if (err) 2483 goto unlock; 2484 2485 err = mv88e6xxx_hwtstamp_setup(chip); 2486 if (err) 2487 goto unlock; 2488 } 2489 2490 err = mv88e6xxx_stats_setup(chip); 2491 if (err) 2492 goto unlock; 2493 2494 unlock: 2495 mutex_unlock(&chip->reg_lock); 2496 2497 return err; 2498 } 2499 2500 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2501 { 2502 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2503 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2504 u16 val; 2505 int err; 2506 2507 if (!chip->info->ops->phy_read) 2508 return -EOPNOTSUPP; 2509 2510 mutex_lock(&chip->reg_lock); 2511 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2512 mutex_unlock(&chip->reg_lock); 2513 2514 if (reg == MII_PHYSID2) { 2515 /* Some internal PHYS don't have a model number. Use 2516 * the mv88e6390 family model number instead. 2517 */ 2518 if (!(val & 0x3f0)) 2519 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2520 } 2521 2522 return err ? err : val; 2523 } 2524 2525 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2526 { 2527 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2528 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2529 int err; 2530 2531 if (!chip->info->ops->phy_write) 2532 return -EOPNOTSUPP; 2533 2534 mutex_lock(&chip->reg_lock); 2535 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2536 mutex_unlock(&chip->reg_lock); 2537 2538 return err; 2539 } 2540 2541 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2542 struct device_node *np, 2543 bool external) 2544 { 2545 static int index; 2546 struct mv88e6xxx_mdio_bus *mdio_bus; 2547 struct mii_bus *bus; 2548 int err; 2549 2550 if (external) { 2551 mutex_lock(&chip->reg_lock); 2552 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 2553 mutex_unlock(&chip->reg_lock); 2554 2555 if (err) 2556 return err; 2557 } 2558 2559 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2560 if (!bus) 2561 return -ENOMEM; 2562 2563 mdio_bus = bus->priv; 2564 mdio_bus->bus = bus; 2565 mdio_bus->chip = chip; 2566 INIT_LIST_HEAD(&mdio_bus->list); 2567 mdio_bus->external = external; 2568 2569 if (np) { 2570 bus->name = np->full_name; 2571 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2572 } else { 2573 bus->name = "mv88e6xxx SMI"; 2574 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2575 } 2576 2577 bus->read = mv88e6xxx_mdio_read; 2578 bus->write = mv88e6xxx_mdio_write; 2579 bus->parent = chip->dev; 2580 2581 if (!external) { 2582 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 2583 if (err) 2584 return err; 2585 } 2586 2587 err = of_mdiobus_register(bus, np); 2588 if (err) { 2589 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2590 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2591 return err; 2592 } 2593 2594 if (external) 2595 list_add_tail(&mdio_bus->list, &chip->mdios); 2596 else 2597 list_add(&mdio_bus->list, &chip->mdios); 2598 2599 return 0; 2600 } 2601 2602 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2603 { .compatible = "marvell,mv88e6xxx-mdio-external", 2604 .data = (void *)true }, 2605 { }, 2606 }; 2607 2608 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2609 2610 { 2611 struct mv88e6xxx_mdio_bus *mdio_bus; 2612 struct mii_bus *bus; 2613 2614 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2615 bus = mdio_bus->bus; 2616 2617 if (!mdio_bus->external) 2618 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2619 2620 mdiobus_unregister(bus); 2621 } 2622 } 2623 2624 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2625 struct device_node *np) 2626 { 2627 const struct of_device_id *match; 2628 struct device_node *child; 2629 int err; 2630 2631 /* Always register one mdio bus for the internal/default mdio 2632 * bus. This maybe represented in the device tree, but is 2633 * optional. 2634 */ 2635 child = of_get_child_by_name(np, "mdio"); 2636 err = mv88e6xxx_mdio_register(chip, child, false); 2637 if (err) 2638 return err; 2639 2640 /* Walk the device tree, and see if there are any other nodes 2641 * which say they are compatible with the external mdio 2642 * bus. 2643 */ 2644 for_each_available_child_of_node(np, child) { 2645 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2646 if (match) { 2647 err = mv88e6xxx_mdio_register(chip, child, true); 2648 if (err) { 2649 mv88e6xxx_mdios_unregister(chip); 2650 return err; 2651 } 2652 } 2653 } 2654 2655 return 0; 2656 } 2657 2658 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2659 { 2660 struct mv88e6xxx_chip *chip = ds->priv; 2661 2662 return chip->eeprom_len; 2663 } 2664 2665 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2666 struct ethtool_eeprom *eeprom, u8 *data) 2667 { 2668 struct mv88e6xxx_chip *chip = ds->priv; 2669 int err; 2670 2671 if (!chip->info->ops->get_eeprom) 2672 return -EOPNOTSUPP; 2673 2674 mutex_lock(&chip->reg_lock); 2675 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2676 mutex_unlock(&chip->reg_lock); 2677 2678 if (err) 2679 return err; 2680 2681 eeprom->magic = 0xc3ec4951; 2682 2683 return 0; 2684 } 2685 2686 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2687 struct ethtool_eeprom *eeprom, u8 *data) 2688 { 2689 struct mv88e6xxx_chip *chip = ds->priv; 2690 int err; 2691 2692 if (!chip->info->ops->set_eeprom) 2693 return -EOPNOTSUPP; 2694 2695 if (eeprom->magic != 0xc3ec4951) 2696 return -EINVAL; 2697 2698 mutex_lock(&chip->reg_lock); 2699 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2700 mutex_unlock(&chip->reg_lock); 2701 2702 return err; 2703 } 2704 2705 static const struct mv88e6xxx_ops mv88e6085_ops = { 2706 /* MV88E6XXX_FAMILY_6097 */ 2707 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2708 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2709 .irl_init_all = mv88e6352_g2_irl_init_all, 2710 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2711 .phy_read = mv88e6185_phy_ppu_read, 2712 .phy_write = mv88e6185_phy_ppu_write, 2713 .port_set_link = mv88e6xxx_port_set_link, 2714 .port_set_duplex = mv88e6xxx_port_set_duplex, 2715 .port_set_speed = mv88e6185_port_set_speed, 2716 .port_tag_remap = mv88e6095_port_tag_remap, 2717 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2718 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2719 .port_set_ether_type = mv88e6351_port_set_ether_type, 2720 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2721 .port_pause_limit = mv88e6097_port_pause_limit, 2722 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2723 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2724 .port_link_state = mv88e6352_port_link_state, 2725 .port_get_cmode = mv88e6185_port_get_cmode, 2726 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2727 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2728 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2729 .stats_get_strings = mv88e6095_stats_get_strings, 2730 .stats_get_stats = mv88e6095_stats_get_stats, 2731 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2732 .set_egress_port = mv88e6095_g1_set_egress_port, 2733 .watchdog_ops = &mv88e6097_watchdog_ops, 2734 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2735 .pot_clear = mv88e6xxx_g2_pot_clear, 2736 .ppu_enable = mv88e6185_g1_ppu_enable, 2737 .ppu_disable = mv88e6185_g1_ppu_disable, 2738 .reset = mv88e6185_g1_reset, 2739 .rmu_disable = mv88e6085_g1_rmu_disable, 2740 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2741 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2742 .phylink_validate = mv88e6185_phylink_validate, 2743 }; 2744 2745 static const struct mv88e6xxx_ops mv88e6095_ops = { 2746 /* MV88E6XXX_FAMILY_6095 */ 2747 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2748 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2749 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2750 .phy_read = mv88e6185_phy_ppu_read, 2751 .phy_write = mv88e6185_phy_ppu_write, 2752 .port_set_link = mv88e6xxx_port_set_link, 2753 .port_set_duplex = mv88e6xxx_port_set_duplex, 2754 .port_set_speed = mv88e6185_port_set_speed, 2755 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2756 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2757 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2758 .port_link_state = mv88e6185_port_link_state, 2759 .port_get_cmode = mv88e6185_port_get_cmode, 2760 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2761 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2762 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2763 .stats_get_strings = mv88e6095_stats_get_strings, 2764 .stats_get_stats = mv88e6095_stats_get_stats, 2765 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2766 .ppu_enable = mv88e6185_g1_ppu_enable, 2767 .ppu_disable = mv88e6185_g1_ppu_disable, 2768 .reset = mv88e6185_g1_reset, 2769 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2770 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2771 .phylink_validate = mv88e6185_phylink_validate, 2772 }; 2773 2774 static const struct mv88e6xxx_ops mv88e6097_ops = { 2775 /* MV88E6XXX_FAMILY_6097 */ 2776 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2777 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2778 .irl_init_all = mv88e6352_g2_irl_init_all, 2779 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2780 .phy_read = mv88e6xxx_g2_smi_phy_read, 2781 .phy_write = mv88e6xxx_g2_smi_phy_write, 2782 .port_set_link = mv88e6xxx_port_set_link, 2783 .port_set_duplex = mv88e6xxx_port_set_duplex, 2784 .port_set_speed = mv88e6185_port_set_speed, 2785 .port_tag_remap = mv88e6095_port_tag_remap, 2786 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2787 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2788 .port_set_ether_type = mv88e6351_port_set_ether_type, 2789 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2790 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2791 .port_pause_limit = mv88e6097_port_pause_limit, 2792 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2793 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2794 .port_link_state = mv88e6352_port_link_state, 2795 .port_get_cmode = mv88e6185_port_get_cmode, 2796 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2797 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2798 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2799 .stats_get_strings = mv88e6095_stats_get_strings, 2800 .stats_get_stats = mv88e6095_stats_get_stats, 2801 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2802 .set_egress_port = mv88e6095_g1_set_egress_port, 2803 .watchdog_ops = &mv88e6097_watchdog_ops, 2804 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2805 .pot_clear = mv88e6xxx_g2_pot_clear, 2806 .reset = mv88e6352_g1_reset, 2807 .rmu_disable = mv88e6085_g1_rmu_disable, 2808 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2809 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2810 .phylink_validate = mv88e6185_phylink_validate, 2811 }; 2812 2813 static const struct mv88e6xxx_ops mv88e6123_ops = { 2814 /* MV88E6XXX_FAMILY_6165 */ 2815 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2816 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2817 .irl_init_all = mv88e6352_g2_irl_init_all, 2818 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2819 .phy_read = mv88e6xxx_g2_smi_phy_read, 2820 .phy_write = mv88e6xxx_g2_smi_phy_write, 2821 .port_set_link = mv88e6xxx_port_set_link, 2822 .port_set_duplex = mv88e6xxx_port_set_duplex, 2823 .port_set_speed = mv88e6185_port_set_speed, 2824 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2825 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2826 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2827 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2828 .port_link_state = mv88e6352_port_link_state, 2829 .port_get_cmode = mv88e6185_port_get_cmode, 2830 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2831 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2832 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2833 .stats_get_strings = mv88e6095_stats_get_strings, 2834 .stats_get_stats = mv88e6095_stats_get_stats, 2835 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2836 .set_egress_port = mv88e6095_g1_set_egress_port, 2837 .watchdog_ops = &mv88e6097_watchdog_ops, 2838 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2839 .pot_clear = mv88e6xxx_g2_pot_clear, 2840 .reset = mv88e6352_g1_reset, 2841 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2842 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2843 .phylink_validate = mv88e6185_phylink_validate, 2844 }; 2845 2846 static const struct mv88e6xxx_ops mv88e6131_ops = { 2847 /* MV88E6XXX_FAMILY_6185 */ 2848 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2849 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2850 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2851 .phy_read = mv88e6185_phy_ppu_read, 2852 .phy_write = mv88e6185_phy_ppu_write, 2853 .port_set_link = mv88e6xxx_port_set_link, 2854 .port_set_duplex = mv88e6xxx_port_set_duplex, 2855 .port_set_speed = mv88e6185_port_set_speed, 2856 .port_tag_remap = mv88e6095_port_tag_remap, 2857 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2858 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2859 .port_set_ether_type = mv88e6351_port_set_ether_type, 2860 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2861 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2862 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2863 .port_pause_limit = mv88e6097_port_pause_limit, 2864 .port_set_pause = mv88e6185_port_set_pause, 2865 .port_link_state = mv88e6352_port_link_state, 2866 .port_get_cmode = mv88e6185_port_get_cmode, 2867 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2868 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2869 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2870 .stats_get_strings = mv88e6095_stats_get_strings, 2871 .stats_get_stats = mv88e6095_stats_get_stats, 2872 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2873 .set_egress_port = mv88e6095_g1_set_egress_port, 2874 .watchdog_ops = &mv88e6097_watchdog_ops, 2875 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2876 .ppu_enable = mv88e6185_g1_ppu_enable, 2877 .set_cascade_port = mv88e6185_g1_set_cascade_port, 2878 .ppu_disable = mv88e6185_g1_ppu_disable, 2879 .reset = mv88e6185_g1_reset, 2880 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2881 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2882 .phylink_validate = mv88e6185_phylink_validate, 2883 }; 2884 2885 static const struct mv88e6xxx_ops mv88e6141_ops = { 2886 /* MV88E6XXX_FAMILY_6341 */ 2887 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2888 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2889 .irl_init_all = mv88e6352_g2_irl_init_all, 2890 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2891 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2892 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2893 .phy_read = mv88e6xxx_g2_smi_phy_read, 2894 .phy_write = mv88e6xxx_g2_smi_phy_write, 2895 .port_set_link = mv88e6xxx_port_set_link, 2896 .port_set_duplex = mv88e6xxx_port_set_duplex, 2897 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2898 .port_set_speed = mv88e6390_port_set_speed, 2899 .port_tag_remap = mv88e6095_port_tag_remap, 2900 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2901 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2902 .port_set_ether_type = mv88e6351_port_set_ether_type, 2903 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2904 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2905 .port_pause_limit = mv88e6097_port_pause_limit, 2906 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2907 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2908 .port_link_state = mv88e6352_port_link_state, 2909 .port_get_cmode = mv88e6352_port_get_cmode, 2910 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2911 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2912 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2913 .stats_get_strings = mv88e6320_stats_get_strings, 2914 .stats_get_stats = mv88e6390_stats_get_stats, 2915 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2916 .set_egress_port = mv88e6390_g1_set_egress_port, 2917 .watchdog_ops = &mv88e6390_watchdog_ops, 2918 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2919 .pot_clear = mv88e6xxx_g2_pot_clear, 2920 .reset = mv88e6352_g1_reset, 2921 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2922 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2923 .serdes_power = mv88e6341_serdes_power, 2924 .gpio_ops = &mv88e6352_gpio_ops, 2925 .phylink_validate = mv88e6390_phylink_validate, 2926 }; 2927 2928 static const struct mv88e6xxx_ops mv88e6161_ops = { 2929 /* MV88E6XXX_FAMILY_6165 */ 2930 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2931 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2932 .irl_init_all = mv88e6352_g2_irl_init_all, 2933 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2934 .phy_read = mv88e6xxx_g2_smi_phy_read, 2935 .phy_write = mv88e6xxx_g2_smi_phy_write, 2936 .port_set_link = mv88e6xxx_port_set_link, 2937 .port_set_duplex = mv88e6xxx_port_set_duplex, 2938 .port_set_speed = mv88e6185_port_set_speed, 2939 .port_tag_remap = mv88e6095_port_tag_remap, 2940 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2941 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2942 .port_set_ether_type = mv88e6351_port_set_ether_type, 2943 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2944 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2945 .port_pause_limit = mv88e6097_port_pause_limit, 2946 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2947 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2948 .port_link_state = mv88e6352_port_link_state, 2949 .port_get_cmode = mv88e6185_port_get_cmode, 2950 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2951 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2952 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2953 .stats_get_strings = mv88e6095_stats_get_strings, 2954 .stats_get_stats = mv88e6095_stats_get_stats, 2955 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2956 .set_egress_port = mv88e6095_g1_set_egress_port, 2957 .watchdog_ops = &mv88e6097_watchdog_ops, 2958 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2959 .pot_clear = mv88e6xxx_g2_pot_clear, 2960 .reset = mv88e6352_g1_reset, 2961 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2962 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2963 .avb_ops = &mv88e6165_avb_ops, 2964 .ptp_ops = &mv88e6165_ptp_ops, 2965 .phylink_validate = mv88e6185_phylink_validate, 2966 }; 2967 2968 static const struct mv88e6xxx_ops mv88e6165_ops = { 2969 /* MV88E6XXX_FAMILY_6165 */ 2970 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2971 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2972 .irl_init_all = mv88e6352_g2_irl_init_all, 2973 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2974 .phy_read = mv88e6165_phy_read, 2975 .phy_write = mv88e6165_phy_write, 2976 .port_set_link = mv88e6xxx_port_set_link, 2977 .port_set_duplex = mv88e6xxx_port_set_duplex, 2978 .port_set_speed = mv88e6185_port_set_speed, 2979 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2980 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2981 .port_link_state = mv88e6352_port_link_state, 2982 .port_get_cmode = mv88e6185_port_get_cmode, 2983 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2984 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2985 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2986 .stats_get_strings = mv88e6095_stats_get_strings, 2987 .stats_get_stats = mv88e6095_stats_get_stats, 2988 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2989 .set_egress_port = mv88e6095_g1_set_egress_port, 2990 .watchdog_ops = &mv88e6097_watchdog_ops, 2991 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2992 .pot_clear = mv88e6xxx_g2_pot_clear, 2993 .reset = mv88e6352_g1_reset, 2994 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2995 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2996 .avb_ops = &mv88e6165_avb_ops, 2997 .ptp_ops = &mv88e6165_ptp_ops, 2998 .phylink_validate = mv88e6185_phylink_validate, 2999 }; 3000 3001 static const struct mv88e6xxx_ops mv88e6171_ops = { 3002 /* MV88E6XXX_FAMILY_6351 */ 3003 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3004 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3005 .irl_init_all = mv88e6352_g2_irl_init_all, 3006 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3007 .phy_read = mv88e6xxx_g2_smi_phy_read, 3008 .phy_write = mv88e6xxx_g2_smi_phy_write, 3009 .port_set_link = mv88e6xxx_port_set_link, 3010 .port_set_duplex = mv88e6xxx_port_set_duplex, 3011 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3012 .port_set_speed = mv88e6185_port_set_speed, 3013 .port_tag_remap = mv88e6095_port_tag_remap, 3014 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3015 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3016 .port_set_ether_type = mv88e6351_port_set_ether_type, 3017 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3018 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3019 .port_pause_limit = mv88e6097_port_pause_limit, 3020 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3021 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3022 .port_link_state = mv88e6352_port_link_state, 3023 .port_get_cmode = mv88e6352_port_get_cmode, 3024 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3025 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3026 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3027 .stats_get_strings = mv88e6095_stats_get_strings, 3028 .stats_get_stats = mv88e6095_stats_get_stats, 3029 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3030 .set_egress_port = mv88e6095_g1_set_egress_port, 3031 .watchdog_ops = &mv88e6097_watchdog_ops, 3032 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3033 .pot_clear = mv88e6xxx_g2_pot_clear, 3034 .reset = mv88e6352_g1_reset, 3035 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3036 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3037 .phylink_validate = mv88e6185_phylink_validate, 3038 }; 3039 3040 static const struct mv88e6xxx_ops mv88e6172_ops = { 3041 /* MV88E6XXX_FAMILY_6352 */ 3042 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3043 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3044 .irl_init_all = mv88e6352_g2_irl_init_all, 3045 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3046 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3047 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3048 .phy_read = mv88e6xxx_g2_smi_phy_read, 3049 .phy_write = mv88e6xxx_g2_smi_phy_write, 3050 .port_set_link = mv88e6xxx_port_set_link, 3051 .port_set_duplex = mv88e6xxx_port_set_duplex, 3052 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3053 .port_set_speed = mv88e6352_port_set_speed, 3054 .port_tag_remap = mv88e6095_port_tag_remap, 3055 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3056 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3057 .port_set_ether_type = mv88e6351_port_set_ether_type, 3058 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3059 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3060 .port_pause_limit = mv88e6097_port_pause_limit, 3061 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3062 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3063 .port_link_state = mv88e6352_port_link_state, 3064 .port_get_cmode = mv88e6352_port_get_cmode, 3065 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3066 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3067 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3068 .stats_get_strings = mv88e6095_stats_get_strings, 3069 .stats_get_stats = mv88e6095_stats_get_stats, 3070 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3071 .set_egress_port = mv88e6095_g1_set_egress_port, 3072 .watchdog_ops = &mv88e6097_watchdog_ops, 3073 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3074 .pot_clear = mv88e6xxx_g2_pot_clear, 3075 .reset = mv88e6352_g1_reset, 3076 .rmu_disable = mv88e6352_g1_rmu_disable, 3077 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3078 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3079 .serdes_power = mv88e6352_serdes_power, 3080 .gpio_ops = &mv88e6352_gpio_ops, 3081 .phylink_validate = mv88e6352_phylink_validate, 3082 }; 3083 3084 static const struct mv88e6xxx_ops mv88e6175_ops = { 3085 /* MV88E6XXX_FAMILY_6351 */ 3086 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3087 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3088 .irl_init_all = mv88e6352_g2_irl_init_all, 3089 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3090 .phy_read = mv88e6xxx_g2_smi_phy_read, 3091 .phy_write = mv88e6xxx_g2_smi_phy_write, 3092 .port_set_link = mv88e6xxx_port_set_link, 3093 .port_set_duplex = mv88e6xxx_port_set_duplex, 3094 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3095 .port_set_speed = mv88e6185_port_set_speed, 3096 .port_tag_remap = mv88e6095_port_tag_remap, 3097 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3098 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3099 .port_set_ether_type = mv88e6351_port_set_ether_type, 3100 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3101 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3102 .port_pause_limit = mv88e6097_port_pause_limit, 3103 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3104 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3105 .port_link_state = mv88e6352_port_link_state, 3106 .port_get_cmode = mv88e6352_port_get_cmode, 3107 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3108 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3109 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3110 .stats_get_strings = mv88e6095_stats_get_strings, 3111 .stats_get_stats = mv88e6095_stats_get_stats, 3112 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3113 .set_egress_port = mv88e6095_g1_set_egress_port, 3114 .watchdog_ops = &mv88e6097_watchdog_ops, 3115 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3116 .pot_clear = mv88e6xxx_g2_pot_clear, 3117 .reset = mv88e6352_g1_reset, 3118 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3119 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3120 .phylink_validate = mv88e6185_phylink_validate, 3121 }; 3122 3123 static const struct mv88e6xxx_ops mv88e6176_ops = { 3124 /* MV88E6XXX_FAMILY_6352 */ 3125 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3126 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3127 .irl_init_all = mv88e6352_g2_irl_init_all, 3128 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3129 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3130 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3131 .phy_read = mv88e6xxx_g2_smi_phy_read, 3132 .phy_write = mv88e6xxx_g2_smi_phy_write, 3133 .port_set_link = mv88e6xxx_port_set_link, 3134 .port_set_duplex = mv88e6xxx_port_set_duplex, 3135 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3136 .port_set_speed = mv88e6352_port_set_speed, 3137 .port_tag_remap = mv88e6095_port_tag_remap, 3138 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3139 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3140 .port_set_ether_type = mv88e6351_port_set_ether_type, 3141 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3142 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3143 .port_pause_limit = mv88e6097_port_pause_limit, 3144 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3145 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3146 .port_link_state = mv88e6352_port_link_state, 3147 .port_get_cmode = mv88e6352_port_get_cmode, 3148 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3149 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3150 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3151 .stats_get_strings = mv88e6095_stats_get_strings, 3152 .stats_get_stats = mv88e6095_stats_get_stats, 3153 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3154 .set_egress_port = mv88e6095_g1_set_egress_port, 3155 .watchdog_ops = &mv88e6097_watchdog_ops, 3156 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3157 .pot_clear = mv88e6xxx_g2_pot_clear, 3158 .reset = mv88e6352_g1_reset, 3159 .rmu_disable = mv88e6352_g1_rmu_disable, 3160 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3161 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3162 .serdes_power = mv88e6352_serdes_power, 3163 .gpio_ops = &mv88e6352_gpio_ops, 3164 .phylink_validate = mv88e6352_phylink_validate, 3165 }; 3166 3167 static const struct mv88e6xxx_ops mv88e6185_ops = { 3168 /* MV88E6XXX_FAMILY_6185 */ 3169 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3170 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3171 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3172 .phy_read = mv88e6185_phy_ppu_read, 3173 .phy_write = mv88e6185_phy_ppu_write, 3174 .port_set_link = mv88e6xxx_port_set_link, 3175 .port_set_duplex = mv88e6xxx_port_set_duplex, 3176 .port_set_speed = mv88e6185_port_set_speed, 3177 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3178 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3179 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3180 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3181 .port_set_pause = mv88e6185_port_set_pause, 3182 .port_link_state = mv88e6185_port_link_state, 3183 .port_get_cmode = mv88e6185_port_get_cmode, 3184 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3185 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3186 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3187 .stats_get_strings = mv88e6095_stats_get_strings, 3188 .stats_get_stats = mv88e6095_stats_get_stats, 3189 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3190 .set_egress_port = mv88e6095_g1_set_egress_port, 3191 .watchdog_ops = &mv88e6097_watchdog_ops, 3192 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3193 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3194 .ppu_enable = mv88e6185_g1_ppu_enable, 3195 .ppu_disable = mv88e6185_g1_ppu_disable, 3196 .reset = mv88e6185_g1_reset, 3197 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3198 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3199 .phylink_validate = mv88e6185_phylink_validate, 3200 }; 3201 3202 static const struct mv88e6xxx_ops mv88e6190_ops = { 3203 /* MV88E6XXX_FAMILY_6390 */ 3204 .irl_init_all = mv88e6390_g2_irl_init_all, 3205 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3206 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3207 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3208 .phy_read = mv88e6xxx_g2_smi_phy_read, 3209 .phy_write = mv88e6xxx_g2_smi_phy_write, 3210 .port_set_link = mv88e6xxx_port_set_link, 3211 .port_set_duplex = mv88e6xxx_port_set_duplex, 3212 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3213 .port_set_speed = mv88e6390_port_set_speed, 3214 .port_tag_remap = mv88e6390_port_tag_remap, 3215 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3216 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3217 .port_set_ether_type = mv88e6351_port_set_ether_type, 3218 .port_pause_limit = mv88e6390_port_pause_limit, 3219 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3220 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3221 .port_link_state = mv88e6352_port_link_state, 3222 .port_get_cmode = mv88e6352_port_get_cmode, 3223 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3224 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3225 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3226 .stats_get_strings = mv88e6320_stats_get_strings, 3227 .stats_get_stats = mv88e6390_stats_get_stats, 3228 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3229 .set_egress_port = mv88e6390_g1_set_egress_port, 3230 .watchdog_ops = &mv88e6390_watchdog_ops, 3231 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3232 .pot_clear = mv88e6xxx_g2_pot_clear, 3233 .reset = mv88e6352_g1_reset, 3234 .rmu_disable = mv88e6390_g1_rmu_disable, 3235 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3236 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3237 .serdes_power = mv88e6390_serdes_power, 3238 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3239 .serdes_irq_free = mv88e6390_serdes_irq_free, 3240 .gpio_ops = &mv88e6352_gpio_ops, 3241 .phylink_validate = mv88e6390_phylink_validate, 3242 }; 3243 3244 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3245 /* MV88E6XXX_FAMILY_6390 */ 3246 .irl_init_all = mv88e6390_g2_irl_init_all, 3247 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3248 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3249 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3250 .phy_read = mv88e6xxx_g2_smi_phy_read, 3251 .phy_write = mv88e6xxx_g2_smi_phy_write, 3252 .port_set_link = mv88e6xxx_port_set_link, 3253 .port_set_duplex = mv88e6xxx_port_set_duplex, 3254 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3255 .port_set_speed = mv88e6390x_port_set_speed, 3256 .port_tag_remap = mv88e6390_port_tag_remap, 3257 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3258 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3259 .port_set_ether_type = mv88e6351_port_set_ether_type, 3260 .port_pause_limit = mv88e6390_port_pause_limit, 3261 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3262 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3263 .port_link_state = mv88e6352_port_link_state, 3264 .port_get_cmode = mv88e6352_port_get_cmode, 3265 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3266 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3267 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3268 .stats_get_strings = mv88e6320_stats_get_strings, 3269 .stats_get_stats = mv88e6390_stats_get_stats, 3270 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3271 .set_egress_port = mv88e6390_g1_set_egress_port, 3272 .watchdog_ops = &mv88e6390_watchdog_ops, 3273 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3274 .pot_clear = mv88e6xxx_g2_pot_clear, 3275 .reset = mv88e6352_g1_reset, 3276 .rmu_disable = mv88e6390_g1_rmu_disable, 3277 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3278 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3279 .serdes_power = mv88e6390x_serdes_power, 3280 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3281 .serdes_irq_free = mv88e6390_serdes_irq_free, 3282 .gpio_ops = &mv88e6352_gpio_ops, 3283 .phylink_validate = mv88e6390x_phylink_validate, 3284 }; 3285 3286 static const struct mv88e6xxx_ops mv88e6191_ops = { 3287 /* MV88E6XXX_FAMILY_6390 */ 3288 .irl_init_all = mv88e6390_g2_irl_init_all, 3289 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3290 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3291 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3292 .phy_read = mv88e6xxx_g2_smi_phy_read, 3293 .phy_write = mv88e6xxx_g2_smi_phy_write, 3294 .port_set_link = mv88e6xxx_port_set_link, 3295 .port_set_duplex = mv88e6xxx_port_set_duplex, 3296 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3297 .port_set_speed = mv88e6390_port_set_speed, 3298 .port_tag_remap = mv88e6390_port_tag_remap, 3299 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3300 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3301 .port_set_ether_type = mv88e6351_port_set_ether_type, 3302 .port_pause_limit = mv88e6390_port_pause_limit, 3303 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3304 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3305 .port_link_state = mv88e6352_port_link_state, 3306 .port_get_cmode = mv88e6352_port_get_cmode, 3307 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3308 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3309 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3310 .stats_get_strings = mv88e6320_stats_get_strings, 3311 .stats_get_stats = mv88e6390_stats_get_stats, 3312 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3313 .set_egress_port = mv88e6390_g1_set_egress_port, 3314 .watchdog_ops = &mv88e6390_watchdog_ops, 3315 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3316 .pot_clear = mv88e6xxx_g2_pot_clear, 3317 .reset = mv88e6352_g1_reset, 3318 .rmu_disable = mv88e6390_g1_rmu_disable, 3319 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3320 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3321 .serdes_power = mv88e6390_serdes_power, 3322 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3323 .serdes_irq_free = mv88e6390_serdes_irq_free, 3324 .avb_ops = &mv88e6390_avb_ops, 3325 .ptp_ops = &mv88e6352_ptp_ops, 3326 .phylink_validate = mv88e6390_phylink_validate, 3327 }; 3328 3329 static const struct mv88e6xxx_ops mv88e6240_ops = { 3330 /* MV88E6XXX_FAMILY_6352 */ 3331 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3332 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3333 .irl_init_all = mv88e6352_g2_irl_init_all, 3334 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3335 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3336 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3337 .phy_read = mv88e6xxx_g2_smi_phy_read, 3338 .phy_write = mv88e6xxx_g2_smi_phy_write, 3339 .port_set_link = mv88e6xxx_port_set_link, 3340 .port_set_duplex = mv88e6xxx_port_set_duplex, 3341 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3342 .port_set_speed = mv88e6352_port_set_speed, 3343 .port_tag_remap = mv88e6095_port_tag_remap, 3344 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3345 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3346 .port_set_ether_type = mv88e6351_port_set_ether_type, 3347 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3348 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3349 .port_pause_limit = mv88e6097_port_pause_limit, 3350 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3351 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3352 .port_link_state = mv88e6352_port_link_state, 3353 .port_get_cmode = mv88e6352_port_get_cmode, 3354 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3355 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3356 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3357 .stats_get_strings = mv88e6095_stats_get_strings, 3358 .stats_get_stats = mv88e6095_stats_get_stats, 3359 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3360 .set_egress_port = mv88e6095_g1_set_egress_port, 3361 .watchdog_ops = &mv88e6097_watchdog_ops, 3362 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3363 .pot_clear = mv88e6xxx_g2_pot_clear, 3364 .reset = mv88e6352_g1_reset, 3365 .rmu_disable = mv88e6352_g1_rmu_disable, 3366 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3367 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3368 .serdes_power = mv88e6352_serdes_power, 3369 .gpio_ops = &mv88e6352_gpio_ops, 3370 .avb_ops = &mv88e6352_avb_ops, 3371 .ptp_ops = &mv88e6352_ptp_ops, 3372 .phylink_validate = mv88e6352_phylink_validate, 3373 }; 3374 3375 static const struct mv88e6xxx_ops mv88e6290_ops = { 3376 /* MV88E6XXX_FAMILY_6390 */ 3377 .irl_init_all = mv88e6390_g2_irl_init_all, 3378 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3379 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3380 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3381 .phy_read = mv88e6xxx_g2_smi_phy_read, 3382 .phy_write = mv88e6xxx_g2_smi_phy_write, 3383 .port_set_link = mv88e6xxx_port_set_link, 3384 .port_set_duplex = mv88e6xxx_port_set_duplex, 3385 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3386 .port_set_speed = mv88e6390_port_set_speed, 3387 .port_tag_remap = mv88e6390_port_tag_remap, 3388 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3389 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3390 .port_set_ether_type = mv88e6351_port_set_ether_type, 3391 .port_pause_limit = mv88e6390_port_pause_limit, 3392 .port_set_cmode = mv88e6390x_port_set_cmode, 3393 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3394 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3395 .port_link_state = mv88e6352_port_link_state, 3396 .port_get_cmode = mv88e6352_port_get_cmode, 3397 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3398 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3399 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3400 .stats_get_strings = mv88e6320_stats_get_strings, 3401 .stats_get_stats = mv88e6390_stats_get_stats, 3402 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3403 .set_egress_port = mv88e6390_g1_set_egress_port, 3404 .watchdog_ops = &mv88e6390_watchdog_ops, 3405 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3406 .pot_clear = mv88e6xxx_g2_pot_clear, 3407 .reset = mv88e6352_g1_reset, 3408 .rmu_disable = mv88e6390_g1_rmu_disable, 3409 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3410 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3411 .serdes_power = mv88e6390_serdes_power, 3412 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3413 .serdes_irq_free = mv88e6390_serdes_irq_free, 3414 .gpio_ops = &mv88e6352_gpio_ops, 3415 .avb_ops = &mv88e6390_avb_ops, 3416 .ptp_ops = &mv88e6352_ptp_ops, 3417 .phylink_validate = mv88e6390_phylink_validate, 3418 }; 3419 3420 static const struct mv88e6xxx_ops mv88e6320_ops = { 3421 /* MV88E6XXX_FAMILY_6320 */ 3422 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3423 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3424 .irl_init_all = mv88e6352_g2_irl_init_all, 3425 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3426 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3427 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3428 .phy_read = mv88e6xxx_g2_smi_phy_read, 3429 .phy_write = mv88e6xxx_g2_smi_phy_write, 3430 .port_set_link = mv88e6xxx_port_set_link, 3431 .port_set_duplex = mv88e6xxx_port_set_duplex, 3432 .port_set_speed = mv88e6185_port_set_speed, 3433 .port_tag_remap = mv88e6095_port_tag_remap, 3434 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3435 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3436 .port_set_ether_type = mv88e6351_port_set_ether_type, 3437 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3438 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3439 .port_pause_limit = mv88e6097_port_pause_limit, 3440 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3441 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3442 .port_link_state = mv88e6352_port_link_state, 3443 .port_get_cmode = mv88e6352_port_get_cmode, 3444 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3445 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3446 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3447 .stats_get_strings = mv88e6320_stats_get_strings, 3448 .stats_get_stats = mv88e6320_stats_get_stats, 3449 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3450 .set_egress_port = mv88e6095_g1_set_egress_port, 3451 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3452 .pot_clear = mv88e6xxx_g2_pot_clear, 3453 .reset = mv88e6352_g1_reset, 3454 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3455 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3456 .gpio_ops = &mv88e6352_gpio_ops, 3457 .avb_ops = &mv88e6352_avb_ops, 3458 .ptp_ops = &mv88e6352_ptp_ops, 3459 .phylink_validate = mv88e6185_phylink_validate, 3460 }; 3461 3462 static const struct mv88e6xxx_ops mv88e6321_ops = { 3463 /* MV88E6XXX_FAMILY_6320 */ 3464 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3465 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3466 .irl_init_all = mv88e6352_g2_irl_init_all, 3467 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3468 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3469 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3470 .phy_read = mv88e6xxx_g2_smi_phy_read, 3471 .phy_write = mv88e6xxx_g2_smi_phy_write, 3472 .port_set_link = mv88e6xxx_port_set_link, 3473 .port_set_duplex = mv88e6xxx_port_set_duplex, 3474 .port_set_speed = mv88e6185_port_set_speed, 3475 .port_tag_remap = mv88e6095_port_tag_remap, 3476 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3477 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3478 .port_set_ether_type = mv88e6351_port_set_ether_type, 3479 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3480 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3481 .port_pause_limit = mv88e6097_port_pause_limit, 3482 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3483 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3484 .port_link_state = mv88e6352_port_link_state, 3485 .port_get_cmode = mv88e6352_port_get_cmode, 3486 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3487 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3488 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3489 .stats_get_strings = mv88e6320_stats_get_strings, 3490 .stats_get_stats = mv88e6320_stats_get_stats, 3491 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3492 .set_egress_port = mv88e6095_g1_set_egress_port, 3493 .reset = mv88e6352_g1_reset, 3494 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3495 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3496 .gpio_ops = &mv88e6352_gpio_ops, 3497 .avb_ops = &mv88e6352_avb_ops, 3498 .ptp_ops = &mv88e6352_ptp_ops, 3499 .phylink_validate = mv88e6185_phylink_validate, 3500 }; 3501 3502 static const struct mv88e6xxx_ops mv88e6341_ops = { 3503 /* MV88E6XXX_FAMILY_6341 */ 3504 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3505 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3506 .irl_init_all = mv88e6352_g2_irl_init_all, 3507 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3508 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3509 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3510 .phy_read = mv88e6xxx_g2_smi_phy_read, 3511 .phy_write = mv88e6xxx_g2_smi_phy_write, 3512 .port_set_link = mv88e6xxx_port_set_link, 3513 .port_set_duplex = mv88e6xxx_port_set_duplex, 3514 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3515 .port_set_speed = mv88e6390_port_set_speed, 3516 .port_tag_remap = mv88e6095_port_tag_remap, 3517 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3518 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3519 .port_set_ether_type = mv88e6351_port_set_ether_type, 3520 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3521 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3522 .port_pause_limit = mv88e6097_port_pause_limit, 3523 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3524 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3525 .port_link_state = mv88e6352_port_link_state, 3526 .port_get_cmode = mv88e6352_port_get_cmode, 3527 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3528 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3529 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3530 .stats_get_strings = mv88e6320_stats_get_strings, 3531 .stats_get_stats = mv88e6390_stats_get_stats, 3532 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3533 .set_egress_port = mv88e6390_g1_set_egress_port, 3534 .watchdog_ops = &mv88e6390_watchdog_ops, 3535 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3536 .pot_clear = mv88e6xxx_g2_pot_clear, 3537 .reset = mv88e6352_g1_reset, 3538 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3539 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3540 .serdes_power = mv88e6341_serdes_power, 3541 .gpio_ops = &mv88e6352_gpio_ops, 3542 .avb_ops = &mv88e6390_avb_ops, 3543 .ptp_ops = &mv88e6352_ptp_ops, 3544 .phylink_validate = mv88e6390_phylink_validate, 3545 }; 3546 3547 static const struct mv88e6xxx_ops mv88e6350_ops = { 3548 /* MV88E6XXX_FAMILY_6351 */ 3549 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3550 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3551 .irl_init_all = mv88e6352_g2_irl_init_all, 3552 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3553 .phy_read = mv88e6xxx_g2_smi_phy_read, 3554 .phy_write = mv88e6xxx_g2_smi_phy_write, 3555 .port_set_link = mv88e6xxx_port_set_link, 3556 .port_set_duplex = mv88e6xxx_port_set_duplex, 3557 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3558 .port_set_speed = mv88e6185_port_set_speed, 3559 .port_tag_remap = mv88e6095_port_tag_remap, 3560 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3561 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3562 .port_set_ether_type = mv88e6351_port_set_ether_type, 3563 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3564 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3565 .port_pause_limit = mv88e6097_port_pause_limit, 3566 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3567 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3568 .port_link_state = mv88e6352_port_link_state, 3569 .port_get_cmode = mv88e6352_port_get_cmode, 3570 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3571 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3572 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3573 .stats_get_strings = mv88e6095_stats_get_strings, 3574 .stats_get_stats = mv88e6095_stats_get_stats, 3575 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3576 .set_egress_port = mv88e6095_g1_set_egress_port, 3577 .watchdog_ops = &mv88e6097_watchdog_ops, 3578 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3579 .pot_clear = mv88e6xxx_g2_pot_clear, 3580 .reset = mv88e6352_g1_reset, 3581 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3582 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3583 .phylink_validate = mv88e6185_phylink_validate, 3584 }; 3585 3586 static const struct mv88e6xxx_ops mv88e6351_ops = { 3587 /* MV88E6XXX_FAMILY_6351 */ 3588 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3589 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3590 .irl_init_all = mv88e6352_g2_irl_init_all, 3591 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3592 .phy_read = mv88e6xxx_g2_smi_phy_read, 3593 .phy_write = mv88e6xxx_g2_smi_phy_write, 3594 .port_set_link = mv88e6xxx_port_set_link, 3595 .port_set_duplex = mv88e6xxx_port_set_duplex, 3596 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3597 .port_set_speed = mv88e6185_port_set_speed, 3598 .port_tag_remap = mv88e6095_port_tag_remap, 3599 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3600 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3601 .port_set_ether_type = mv88e6351_port_set_ether_type, 3602 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3603 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3604 .port_pause_limit = mv88e6097_port_pause_limit, 3605 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3606 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3607 .port_link_state = mv88e6352_port_link_state, 3608 .port_get_cmode = mv88e6352_port_get_cmode, 3609 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3610 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3611 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3612 .stats_get_strings = mv88e6095_stats_get_strings, 3613 .stats_get_stats = mv88e6095_stats_get_stats, 3614 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3615 .set_egress_port = mv88e6095_g1_set_egress_port, 3616 .watchdog_ops = &mv88e6097_watchdog_ops, 3617 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3618 .pot_clear = mv88e6xxx_g2_pot_clear, 3619 .reset = mv88e6352_g1_reset, 3620 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3621 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3622 .avb_ops = &mv88e6352_avb_ops, 3623 .ptp_ops = &mv88e6352_ptp_ops, 3624 .phylink_validate = mv88e6185_phylink_validate, 3625 }; 3626 3627 static const struct mv88e6xxx_ops mv88e6352_ops = { 3628 /* MV88E6XXX_FAMILY_6352 */ 3629 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3630 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3631 .irl_init_all = mv88e6352_g2_irl_init_all, 3632 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3633 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3634 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3635 .phy_read = mv88e6xxx_g2_smi_phy_read, 3636 .phy_write = mv88e6xxx_g2_smi_phy_write, 3637 .port_set_link = mv88e6xxx_port_set_link, 3638 .port_set_duplex = mv88e6xxx_port_set_duplex, 3639 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3640 .port_set_speed = mv88e6352_port_set_speed, 3641 .port_tag_remap = mv88e6095_port_tag_remap, 3642 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3643 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3644 .port_set_ether_type = mv88e6351_port_set_ether_type, 3645 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3646 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3647 .port_pause_limit = mv88e6097_port_pause_limit, 3648 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3649 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3650 .port_link_state = mv88e6352_port_link_state, 3651 .port_get_cmode = mv88e6352_port_get_cmode, 3652 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3653 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3654 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3655 .stats_get_strings = mv88e6095_stats_get_strings, 3656 .stats_get_stats = mv88e6095_stats_get_stats, 3657 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3658 .set_egress_port = mv88e6095_g1_set_egress_port, 3659 .watchdog_ops = &mv88e6097_watchdog_ops, 3660 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3661 .pot_clear = mv88e6xxx_g2_pot_clear, 3662 .reset = mv88e6352_g1_reset, 3663 .rmu_disable = mv88e6352_g1_rmu_disable, 3664 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3665 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3666 .serdes_power = mv88e6352_serdes_power, 3667 .gpio_ops = &mv88e6352_gpio_ops, 3668 .avb_ops = &mv88e6352_avb_ops, 3669 .ptp_ops = &mv88e6352_ptp_ops, 3670 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 3671 .serdes_get_strings = mv88e6352_serdes_get_strings, 3672 .serdes_get_stats = mv88e6352_serdes_get_stats, 3673 .phylink_validate = mv88e6352_phylink_validate, 3674 }; 3675 3676 static const struct mv88e6xxx_ops mv88e6390_ops = { 3677 /* MV88E6XXX_FAMILY_6390 */ 3678 .irl_init_all = mv88e6390_g2_irl_init_all, 3679 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3680 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3681 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3682 .phy_read = mv88e6xxx_g2_smi_phy_read, 3683 .phy_write = mv88e6xxx_g2_smi_phy_write, 3684 .port_set_link = mv88e6xxx_port_set_link, 3685 .port_set_duplex = mv88e6xxx_port_set_duplex, 3686 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3687 .port_set_speed = mv88e6390_port_set_speed, 3688 .port_tag_remap = mv88e6390_port_tag_remap, 3689 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3690 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3691 .port_set_ether_type = mv88e6351_port_set_ether_type, 3692 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3693 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3694 .port_pause_limit = mv88e6390_port_pause_limit, 3695 .port_set_cmode = mv88e6390x_port_set_cmode, 3696 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3697 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3698 .port_link_state = mv88e6352_port_link_state, 3699 .port_get_cmode = mv88e6352_port_get_cmode, 3700 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3701 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3702 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3703 .stats_get_strings = mv88e6320_stats_get_strings, 3704 .stats_get_stats = mv88e6390_stats_get_stats, 3705 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3706 .set_egress_port = mv88e6390_g1_set_egress_port, 3707 .watchdog_ops = &mv88e6390_watchdog_ops, 3708 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3709 .pot_clear = mv88e6xxx_g2_pot_clear, 3710 .reset = mv88e6352_g1_reset, 3711 .rmu_disable = mv88e6390_g1_rmu_disable, 3712 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3713 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3714 .serdes_power = mv88e6390_serdes_power, 3715 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3716 .serdes_irq_free = mv88e6390_serdes_irq_free, 3717 .gpio_ops = &mv88e6352_gpio_ops, 3718 .avb_ops = &mv88e6390_avb_ops, 3719 .ptp_ops = &mv88e6352_ptp_ops, 3720 .phylink_validate = mv88e6390_phylink_validate, 3721 }; 3722 3723 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3724 /* MV88E6XXX_FAMILY_6390 */ 3725 .irl_init_all = mv88e6390_g2_irl_init_all, 3726 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3727 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3728 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3729 .phy_read = mv88e6xxx_g2_smi_phy_read, 3730 .phy_write = mv88e6xxx_g2_smi_phy_write, 3731 .port_set_link = mv88e6xxx_port_set_link, 3732 .port_set_duplex = mv88e6xxx_port_set_duplex, 3733 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3734 .port_set_speed = mv88e6390x_port_set_speed, 3735 .port_tag_remap = mv88e6390_port_tag_remap, 3736 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3737 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3738 .port_set_ether_type = mv88e6351_port_set_ether_type, 3739 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3740 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3741 .port_pause_limit = mv88e6390_port_pause_limit, 3742 .port_set_cmode = mv88e6390x_port_set_cmode, 3743 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3744 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3745 .port_link_state = mv88e6352_port_link_state, 3746 .port_get_cmode = mv88e6352_port_get_cmode, 3747 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3748 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3749 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3750 .stats_get_strings = mv88e6320_stats_get_strings, 3751 .stats_get_stats = mv88e6390_stats_get_stats, 3752 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3753 .set_egress_port = mv88e6390_g1_set_egress_port, 3754 .watchdog_ops = &mv88e6390_watchdog_ops, 3755 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3756 .pot_clear = mv88e6xxx_g2_pot_clear, 3757 .reset = mv88e6352_g1_reset, 3758 .rmu_disable = mv88e6390_g1_rmu_disable, 3759 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3760 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3761 .serdes_power = mv88e6390x_serdes_power, 3762 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3763 .serdes_irq_free = mv88e6390_serdes_irq_free, 3764 .gpio_ops = &mv88e6352_gpio_ops, 3765 .avb_ops = &mv88e6390_avb_ops, 3766 .ptp_ops = &mv88e6352_ptp_ops, 3767 .phylink_validate = mv88e6390x_phylink_validate, 3768 }; 3769 3770 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3771 [MV88E6085] = { 3772 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3773 .family = MV88E6XXX_FAMILY_6097, 3774 .name = "Marvell 88E6085", 3775 .num_databases = 4096, 3776 .num_ports = 10, 3777 .num_internal_phys = 5, 3778 .max_vid = 4095, 3779 .port_base_addr = 0x10, 3780 .phy_base_addr = 0x0, 3781 .global1_addr = 0x1b, 3782 .global2_addr = 0x1c, 3783 .age_time_coeff = 15000, 3784 .g1_irqs = 8, 3785 .g2_irqs = 10, 3786 .atu_move_port_mask = 0xf, 3787 .pvt = true, 3788 .multi_chip = true, 3789 .tag_protocol = DSA_TAG_PROTO_DSA, 3790 .ops = &mv88e6085_ops, 3791 }, 3792 3793 [MV88E6095] = { 3794 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3795 .family = MV88E6XXX_FAMILY_6095, 3796 .name = "Marvell 88E6095/88E6095F", 3797 .num_databases = 256, 3798 .num_ports = 11, 3799 .num_internal_phys = 0, 3800 .max_vid = 4095, 3801 .port_base_addr = 0x10, 3802 .phy_base_addr = 0x0, 3803 .global1_addr = 0x1b, 3804 .global2_addr = 0x1c, 3805 .age_time_coeff = 15000, 3806 .g1_irqs = 8, 3807 .atu_move_port_mask = 0xf, 3808 .multi_chip = true, 3809 .tag_protocol = DSA_TAG_PROTO_DSA, 3810 .ops = &mv88e6095_ops, 3811 }, 3812 3813 [MV88E6097] = { 3814 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 3815 .family = MV88E6XXX_FAMILY_6097, 3816 .name = "Marvell 88E6097/88E6097F", 3817 .num_databases = 4096, 3818 .num_ports = 11, 3819 .num_internal_phys = 8, 3820 .max_vid = 4095, 3821 .port_base_addr = 0x10, 3822 .phy_base_addr = 0x0, 3823 .global1_addr = 0x1b, 3824 .global2_addr = 0x1c, 3825 .age_time_coeff = 15000, 3826 .g1_irqs = 8, 3827 .g2_irqs = 10, 3828 .atu_move_port_mask = 0xf, 3829 .pvt = true, 3830 .multi_chip = true, 3831 .tag_protocol = DSA_TAG_PROTO_EDSA, 3832 .ops = &mv88e6097_ops, 3833 }, 3834 3835 [MV88E6123] = { 3836 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 3837 .family = MV88E6XXX_FAMILY_6165, 3838 .name = "Marvell 88E6123", 3839 .num_databases = 4096, 3840 .num_ports = 3, 3841 .num_internal_phys = 5, 3842 .max_vid = 4095, 3843 .port_base_addr = 0x10, 3844 .phy_base_addr = 0x0, 3845 .global1_addr = 0x1b, 3846 .global2_addr = 0x1c, 3847 .age_time_coeff = 15000, 3848 .g1_irqs = 9, 3849 .g2_irqs = 10, 3850 .atu_move_port_mask = 0xf, 3851 .pvt = true, 3852 .multi_chip = true, 3853 .tag_protocol = DSA_TAG_PROTO_EDSA, 3854 .ops = &mv88e6123_ops, 3855 }, 3856 3857 [MV88E6131] = { 3858 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 3859 .family = MV88E6XXX_FAMILY_6185, 3860 .name = "Marvell 88E6131", 3861 .num_databases = 256, 3862 .num_ports = 8, 3863 .num_internal_phys = 0, 3864 .max_vid = 4095, 3865 .port_base_addr = 0x10, 3866 .phy_base_addr = 0x0, 3867 .global1_addr = 0x1b, 3868 .global2_addr = 0x1c, 3869 .age_time_coeff = 15000, 3870 .g1_irqs = 9, 3871 .atu_move_port_mask = 0xf, 3872 .multi_chip = true, 3873 .tag_protocol = DSA_TAG_PROTO_DSA, 3874 .ops = &mv88e6131_ops, 3875 }, 3876 3877 [MV88E6141] = { 3878 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 3879 .family = MV88E6XXX_FAMILY_6341, 3880 .name = "Marvell 88E6141", 3881 .num_databases = 4096, 3882 .num_ports = 6, 3883 .num_internal_phys = 5, 3884 .num_gpio = 11, 3885 .max_vid = 4095, 3886 .port_base_addr = 0x10, 3887 .phy_base_addr = 0x10, 3888 .global1_addr = 0x1b, 3889 .global2_addr = 0x1c, 3890 .age_time_coeff = 3750, 3891 .atu_move_port_mask = 0x1f, 3892 .g1_irqs = 9, 3893 .g2_irqs = 10, 3894 .pvt = true, 3895 .multi_chip = true, 3896 .tag_protocol = DSA_TAG_PROTO_EDSA, 3897 .ops = &mv88e6141_ops, 3898 }, 3899 3900 [MV88E6161] = { 3901 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 3902 .family = MV88E6XXX_FAMILY_6165, 3903 .name = "Marvell 88E6161", 3904 .num_databases = 4096, 3905 .num_ports = 6, 3906 .num_internal_phys = 5, 3907 .max_vid = 4095, 3908 .port_base_addr = 0x10, 3909 .phy_base_addr = 0x0, 3910 .global1_addr = 0x1b, 3911 .global2_addr = 0x1c, 3912 .age_time_coeff = 15000, 3913 .g1_irqs = 9, 3914 .g2_irqs = 10, 3915 .atu_move_port_mask = 0xf, 3916 .pvt = true, 3917 .multi_chip = true, 3918 .tag_protocol = DSA_TAG_PROTO_EDSA, 3919 .ptp_support = true, 3920 .ops = &mv88e6161_ops, 3921 }, 3922 3923 [MV88E6165] = { 3924 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 3925 .family = MV88E6XXX_FAMILY_6165, 3926 .name = "Marvell 88E6165", 3927 .num_databases = 4096, 3928 .num_ports = 6, 3929 .num_internal_phys = 0, 3930 .max_vid = 4095, 3931 .port_base_addr = 0x10, 3932 .phy_base_addr = 0x0, 3933 .global1_addr = 0x1b, 3934 .global2_addr = 0x1c, 3935 .age_time_coeff = 15000, 3936 .g1_irqs = 9, 3937 .g2_irqs = 10, 3938 .atu_move_port_mask = 0xf, 3939 .pvt = true, 3940 .multi_chip = true, 3941 .tag_protocol = DSA_TAG_PROTO_DSA, 3942 .ptp_support = true, 3943 .ops = &mv88e6165_ops, 3944 }, 3945 3946 [MV88E6171] = { 3947 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 3948 .family = MV88E6XXX_FAMILY_6351, 3949 .name = "Marvell 88E6171", 3950 .num_databases = 4096, 3951 .num_ports = 7, 3952 .num_internal_phys = 5, 3953 .max_vid = 4095, 3954 .port_base_addr = 0x10, 3955 .phy_base_addr = 0x0, 3956 .global1_addr = 0x1b, 3957 .global2_addr = 0x1c, 3958 .age_time_coeff = 15000, 3959 .g1_irqs = 9, 3960 .g2_irqs = 10, 3961 .atu_move_port_mask = 0xf, 3962 .pvt = true, 3963 .multi_chip = true, 3964 .tag_protocol = DSA_TAG_PROTO_EDSA, 3965 .ops = &mv88e6171_ops, 3966 }, 3967 3968 [MV88E6172] = { 3969 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 3970 .family = MV88E6XXX_FAMILY_6352, 3971 .name = "Marvell 88E6172", 3972 .num_databases = 4096, 3973 .num_ports = 7, 3974 .num_internal_phys = 5, 3975 .num_gpio = 15, 3976 .max_vid = 4095, 3977 .port_base_addr = 0x10, 3978 .phy_base_addr = 0x0, 3979 .global1_addr = 0x1b, 3980 .global2_addr = 0x1c, 3981 .age_time_coeff = 15000, 3982 .g1_irqs = 9, 3983 .g2_irqs = 10, 3984 .atu_move_port_mask = 0xf, 3985 .pvt = true, 3986 .multi_chip = true, 3987 .tag_protocol = DSA_TAG_PROTO_EDSA, 3988 .ops = &mv88e6172_ops, 3989 }, 3990 3991 [MV88E6175] = { 3992 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 3993 .family = MV88E6XXX_FAMILY_6351, 3994 .name = "Marvell 88E6175", 3995 .num_databases = 4096, 3996 .num_ports = 7, 3997 .num_internal_phys = 5, 3998 .max_vid = 4095, 3999 .port_base_addr = 0x10, 4000 .phy_base_addr = 0x0, 4001 .global1_addr = 0x1b, 4002 .global2_addr = 0x1c, 4003 .age_time_coeff = 15000, 4004 .g1_irqs = 9, 4005 .g2_irqs = 10, 4006 .atu_move_port_mask = 0xf, 4007 .pvt = true, 4008 .multi_chip = true, 4009 .tag_protocol = DSA_TAG_PROTO_EDSA, 4010 .ops = &mv88e6175_ops, 4011 }, 4012 4013 [MV88E6176] = { 4014 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4015 .family = MV88E6XXX_FAMILY_6352, 4016 .name = "Marvell 88E6176", 4017 .num_databases = 4096, 4018 .num_ports = 7, 4019 .num_internal_phys = 5, 4020 .num_gpio = 15, 4021 .max_vid = 4095, 4022 .port_base_addr = 0x10, 4023 .phy_base_addr = 0x0, 4024 .global1_addr = 0x1b, 4025 .global2_addr = 0x1c, 4026 .age_time_coeff = 15000, 4027 .g1_irqs = 9, 4028 .g2_irqs = 10, 4029 .atu_move_port_mask = 0xf, 4030 .pvt = true, 4031 .multi_chip = true, 4032 .tag_protocol = DSA_TAG_PROTO_EDSA, 4033 .ops = &mv88e6176_ops, 4034 }, 4035 4036 [MV88E6185] = { 4037 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4038 .family = MV88E6XXX_FAMILY_6185, 4039 .name = "Marvell 88E6185", 4040 .num_databases = 256, 4041 .num_ports = 10, 4042 .num_internal_phys = 0, 4043 .max_vid = 4095, 4044 .port_base_addr = 0x10, 4045 .phy_base_addr = 0x0, 4046 .global1_addr = 0x1b, 4047 .global2_addr = 0x1c, 4048 .age_time_coeff = 15000, 4049 .g1_irqs = 8, 4050 .atu_move_port_mask = 0xf, 4051 .multi_chip = true, 4052 .tag_protocol = DSA_TAG_PROTO_EDSA, 4053 .ops = &mv88e6185_ops, 4054 }, 4055 4056 [MV88E6190] = { 4057 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4058 .family = MV88E6XXX_FAMILY_6390, 4059 .name = "Marvell 88E6190", 4060 .num_databases = 4096, 4061 .num_ports = 11, /* 10 + Z80 */ 4062 .num_internal_phys = 11, 4063 .num_gpio = 16, 4064 .max_vid = 8191, 4065 .port_base_addr = 0x0, 4066 .phy_base_addr = 0x0, 4067 .global1_addr = 0x1b, 4068 .global2_addr = 0x1c, 4069 .tag_protocol = DSA_TAG_PROTO_DSA, 4070 .age_time_coeff = 3750, 4071 .g1_irqs = 9, 4072 .g2_irqs = 14, 4073 .pvt = true, 4074 .multi_chip = true, 4075 .atu_move_port_mask = 0x1f, 4076 .ops = &mv88e6190_ops, 4077 }, 4078 4079 [MV88E6190X] = { 4080 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4081 .family = MV88E6XXX_FAMILY_6390, 4082 .name = "Marvell 88E6190X", 4083 .num_databases = 4096, 4084 .num_ports = 11, /* 10 + Z80 */ 4085 .num_internal_phys = 11, 4086 .num_gpio = 16, 4087 .max_vid = 8191, 4088 .port_base_addr = 0x0, 4089 .phy_base_addr = 0x0, 4090 .global1_addr = 0x1b, 4091 .global2_addr = 0x1c, 4092 .age_time_coeff = 3750, 4093 .g1_irqs = 9, 4094 .g2_irqs = 14, 4095 .atu_move_port_mask = 0x1f, 4096 .pvt = true, 4097 .multi_chip = true, 4098 .tag_protocol = DSA_TAG_PROTO_DSA, 4099 .ops = &mv88e6190x_ops, 4100 }, 4101 4102 [MV88E6191] = { 4103 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4104 .family = MV88E6XXX_FAMILY_6390, 4105 .name = "Marvell 88E6191", 4106 .num_databases = 4096, 4107 .num_ports = 11, /* 10 + Z80 */ 4108 .num_internal_phys = 11, 4109 .max_vid = 8191, 4110 .port_base_addr = 0x0, 4111 .phy_base_addr = 0x0, 4112 .global1_addr = 0x1b, 4113 .global2_addr = 0x1c, 4114 .age_time_coeff = 3750, 4115 .g1_irqs = 9, 4116 .g2_irqs = 14, 4117 .atu_move_port_mask = 0x1f, 4118 .pvt = true, 4119 .multi_chip = true, 4120 .tag_protocol = DSA_TAG_PROTO_DSA, 4121 .ptp_support = true, 4122 .ops = &mv88e6191_ops, 4123 }, 4124 4125 [MV88E6240] = { 4126 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 4127 .family = MV88E6XXX_FAMILY_6352, 4128 .name = "Marvell 88E6240", 4129 .num_databases = 4096, 4130 .num_ports = 7, 4131 .num_internal_phys = 5, 4132 .num_gpio = 15, 4133 .max_vid = 4095, 4134 .port_base_addr = 0x10, 4135 .phy_base_addr = 0x0, 4136 .global1_addr = 0x1b, 4137 .global2_addr = 0x1c, 4138 .age_time_coeff = 15000, 4139 .g1_irqs = 9, 4140 .g2_irqs = 10, 4141 .atu_move_port_mask = 0xf, 4142 .pvt = true, 4143 .multi_chip = true, 4144 .tag_protocol = DSA_TAG_PROTO_EDSA, 4145 .ptp_support = true, 4146 .ops = &mv88e6240_ops, 4147 }, 4148 4149 [MV88E6290] = { 4150 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 4151 .family = MV88E6XXX_FAMILY_6390, 4152 .name = "Marvell 88E6290", 4153 .num_databases = 4096, 4154 .num_ports = 11, /* 10 + Z80 */ 4155 .num_internal_phys = 11, 4156 .num_gpio = 16, 4157 .max_vid = 8191, 4158 .port_base_addr = 0x0, 4159 .phy_base_addr = 0x0, 4160 .global1_addr = 0x1b, 4161 .global2_addr = 0x1c, 4162 .age_time_coeff = 3750, 4163 .g1_irqs = 9, 4164 .g2_irqs = 14, 4165 .atu_move_port_mask = 0x1f, 4166 .pvt = true, 4167 .multi_chip = true, 4168 .tag_protocol = DSA_TAG_PROTO_DSA, 4169 .ptp_support = true, 4170 .ops = &mv88e6290_ops, 4171 }, 4172 4173 [MV88E6320] = { 4174 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 4175 .family = MV88E6XXX_FAMILY_6320, 4176 .name = "Marvell 88E6320", 4177 .num_databases = 4096, 4178 .num_ports = 7, 4179 .num_internal_phys = 5, 4180 .num_gpio = 15, 4181 .max_vid = 4095, 4182 .port_base_addr = 0x10, 4183 .phy_base_addr = 0x0, 4184 .global1_addr = 0x1b, 4185 .global2_addr = 0x1c, 4186 .age_time_coeff = 15000, 4187 .g1_irqs = 8, 4188 .g2_irqs = 10, 4189 .atu_move_port_mask = 0xf, 4190 .pvt = true, 4191 .multi_chip = true, 4192 .tag_protocol = DSA_TAG_PROTO_EDSA, 4193 .ptp_support = true, 4194 .ops = &mv88e6320_ops, 4195 }, 4196 4197 [MV88E6321] = { 4198 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 4199 .family = MV88E6XXX_FAMILY_6320, 4200 .name = "Marvell 88E6321", 4201 .num_databases = 4096, 4202 .num_ports = 7, 4203 .num_internal_phys = 5, 4204 .num_gpio = 15, 4205 .max_vid = 4095, 4206 .port_base_addr = 0x10, 4207 .phy_base_addr = 0x0, 4208 .global1_addr = 0x1b, 4209 .global2_addr = 0x1c, 4210 .age_time_coeff = 15000, 4211 .g1_irqs = 8, 4212 .g2_irqs = 10, 4213 .atu_move_port_mask = 0xf, 4214 .multi_chip = true, 4215 .tag_protocol = DSA_TAG_PROTO_EDSA, 4216 .ptp_support = true, 4217 .ops = &mv88e6321_ops, 4218 }, 4219 4220 [MV88E6341] = { 4221 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 4222 .family = MV88E6XXX_FAMILY_6341, 4223 .name = "Marvell 88E6341", 4224 .num_databases = 4096, 4225 .num_internal_phys = 5, 4226 .num_ports = 6, 4227 .num_gpio = 11, 4228 .max_vid = 4095, 4229 .port_base_addr = 0x10, 4230 .phy_base_addr = 0x10, 4231 .global1_addr = 0x1b, 4232 .global2_addr = 0x1c, 4233 .age_time_coeff = 3750, 4234 .atu_move_port_mask = 0x1f, 4235 .g1_irqs = 9, 4236 .g2_irqs = 10, 4237 .pvt = true, 4238 .multi_chip = true, 4239 .tag_protocol = DSA_TAG_PROTO_EDSA, 4240 .ptp_support = true, 4241 .ops = &mv88e6341_ops, 4242 }, 4243 4244 [MV88E6350] = { 4245 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 4246 .family = MV88E6XXX_FAMILY_6351, 4247 .name = "Marvell 88E6350", 4248 .num_databases = 4096, 4249 .num_ports = 7, 4250 .num_internal_phys = 5, 4251 .max_vid = 4095, 4252 .port_base_addr = 0x10, 4253 .phy_base_addr = 0x0, 4254 .global1_addr = 0x1b, 4255 .global2_addr = 0x1c, 4256 .age_time_coeff = 15000, 4257 .g1_irqs = 9, 4258 .g2_irqs = 10, 4259 .atu_move_port_mask = 0xf, 4260 .pvt = true, 4261 .multi_chip = true, 4262 .tag_protocol = DSA_TAG_PROTO_EDSA, 4263 .ops = &mv88e6350_ops, 4264 }, 4265 4266 [MV88E6351] = { 4267 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 4268 .family = MV88E6XXX_FAMILY_6351, 4269 .name = "Marvell 88E6351", 4270 .num_databases = 4096, 4271 .num_ports = 7, 4272 .num_internal_phys = 5, 4273 .max_vid = 4095, 4274 .port_base_addr = 0x10, 4275 .phy_base_addr = 0x0, 4276 .global1_addr = 0x1b, 4277 .global2_addr = 0x1c, 4278 .age_time_coeff = 15000, 4279 .g1_irqs = 9, 4280 .g2_irqs = 10, 4281 .atu_move_port_mask = 0xf, 4282 .pvt = true, 4283 .multi_chip = true, 4284 .tag_protocol = DSA_TAG_PROTO_EDSA, 4285 .ops = &mv88e6351_ops, 4286 }, 4287 4288 [MV88E6352] = { 4289 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 4290 .family = MV88E6XXX_FAMILY_6352, 4291 .name = "Marvell 88E6352", 4292 .num_databases = 4096, 4293 .num_ports = 7, 4294 .num_internal_phys = 5, 4295 .num_gpio = 15, 4296 .max_vid = 4095, 4297 .port_base_addr = 0x10, 4298 .phy_base_addr = 0x0, 4299 .global1_addr = 0x1b, 4300 .global2_addr = 0x1c, 4301 .age_time_coeff = 15000, 4302 .g1_irqs = 9, 4303 .g2_irqs = 10, 4304 .atu_move_port_mask = 0xf, 4305 .pvt = true, 4306 .multi_chip = true, 4307 .tag_protocol = DSA_TAG_PROTO_EDSA, 4308 .ptp_support = true, 4309 .ops = &mv88e6352_ops, 4310 }, 4311 [MV88E6390] = { 4312 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 4313 .family = MV88E6XXX_FAMILY_6390, 4314 .name = "Marvell 88E6390", 4315 .num_databases = 4096, 4316 .num_ports = 11, /* 10 + Z80 */ 4317 .num_internal_phys = 11, 4318 .num_gpio = 16, 4319 .max_vid = 8191, 4320 .port_base_addr = 0x0, 4321 .phy_base_addr = 0x0, 4322 .global1_addr = 0x1b, 4323 .global2_addr = 0x1c, 4324 .age_time_coeff = 3750, 4325 .g1_irqs = 9, 4326 .g2_irqs = 14, 4327 .atu_move_port_mask = 0x1f, 4328 .pvt = true, 4329 .multi_chip = true, 4330 .tag_protocol = DSA_TAG_PROTO_DSA, 4331 .ptp_support = true, 4332 .ops = &mv88e6390_ops, 4333 }, 4334 [MV88E6390X] = { 4335 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 4336 .family = MV88E6XXX_FAMILY_6390, 4337 .name = "Marvell 88E6390X", 4338 .num_databases = 4096, 4339 .num_ports = 11, /* 10 + Z80 */ 4340 .num_internal_phys = 11, 4341 .num_gpio = 16, 4342 .max_vid = 8191, 4343 .port_base_addr = 0x0, 4344 .phy_base_addr = 0x0, 4345 .global1_addr = 0x1b, 4346 .global2_addr = 0x1c, 4347 .age_time_coeff = 3750, 4348 .g1_irqs = 9, 4349 .g2_irqs = 14, 4350 .atu_move_port_mask = 0x1f, 4351 .pvt = true, 4352 .multi_chip = true, 4353 .tag_protocol = DSA_TAG_PROTO_DSA, 4354 .ptp_support = true, 4355 .ops = &mv88e6390x_ops, 4356 }, 4357 }; 4358 4359 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 4360 { 4361 int i; 4362 4363 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 4364 if (mv88e6xxx_table[i].prod_num == prod_num) 4365 return &mv88e6xxx_table[i]; 4366 4367 return NULL; 4368 } 4369 4370 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 4371 { 4372 const struct mv88e6xxx_info *info; 4373 unsigned int prod_num, rev; 4374 u16 id; 4375 int err; 4376 4377 mutex_lock(&chip->reg_lock); 4378 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 4379 mutex_unlock(&chip->reg_lock); 4380 if (err) 4381 return err; 4382 4383 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 4384 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 4385 4386 info = mv88e6xxx_lookup_info(prod_num); 4387 if (!info) 4388 return -ENODEV; 4389 4390 /* Update the compatible info with the probed one */ 4391 chip->info = info; 4392 4393 err = mv88e6xxx_g2_require(chip); 4394 if (err) 4395 return err; 4396 4397 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 4398 chip->info->prod_num, chip->info->name, rev); 4399 4400 return 0; 4401 } 4402 4403 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 4404 { 4405 struct mv88e6xxx_chip *chip; 4406 4407 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 4408 if (!chip) 4409 return NULL; 4410 4411 chip->dev = dev; 4412 4413 mutex_init(&chip->reg_lock); 4414 INIT_LIST_HEAD(&chip->mdios); 4415 4416 return chip; 4417 } 4418 4419 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 4420 struct mii_bus *bus, int sw_addr) 4421 { 4422 if (sw_addr == 0) 4423 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 4424 else if (chip->info->multi_chip) 4425 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 4426 else 4427 return -EINVAL; 4428 4429 chip->bus = bus; 4430 chip->sw_addr = sw_addr; 4431 4432 return 0; 4433 } 4434 4435 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 4436 int port) 4437 { 4438 struct mv88e6xxx_chip *chip = ds->priv; 4439 4440 return chip->info->tag_protocol; 4441 } 4442 4443 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 4444 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 4445 struct device *host_dev, int sw_addr, 4446 void **priv) 4447 { 4448 struct mv88e6xxx_chip *chip; 4449 struct mii_bus *bus; 4450 int err; 4451 4452 bus = dsa_host_dev_to_mii_bus(host_dev); 4453 if (!bus) 4454 return NULL; 4455 4456 chip = mv88e6xxx_alloc_chip(dsa_dev); 4457 if (!chip) 4458 return NULL; 4459 4460 /* Legacy SMI probing will only support chips similar to 88E6085 */ 4461 chip->info = &mv88e6xxx_table[MV88E6085]; 4462 4463 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 4464 if (err) 4465 goto free; 4466 4467 err = mv88e6xxx_detect(chip); 4468 if (err) 4469 goto free; 4470 4471 mutex_lock(&chip->reg_lock); 4472 err = mv88e6xxx_switch_reset(chip); 4473 mutex_unlock(&chip->reg_lock); 4474 if (err) 4475 goto free; 4476 4477 mv88e6xxx_phy_init(chip); 4478 4479 err = mv88e6xxx_mdios_register(chip, NULL); 4480 if (err) 4481 goto free; 4482 4483 *priv = chip; 4484 4485 return chip->info->name; 4486 free: 4487 devm_kfree(dsa_dev, chip); 4488 4489 return NULL; 4490 } 4491 #endif 4492 4493 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 4494 const struct switchdev_obj_port_mdb *mdb) 4495 { 4496 /* We don't need any dynamic resource from the kernel (yet), 4497 * so skip the prepare phase. 4498 */ 4499 4500 return 0; 4501 } 4502 4503 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 4504 const struct switchdev_obj_port_mdb *mdb) 4505 { 4506 struct mv88e6xxx_chip *chip = ds->priv; 4507 4508 mutex_lock(&chip->reg_lock); 4509 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4510 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 4511 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 4512 port); 4513 mutex_unlock(&chip->reg_lock); 4514 } 4515 4516 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 4517 const struct switchdev_obj_port_mdb *mdb) 4518 { 4519 struct mv88e6xxx_chip *chip = ds->priv; 4520 int err; 4521 4522 mutex_lock(&chip->reg_lock); 4523 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4524 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 4525 mutex_unlock(&chip->reg_lock); 4526 4527 return err; 4528 } 4529 4530 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 4531 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 4532 .probe = mv88e6xxx_drv_probe, 4533 #endif 4534 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 4535 .setup = mv88e6xxx_setup, 4536 .adjust_link = mv88e6xxx_adjust_link, 4537 .phylink_validate = mv88e6xxx_validate, 4538 .phylink_mac_link_state = mv88e6xxx_link_state, 4539 .phylink_mac_config = mv88e6xxx_mac_config, 4540 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 4541 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 4542 .get_strings = mv88e6xxx_get_strings, 4543 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 4544 .get_sset_count = mv88e6xxx_get_sset_count, 4545 .port_enable = mv88e6xxx_port_enable, 4546 .port_disable = mv88e6xxx_port_disable, 4547 .get_mac_eee = mv88e6xxx_get_mac_eee, 4548 .set_mac_eee = mv88e6xxx_set_mac_eee, 4549 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 4550 .get_eeprom = mv88e6xxx_get_eeprom, 4551 .set_eeprom = mv88e6xxx_set_eeprom, 4552 .get_regs_len = mv88e6xxx_get_regs_len, 4553 .get_regs = mv88e6xxx_get_regs, 4554 .set_ageing_time = mv88e6xxx_set_ageing_time, 4555 .port_bridge_join = mv88e6xxx_port_bridge_join, 4556 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 4557 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 4558 .port_fast_age = mv88e6xxx_port_fast_age, 4559 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 4560 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 4561 .port_vlan_add = mv88e6xxx_port_vlan_add, 4562 .port_vlan_del = mv88e6xxx_port_vlan_del, 4563 .port_fdb_add = mv88e6xxx_port_fdb_add, 4564 .port_fdb_del = mv88e6xxx_port_fdb_del, 4565 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4566 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 4567 .port_mdb_add = mv88e6xxx_port_mdb_add, 4568 .port_mdb_del = mv88e6xxx_port_mdb_del, 4569 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 4570 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 4571 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 4572 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 4573 .port_txtstamp = mv88e6xxx_port_txtstamp, 4574 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 4575 .get_ts_info = mv88e6xxx_get_ts_info, 4576 }; 4577 4578 static struct dsa_switch_driver mv88e6xxx_switch_drv = { 4579 .ops = &mv88e6xxx_switch_ops, 4580 }; 4581 4582 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 4583 { 4584 struct device *dev = chip->dev; 4585 struct dsa_switch *ds; 4586 4587 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 4588 if (!ds) 4589 return -ENOMEM; 4590 4591 ds->priv = chip; 4592 ds->dev = dev; 4593 ds->ops = &mv88e6xxx_switch_ops; 4594 ds->ageing_time_min = chip->info->age_time_coeff; 4595 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 4596 4597 dev_set_drvdata(dev, ds); 4598 4599 return dsa_register_switch(ds); 4600 } 4601 4602 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 4603 { 4604 dsa_unregister_switch(chip->ds); 4605 } 4606 4607 static const void *pdata_device_get_match_data(struct device *dev) 4608 { 4609 const struct of_device_id *matches = dev->driver->of_match_table; 4610 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 4611 4612 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 4613 matches++) { 4614 if (!strcmp(pdata->compatible, matches->compatible)) 4615 return matches->data; 4616 } 4617 return NULL; 4618 } 4619 4620 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 4621 { 4622 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 4623 const struct mv88e6xxx_info *compat_info = NULL; 4624 struct device *dev = &mdiodev->dev; 4625 struct device_node *np = dev->of_node; 4626 struct mv88e6xxx_chip *chip; 4627 int port; 4628 int err; 4629 4630 if (!np && !pdata) 4631 return -EINVAL; 4632 4633 if (np) 4634 compat_info = of_device_get_match_data(dev); 4635 4636 if (pdata) { 4637 compat_info = pdata_device_get_match_data(dev); 4638 4639 if (!pdata->netdev) 4640 return -EINVAL; 4641 4642 for (port = 0; port < DSA_MAX_PORTS; port++) { 4643 if (!(pdata->enabled_ports & (1 << port))) 4644 continue; 4645 if (strcmp(pdata->cd.port_names[port], "cpu")) 4646 continue; 4647 pdata->cd.netdev[port] = &pdata->netdev->dev; 4648 break; 4649 } 4650 } 4651 4652 if (!compat_info) 4653 return -EINVAL; 4654 4655 chip = mv88e6xxx_alloc_chip(dev); 4656 if (!chip) { 4657 err = -ENOMEM; 4658 goto out; 4659 } 4660 4661 chip->info = compat_info; 4662 4663 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 4664 if (err) 4665 goto out; 4666 4667 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 4668 if (IS_ERR(chip->reset)) { 4669 err = PTR_ERR(chip->reset); 4670 goto out; 4671 } 4672 4673 err = mv88e6xxx_detect(chip); 4674 if (err) 4675 goto out; 4676 4677 mv88e6xxx_phy_init(chip); 4678 4679 if (chip->info->ops->get_eeprom) { 4680 if (np) 4681 of_property_read_u32(np, "eeprom-length", 4682 &chip->eeprom_len); 4683 else 4684 chip->eeprom_len = pdata->eeprom_len; 4685 } 4686 4687 mutex_lock(&chip->reg_lock); 4688 err = mv88e6xxx_switch_reset(chip); 4689 mutex_unlock(&chip->reg_lock); 4690 if (err) 4691 goto out; 4692 4693 chip->irq = of_irq_get(np, 0); 4694 if (chip->irq == -EPROBE_DEFER) { 4695 err = chip->irq; 4696 goto out; 4697 } 4698 4699 /* Has to be performed before the MDIO bus is created, because 4700 * the PHYs will link their interrupts to these interrupt 4701 * controllers 4702 */ 4703 mutex_lock(&chip->reg_lock); 4704 if (chip->irq > 0) 4705 err = mv88e6xxx_g1_irq_setup(chip); 4706 else 4707 err = mv88e6xxx_irq_poll_setup(chip); 4708 mutex_unlock(&chip->reg_lock); 4709 4710 if (err) 4711 goto out; 4712 4713 if (chip->info->g2_irqs > 0) { 4714 err = mv88e6xxx_g2_irq_setup(chip); 4715 if (err) 4716 goto out_g1_irq; 4717 } 4718 4719 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 4720 if (err) 4721 goto out_g2_irq; 4722 4723 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 4724 if (err) 4725 goto out_g1_atu_prob_irq; 4726 4727 err = mv88e6xxx_mdios_register(chip, np); 4728 if (err) 4729 goto out_g1_vtu_prob_irq; 4730 4731 err = mv88e6xxx_register_switch(chip); 4732 if (err) 4733 goto out_mdio; 4734 4735 return 0; 4736 4737 out_mdio: 4738 mv88e6xxx_mdios_unregister(chip); 4739 out_g1_vtu_prob_irq: 4740 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4741 out_g1_atu_prob_irq: 4742 mv88e6xxx_g1_atu_prob_irq_free(chip); 4743 out_g2_irq: 4744 if (chip->info->g2_irqs > 0) 4745 mv88e6xxx_g2_irq_free(chip); 4746 out_g1_irq: 4747 if (chip->irq > 0) 4748 mv88e6xxx_g1_irq_free(chip); 4749 else 4750 mv88e6xxx_irq_poll_free(chip); 4751 out: 4752 if (pdata) 4753 dev_put(pdata->netdev); 4754 4755 return err; 4756 } 4757 4758 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 4759 { 4760 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 4761 struct mv88e6xxx_chip *chip = ds->priv; 4762 4763 if (chip->info->ptp_support) { 4764 mv88e6xxx_hwtstamp_free(chip); 4765 mv88e6xxx_ptp_free(chip); 4766 } 4767 4768 mv88e6xxx_phy_destroy(chip); 4769 mv88e6xxx_unregister_switch(chip); 4770 mv88e6xxx_mdios_unregister(chip); 4771 4772 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4773 mv88e6xxx_g1_atu_prob_irq_free(chip); 4774 4775 if (chip->info->g2_irqs > 0) 4776 mv88e6xxx_g2_irq_free(chip); 4777 4778 if (chip->irq > 0) 4779 mv88e6xxx_g1_irq_free(chip); 4780 else 4781 mv88e6xxx_irq_poll_free(chip); 4782 } 4783 4784 static const struct of_device_id mv88e6xxx_of_match[] = { 4785 { 4786 .compatible = "marvell,mv88e6085", 4787 .data = &mv88e6xxx_table[MV88E6085], 4788 }, 4789 { 4790 .compatible = "marvell,mv88e6190", 4791 .data = &mv88e6xxx_table[MV88E6190], 4792 }, 4793 { /* sentinel */ }, 4794 }; 4795 4796 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 4797 4798 static struct mdio_driver mv88e6xxx_driver = { 4799 .probe = mv88e6xxx_probe, 4800 .remove = mv88e6xxx_remove, 4801 .mdiodrv.driver = { 4802 .name = "mv88e6085", 4803 .of_match_table = mv88e6xxx_of_match, 4804 }, 4805 }; 4806 4807 static int __init mv88e6xxx_init(void) 4808 { 4809 register_switch_driver(&mv88e6xxx_switch_drv); 4810 return mdio_driver_register(&mv88e6xxx_driver); 4811 } 4812 module_init(mv88e6xxx_init); 4813 4814 static void __exit mv88e6xxx_cleanup(void) 4815 { 4816 mdio_driver_unregister(&mv88e6xxx_driver); 4817 unregister_switch_driver(&mv88e6xxx_switch_drv); 4818 } 4819 module_exit(mv88e6xxx_cleanup); 4820 4821 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 4822 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 4823 MODULE_LICENSE("GPL"); 4824