xref: /openbmc/linux/drivers/net/dsa/mv88e6xxx/chip.c (revision e7253313)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Marvell 88e6xxx Ethernet switch single-chip support
4  *
5  * Copyright (c) 2008 Marvell Semiconductor
6  *
7  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8  *
9  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11  */
12 
13 #include <linux/bitfield.h>
14 #include <linux/delay.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if_bridge.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/jiffies.h>
22 #include <linux/list.h>
23 #include <linux/mdio.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_mdio.h>
28 #include <linux/platform_data/mv88e6xxx.h>
29 #include <linux/netdevice.h>
30 #include <linux/gpio/consumer.h>
31 #include <linux/phylink.h>
32 #include <net/dsa.h>
33 
34 #include "chip.h"
35 #include "global1.h"
36 #include "global2.h"
37 #include "hwtstamp.h"
38 #include "phy.h"
39 #include "port.h"
40 #include "ptp.h"
41 #include "serdes.h"
42 #include "smi.h"
43 
44 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
45 {
46 	if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
47 		dev_err(chip->dev, "Switch registers lock not held!\n");
48 		dump_stack();
49 	}
50 }
51 
52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
53 {
54 	int err;
55 
56 	assert_reg_lock(chip);
57 
58 	err = mv88e6xxx_smi_read(chip, addr, reg, val);
59 	if (err)
60 		return err;
61 
62 	dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
63 		addr, reg, *val);
64 
65 	return 0;
66 }
67 
68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
69 {
70 	int err;
71 
72 	assert_reg_lock(chip);
73 
74 	err = mv88e6xxx_smi_write(chip, addr, reg, val);
75 	if (err)
76 		return err;
77 
78 	dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
79 		addr, reg, val);
80 
81 	return 0;
82 }
83 
84 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
85 			u16 mask, u16 val)
86 {
87 	u16 data;
88 	int err;
89 	int i;
90 
91 	/* There's no bus specific operation to wait for a mask */
92 	for (i = 0; i < 16; i++) {
93 		err = mv88e6xxx_read(chip, addr, reg, &data);
94 		if (err)
95 			return err;
96 
97 		if ((data & mask) == val)
98 			return 0;
99 
100 		usleep_range(1000, 2000);
101 	}
102 
103 	dev_err(chip->dev, "Timeout while waiting for switch\n");
104 	return -ETIMEDOUT;
105 }
106 
107 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
108 		       int bit, int val)
109 {
110 	return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
111 				   val ? BIT(bit) : 0x0000);
112 }
113 
114 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
115 {
116 	struct mv88e6xxx_mdio_bus *mdio_bus;
117 
118 	mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
119 				    list);
120 	if (!mdio_bus)
121 		return NULL;
122 
123 	return mdio_bus->bus;
124 }
125 
126 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
127 {
128 	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
129 	unsigned int n = d->hwirq;
130 
131 	chip->g1_irq.masked |= (1 << n);
132 }
133 
134 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
135 {
136 	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
137 	unsigned int n = d->hwirq;
138 
139 	chip->g1_irq.masked &= ~(1 << n);
140 }
141 
142 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
143 {
144 	unsigned int nhandled = 0;
145 	unsigned int sub_irq;
146 	unsigned int n;
147 	u16 reg;
148 	u16 ctl1;
149 	int err;
150 
151 	mv88e6xxx_reg_lock(chip);
152 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
153 	mv88e6xxx_reg_unlock(chip);
154 
155 	if (err)
156 		goto out;
157 
158 	do {
159 		for (n = 0; n < chip->g1_irq.nirqs; ++n) {
160 			if (reg & (1 << n)) {
161 				sub_irq = irq_find_mapping(chip->g1_irq.domain,
162 							   n);
163 				handle_nested_irq(sub_irq);
164 				++nhandled;
165 			}
166 		}
167 
168 		mv88e6xxx_reg_lock(chip);
169 		err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
170 		if (err)
171 			goto unlock;
172 		err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
173 unlock:
174 		mv88e6xxx_reg_unlock(chip);
175 		if (err)
176 			goto out;
177 		ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
178 	} while (reg & ctl1);
179 
180 out:
181 	return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
182 }
183 
184 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
185 {
186 	struct mv88e6xxx_chip *chip = dev_id;
187 
188 	return mv88e6xxx_g1_irq_thread_work(chip);
189 }
190 
191 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
192 {
193 	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
194 
195 	mv88e6xxx_reg_lock(chip);
196 }
197 
198 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
199 {
200 	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
201 	u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
202 	u16 reg;
203 	int err;
204 
205 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
206 	if (err)
207 		goto out;
208 
209 	reg &= ~mask;
210 	reg |= (~chip->g1_irq.masked & mask);
211 
212 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
213 	if (err)
214 		goto out;
215 
216 out:
217 	mv88e6xxx_reg_unlock(chip);
218 }
219 
220 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
221 	.name			= "mv88e6xxx-g1",
222 	.irq_mask		= mv88e6xxx_g1_irq_mask,
223 	.irq_unmask		= mv88e6xxx_g1_irq_unmask,
224 	.irq_bus_lock		= mv88e6xxx_g1_irq_bus_lock,
225 	.irq_bus_sync_unlock	= mv88e6xxx_g1_irq_bus_sync_unlock,
226 };
227 
228 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
229 				       unsigned int irq,
230 				       irq_hw_number_t hwirq)
231 {
232 	struct mv88e6xxx_chip *chip = d->host_data;
233 
234 	irq_set_chip_data(irq, d->host_data);
235 	irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
236 	irq_set_noprobe(irq);
237 
238 	return 0;
239 }
240 
241 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
242 	.map	= mv88e6xxx_g1_irq_domain_map,
243 	.xlate	= irq_domain_xlate_twocell,
244 };
245 
246 /* To be called with reg_lock held */
247 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
248 {
249 	int irq, virq;
250 	u16 mask;
251 
252 	mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
253 	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
254 	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
255 
256 	for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
257 		virq = irq_find_mapping(chip->g1_irq.domain, irq);
258 		irq_dispose_mapping(virq);
259 	}
260 
261 	irq_domain_remove(chip->g1_irq.domain);
262 }
263 
264 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
265 {
266 	/*
267 	 * free_irq must be called without reg_lock taken because the irq
268 	 * handler takes this lock, too.
269 	 */
270 	free_irq(chip->irq, chip);
271 
272 	mv88e6xxx_reg_lock(chip);
273 	mv88e6xxx_g1_irq_free_common(chip);
274 	mv88e6xxx_reg_unlock(chip);
275 }
276 
277 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
278 {
279 	int err, irq, virq;
280 	u16 reg, mask;
281 
282 	chip->g1_irq.nirqs = chip->info->g1_irqs;
283 	chip->g1_irq.domain = irq_domain_add_simple(
284 		NULL, chip->g1_irq.nirqs, 0,
285 		&mv88e6xxx_g1_irq_domain_ops, chip);
286 	if (!chip->g1_irq.domain)
287 		return -ENOMEM;
288 
289 	for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
290 		irq_create_mapping(chip->g1_irq.domain, irq);
291 
292 	chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
293 	chip->g1_irq.masked = ~0;
294 
295 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
296 	if (err)
297 		goto out_mapping;
298 
299 	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
300 
301 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
302 	if (err)
303 		goto out_disable;
304 
305 	/* Reading the interrupt status clears (most of) them */
306 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
307 	if (err)
308 		goto out_disable;
309 
310 	return 0;
311 
312 out_disable:
313 	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
314 	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
315 
316 out_mapping:
317 	for (irq = 0; irq < 16; irq++) {
318 		virq = irq_find_mapping(chip->g1_irq.domain, irq);
319 		irq_dispose_mapping(virq);
320 	}
321 
322 	irq_domain_remove(chip->g1_irq.domain);
323 
324 	return err;
325 }
326 
327 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
328 {
329 	static struct lock_class_key lock_key;
330 	static struct lock_class_key request_key;
331 	int err;
332 
333 	err = mv88e6xxx_g1_irq_setup_common(chip);
334 	if (err)
335 		return err;
336 
337 	/* These lock classes tells lockdep that global 1 irqs are in
338 	 * a different category than their parent GPIO, so it won't
339 	 * report false recursion.
340 	 */
341 	irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
342 
343 	mv88e6xxx_reg_unlock(chip);
344 	err = request_threaded_irq(chip->irq, NULL,
345 				   mv88e6xxx_g1_irq_thread_fn,
346 				   IRQF_ONESHOT | IRQF_SHARED,
347 				   dev_name(chip->dev), chip);
348 	mv88e6xxx_reg_lock(chip);
349 	if (err)
350 		mv88e6xxx_g1_irq_free_common(chip);
351 
352 	return err;
353 }
354 
355 static void mv88e6xxx_irq_poll(struct kthread_work *work)
356 {
357 	struct mv88e6xxx_chip *chip = container_of(work,
358 						   struct mv88e6xxx_chip,
359 						   irq_poll_work.work);
360 	mv88e6xxx_g1_irq_thread_work(chip);
361 
362 	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
363 				   msecs_to_jiffies(100));
364 }
365 
366 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
367 {
368 	int err;
369 
370 	err = mv88e6xxx_g1_irq_setup_common(chip);
371 	if (err)
372 		return err;
373 
374 	kthread_init_delayed_work(&chip->irq_poll_work,
375 				  mv88e6xxx_irq_poll);
376 
377 	chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
378 	if (IS_ERR(chip->kworker))
379 		return PTR_ERR(chip->kworker);
380 
381 	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
382 				   msecs_to_jiffies(100));
383 
384 	return 0;
385 }
386 
387 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
388 {
389 	kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
390 	kthread_destroy_worker(chip->kworker);
391 
392 	mv88e6xxx_reg_lock(chip);
393 	mv88e6xxx_g1_irq_free_common(chip);
394 	mv88e6xxx_reg_unlock(chip);
395 }
396 
397 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
398 			     int speed, int duplex, int pause,
399 			     phy_interface_t mode)
400 {
401 	struct phylink_link_state state;
402 	int err;
403 
404 	if (!chip->info->ops->port_set_link)
405 		return 0;
406 
407 	if (!chip->info->ops->port_link_state)
408 		return 0;
409 
410 	err = chip->info->ops->port_link_state(chip, port, &state);
411 	if (err)
412 		return err;
413 
414 	/* Has anything actually changed? We don't expect the
415 	 * interface mode to change without one of the other
416 	 * parameters also changing
417 	 */
418 	if (state.link == link &&
419 	    state.speed == speed &&
420 	    state.duplex == duplex &&
421 	    (state.interface == mode ||
422 	     state.interface == PHY_INTERFACE_MODE_NA))
423 		return 0;
424 
425 	/* Port's MAC control must not be changed unless the link is down */
426 	err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
427 	if (err)
428 		return err;
429 
430 	if (chip->info->ops->port_set_speed) {
431 		err = chip->info->ops->port_set_speed(chip, port, speed);
432 		if (err && err != -EOPNOTSUPP)
433 			goto restore_link;
434 	}
435 
436 	if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
437 		mode = chip->info->ops->port_max_speed_mode(port);
438 
439 	if (chip->info->ops->port_set_pause) {
440 		err = chip->info->ops->port_set_pause(chip, port, pause);
441 		if (err)
442 			goto restore_link;
443 	}
444 
445 	if (chip->info->ops->port_set_duplex) {
446 		err = chip->info->ops->port_set_duplex(chip, port, duplex);
447 		if (err && err != -EOPNOTSUPP)
448 			goto restore_link;
449 	}
450 
451 	if (chip->info->ops->port_set_rgmii_delay) {
452 		err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
453 		if (err && err != -EOPNOTSUPP)
454 			goto restore_link;
455 	}
456 
457 	if (chip->info->ops->port_set_cmode) {
458 		err = chip->info->ops->port_set_cmode(chip, port, mode);
459 		if (err && err != -EOPNOTSUPP)
460 			goto restore_link;
461 	}
462 
463 	err = 0;
464 restore_link:
465 	if (chip->info->ops->port_set_link(chip, port, link))
466 		dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
467 
468 	return err;
469 }
470 
471 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
472 {
473 	struct mv88e6xxx_chip *chip = ds->priv;
474 
475 	return port < chip->info->num_internal_phys;
476 }
477 
478 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
479 				       unsigned long *mask,
480 				       struct phylink_link_state *state)
481 {
482 	if (!phy_interface_mode_is_8023z(state->interface)) {
483 		/* 10M and 100M are only supported in non-802.3z mode */
484 		phylink_set(mask, 10baseT_Half);
485 		phylink_set(mask, 10baseT_Full);
486 		phylink_set(mask, 100baseT_Half);
487 		phylink_set(mask, 100baseT_Full);
488 	}
489 }
490 
491 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
492 				       unsigned long *mask,
493 				       struct phylink_link_state *state)
494 {
495 	/* FIXME: if the port is in 1000Base-X mode, then it only supports
496 	 * 1000M FD speeds.  In this case, CMODE will indicate 5.
497 	 */
498 	phylink_set(mask, 1000baseT_Full);
499 	phylink_set(mask, 1000baseX_Full);
500 
501 	mv88e6065_phylink_validate(chip, port, mask, state);
502 }
503 
504 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
505 				       unsigned long *mask,
506 				       struct phylink_link_state *state)
507 {
508 	if (port >= 5)
509 		phylink_set(mask, 2500baseX_Full);
510 
511 	/* No ethtool bits for 200Mbps */
512 	phylink_set(mask, 1000baseT_Full);
513 	phylink_set(mask, 1000baseX_Full);
514 
515 	mv88e6065_phylink_validate(chip, port, mask, state);
516 }
517 
518 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
519 				       unsigned long *mask,
520 				       struct phylink_link_state *state)
521 {
522 	/* No ethtool bits for 200Mbps */
523 	phylink_set(mask, 1000baseT_Full);
524 	phylink_set(mask, 1000baseX_Full);
525 
526 	mv88e6065_phylink_validate(chip, port, mask, state);
527 }
528 
529 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
530 				       unsigned long *mask,
531 				       struct phylink_link_state *state)
532 {
533 	if (port >= 9) {
534 		phylink_set(mask, 2500baseX_Full);
535 		phylink_set(mask, 2500baseT_Full);
536 	}
537 
538 	/* No ethtool bits for 200Mbps */
539 	phylink_set(mask, 1000baseT_Full);
540 	phylink_set(mask, 1000baseX_Full);
541 
542 	mv88e6065_phylink_validate(chip, port, mask, state);
543 }
544 
545 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
546 					unsigned long *mask,
547 					struct phylink_link_state *state)
548 {
549 	if (port >= 9) {
550 		phylink_set(mask, 10000baseT_Full);
551 		phylink_set(mask, 10000baseKR_Full);
552 	}
553 
554 	mv88e6390_phylink_validate(chip, port, mask, state);
555 }
556 
557 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
558 			       unsigned long *supported,
559 			       struct phylink_link_state *state)
560 {
561 	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
562 	struct mv88e6xxx_chip *chip = ds->priv;
563 
564 	/* Allow all the expected bits */
565 	phylink_set(mask, Autoneg);
566 	phylink_set(mask, Pause);
567 	phylink_set_port_modes(mask);
568 
569 	if (chip->info->ops->phylink_validate)
570 		chip->info->ops->phylink_validate(chip, port, mask, state);
571 
572 	bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
573 	bitmap_and(state->advertising, state->advertising, mask,
574 		   __ETHTOOL_LINK_MODE_MASK_NBITS);
575 
576 	/* We can only operate at 2500BaseX or 1000BaseX.  If requested
577 	 * to advertise both, only report advertising at 2500BaseX.
578 	 */
579 	phylink_helper_basex_speed(state);
580 }
581 
582 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port,
583 				struct phylink_link_state *state)
584 {
585 	struct mv88e6xxx_chip *chip = ds->priv;
586 	int err;
587 
588 	mv88e6xxx_reg_lock(chip);
589 	if (chip->info->ops->port_link_state)
590 		err = chip->info->ops->port_link_state(chip, port, state);
591 	else
592 		err = -EOPNOTSUPP;
593 	mv88e6xxx_reg_unlock(chip);
594 
595 	return err;
596 }
597 
598 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
599 				 unsigned int mode,
600 				 const struct phylink_link_state *state)
601 {
602 	struct mv88e6xxx_chip *chip = ds->priv;
603 	int speed, duplex, link, pause, err;
604 
605 	if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
606 		return;
607 
608 	if (mode == MLO_AN_FIXED) {
609 		link = LINK_FORCED_UP;
610 		speed = state->speed;
611 		duplex = state->duplex;
612 	} else if (!mv88e6xxx_phy_is_internal(ds, port)) {
613 		link = state->link;
614 		speed = state->speed;
615 		duplex = state->duplex;
616 	} else {
617 		speed = SPEED_UNFORCED;
618 		duplex = DUPLEX_UNFORCED;
619 		link = LINK_UNFORCED;
620 	}
621 	pause = !!phylink_test(state->advertising, Pause);
622 
623 	mv88e6xxx_reg_lock(chip);
624 	err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause,
625 				       state->interface);
626 	mv88e6xxx_reg_unlock(chip);
627 
628 	if (err && err != -EOPNOTSUPP)
629 		dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
630 }
631 
632 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link)
633 {
634 	struct mv88e6xxx_chip *chip = ds->priv;
635 	int err;
636 
637 	mv88e6xxx_reg_lock(chip);
638 	err = chip->info->ops->port_set_link(chip, port, link);
639 	mv88e6xxx_reg_unlock(chip);
640 
641 	if (err)
642 		dev_err(chip->dev, "p%d: failed to force MAC link\n", port);
643 }
644 
645 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
646 				    unsigned int mode,
647 				    phy_interface_t interface)
648 {
649 	if (mode == MLO_AN_FIXED)
650 		mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN);
651 }
652 
653 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
654 				  unsigned int mode, phy_interface_t interface,
655 				  struct phy_device *phydev)
656 {
657 	if (mode == MLO_AN_FIXED)
658 		mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP);
659 }
660 
661 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
662 {
663 	if (!chip->info->ops->stats_snapshot)
664 		return -EOPNOTSUPP;
665 
666 	return chip->info->ops->stats_snapshot(chip, port);
667 }
668 
669 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
670 	{ "in_good_octets",		8, 0x00, STATS_TYPE_BANK0, },
671 	{ "in_bad_octets",		4, 0x02, STATS_TYPE_BANK0, },
672 	{ "in_unicast",			4, 0x04, STATS_TYPE_BANK0, },
673 	{ "in_broadcasts",		4, 0x06, STATS_TYPE_BANK0, },
674 	{ "in_multicasts",		4, 0x07, STATS_TYPE_BANK0, },
675 	{ "in_pause",			4, 0x16, STATS_TYPE_BANK0, },
676 	{ "in_undersize",		4, 0x18, STATS_TYPE_BANK0, },
677 	{ "in_fragments",		4, 0x19, STATS_TYPE_BANK0, },
678 	{ "in_oversize",		4, 0x1a, STATS_TYPE_BANK0, },
679 	{ "in_jabber",			4, 0x1b, STATS_TYPE_BANK0, },
680 	{ "in_rx_error",		4, 0x1c, STATS_TYPE_BANK0, },
681 	{ "in_fcs_error",		4, 0x1d, STATS_TYPE_BANK0, },
682 	{ "out_octets",			8, 0x0e, STATS_TYPE_BANK0, },
683 	{ "out_unicast",		4, 0x10, STATS_TYPE_BANK0, },
684 	{ "out_broadcasts",		4, 0x13, STATS_TYPE_BANK0, },
685 	{ "out_multicasts",		4, 0x12, STATS_TYPE_BANK0, },
686 	{ "out_pause",			4, 0x15, STATS_TYPE_BANK0, },
687 	{ "excessive",			4, 0x11, STATS_TYPE_BANK0, },
688 	{ "collisions",			4, 0x1e, STATS_TYPE_BANK0, },
689 	{ "deferred",			4, 0x05, STATS_TYPE_BANK0, },
690 	{ "single",			4, 0x14, STATS_TYPE_BANK0, },
691 	{ "multiple",			4, 0x17, STATS_TYPE_BANK0, },
692 	{ "out_fcs_error",		4, 0x03, STATS_TYPE_BANK0, },
693 	{ "late",			4, 0x1f, STATS_TYPE_BANK0, },
694 	{ "hist_64bytes",		4, 0x08, STATS_TYPE_BANK0, },
695 	{ "hist_65_127bytes",		4, 0x09, STATS_TYPE_BANK0, },
696 	{ "hist_128_255bytes",		4, 0x0a, STATS_TYPE_BANK0, },
697 	{ "hist_256_511bytes",		4, 0x0b, STATS_TYPE_BANK0, },
698 	{ "hist_512_1023bytes",		4, 0x0c, STATS_TYPE_BANK0, },
699 	{ "hist_1024_max_bytes",	4, 0x0d, STATS_TYPE_BANK0, },
700 	{ "sw_in_discards",		4, 0x10, STATS_TYPE_PORT, },
701 	{ "sw_in_filtered",		2, 0x12, STATS_TYPE_PORT, },
702 	{ "sw_out_filtered",		2, 0x13, STATS_TYPE_PORT, },
703 	{ "in_discards",		4, 0x00, STATS_TYPE_BANK1, },
704 	{ "in_filtered",		4, 0x01, STATS_TYPE_BANK1, },
705 	{ "in_accepted",		4, 0x02, STATS_TYPE_BANK1, },
706 	{ "in_bad_accepted",		4, 0x03, STATS_TYPE_BANK1, },
707 	{ "in_good_avb_class_a",	4, 0x04, STATS_TYPE_BANK1, },
708 	{ "in_good_avb_class_b",	4, 0x05, STATS_TYPE_BANK1, },
709 	{ "in_bad_avb_class_a",		4, 0x06, STATS_TYPE_BANK1, },
710 	{ "in_bad_avb_class_b",		4, 0x07, STATS_TYPE_BANK1, },
711 	{ "tcam_counter_0",		4, 0x08, STATS_TYPE_BANK1, },
712 	{ "tcam_counter_1",		4, 0x09, STATS_TYPE_BANK1, },
713 	{ "tcam_counter_2",		4, 0x0a, STATS_TYPE_BANK1, },
714 	{ "tcam_counter_3",		4, 0x0b, STATS_TYPE_BANK1, },
715 	{ "in_da_unknown",		4, 0x0e, STATS_TYPE_BANK1, },
716 	{ "in_management",		4, 0x0f, STATS_TYPE_BANK1, },
717 	{ "out_queue_0",		4, 0x10, STATS_TYPE_BANK1, },
718 	{ "out_queue_1",		4, 0x11, STATS_TYPE_BANK1, },
719 	{ "out_queue_2",		4, 0x12, STATS_TYPE_BANK1, },
720 	{ "out_queue_3",		4, 0x13, STATS_TYPE_BANK1, },
721 	{ "out_queue_4",		4, 0x14, STATS_TYPE_BANK1, },
722 	{ "out_queue_5",		4, 0x15, STATS_TYPE_BANK1, },
723 	{ "out_queue_6",		4, 0x16, STATS_TYPE_BANK1, },
724 	{ "out_queue_7",		4, 0x17, STATS_TYPE_BANK1, },
725 	{ "out_cut_through",		4, 0x18, STATS_TYPE_BANK1, },
726 	{ "out_octets_a",		4, 0x1a, STATS_TYPE_BANK1, },
727 	{ "out_octets_b",		4, 0x1b, STATS_TYPE_BANK1, },
728 	{ "out_management",		4, 0x1f, STATS_TYPE_BANK1, },
729 };
730 
731 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
732 					    struct mv88e6xxx_hw_stat *s,
733 					    int port, u16 bank1_select,
734 					    u16 histogram)
735 {
736 	u32 low;
737 	u32 high = 0;
738 	u16 reg = 0;
739 	int err;
740 	u64 value;
741 
742 	switch (s->type) {
743 	case STATS_TYPE_PORT:
744 		err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
745 		if (err)
746 			return U64_MAX;
747 
748 		low = reg;
749 		if (s->size == 4) {
750 			err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
751 			if (err)
752 				return U64_MAX;
753 			low |= ((u32)reg) << 16;
754 		}
755 		break;
756 	case STATS_TYPE_BANK1:
757 		reg = bank1_select;
758 		/* fall through */
759 	case STATS_TYPE_BANK0:
760 		reg |= s->reg | histogram;
761 		mv88e6xxx_g1_stats_read(chip, reg, &low);
762 		if (s->size == 8)
763 			mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
764 		break;
765 	default:
766 		return U64_MAX;
767 	}
768 	value = (((u64)high) << 32) | low;
769 	return value;
770 }
771 
772 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
773 				       uint8_t *data, int types)
774 {
775 	struct mv88e6xxx_hw_stat *stat;
776 	int i, j;
777 
778 	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
779 		stat = &mv88e6xxx_hw_stats[i];
780 		if (stat->type & types) {
781 			memcpy(data + j * ETH_GSTRING_LEN, stat->string,
782 			       ETH_GSTRING_LEN);
783 			j++;
784 		}
785 	}
786 
787 	return j;
788 }
789 
790 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
791 				       uint8_t *data)
792 {
793 	return mv88e6xxx_stats_get_strings(chip, data,
794 					   STATS_TYPE_BANK0 | STATS_TYPE_PORT);
795 }
796 
797 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
798 				       uint8_t *data)
799 {
800 	return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
801 }
802 
803 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
804 				       uint8_t *data)
805 {
806 	return mv88e6xxx_stats_get_strings(chip, data,
807 					   STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
808 }
809 
810 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
811 	"atu_member_violation",
812 	"atu_miss_violation",
813 	"atu_full_violation",
814 	"vtu_member_violation",
815 	"vtu_miss_violation",
816 };
817 
818 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
819 {
820 	unsigned int i;
821 
822 	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
823 		strlcpy(data + i * ETH_GSTRING_LEN,
824 			mv88e6xxx_atu_vtu_stats_strings[i],
825 			ETH_GSTRING_LEN);
826 }
827 
828 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
829 				  u32 stringset, uint8_t *data)
830 {
831 	struct mv88e6xxx_chip *chip = ds->priv;
832 	int count = 0;
833 
834 	if (stringset != ETH_SS_STATS)
835 		return;
836 
837 	mv88e6xxx_reg_lock(chip);
838 
839 	if (chip->info->ops->stats_get_strings)
840 		count = chip->info->ops->stats_get_strings(chip, data);
841 
842 	if (chip->info->ops->serdes_get_strings) {
843 		data += count * ETH_GSTRING_LEN;
844 		count = chip->info->ops->serdes_get_strings(chip, port, data);
845 	}
846 
847 	data += count * ETH_GSTRING_LEN;
848 	mv88e6xxx_atu_vtu_get_strings(data);
849 
850 	mv88e6xxx_reg_unlock(chip);
851 }
852 
853 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
854 					  int types)
855 {
856 	struct mv88e6xxx_hw_stat *stat;
857 	int i, j;
858 
859 	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
860 		stat = &mv88e6xxx_hw_stats[i];
861 		if (stat->type & types)
862 			j++;
863 	}
864 	return j;
865 }
866 
867 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
868 {
869 	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
870 					      STATS_TYPE_PORT);
871 }
872 
873 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
874 {
875 	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
876 }
877 
878 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
879 {
880 	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
881 					      STATS_TYPE_BANK1);
882 }
883 
884 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
885 {
886 	struct mv88e6xxx_chip *chip = ds->priv;
887 	int serdes_count = 0;
888 	int count = 0;
889 
890 	if (sset != ETH_SS_STATS)
891 		return 0;
892 
893 	mv88e6xxx_reg_lock(chip);
894 	if (chip->info->ops->stats_get_sset_count)
895 		count = chip->info->ops->stats_get_sset_count(chip);
896 	if (count < 0)
897 		goto out;
898 
899 	if (chip->info->ops->serdes_get_sset_count)
900 		serdes_count = chip->info->ops->serdes_get_sset_count(chip,
901 								      port);
902 	if (serdes_count < 0) {
903 		count = serdes_count;
904 		goto out;
905 	}
906 	count += serdes_count;
907 	count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
908 
909 out:
910 	mv88e6xxx_reg_unlock(chip);
911 
912 	return count;
913 }
914 
915 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
916 				     uint64_t *data, int types,
917 				     u16 bank1_select, u16 histogram)
918 {
919 	struct mv88e6xxx_hw_stat *stat;
920 	int i, j;
921 
922 	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
923 		stat = &mv88e6xxx_hw_stats[i];
924 		if (stat->type & types) {
925 			mv88e6xxx_reg_lock(chip);
926 			data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
927 							      bank1_select,
928 							      histogram);
929 			mv88e6xxx_reg_unlock(chip);
930 
931 			j++;
932 		}
933 	}
934 	return j;
935 }
936 
937 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
938 				     uint64_t *data)
939 {
940 	return mv88e6xxx_stats_get_stats(chip, port, data,
941 					 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
942 					 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
943 }
944 
945 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
946 				     uint64_t *data)
947 {
948 	return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
949 					 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
950 }
951 
952 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
953 				     uint64_t *data)
954 {
955 	return mv88e6xxx_stats_get_stats(chip, port, data,
956 					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
957 					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
958 					 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
959 }
960 
961 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
962 				     uint64_t *data)
963 {
964 	return mv88e6xxx_stats_get_stats(chip, port, data,
965 					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
966 					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
967 					 0);
968 }
969 
970 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
971 					uint64_t *data)
972 {
973 	*data++ = chip->ports[port].atu_member_violation;
974 	*data++ = chip->ports[port].atu_miss_violation;
975 	*data++ = chip->ports[port].atu_full_violation;
976 	*data++ = chip->ports[port].vtu_member_violation;
977 	*data++ = chip->ports[port].vtu_miss_violation;
978 }
979 
980 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
981 				uint64_t *data)
982 {
983 	int count = 0;
984 
985 	if (chip->info->ops->stats_get_stats)
986 		count = chip->info->ops->stats_get_stats(chip, port, data);
987 
988 	mv88e6xxx_reg_lock(chip);
989 	if (chip->info->ops->serdes_get_stats) {
990 		data += count;
991 		count = chip->info->ops->serdes_get_stats(chip, port, data);
992 	}
993 	data += count;
994 	mv88e6xxx_atu_vtu_get_stats(chip, port, data);
995 	mv88e6xxx_reg_unlock(chip);
996 }
997 
998 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
999 					uint64_t *data)
1000 {
1001 	struct mv88e6xxx_chip *chip = ds->priv;
1002 	int ret;
1003 
1004 	mv88e6xxx_reg_lock(chip);
1005 
1006 	ret = mv88e6xxx_stats_snapshot(chip, port);
1007 	mv88e6xxx_reg_unlock(chip);
1008 
1009 	if (ret < 0)
1010 		return;
1011 
1012 	mv88e6xxx_get_stats(chip, port, data);
1013 
1014 }
1015 
1016 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1017 {
1018 	return 32 * sizeof(u16);
1019 }
1020 
1021 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1022 			       struct ethtool_regs *regs, void *_p)
1023 {
1024 	struct mv88e6xxx_chip *chip = ds->priv;
1025 	int err;
1026 	u16 reg;
1027 	u16 *p = _p;
1028 	int i;
1029 
1030 	regs->version = chip->info->prod_num;
1031 
1032 	memset(p, 0xff, 32 * sizeof(u16));
1033 
1034 	mv88e6xxx_reg_lock(chip);
1035 
1036 	for (i = 0; i < 32; i++) {
1037 
1038 		err = mv88e6xxx_port_read(chip, port, i, &reg);
1039 		if (!err)
1040 			p[i] = reg;
1041 	}
1042 
1043 	mv88e6xxx_reg_unlock(chip);
1044 }
1045 
1046 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1047 				 struct ethtool_eee *e)
1048 {
1049 	/* Nothing to do on the port's MAC */
1050 	return 0;
1051 }
1052 
1053 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1054 				 struct ethtool_eee *e)
1055 {
1056 	/* Nothing to do on the port's MAC */
1057 	return 0;
1058 }
1059 
1060 /* Mask of the local ports allowed to receive frames from a given fabric port */
1061 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1062 {
1063 	struct dsa_switch *ds = chip->ds;
1064 	struct dsa_switch_tree *dst = ds->dst;
1065 	struct net_device *br;
1066 	struct dsa_port *dp;
1067 	bool found = false;
1068 	u16 pvlan;
1069 
1070 	list_for_each_entry(dp, &dst->ports, list) {
1071 		if (dp->ds->index == dev && dp->index == port) {
1072 			found = true;
1073 			break;
1074 		}
1075 	}
1076 
1077 	/* Prevent frames from unknown switch or port */
1078 	if (!found)
1079 		return 0;
1080 
1081 	/* Frames from DSA links and CPU ports can egress any local port */
1082 	if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1083 		return mv88e6xxx_port_mask(chip);
1084 
1085 	br = dp->bridge_dev;
1086 	pvlan = 0;
1087 
1088 	/* Frames from user ports can egress any local DSA links and CPU ports,
1089 	 * as well as any local member of their bridge group.
1090 	 */
1091 	list_for_each_entry(dp, &dst->ports, list)
1092 		if (dp->ds == ds &&
1093 		    (dp->type == DSA_PORT_TYPE_CPU ||
1094 		     dp->type == DSA_PORT_TYPE_DSA ||
1095 		     (br && dp->bridge_dev == br)))
1096 			pvlan |= BIT(dp->index);
1097 
1098 	return pvlan;
1099 }
1100 
1101 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1102 {
1103 	u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1104 
1105 	/* prevent frames from going back out of the port they came in on */
1106 	output_ports &= ~BIT(port);
1107 
1108 	return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1109 }
1110 
1111 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1112 					 u8 state)
1113 {
1114 	struct mv88e6xxx_chip *chip = ds->priv;
1115 	int err;
1116 
1117 	mv88e6xxx_reg_lock(chip);
1118 	err = mv88e6xxx_port_set_state(chip, port, state);
1119 	mv88e6xxx_reg_unlock(chip);
1120 
1121 	if (err)
1122 		dev_err(ds->dev, "p%d: failed to update state\n", port);
1123 }
1124 
1125 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1126 {
1127 	int err;
1128 
1129 	if (chip->info->ops->ieee_pri_map) {
1130 		err = chip->info->ops->ieee_pri_map(chip);
1131 		if (err)
1132 			return err;
1133 	}
1134 
1135 	if (chip->info->ops->ip_pri_map) {
1136 		err = chip->info->ops->ip_pri_map(chip);
1137 		if (err)
1138 			return err;
1139 	}
1140 
1141 	return 0;
1142 }
1143 
1144 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1145 {
1146 	struct dsa_switch *ds = chip->ds;
1147 	int target, port;
1148 	int err;
1149 
1150 	if (!chip->info->global2_addr)
1151 		return 0;
1152 
1153 	/* Initialize the routing port to the 32 possible target devices */
1154 	for (target = 0; target < 32; target++) {
1155 		port = dsa_routing_port(ds, target);
1156 		if (port == ds->num_ports)
1157 			port = 0x1f;
1158 
1159 		err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1160 		if (err)
1161 			return err;
1162 	}
1163 
1164 	if (chip->info->ops->set_cascade_port) {
1165 		port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1166 		err = chip->info->ops->set_cascade_port(chip, port);
1167 		if (err)
1168 			return err;
1169 	}
1170 
1171 	err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1172 	if (err)
1173 		return err;
1174 
1175 	return 0;
1176 }
1177 
1178 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1179 {
1180 	/* Clear all trunk masks and mapping */
1181 	if (chip->info->global2_addr)
1182 		return mv88e6xxx_g2_trunk_clear(chip);
1183 
1184 	return 0;
1185 }
1186 
1187 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1188 {
1189 	if (chip->info->ops->rmu_disable)
1190 		return chip->info->ops->rmu_disable(chip);
1191 
1192 	return 0;
1193 }
1194 
1195 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1196 {
1197 	if (chip->info->ops->pot_clear)
1198 		return chip->info->ops->pot_clear(chip);
1199 
1200 	return 0;
1201 }
1202 
1203 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1204 {
1205 	if (chip->info->ops->mgmt_rsvd2cpu)
1206 		return chip->info->ops->mgmt_rsvd2cpu(chip);
1207 
1208 	return 0;
1209 }
1210 
1211 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1212 {
1213 	int err;
1214 
1215 	err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1216 	if (err)
1217 		return err;
1218 
1219 	err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1220 	if (err)
1221 		return err;
1222 
1223 	return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1224 }
1225 
1226 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1227 {
1228 	int port;
1229 	int err;
1230 
1231 	if (!chip->info->ops->irl_init_all)
1232 		return 0;
1233 
1234 	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1235 		/* Disable ingress rate limiting by resetting all per port
1236 		 * ingress rate limit resources to their initial state.
1237 		 */
1238 		err = chip->info->ops->irl_init_all(chip, port);
1239 		if (err)
1240 			return err;
1241 	}
1242 
1243 	return 0;
1244 }
1245 
1246 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1247 {
1248 	if (chip->info->ops->set_switch_mac) {
1249 		u8 addr[ETH_ALEN];
1250 
1251 		eth_random_addr(addr);
1252 
1253 		return chip->info->ops->set_switch_mac(chip, addr);
1254 	}
1255 
1256 	return 0;
1257 }
1258 
1259 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1260 {
1261 	u16 pvlan = 0;
1262 
1263 	if (!mv88e6xxx_has_pvt(chip))
1264 		return 0;
1265 
1266 	/* Skip the local source device, which uses in-chip port VLAN */
1267 	if (dev != chip->ds->index)
1268 		pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1269 
1270 	return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1271 }
1272 
1273 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1274 {
1275 	int dev, port;
1276 	int err;
1277 
1278 	if (!mv88e6xxx_has_pvt(chip))
1279 		return 0;
1280 
1281 	/* Clear 5 Bit Port for usage with Marvell Link Street devices:
1282 	 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1283 	 */
1284 	err = mv88e6xxx_g2_misc_4_bit_port(chip);
1285 	if (err)
1286 		return err;
1287 
1288 	for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1289 		for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1290 			err = mv88e6xxx_pvt_map(chip, dev, port);
1291 			if (err)
1292 				return err;
1293 		}
1294 	}
1295 
1296 	return 0;
1297 }
1298 
1299 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1300 {
1301 	struct mv88e6xxx_chip *chip = ds->priv;
1302 	int err;
1303 
1304 	mv88e6xxx_reg_lock(chip);
1305 	err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1306 	mv88e6xxx_reg_unlock(chip);
1307 
1308 	if (err)
1309 		dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1310 }
1311 
1312 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1313 {
1314 	if (!chip->info->max_vid)
1315 		return 0;
1316 
1317 	return mv88e6xxx_g1_vtu_flush(chip);
1318 }
1319 
1320 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1321 				 struct mv88e6xxx_vtu_entry *entry)
1322 {
1323 	if (!chip->info->ops->vtu_getnext)
1324 		return -EOPNOTSUPP;
1325 
1326 	return chip->info->ops->vtu_getnext(chip, entry);
1327 }
1328 
1329 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1330 				   struct mv88e6xxx_vtu_entry *entry)
1331 {
1332 	if (!chip->info->ops->vtu_loadpurge)
1333 		return -EOPNOTSUPP;
1334 
1335 	return chip->info->ops->vtu_loadpurge(chip, entry);
1336 }
1337 
1338 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1339 {
1340 	DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1341 	struct mv88e6xxx_vtu_entry vlan;
1342 	int i, err;
1343 
1344 	bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1345 
1346 	/* Set every FID bit used by the (un)bridged ports */
1347 	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1348 		err = mv88e6xxx_port_get_fid(chip, i, fid);
1349 		if (err)
1350 			return err;
1351 
1352 		set_bit(*fid, fid_bitmap);
1353 	}
1354 
1355 	/* Set every FID bit used by the VLAN entries */
1356 	vlan.vid = chip->info->max_vid;
1357 	vlan.valid = false;
1358 
1359 	do {
1360 		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1361 		if (err)
1362 			return err;
1363 
1364 		if (!vlan.valid)
1365 			break;
1366 
1367 		set_bit(vlan.fid, fid_bitmap);
1368 	} while (vlan.vid < chip->info->max_vid);
1369 
1370 	/* The reset value 0x000 is used to indicate that multiple address
1371 	 * databases are not needed. Return the next positive available.
1372 	 */
1373 	*fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1374 	if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1375 		return -ENOSPC;
1376 
1377 	/* Clear the database */
1378 	return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1379 }
1380 
1381 static int mv88e6xxx_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash)
1382 {
1383 	if (chip->info->ops->atu_get_hash)
1384 		return chip->info->ops->atu_get_hash(chip, hash);
1385 
1386 	return -EOPNOTSUPP;
1387 }
1388 
1389 static int mv88e6xxx_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash)
1390 {
1391 	if (chip->info->ops->atu_set_hash)
1392 		return chip->info->ops->atu_set_hash(chip, hash);
1393 
1394 	return -EOPNOTSUPP;
1395 }
1396 
1397 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1398 					u16 vid_begin, u16 vid_end)
1399 {
1400 	struct mv88e6xxx_chip *chip = ds->priv;
1401 	struct mv88e6xxx_vtu_entry vlan;
1402 	int i, err;
1403 
1404 	/* DSA and CPU ports have to be members of multiple vlans */
1405 	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1406 		return 0;
1407 
1408 	if (!vid_begin)
1409 		return -EOPNOTSUPP;
1410 
1411 	vlan.vid = vid_begin - 1;
1412 	vlan.valid = false;
1413 
1414 	do {
1415 		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1416 		if (err)
1417 			return err;
1418 
1419 		if (!vlan.valid)
1420 			break;
1421 
1422 		if (vlan.vid > vid_end)
1423 			break;
1424 
1425 		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1426 			if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1427 				continue;
1428 
1429 			if (!dsa_to_port(ds, i)->slave)
1430 				continue;
1431 
1432 			if (vlan.member[i] ==
1433 			    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1434 				continue;
1435 
1436 			if (dsa_to_port(ds, i)->bridge_dev ==
1437 			    dsa_to_port(ds, port)->bridge_dev)
1438 				break; /* same bridge, check next VLAN */
1439 
1440 			if (!dsa_to_port(ds, i)->bridge_dev)
1441 				continue;
1442 
1443 			dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1444 				port, vlan.vid, i,
1445 				netdev_name(dsa_to_port(ds, i)->bridge_dev));
1446 			return -EOPNOTSUPP;
1447 		}
1448 	} while (vlan.vid < vid_end);
1449 
1450 	return 0;
1451 }
1452 
1453 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1454 					 bool vlan_filtering)
1455 {
1456 	struct mv88e6xxx_chip *chip = ds->priv;
1457 	u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1458 		MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1459 	int err;
1460 
1461 	if (!chip->info->max_vid)
1462 		return -EOPNOTSUPP;
1463 
1464 	mv88e6xxx_reg_lock(chip);
1465 	err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1466 	mv88e6xxx_reg_unlock(chip);
1467 
1468 	return err;
1469 }
1470 
1471 static int
1472 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1473 			    const struct switchdev_obj_port_vlan *vlan)
1474 {
1475 	struct mv88e6xxx_chip *chip = ds->priv;
1476 	int err;
1477 
1478 	if (!chip->info->max_vid)
1479 		return -EOPNOTSUPP;
1480 
1481 	/* If the requested port doesn't belong to the same bridge as the VLAN
1482 	 * members, do not support it (yet) and fallback to software VLAN.
1483 	 */
1484 	mv88e6xxx_reg_lock(chip);
1485 	err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1486 					   vlan->vid_end);
1487 	mv88e6xxx_reg_unlock(chip);
1488 
1489 	/* We don't need any dynamic resource from the kernel (yet),
1490 	 * so skip the prepare phase.
1491 	 */
1492 	return err;
1493 }
1494 
1495 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1496 					const unsigned char *addr, u16 vid,
1497 					u8 state)
1498 {
1499 	struct mv88e6xxx_atu_entry entry;
1500 	struct mv88e6xxx_vtu_entry vlan;
1501 	u16 fid;
1502 	int err;
1503 
1504 	/* Null VLAN ID corresponds to the port private database */
1505 	if (vid == 0) {
1506 		err = mv88e6xxx_port_get_fid(chip, port, &fid);
1507 		if (err)
1508 			return err;
1509 	} else {
1510 		vlan.vid = vid - 1;
1511 		vlan.valid = false;
1512 
1513 		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1514 		if (err)
1515 			return err;
1516 
1517 		/* switchdev expects -EOPNOTSUPP to honor software VLANs */
1518 		if (vlan.vid != vid || !vlan.valid)
1519 			return -EOPNOTSUPP;
1520 
1521 		fid = vlan.fid;
1522 	}
1523 
1524 	entry.state = 0;
1525 	ether_addr_copy(entry.mac, addr);
1526 	eth_addr_dec(entry.mac);
1527 
1528 	err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
1529 	if (err)
1530 		return err;
1531 
1532 	/* Initialize a fresh ATU entry if it isn't found */
1533 	if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
1534 		memset(&entry, 0, sizeof(entry));
1535 		ether_addr_copy(entry.mac, addr);
1536 	}
1537 
1538 	/* Purge the ATU entry only if no port is using it anymore */
1539 	if (!state) {
1540 		entry.portvec &= ~BIT(port);
1541 		if (!entry.portvec)
1542 			entry.state = 0;
1543 	} else {
1544 		entry.portvec |= BIT(port);
1545 		entry.state = state;
1546 	}
1547 
1548 	return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
1549 }
1550 
1551 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1552 				  const struct mv88e6xxx_policy *policy)
1553 {
1554 	enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1555 	enum mv88e6xxx_policy_action action = policy->action;
1556 	const u8 *addr = policy->addr;
1557 	u16 vid = policy->vid;
1558 	u8 state;
1559 	int err;
1560 	int id;
1561 
1562 	if (!chip->info->ops->port_set_policy)
1563 		return -EOPNOTSUPP;
1564 
1565 	switch (mapping) {
1566 	case MV88E6XXX_POLICY_MAPPING_DA:
1567 	case MV88E6XXX_POLICY_MAPPING_SA:
1568 		if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1569 			state = 0; /* Dissociate the port and address */
1570 		else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1571 			 is_multicast_ether_addr(addr))
1572 			state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1573 		else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1574 			 is_unicast_ether_addr(addr))
1575 			state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1576 		else
1577 			return -EOPNOTSUPP;
1578 
1579 		err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1580 						   state);
1581 		if (err)
1582 			return err;
1583 		break;
1584 	default:
1585 		return -EOPNOTSUPP;
1586 	}
1587 
1588 	/* Skip the port's policy clearing if the mapping is still in use */
1589 	if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1590 		idr_for_each_entry(&chip->policies, policy, id)
1591 			if (policy->port == port &&
1592 			    policy->mapping == mapping &&
1593 			    policy->action != action)
1594 				return 0;
1595 
1596 	return chip->info->ops->port_set_policy(chip, port, mapping, action);
1597 }
1598 
1599 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1600 				   struct ethtool_rx_flow_spec *fs)
1601 {
1602 	struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1603 	struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1604 	enum mv88e6xxx_policy_mapping mapping;
1605 	enum mv88e6xxx_policy_action action;
1606 	struct mv88e6xxx_policy *policy;
1607 	u16 vid = 0;
1608 	u8 *addr;
1609 	int err;
1610 	int id;
1611 
1612 	if (fs->location != RX_CLS_LOC_ANY)
1613 		return -EINVAL;
1614 
1615 	if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1616 		action = MV88E6XXX_POLICY_ACTION_DISCARD;
1617 	else
1618 		return -EOPNOTSUPP;
1619 
1620 	switch (fs->flow_type & ~FLOW_EXT) {
1621 	case ETHER_FLOW:
1622 		if (!is_zero_ether_addr(mac_mask->h_dest) &&
1623 		    is_zero_ether_addr(mac_mask->h_source)) {
1624 			mapping = MV88E6XXX_POLICY_MAPPING_DA;
1625 			addr = mac_entry->h_dest;
1626 		} else if (is_zero_ether_addr(mac_mask->h_dest) &&
1627 		    !is_zero_ether_addr(mac_mask->h_source)) {
1628 			mapping = MV88E6XXX_POLICY_MAPPING_SA;
1629 			addr = mac_entry->h_source;
1630 		} else {
1631 			/* Cannot support DA and SA mapping in the same rule */
1632 			return -EOPNOTSUPP;
1633 		}
1634 		break;
1635 	default:
1636 		return -EOPNOTSUPP;
1637 	}
1638 
1639 	if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
1640 		if (fs->m_ext.vlan_tci != 0xffff)
1641 			return -EOPNOTSUPP;
1642 		vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1643 	}
1644 
1645 	idr_for_each_entry(&chip->policies, policy, id) {
1646 		if (policy->port == port && policy->mapping == mapping &&
1647 		    policy->action == action && policy->vid == vid &&
1648 		    ether_addr_equal(policy->addr, addr))
1649 			return -EEXIST;
1650 	}
1651 
1652 	policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1653 	if (!policy)
1654 		return -ENOMEM;
1655 
1656 	fs->location = 0;
1657 	err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1658 			    GFP_KERNEL);
1659 	if (err) {
1660 		devm_kfree(chip->dev, policy);
1661 		return err;
1662 	}
1663 
1664 	memcpy(&policy->fs, fs, sizeof(*fs));
1665 	ether_addr_copy(policy->addr, addr);
1666 	policy->mapping = mapping;
1667 	policy->action = action;
1668 	policy->port = port;
1669 	policy->vid = vid;
1670 
1671 	err = mv88e6xxx_policy_apply(chip, port, policy);
1672 	if (err) {
1673 		idr_remove(&chip->policies, fs->location);
1674 		devm_kfree(chip->dev, policy);
1675 		return err;
1676 	}
1677 
1678 	return 0;
1679 }
1680 
1681 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1682 			       struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1683 {
1684 	struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1685 	struct mv88e6xxx_chip *chip = ds->priv;
1686 	struct mv88e6xxx_policy *policy;
1687 	int err;
1688 	int id;
1689 
1690 	mv88e6xxx_reg_lock(chip);
1691 
1692 	switch (rxnfc->cmd) {
1693 	case ETHTOOL_GRXCLSRLCNT:
1694 		rxnfc->data = 0;
1695 		rxnfc->data |= RX_CLS_LOC_SPECIAL;
1696 		rxnfc->rule_cnt = 0;
1697 		idr_for_each_entry(&chip->policies, policy, id)
1698 			if (policy->port == port)
1699 				rxnfc->rule_cnt++;
1700 		err = 0;
1701 		break;
1702 	case ETHTOOL_GRXCLSRULE:
1703 		err = -ENOENT;
1704 		policy = idr_find(&chip->policies, fs->location);
1705 		if (policy) {
1706 			memcpy(fs, &policy->fs, sizeof(*fs));
1707 			err = 0;
1708 		}
1709 		break;
1710 	case ETHTOOL_GRXCLSRLALL:
1711 		rxnfc->data = 0;
1712 		rxnfc->rule_cnt = 0;
1713 		idr_for_each_entry(&chip->policies, policy, id)
1714 			if (policy->port == port)
1715 				rule_locs[rxnfc->rule_cnt++] = id;
1716 		err = 0;
1717 		break;
1718 	default:
1719 		err = -EOPNOTSUPP;
1720 		break;
1721 	}
1722 
1723 	mv88e6xxx_reg_unlock(chip);
1724 
1725 	return err;
1726 }
1727 
1728 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1729 			       struct ethtool_rxnfc *rxnfc)
1730 {
1731 	struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1732 	struct mv88e6xxx_chip *chip = ds->priv;
1733 	struct mv88e6xxx_policy *policy;
1734 	int err;
1735 
1736 	mv88e6xxx_reg_lock(chip);
1737 
1738 	switch (rxnfc->cmd) {
1739 	case ETHTOOL_SRXCLSRLINS:
1740 		err = mv88e6xxx_policy_insert(chip, port, fs);
1741 		break;
1742 	case ETHTOOL_SRXCLSRLDEL:
1743 		err = -ENOENT;
1744 		policy = idr_remove(&chip->policies, fs->location);
1745 		if (policy) {
1746 			policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
1747 			err = mv88e6xxx_policy_apply(chip, port, policy);
1748 			devm_kfree(chip->dev, policy);
1749 		}
1750 		break;
1751 	default:
1752 		err = -EOPNOTSUPP;
1753 		break;
1754 	}
1755 
1756 	mv88e6xxx_reg_unlock(chip);
1757 
1758 	return err;
1759 }
1760 
1761 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1762 					u16 vid)
1763 {
1764 	const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1765 	u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1766 
1767 	return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1768 }
1769 
1770 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1771 {
1772 	int port;
1773 	int err;
1774 
1775 	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1776 		err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1777 		if (err)
1778 			return err;
1779 	}
1780 
1781 	return 0;
1782 }
1783 
1784 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
1785 				    u16 vid, u8 member)
1786 {
1787 	const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1788 	struct mv88e6xxx_vtu_entry vlan;
1789 	int i, err;
1790 
1791 	if (!vid)
1792 		return -EOPNOTSUPP;
1793 
1794 	vlan.vid = vid - 1;
1795 	vlan.valid = false;
1796 
1797 	err = mv88e6xxx_vtu_getnext(chip, &vlan);
1798 	if (err)
1799 		return err;
1800 
1801 	if (vlan.vid != vid || !vlan.valid) {
1802 		memset(&vlan, 0, sizeof(vlan));
1803 
1804 		err = mv88e6xxx_atu_new(chip, &vlan.fid);
1805 		if (err)
1806 			return err;
1807 
1808 		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1809 			if (i == port)
1810 				vlan.member[i] = member;
1811 			else
1812 				vlan.member[i] = non_member;
1813 
1814 		vlan.vid = vid;
1815 		vlan.valid = true;
1816 
1817 		err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1818 		if (err)
1819 			return err;
1820 
1821 		err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
1822 		if (err)
1823 			return err;
1824 	} else if (vlan.member[port] != member) {
1825 		vlan.member[port] = member;
1826 
1827 		err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1828 		if (err)
1829 			return err;
1830 	} else {
1831 		dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
1832 			 port, vid);
1833 	}
1834 
1835 	return 0;
1836 }
1837 
1838 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1839 				    const struct switchdev_obj_port_vlan *vlan)
1840 {
1841 	struct mv88e6xxx_chip *chip = ds->priv;
1842 	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1843 	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1844 	u8 member;
1845 	u16 vid;
1846 
1847 	if (!chip->info->max_vid)
1848 		return;
1849 
1850 	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1851 		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1852 	else if (untagged)
1853 		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1854 	else
1855 		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1856 
1857 	mv88e6xxx_reg_lock(chip);
1858 
1859 	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1860 		if (mv88e6xxx_port_vlan_join(chip, port, vid, member))
1861 			dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1862 				vid, untagged ? 'u' : 't');
1863 
1864 	if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1865 		dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1866 			vlan->vid_end);
1867 
1868 	mv88e6xxx_reg_unlock(chip);
1869 }
1870 
1871 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
1872 				     int port, u16 vid)
1873 {
1874 	struct mv88e6xxx_vtu_entry vlan;
1875 	int i, err;
1876 
1877 	if (!vid)
1878 		return -EOPNOTSUPP;
1879 
1880 	vlan.vid = vid - 1;
1881 	vlan.valid = false;
1882 
1883 	err = mv88e6xxx_vtu_getnext(chip, &vlan);
1884 	if (err)
1885 		return err;
1886 
1887 	/* If the VLAN doesn't exist in hardware or the port isn't a member,
1888 	 * tell switchdev that this VLAN is likely handled in software.
1889 	 */
1890 	if (vlan.vid != vid || !vlan.valid ||
1891 	    vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1892 		return -EOPNOTSUPP;
1893 
1894 	vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1895 
1896 	/* keep the VLAN unless all ports are excluded */
1897 	vlan.valid = false;
1898 	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1899 		if (vlan.member[i] !=
1900 		    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1901 			vlan.valid = true;
1902 			break;
1903 		}
1904 	}
1905 
1906 	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1907 	if (err)
1908 		return err;
1909 
1910 	return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1911 }
1912 
1913 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1914 				   const struct switchdev_obj_port_vlan *vlan)
1915 {
1916 	struct mv88e6xxx_chip *chip = ds->priv;
1917 	u16 pvid, vid;
1918 	int err = 0;
1919 
1920 	if (!chip->info->max_vid)
1921 		return -EOPNOTSUPP;
1922 
1923 	mv88e6xxx_reg_lock(chip);
1924 
1925 	err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1926 	if (err)
1927 		goto unlock;
1928 
1929 	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1930 		err = mv88e6xxx_port_vlan_leave(chip, port, vid);
1931 		if (err)
1932 			goto unlock;
1933 
1934 		if (vid == pvid) {
1935 			err = mv88e6xxx_port_set_pvid(chip, port, 0);
1936 			if (err)
1937 				goto unlock;
1938 		}
1939 	}
1940 
1941 unlock:
1942 	mv88e6xxx_reg_unlock(chip);
1943 
1944 	return err;
1945 }
1946 
1947 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1948 				  const unsigned char *addr, u16 vid)
1949 {
1950 	struct mv88e6xxx_chip *chip = ds->priv;
1951 	int err;
1952 
1953 	mv88e6xxx_reg_lock(chip);
1954 	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1955 					   MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1956 	mv88e6xxx_reg_unlock(chip);
1957 
1958 	return err;
1959 }
1960 
1961 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1962 				  const unsigned char *addr, u16 vid)
1963 {
1964 	struct mv88e6xxx_chip *chip = ds->priv;
1965 	int err;
1966 
1967 	mv88e6xxx_reg_lock(chip);
1968 	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
1969 	mv88e6xxx_reg_unlock(chip);
1970 
1971 	return err;
1972 }
1973 
1974 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1975 				      u16 fid, u16 vid, int port,
1976 				      dsa_fdb_dump_cb_t *cb, void *data)
1977 {
1978 	struct mv88e6xxx_atu_entry addr;
1979 	bool is_static;
1980 	int err;
1981 
1982 	addr.state = 0;
1983 	eth_broadcast_addr(addr.mac);
1984 
1985 	do {
1986 		err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1987 		if (err)
1988 			return err;
1989 
1990 		if (!addr.state)
1991 			break;
1992 
1993 		if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1994 			continue;
1995 
1996 		if (!is_unicast_ether_addr(addr.mac))
1997 			continue;
1998 
1999 		is_static = (addr.state ==
2000 			     MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2001 		err = cb(addr.mac, vid, is_static, data);
2002 		if (err)
2003 			return err;
2004 	} while (!is_broadcast_ether_addr(addr.mac));
2005 
2006 	return err;
2007 }
2008 
2009 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2010 				  dsa_fdb_dump_cb_t *cb, void *data)
2011 {
2012 	struct mv88e6xxx_vtu_entry vlan;
2013 	u16 fid;
2014 	int err;
2015 
2016 	/* Dump port's default Filtering Information Database (VLAN ID 0) */
2017 	err = mv88e6xxx_port_get_fid(chip, port, &fid);
2018 	if (err)
2019 		return err;
2020 
2021 	err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2022 	if (err)
2023 		return err;
2024 
2025 	/* Dump VLANs' Filtering Information Databases */
2026 	vlan.vid = chip->info->max_vid;
2027 	vlan.valid = false;
2028 
2029 	do {
2030 		err = mv88e6xxx_vtu_getnext(chip, &vlan);
2031 		if (err)
2032 			return err;
2033 
2034 		if (!vlan.valid)
2035 			break;
2036 
2037 		err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2038 						 cb, data);
2039 		if (err)
2040 			return err;
2041 	} while (vlan.vid < chip->info->max_vid);
2042 
2043 	return err;
2044 }
2045 
2046 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2047 				   dsa_fdb_dump_cb_t *cb, void *data)
2048 {
2049 	struct mv88e6xxx_chip *chip = ds->priv;
2050 	int err;
2051 
2052 	mv88e6xxx_reg_lock(chip);
2053 	err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2054 	mv88e6xxx_reg_unlock(chip);
2055 
2056 	return err;
2057 }
2058 
2059 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2060 				struct net_device *br)
2061 {
2062 	struct dsa_switch *ds = chip->ds;
2063 	struct dsa_switch_tree *dst = ds->dst;
2064 	struct dsa_port *dp;
2065 	int err;
2066 
2067 	list_for_each_entry(dp, &dst->ports, list) {
2068 		if (dp->bridge_dev == br) {
2069 			if (dp->ds == ds) {
2070 				/* This is a local bridge group member,
2071 				 * remap its Port VLAN Map.
2072 				 */
2073 				err = mv88e6xxx_port_vlan_map(chip, dp->index);
2074 				if (err)
2075 					return err;
2076 			} else {
2077 				/* This is an external bridge group member,
2078 				 * remap its cross-chip Port VLAN Table entry.
2079 				 */
2080 				err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2081 							dp->index);
2082 				if (err)
2083 					return err;
2084 			}
2085 		}
2086 	}
2087 
2088 	return 0;
2089 }
2090 
2091 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2092 				      struct net_device *br)
2093 {
2094 	struct mv88e6xxx_chip *chip = ds->priv;
2095 	int err;
2096 
2097 	mv88e6xxx_reg_lock(chip);
2098 	err = mv88e6xxx_bridge_map(chip, br);
2099 	mv88e6xxx_reg_unlock(chip);
2100 
2101 	return err;
2102 }
2103 
2104 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2105 					struct net_device *br)
2106 {
2107 	struct mv88e6xxx_chip *chip = ds->priv;
2108 
2109 	mv88e6xxx_reg_lock(chip);
2110 	if (mv88e6xxx_bridge_map(chip, br) ||
2111 	    mv88e6xxx_port_vlan_map(chip, port))
2112 		dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2113 	mv88e6xxx_reg_unlock(chip);
2114 }
2115 
2116 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
2117 					   int port, struct net_device *br)
2118 {
2119 	struct mv88e6xxx_chip *chip = ds->priv;
2120 	int err;
2121 
2122 	mv88e6xxx_reg_lock(chip);
2123 	err = mv88e6xxx_pvt_map(chip, dev, port);
2124 	mv88e6xxx_reg_unlock(chip);
2125 
2126 	return err;
2127 }
2128 
2129 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
2130 					     int port, struct net_device *br)
2131 {
2132 	struct mv88e6xxx_chip *chip = ds->priv;
2133 
2134 	mv88e6xxx_reg_lock(chip);
2135 	if (mv88e6xxx_pvt_map(chip, dev, port))
2136 		dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2137 	mv88e6xxx_reg_unlock(chip);
2138 }
2139 
2140 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2141 {
2142 	if (chip->info->ops->reset)
2143 		return chip->info->ops->reset(chip);
2144 
2145 	return 0;
2146 }
2147 
2148 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2149 {
2150 	struct gpio_desc *gpiod = chip->reset;
2151 
2152 	/* If there is a GPIO connected to the reset pin, toggle it */
2153 	if (gpiod) {
2154 		gpiod_set_value_cansleep(gpiod, 1);
2155 		usleep_range(10000, 20000);
2156 		gpiod_set_value_cansleep(gpiod, 0);
2157 		usleep_range(10000, 20000);
2158 	}
2159 }
2160 
2161 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2162 {
2163 	int i, err;
2164 
2165 	/* Set all ports to the Disabled state */
2166 	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2167 		err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2168 		if (err)
2169 			return err;
2170 	}
2171 
2172 	/* Wait for transmit queues to drain,
2173 	 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2174 	 */
2175 	usleep_range(2000, 4000);
2176 
2177 	return 0;
2178 }
2179 
2180 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2181 {
2182 	int err;
2183 
2184 	err = mv88e6xxx_disable_ports(chip);
2185 	if (err)
2186 		return err;
2187 
2188 	mv88e6xxx_hardware_reset(chip);
2189 
2190 	return mv88e6xxx_software_reset(chip);
2191 }
2192 
2193 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2194 				   enum mv88e6xxx_frame_mode frame,
2195 				   enum mv88e6xxx_egress_mode egress, u16 etype)
2196 {
2197 	int err;
2198 
2199 	if (!chip->info->ops->port_set_frame_mode)
2200 		return -EOPNOTSUPP;
2201 
2202 	err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2203 	if (err)
2204 		return err;
2205 
2206 	err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2207 	if (err)
2208 		return err;
2209 
2210 	if (chip->info->ops->port_set_ether_type)
2211 		return chip->info->ops->port_set_ether_type(chip, port, etype);
2212 
2213 	return 0;
2214 }
2215 
2216 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2217 {
2218 	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2219 				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2220 				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2221 }
2222 
2223 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2224 {
2225 	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2226 				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2227 				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2228 }
2229 
2230 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2231 {
2232 	return mv88e6xxx_set_port_mode(chip, port,
2233 				       MV88E6XXX_FRAME_MODE_ETHERTYPE,
2234 				       MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2235 				       ETH_P_EDSA);
2236 }
2237 
2238 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2239 {
2240 	if (dsa_is_dsa_port(chip->ds, port))
2241 		return mv88e6xxx_set_port_mode_dsa(chip, port);
2242 
2243 	if (dsa_is_user_port(chip->ds, port))
2244 		return mv88e6xxx_set_port_mode_normal(chip, port);
2245 
2246 	/* Setup CPU port mode depending on its supported tag format */
2247 	if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2248 		return mv88e6xxx_set_port_mode_dsa(chip, port);
2249 
2250 	if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2251 		return mv88e6xxx_set_port_mode_edsa(chip, port);
2252 
2253 	return -EINVAL;
2254 }
2255 
2256 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2257 {
2258 	bool message = dsa_is_dsa_port(chip->ds, port);
2259 
2260 	return mv88e6xxx_port_set_message_port(chip, port, message);
2261 }
2262 
2263 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2264 {
2265 	struct dsa_switch *ds = chip->ds;
2266 	bool flood;
2267 
2268 	/* Upstream ports flood frames with unknown unicast or multicast DA */
2269 	flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2270 	if (chip->info->ops->port_set_egress_floods)
2271 		return chip->info->ops->port_set_egress_floods(chip, port,
2272 							       flood, flood);
2273 
2274 	return 0;
2275 }
2276 
2277 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2278 {
2279 	struct mv88e6xxx_port *mvp = dev_id;
2280 	struct mv88e6xxx_chip *chip = mvp->chip;
2281 	irqreturn_t ret = IRQ_NONE;
2282 	int port = mvp->port;
2283 	u8 lane;
2284 
2285 	mv88e6xxx_reg_lock(chip);
2286 	lane = mv88e6xxx_serdes_get_lane(chip, port);
2287 	if (lane)
2288 		ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2289 	mv88e6xxx_reg_unlock(chip);
2290 
2291 	return ret;
2292 }
2293 
2294 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
2295 					u8 lane)
2296 {
2297 	struct mv88e6xxx_port *dev_id = &chip->ports[port];
2298 	unsigned int irq;
2299 	int err;
2300 
2301 	/* Nothing to request if this SERDES port has no IRQ */
2302 	irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2303 	if (!irq)
2304 		return 0;
2305 
2306 	/* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2307 	mv88e6xxx_reg_unlock(chip);
2308 	err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
2309 				   IRQF_ONESHOT, "mv88e6xxx-serdes", dev_id);
2310 	mv88e6xxx_reg_lock(chip);
2311 	if (err)
2312 		return err;
2313 
2314 	dev_id->serdes_irq = irq;
2315 
2316 	return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2317 }
2318 
2319 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
2320 				     u8 lane)
2321 {
2322 	struct mv88e6xxx_port *dev_id = &chip->ports[port];
2323 	unsigned int irq = dev_id->serdes_irq;
2324 	int err;
2325 
2326 	/* Nothing to free if no IRQ has been requested */
2327 	if (!irq)
2328 		return 0;
2329 
2330 	err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2331 
2332 	/* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2333 	mv88e6xxx_reg_unlock(chip);
2334 	free_irq(irq, dev_id);
2335 	mv88e6xxx_reg_lock(chip);
2336 
2337 	dev_id->serdes_irq = 0;
2338 
2339 	return err;
2340 }
2341 
2342 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2343 				  bool on)
2344 {
2345 	u8 lane;
2346 	int err;
2347 
2348 	lane = mv88e6xxx_serdes_get_lane(chip, port);
2349 	if (!lane)
2350 		return 0;
2351 
2352 	if (on) {
2353 		err = mv88e6xxx_serdes_power_up(chip, port, lane);
2354 		if (err)
2355 			return err;
2356 
2357 		err = mv88e6xxx_serdes_irq_request(chip, port, lane);
2358 	} else {
2359 		err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2360 		if (err)
2361 			return err;
2362 
2363 		err = mv88e6xxx_serdes_power_down(chip, port, lane);
2364 	}
2365 
2366 	return err;
2367 }
2368 
2369 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2370 {
2371 	struct dsa_switch *ds = chip->ds;
2372 	int upstream_port;
2373 	int err;
2374 
2375 	upstream_port = dsa_upstream_port(ds, port);
2376 	if (chip->info->ops->port_set_upstream_port) {
2377 		err = chip->info->ops->port_set_upstream_port(chip, port,
2378 							      upstream_port);
2379 		if (err)
2380 			return err;
2381 	}
2382 
2383 	if (port == upstream_port) {
2384 		if (chip->info->ops->set_cpu_port) {
2385 			err = chip->info->ops->set_cpu_port(chip,
2386 							    upstream_port);
2387 			if (err)
2388 				return err;
2389 		}
2390 
2391 		if (chip->info->ops->set_egress_port) {
2392 			err = chip->info->ops->set_egress_port(chip,
2393 						MV88E6XXX_EGRESS_DIR_INGRESS,
2394 						upstream_port);
2395 			if (err)
2396 				return err;
2397 
2398 			err = chip->info->ops->set_egress_port(chip,
2399 						MV88E6XXX_EGRESS_DIR_EGRESS,
2400 						upstream_port);
2401 			if (err)
2402 				return err;
2403 		}
2404 	}
2405 
2406 	return 0;
2407 }
2408 
2409 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2410 {
2411 	struct dsa_switch *ds = chip->ds;
2412 	int err;
2413 	u16 reg;
2414 
2415 	chip->ports[port].chip = chip;
2416 	chip->ports[port].port = port;
2417 
2418 	/* MAC Forcing register: don't force link, speed, duplex or flow control
2419 	 * state to any particular values on physical ports, but force the CPU
2420 	 * port and all DSA ports to their maximum bandwidth and full duplex.
2421 	 */
2422 	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2423 		err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2424 					       SPEED_MAX, DUPLEX_FULL,
2425 					       PAUSE_OFF,
2426 					       PHY_INTERFACE_MODE_NA);
2427 	else
2428 		err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2429 					       SPEED_UNFORCED, DUPLEX_UNFORCED,
2430 					       PAUSE_ON,
2431 					       PHY_INTERFACE_MODE_NA);
2432 	if (err)
2433 		return err;
2434 
2435 	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2436 	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2437 	 * tunneling, determine priority by looking at 802.1p and IP
2438 	 * priority fields (IP prio has precedence), and set STP state
2439 	 * to Forwarding.
2440 	 *
2441 	 * If this is the CPU link, use DSA or EDSA tagging depending
2442 	 * on which tagging mode was configured.
2443 	 *
2444 	 * If this is a link to another switch, use DSA tagging mode.
2445 	 *
2446 	 * If this is the upstream port for this switch, enable
2447 	 * forwarding of unknown unicasts and multicasts.
2448 	 */
2449 	reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2450 		MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2451 		MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2452 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2453 	if (err)
2454 		return err;
2455 
2456 	err = mv88e6xxx_setup_port_mode(chip, port);
2457 	if (err)
2458 		return err;
2459 
2460 	err = mv88e6xxx_setup_egress_floods(chip, port);
2461 	if (err)
2462 		return err;
2463 
2464 	/* Port Control 2: don't force a good FCS, set the maximum frame size to
2465 	 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2466 	 * untagged frames on this port, do a destination address lookup on all
2467 	 * received packets as usual, disable ARP mirroring and don't send a
2468 	 * copy of all transmitted/received frames on this port to the CPU.
2469 	 */
2470 	err = mv88e6xxx_port_set_map_da(chip, port);
2471 	if (err)
2472 		return err;
2473 
2474 	err = mv88e6xxx_setup_upstream_port(chip, port);
2475 	if (err)
2476 		return err;
2477 
2478 	err = mv88e6xxx_port_set_8021q_mode(chip, port,
2479 				MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2480 	if (err)
2481 		return err;
2482 
2483 	if (chip->info->ops->port_set_jumbo_size) {
2484 		err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2485 		if (err)
2486 			return err;
2487 	}
2488 
2489 	/* Port Association Vector: when learning source addresses
2490 	 * of packets, add the address to the address database using
2491 	 * a port bitmap that has only the bit for this port set and
2492 	 * the other bits clear.
2493 	 */
2494 	reg = 1 << port;
2495 	/* Disable learning for CPU port */
2496 	if (dsa_is_cpu_port(ds, port))
2497 		reg = 0;
2498 
2499 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2500 				   reg);
2501 	if (err)
2502 		return err;
2503 
2504 	/* Egress rate control 2: disable egress rate control. */
2505 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2506 				   0x0000);
2507 	if (err)
2508 		return err;
2509 
2510 	if (chip->info->ops->port_pause_limit) {
2511 		err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2512 		if (err)
2513 			return err;
2514 	}
2515 
2516 	if (chip->info->ops->port_disable_learn_limit) {
2517 		err = chip->info->ops->port_disable_learn_limit(chip, port);
2518 		if (err)
2519 			return err;
2520 	}
2521 
2522 	if (chip->info->ops->port_disable_pri_override) {
2523 		err = chip->info->ops->port_disable_pri_override(chip, port);
2524 		if (err)
2525 			return err;
2526 	}
2527 
2528 	if (chip->info->ops->port_tag_remap) {
2529 		err = chip->info->ops->port_tag_remap(chip, port);
2530 		if (err)
2531 			return err;
2532 	}
2533 
2534 	if (chip->info->ops->port_egress_rate_limiting) {
2535 		err = chip->info->ops->port_egress_rate_limiting(chip, port);
2536 		if (err)
2537 			return err;
2538 	}
2539 
2540 	if (chip->info->ops->port_setup_message_port) {
2541 		err = chip->info->ops->port_setup_message_port(chip, port);
2542 		if (err)
2543 			return err;
2544 	}
2545 
2546 	/* Port based VLAN map: give each port the same default address
2547 	 * database, and allow bidirectional communication between the
2548 	 * CPU and DSA port(s), and the other ports.
2549 	 */
2550 	err = mv88e6xxx_port_set_fid(chip, port, 0);
2551 	if (err)
2552 		return err;
2553 
2554 	err = mv88e6xxx_port_vlan_map(chip, port);
2555 	if (err)
2556 		return err;
2557 
2558 	/* Default VLAN ID and priority: don't set a default VLAN
2559 	 * ID, and set the default packet priority to zero.
2560 	 */
2561 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2562 }
2563 
2564 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2565 				 struct phy_device *phydev)
2566 {
2567 	struct mv88e6xxx_chip *chip = ds->priv;
2568 	int err;
2569 
2570 	mv88e6xxx_reg_lock(chip);
2571 	err = mv88e6xxx_serdes_power(chip, port, true);
2572 	mv88e6xxx_reg_unlock(chip);
2573 
2574 	return err;
2575 }
2576 
2577 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2578 {
2579 	struct mv88e6xxx_chip *chip = ds->priv;
2580 
2581 	mv88e6xxx_reg_lock(chip);
2582 	if (mv88e6xxx_serdes_power(chip, port, false))
2583 		dev_err(chip->dev, "failed to power off SERDES\n");
2584 	mv88e6xxx_reg_unlock(chip);
2585 }
2586 
2587 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2588 				     unsigned int ageing_time)
2589 {
2590 	struct mv88e6xxx_chip *chip = ds->priv;
2591 	int err;
2592 
2593 	mv88e6xxx_reg_lock(chip);
2594 	err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2595 	mv88e6xxx_reg_unlock(chip);
2596 
2597 	return err;
2598 }
2599 
2600 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2601 {
2602 	int err;
2603 
2604 	/* Initialize the statistics unit */
2605 	if (chip->info->ops->stats_set_histogram) {
2606 		err = chip->info->ops->stats_set_histogram(chip);
2607 		if (err)
2608 			return err;
2609 	}
2610 
2611 	return mv88e6xxx_g1_stats_clear(chip);
2612 }
2613 
2614 /* Check if the errata has already been applied. */
2615 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2616 {
2617 	int port;
2618 	int err;
2619 	u16 val;
2620 
2621 	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2622 		err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
2623 		if (err) {
2624 			dev_err(chip->dev,
2625 				"Error reading hidden register: %d\n", err);
2626 			return false;
2627 		}
2628 		if (val != 0x01c0)
2629 			return false;
2630 	}
2631 
2632 	return true;
2633 }
2634 
2635 /* The 6390 copper ports have an errata which require poking magic
2636  * values into undocumented hidden registers and then performing a
2637  * software reset.
2638  */
2639 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2640 {
2641 	int port;
2642 	int err;
2643 
2644 	if (mv88e6390_setup_errata_applied(chip))
2645 		return 0;
2646 
2647 	/* Set the ports into blocking mode */
2648 	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2649 		err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2650 		if (err)
2651 			return err;
2652 	}
2653 
2654 	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2655 		err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
2656 		if (err)
2657 			return err;
2658 	}
2659 
2660 	return mv88e6xxx_software_reset(chip);
2661 }
2662 
2663 enum mv88e6xxx_devlink_param_id {
2664 	MV88E6XXX_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
2665 	MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH,
2666 };
2667 
2668 static int mv88e6xxx_devlink_param_get(struct dsa_switch *ds, u32 id,
2669 				       struct devlink_param_gset_ctx *ctx)
2670 {
2671 	struct mv88e6xxx_chip *chip = ds->priv;
2672 	int err;
2673 
2674 	mv88e6xxx_reg_lock(chip);
2675 
2676 	switch (id) {
2677 	case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH:
2678 		err = mv88e6xxx_atu_get_hash(chip, &ctx->val.vu8);
2679 		break;
2680 	default:
2681 		err = -EOPNOTSUPP;
2682 		break;
2683 	}
2684 
2685 	mv88e6xxx_reg_unlock(chip);
2686 
2687 	return err;
2688 }
2689 
2690 static int mv88e6xxx_devlink_param_set(struct dsa_switch *ds, u32 id,
2691 				       struct devlink_param_gset_ctx *ctx)
2692 {
2693 	struct mv88e6xxx_chip *chip = ds->priv;
2694 	int err;
2695 
2696 	mv88e6xxx_reg_lock(chip);
2697 
2698 	switch (id) {
2699 	case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH:
2700 		err = mv88e6xxx_atu_set_hash(chip, ctx->val.vu8);
2701 		break;
2702 	default:
2703 		err = -EOPNOTSUPP;
2704 		break;
2705 	}
2706 
2707 	mv88e6xxx_reg_unlock(chip);
2708 
2709 	return err;
2710 }
2711 
2712 static const struct devlink_param mv88e6xxx_devlink_params[] = {
2713 	DSA_DEVLINK_PARAM_DRIVER(MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH,
2714 				 "ATU_hash", DEVLINK_PARAM_TYPE_U8,
2715 				 BIT(DEVLINK_PARAM_CMODE_RUNTIME)),
2716 };
2717 
2718 static int mv88e6xxx_setup_devlink_params(struct dsa_switch *ds)
2719 {
2720 	return dsa_devlink_params_register(ds, mv88e6xxx_devlink_params,
2721 					   ARRAY_SIZE(mv88e6xxx_devlink_params));
2722 }
2723 
2724 static void mv88e6xxx_teardown_devlink_params(struct dsa_switch *ds)
2725 {
2726 	dsa_devlink_params_unregister(ds, mv88e6xxx_devlink_params,
2727 				      ARRAY_SIZE(mv88e6xxx_devlink_params));
2728 }
2729 
2730 enum mv88e6xxx_devlink_resource_id {
2731 	MV88E6XXX_RESOURCE_ID_ATU,
2732 	MV88E6XXX_RESOURCE_ID_ATU_BIN_0,
2733 	MV88E6XXX_RESOURCE_ID_ATU_BIN_1,
2734 	MV88E6XXX_RESOURCE_ID_ATU_BIN_2,
2735 	MV88E6XXX_RESOURCE_ID_ATU_BIN_3,
2736 };
2737 
2738 static u64 mv88e6xxx_devlink_atu_bin_get(struct mv88e6xxx_chip *chip,
2739 					 u16 bin)
2740 {
2741 	u16 occupancy = 0;
2742 	int err;
2743 
2744 	mv88e6xxx_reg_lock(chip);
2745 
2746 	err = mv88e6xxx_g2_atu_stats_set(chip, MV88E6XXX_G2_ATU_STATS_MODE_ALL,
2747 					 bin);
2748 	if (err) {
2749 		dev_err(chip->dev, "failed to set ATU stats kind/bin\n");
2750 		goto unlock;
2751 	}
2752 
2753 	err = mv88e6xxx_g1_atu_get_next(chip, 0);
2754 	if (err) {
2755 		dev_err(chip->dev, "failed to perform ATU get next\n");
2756 		goto unlock;
2757 	}
2758 
2759 	err = mv88e6xxx_g2_atu_stats_get(chip, &occupancy);
2760 	if (err) {
2761 		dev_err(chip->dev, "failed to get ATU stats\n");
2762 		goto unlock;
2763 	}
2764 
2765 unlock:
2766 	mv88e6xxx_reg_unlock(chip);
2767 
2768 	return occupancy;
2769 }
2770 
2771 static u64 mv88e6xxx_devlink_atu_bin_0_get(void *priv)
2772 {
2773 	struct mv88e6xxx_chip *chip = priv;
2774 
2775 	return mv88e6xxx_devlink_atu_bin_get(chip,
2776 					     MV88E6XXX_G2_ATU_STATS_BIN_0);
2777 }
2778 
2779 static u64 mv88e6xxx_devlink_atu_bin_1_get(void *priv)
2780 {
2781 	struct mv88e6xxx_chip *chip = priv;
2782 
2783 	return mv88e6xxx_devlink_atu_bin_get(chip,
2784 					     MV88E6XXX_G2_ATU_STATS_BIN_1);
2785 }
2786 
2787 static u64 mv88e6xxx_devlink_atu_bin_2_get(void *priv)
2788 {
2789 	struct mv88e6xxx_chip *chip = priv;
2790 
2791 	return mv88e6xxx_devlink_atu_bin_get(chip,
2792 					     MV88E6XXX_G2_ATU_STATS_BIN_2);
2793 }
2794 
2795 static u64 mv88e6xxx_devlink_atu_bin_3_get(void *priv)
2796 {
2797 	struct mv88e6xxx_chip *chip = priv;
2798 
2799 	return mv88e6xxx_devlink_atu_bin_get(chip,
2800 					     MV88E6XXX_G2_ATU_STATS_BIN_3);
2801 }
2802 
2803 static u64 mv88e6xxx_devlink_atu_get(void *priv)
2804 {
2805 	return mv88e6xxx_devlink_atu_bin_0_get(priv) +
2806 		mv88e6xxx_devlink_atu_bin_1_get(priv) +
2807 		mv88e6xxx_devlink_atu_bin_2_get(priv) +
2808 		mv88e6xxx_devlink_atu_bin_3_get(priv);
2809 }
2810 
2811 static int mv88e6xxx_setup_devlink_resources(struct dsa_switch *ds)
2812 {
2813 	struct devlink_resource_size_params size_params;
2814 	struct mv88e6xxx_chip *chip = ds->priv;
2815 	int err;
2816 
2817 	devlink_resource_size_params_init(&size_params,
2818 					  mv88e6xxx_num_macs(chip),
2819 					  mv88e6xxx_num_macs(chip),
2820 					  1, DEVLINK_RESOURCE_UNIT_ENTRY);
2821 
2822 	err = dsa_devlink_resource_register(ds, "ATU",
2823 					    mv88e6xxx_num_macs(chip),
2824 					    MV88E6XXX_RESOURCE_ID_ATU,
2825 					    DEVLINK_RESOURCE_ID_PARENT_TOP,
2826 					    &size_params);
2827 	if (err)
2828 		goto out;
2829 
2830 	devlink_resource_size_params_init(&size_params,
2831 					  mv88e6xxx_num_macs(chip) / 4,
2832 					  mv88e6xxx_num_macs(chip) / 4,
2833 					  1, DEVLINK_RESOURCE_UNIT_ENTRY);
2834 
2835 	err = dsa_devlink_resource_register(ds, "ATU_bin_0",
2836 					    mv88e6xxx_num_macs(chip) / 4,
2837 					    MV88E6XXX_RESOURCE_ID_ATU_BIN_0,
2838 					    MV88E6XXX_RESOURCE_ID_ATU,
2839 					    &size_params);
2840 	if (err)
2841 		goto out;
2842 
2843 	err = dsa_devlink_resource_register(ds, "ATU_bin_1",
2844 					    mv88e6xxx_num_macs(chip) / 4,
2845 					    MV88E6XXX_RESOURCE_ID_ATU_BIN_1,
2846 					    MV88E6XXX_RESOURCE_ID_ATU,
2847 					    &size_params);
2848 	if (err)
2849 		goto out;
2850 
2851 	err = dsa_devlink_resource_register(ds, "ATU_bin_2",
2852 					    mv88e6xxx_num_macs(chip) / 4,
2853 					    MV88E6XXX_RESOURCE_ID_ATU_BIN_2,
2854 					    MV88E6XXX_RESOURCE_ID_ATU,
2855 					    &size_params);
2856 	if (err)
2857 		goto out;
2858 
2859 	err = dsa_devlink_resource_register(ds, "ATU_bin_3",
2860 					    mv88e6xxx_num_macs(chip) / 4,
2861 					    MV88E6XXX_RESOURCE_ID_ATU_BIN_3,
2862 					    MV88E6XXX_RESOURCE_ID_ATU,
2863 					    &size_params);
2864 	if (err)
2865 		goto out;
2866 
2867 	dsa_devlink_resource_occ_get_register(ds,
2868 					      MV88E6XXX_RESOURCE_ID_ATU,
2869 					      mv88e6xxx_devlink_atu_get,
2870 					      chip);
2871 
2872 	dsa_devlink_resource_occ_get_register(ds,
2873 					      MV88E6XXX_RESOURCE_ID_ATU_BIN_0,
2874 					      mv88e6xxx_devlink_atu_bin_0_get,
2875 					      chip);
2876 
2877 	dsa_devlink_resource_occ_get_register(ds,
2878 					      MV88E6XXX_RESOURCE_ID_ATU_BIN_1,
2879 					      mv88e6xxx_devlink_atu_bin_1_get,
2880 					      chip);
2881 
2882 	dsa_devlink_resource_occ_get_register(ds,
2883 					      MV88E6XXX_RESOURCE_ID_ATU_BIN_2,
2884 					      mv88e6xxx_devlink_atu_bin_2_get,
2885 					      chip);
2886 
2887 	dsa_devlink_resource_occ_get_register(ds,
2888 					      MV88E6XXX_RESOURCE_ID_ATU_BIN_3,
2889 					      mv88e6xxx_devlink_atu_bin_3_get,
2890 					      chip);
2891 
2892 	return 0;
2893 
2894 out:
2895 	dsa_devlink_resources_unregister(ds);
2896 	return err;
2897 }
2898 
2899 static void mv88e6xxx_teardown(struct dsa_switch *ds)
2900 {
2901 	mv88e6xxx_teardown_devlink_params(ds);
2902 	dsa_devlink_resources_unregister(ds);
2903 }
2904 
2905 static int mv88e6xxx_setup(struct dsa_switch *ds)
2906 {
2907 	struct mv88e6xxx_chip *chip = ds->priv;
2908 	u8 cmode;
2909 	int err;
2910 	int i;
2911 
2912 	chip->ds = ds;
2913 	ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2914 
2915 	mv88e6xxx_reg_lock(chip);
2916 
2917 	if (chip->info->ops->setup_errata) {
2918 		err = chip->info->ops->setup_errata(chip);
2919 		if (err)
2920 			goto unlock;
2921 	}
2922 
2923 	/* Cache the cmode of each port. */
2924 	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2925 		if (chip->info->ops->port_get_cmode) {
2926 			err = chip->info->ops->port_get_cmode(chip, i, &cmode);
2927 			if (err)
2928 				goto unlock;
2929 
2930 			chip->ports[i].cmode = cmode;
2931 		}
2932 	}
2933 
2934 	/* Setup Switch Port Registers */
2935 	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2936 		if (dsa_is_unused_port(ds, i))
2937 			continue;
2938 
2939 		/* Prevent the use of an invalid port. */
2940 		if (mv88e6xxx_is_invalid_port(chip, i)) {
2941 			dev_err(chip->dev, "port %d is invalid\n", i);
2942 			err = -EINVAL;
2943 			goto unlock;
2944 		}
2945 
2946 		err = mv88e6xxx_setup_port(chip, i);
2947 		if (err)
2948 			goto unlock;
2949 	}
2950 
2951 	err = mv88e6xxx_irl_setup(chip);
2952 	if (err)
2953 		goto unlock;
2954 
2955 	err = mv88e6xxx_mac_setup(chip);
2956 	if (err)
2957 		goto unlock;
2958 
2959 	err = mv88e6xxx_phy_setup(chip);
2960 	if (err)
2961 		goto unlock;
2962 
2963 	err = mv88e6xxx_vtu_setup(chip);
2964 	if (err)
2965 		goto unlock;
2966 
2967 	err = mv88e6xxx_pvt_setup(chip);
2968 	if (err)
2969 		goto unlock;
2970 
2971 	err = mv88e6xxx_atu_setup(chip);
2972 	if (err)
2973 		goto unlock;
2974 
2975 	err = mv88e6xxx_broadcast_setup(chip, 0);
2976 	if (err)
2977 		goto unlock;
2978 
2979 	err = mv88e6xxx_pot_setup(chip);
2980 	if (err)
2981 		goto unlock;
2982 
2983 	err = mv88e6xxx_rmu_setup(chip);
2984 	if (err)
2985 		goto unlock;
2986 
2987 	err = mv88e6xxx_rsvd2cpu_setup(chip);
2988 	if (err)
2989 		goto unlock;
2990 
2991 	err = mv88e6xxx_trunk_setup(chip);
2992 	if (err)
2993 		goto unlock;
2994 
2995 	err = mv88e6xxx_devmap_setup(chip);
2996 	if (err)
2997 		goto unlock;
2998 
2999 	err = mv88e6xxx_pri_setup(chip);
3000 	if (err)
3001 		goto unlock;
3002 
3003 	/* Setup PTP Hardware Clock and timestamping */
3004 	if (chip->info->ptp_support) {
3005 		err = mv88e6xxx_ptp_setup(chip);
3006 		if (err)
3007 			goto unlock;
3008 
3009 		err = mv88e6xxx_hwtstamp_setup(chip);
3010 		if (err)
3011 			goto unlock;
3012 	}
3013 
3014 	err = mv88e6xxx_stats_setup(chip);
3015 	if (err)
3016 		goto unlock;
3017 
3018 unlock:
3019 	mv88e6xxx_reg_unlock(chip);
3020 
3021 	if (err)
3022 		return err;
3023 
3024 	/* Have to be called without holding the register lock, since
3025 	 * they take the devlink lock, and we later take the locks in
3026 	 * the reverse order when getting/setting parameters or
3027 	 * resource occupancy.
3028 	 */
3029 	err = mv88e6xxx_setup_devlink_resources(ds);
3030 	if (err)
3031 		return err;
3032 
3033 	err = mv88e6xxx_setup_devlink_params(ds);
3034 	if (err)
3035 		dsa_devlink_resources_unregister(ds);
3036 
3037 	return err;
3038 }
3039 
3040 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3041 {
3042 	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3043 	struct mv88e6xxx_chip *chip = mdio_bus->chip;
3044 	u16 val;
3045 	int err;
3046 
3047 	if (!chip->info->ops->phy_read)
3048 		return -EOPNOTSUPP;
3049 
3050 	mv88e6xxx_reg_lock(chip);
3051 	err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3052 	mv88e6xxx_reg_unlock(chip);
3053 
3054 	if (reg == MII_PHYSID2) {
3055 		/* Some internal PHYs don't have a model number. */
3056 		if (chip->info->family != MV88E6XXX_FAMILY_6165)
3057 			/* Then there is the 6165 family. It gets is
3058 			 * PHYs correct. But it can also have two
3059 			 * SERDES interfaces in the PHY address
3060 			 * space. And these don't have a model
3061 			 * number. But they are not PHYs, so we don't
3062 			 * want to give them something a PHY driver
3063 			 * will recognise.
3064 			 *
3065 			 * Use the mv88e6390 family model number
3066 			 * instead, for anything which really could be
3067 			 * a PHY,
3068 			 */
3069 			if (!(val & 0x3f0))
3070 				val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
3071 	}
3072 
3073 	return err ? err : val;
3074 }
3075 
3076 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3077 {
3078 	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3079 	struct mv88e6xxx_chip *chip = mdio_bus->chip;
3080 	int err;
3081 
3082 	if (!chip->info->ops->phy_write)
3083 		return -EOPNOTSUPP;
3084 
3085 	mv88e6xxx_reg_lock(chip);
3086 	err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3087 	mv88e6xxx_reg_unlock(chip);
3088 
3089 	return err;
3090 }
3091 
3092 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3093 				   struct device_node *np,
3094 				   bool external)
3095 {
3096 	static int index;
3097 	struct mv88e6xxx_mdio_bus *mdio_bus;
3098 	struct mii_bus *bus;
3099 	int err;
3100 
3101 	if (external) {
3102 		mv88e6xxx_reg_lock(chip);
3103 		err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3104 		mv88e6xxx_reg_unlock(chip);
3105 
3106 		if (err)
3107 			return err;
3108 	}
3109 
3110 	bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
3111 	if (!bus)
3112 		return -ENOMEM;
3113 
3114 	mdio_bus = bus->priv;
3115 	mdio_bus->bus = bus;
3116 	mdio_bus->chip = chip;
3117 	INIT_LIST_HEAD(&mdio_bus->list);
3118 	mdio_bus->external = external;
3119 
3120 	if (np) {
3121 		bus->name = np->full_name;
3122 		snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3123 	} else {
3124 		bus->name = "mv88e6xxx SMI";
3125 		snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3126 	}
3127 
3128 	bus->read = mv88e6xxx_mdio_read;
3129 	bus->write = mv88e6xxx_mdio_write;
3130 	bus->parent = chip->dev;
3131 
3132 	if (!external) {
3133 		err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3134 		if (err)
3135 			return err;
3136 	}
3137 
3138 	err = of_mdiobus_register(bus, np);
3139 	if (err) {
3140 		dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3141 		mv88e6xxx_g2_irq_mdio_free(chip, bus);
3142 		return err;
3143 	}
3144 
3145 	if (external)
3146 		list_add_tail(&mdio_bus->list, &chip->mdios);
3147 	else
3148 		list_add(&mdio_bus->list, &chip->mdios);
3149 
3150 	return 0;
3151 }
3152 
3153 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
3154 	{ .compatible = "marvell,mv88e6xxx-mdio-external",
3155 	  .data = (void *)true },
3156 	{ },
3157 };
3158 
3159 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3160 
3161 {
3162 	struct mv88e6xxx_mdio_bus *mdio_bus;
3163 	struct mii_bus *bus;
3164 
3165 	list_for_each_entry(mdio_bus, &chip->mdios, list) {
3166 		bus = mdio_bus->bus;
3167 
3168 		if (!mdio_bus->external)
3169 			mv88e6xxx_g2_irq_mdio_free(chip, bus);
3170 
3171 		mdiobus_unregister(bus);
3172 	}
3173 }
3174 
3175 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3176 				    struct device_node *np)
3177 {
3178 	const struct of_device_id *match;
3179 	struct device_node *child;
3180 	int err;
3181 
3182 	/* Always register one mdio bus for the internal/default mdio
3183 	 * bus. This maybe represented in the device tree, but is
3184 	 * optional.
3185 	 */
3186 	child = of_get_child_by_name(np, "mdio");
3187 	err = mv88e6xxx_mdio_register(chip, child, false);
3188 	if (err)
3189 		return err;
3190 
3191 	/* Walk the device tree, and see if there are any other nodes
3192 	 * which say they are compatible with the external mdio
3193 	 * bus.
3194 	 */
3195 	for_each_available_child_of_node(np, child) {
3196 		match = of_match_node(mv88e6xxx_mdio_external_match, child);
3197 		if (match) {
3198 			err = mv88e6xxx_mdio_register(chip, child, true);
3199 			if (err) {
3200 				mv88e6xxx_mdios_unregister(chip);
3201 				of_node_put(child);
3202 				return err;
3203 			}
3204 		}
3205 	}
3206 
3207 	return 0;
3208 }
3209 
3210 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3211 {
3212 	struct mv88e6xxx_chip *chip = ds->priv;
3213 
3214 	return chip->eeprom_len;
3215 }
3216 
3217 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3218 				struct ethtool_eeprom *eeprom, u8 *data)
3219 {
3220 	struct mv88e6xxx_chip *chip = ds->priv;
3221 	int err;
3222 
3223 	if (!chip->info->ops->get_eeprom)
3224 		return -EOPNOTSUPP;
3225 
3226 	mv88e6xxx_reg_lock(chip);
3227 	err = chip->info->ops->get_eeprom(chip, eeprom, data);
3228 	mv88e6xxx_reg_unlock(chip);
3229 
3230 	if (err)
3231 		return err;
3232 
3233 	eeprom->magic = 0xc3ec4951;
3234 
3235 	return 0;
3236 }
3237 
3238 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3239 				struct ethtool_eeprom *eeprom, u8 *data)
3240 {
3241 	struct mv88e6xxx_chip *chip = ds->priv;
3242 	int err;
3243 
3244 	if (!chip->info->ops->set_eeprom)
3245 		return -EOPNOTSUPP;
3246 
3247 	if (eeprom->magic != 0xc3ec4951)
3248 		return -EINVAL;
3249 
3250 	mv88e6xxx_reg_lock(chip);
3251 	err = chip->info->ops->set_eeprom(chip, eeprom, data);
3252 	mv88e6xxx_reg_unlock(chip);
3253 
3254 	return err;
3255 }
3256 
3257 static const struct mv88e6xxx_ops mv88e6085_ops = {
3258 	/* MV88E6XXX_FAMILY_6097 */
3259 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3260 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3261 	.irl_init_all = mv88e6352_g2_irl_init_all,
3262 	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3263 	.phy_read = mv88e6185_phy_ppu_read,
3264 	.phy_write = mv88e6185_phy_ppu_write,
3265 	.port_set_link = mv88e6xxx_port_set_link,
3266 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3267 	.port_set_speed = mv88e6185_port_set_speed,
3268 	.port_tag_remap = mv88e6095_port_tag_remap,
3269 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3270 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3271 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3272 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3273 	.port_pause_limit = mv88e6097_port_pause_limit,
3274 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3275 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3276 	.port_link_state = mv88e6352_port_link_state,
3277 	.port_get_cmode = mv88e6185_port_get_cmode,
3278 	.port_setup_message_port = mv88e6xxx_setup_message_port,
3279 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3280 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3281 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3282 	.stats_get_strings = mv88e6095_stats_get_strings,
3283 	.stats_get_stats = mv88e6095_stats_get_stats,
3284 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3285 	.set_egress_port = mv88e6095_g1_set_egress_port,
3286 	.watchdog_ops = &mv88e6097_watchdog_ops,
3287 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3288 	.pot_clear = mv88e6xxx_g2_pot_clear,
3289 	.ppu_enable = mv88e6185_g1_ppu_enable,
3290 	.ppu_disable = mv88e6185_g1_ppu_disable,
3291 	.reset = mv88e6185_g1_reset,
3292 	.rmu_disable = mv88e6085_g1_rmu_disable,
3293 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3294 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3295 	.phylink_validate = mv88e6185_phylink_validate,
3296 };
3297 
3298 static const struct mv88e6xxx_ops mv88e6095_ops = {
3299 	/* MV88E6XXX_FAMILY_6095 */
3300 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3301 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3302 	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3303 	.phy_read = mv88e6185_phy_ppu_read,
3304 	.phy_write = mv88e6185_phy_ppu_write,
3305 	.port_set_link = mv88e6xxx_port_set_link,
3306 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3307 	.port_set_speed = mv88e6185_port_set_speed,
3308 	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
3309 	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
3310 	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
3311 	.port_link_state = mv88e6185_port_link_state,
3312 	.port_get_cmode = mv88e6185_port_get_cmode,
3313 	.port_setup_message_port = mv88e6xxx_setup_message_port,
3314 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3315 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3316 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3317 	.stats_get_strings = mv88e6095_stats_get_strings,
3318 	.stats_get_stats = mv88e6095_stats_get_stats,
3319 	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3320 	.ppu_enable = mv88e6185_g1_ppu_enable,
3321 	.ppu_disable = mv88e6185_g1_ppu_disable,
3322 	.reset = mv88e6185_g1_reset,
3323 	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3324 	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3325 	.phylink_validate = mv88e6185_phylink_validate,
3326 };
3327 
3328 static const struct mv88e6xxx_ops mv88e6097_ops = {
3329 	/* MV88E6XXX_FAMILY_6097 */
3330 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3331 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3332 	.irl_init_all = mv88e6352_g2_irl_init_all,
3333 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3334 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3335 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3336 	.port_set_link = mv88e6xxx_port_set_link,
3337 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3338 	.port_set_speed = mv88e6185_port_set_speed,
3339 	.port_tag_remap = mv88e6095_port_tag_remap,
3340 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3341 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3342 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3343 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3344 	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3345 	.port_pause_limit = mv88e6097_port_pause_limit,
3346 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3347 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3348 	.port_link_state = mv88e6352_port_link_state,
3349 	.port_get_cmode = mv88e6185_port_get_cmode,
3350 	.port_setup_message_port = mv88e6xxx_setup_message_port,
3351 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3352 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3353 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3354 	.stats_get_strings = mv88e6095_stats_get_strings,
3355 	.stats_get_stats = mv88e6095_stats_get_stats,
3356 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3357 	.set_egress_port = mv88e6095_g1_set_egress_port,
3358 	.watchdog_ops = &mv88e6097_watchdog_ops,
3359 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3360 	.pot_clear = mv88e6xxx_g2_pot_clear,
3361 	.reset = mv88e6352_g1_reset,
3362 	.rmu_disable = mv88e6085_g1_rmu_disable,
3363 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3364 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3365 	.phylink_validate = mv88e6185_phylink_validate,
3366 };
3367 
3368 static const struct mv88e6xxx_ops mv88e6123_ops = {
3369 	/* MV88E6XXX_FAMILY_6165 */
3370 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3371 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3372 	.irl_init_all = mv88e6352_g2_irl_init_all,
3373 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3374 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3375 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3376 	.port_set_link = mv88e6xxx_port_set_link,
3377 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3378 	.port_set_speed = mv88e6185_port_set_speed,
3379 	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
3380 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3381 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3382 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3383 	.port_link_state = mv88e6352_port_link_state,
3384 	.port_get_cmode = mv88e6185_port_get_cmode,
3385 	.port_setup_message_port = mv88e6xxx_setup_message_port,
3386 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3387 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3388 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3389 	.stats_get_strings = mv88e6095_stats_get_strings,
3390 	.stats_get_stats = mv88e6095_stats_get_stats,
3391 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3392 	.set_egress_port = mv88e6095_g1_set_egress_port,
3393 	.watchdog_ops = &mv88e6097_watchdog_ops,
3394 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3395 	.pot_clear = mv88e6xxx_g2_pot_clear,
3396 	.reset = mv88e6352_g1_reset,
3397 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
3398 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
3399 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3400 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3401 	.phylink_validate = mv88e6185_phylink_validate,
3402 };
3403 
3404 static const struct mv88e6xxx_ops mv88e6131_ops = {
3405 	/* MV88E6XXX_FAMILY_6185 */
3406 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3407 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3408 	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3409 	.phy_read = mv88e6185_phy_ppu_read,
3410 	.phy_write = mv88e6185_phy_ppu_write,
3411 	.port_set_link = mv88e6xxx_port_set_link,
3412 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3413 	.port_set_speed = mv88e6185_port_set_speed,
3414 	.port_tag_remap = mv88e6095_port_tag_remap,
3415 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3416 	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
3417 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3418 	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
3419 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3420 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3421 	.port_pause_limit = mv88e6097_port_pause_limit,
3422 	.port_set_pause = mv88e6185_port_set_pause,
3423 	.port_link_state = mv88e6352_port_link_state,
3424 	.port_get_cmode = mv88e6185_port_get_cmode,
3425 	.port_setup_message_port = mv88e6xxx_setup_message_port,
3426 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3427 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3428 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3429 	.stats_get_strings = mv88e6095_stats_get_strings,
3430 	.stats_get_stats = mv88e6095_stats_get_stats,
3431 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3432 	.set_egress_port = mv88e6095_g1_set_egress_port,
3433 	.watchdog_ops = &mv88e6097_watchdog_ops,
3434 	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3435 	.ppu_enable = mv88e6185_g1_ppu_enable,
3436 	.set_cascade_port = mv88e6185_g1_set_cascade_port,
3437 	.ppu_disable = mv88e6185_g1_ppu_disable,
3438 	.reset = mv88e6185_g1_reset,
3439 	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3440 	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3441 	.phylink_validate = mv88e6185_phylink_validate,
3442 };
3443 
3444 static const struct mv88e6xxx_ops mv88e6141_ops = {
3445 	/* MV88E6XXX_FAMILY_6341 */
3446 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3447 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3448 	.irl_init_all = mv88e6352_g2_irl_init_all,
3449 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
3450 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3451 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3452 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3453 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3454 	.port_set_link = mv88e6xxx_port_set_link,
3455 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3456 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3457 	.port_set_speed = mv88e6341_port_set_speed,
3458 	.port_max_speed_mode = mv88e6341_port_max_speed_mode,
3459 	.port_tag_remap = mv88e6095_port_tag_remap,
3460 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3461 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3462 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3463 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3464 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3465 	.port_pause_limit = mv88e6097_port_pause_limit,
3466 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3467 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3468 	.port_link_state = mv88e6352_port_link_state,
3469 	.port_get_cmode = mv88e6352_port_get_cmode,
3470 	.port_set_cmode = mv88e6341_port_set_cmode,
3471 	.port_setup_message_port = mv88e6xxx_setup_message_port,
3472 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3473 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3474 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
3475 	.stats_get_strings = mv88e6320_stats_get_strings,
3476 	.stats_get_stats = mv88e6390_stats_get_stats,
3477 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
3478 	.set_egress_port = mv88e6390_g1_set_egress_port,
3479 	.watchdog_ops = &mv88e6390_watchdog_ops,
3480 	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
3481 	.pot_clear = mv88e6xxx_g2_pot_clear,
3482 	.reset = mv88e6352_g1_reset,
3483 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3484 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3485 	.serdes_power = mv88e6390_serdes_power,
3486 	.serdes_get_lane = mv88e6341_serdes_get_lane,
3487 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3488 	.serdes_irq_enable = mv88e6390_serdes_irq_enable,
3489 	.serdes_irq_status = mv88e6390_serdes_irq_status,
3490 	.gpio_ops = &mv88e6352_gpio_ops,
3491 	.phylink_validate = mv88e6341_phylink_validate,
3492 };
3493 
3494 static const struct mv88e6xxx_ops mv88e6161_ops = {
3495 	/* MV88E6XXX_FAMILY_6165 */
3496 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3497 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3498 	.irl_init_all = mv88e6352_g2_irl_init_all,
3499 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3500 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3501 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3502 	.port_set_link = mv88e6xxx_port_set_link,
3503 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3504 	.port_set_speed = mv88e6185_port_set_speed,
3505 	.port_tag_remap = mv88e6095_port_tag_remap,
3506 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3507 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3508 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3509 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3510 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3511 	.port_pause_limit = mv88e6097_port_pause_limit,
3512 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3513 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3514 	.port_link_state = mv88e6352_port_link_state,
3515 	.port_get_cmode = mv88e6185_port_get_cmode,
3516 	.port_setup_message_port = mv88e6xxx_setup_message_port,
3517 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3518 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3519 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3520 	.stats_get_strings = mv88e6095_stats_get_strings,
3521 	.stats_get_stats = mv88e6095_stats_get_stats,
3522 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3523 	.set_egress_port = mv88e6095_g1_set_egress_port,
3524 	.watchdog_ops = &mv88e6097_watchdog_ops,
3525 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3526 	.pot_clear = mv88e6xxx_g2_pot_clear,
3527 	.reset = mv88e6352_g1_reset,
3528 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
3529 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
3530 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3531 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3532 	.avb_ops = &mv88e6165_avb_ops,
3533 	.ptp_ops = &mv88e6165_ptp_ops,
3534 	.phylink_validate = mv88e6185_phylink_validate,
3535 };
3536 
3537 static const struct mv88e6xxx_ops mv88e6165_ops = {
3538 	/* MV88E6XXX_FAMILY_6165 */
3539 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3540 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3541 	.irl_init_all = mv88e6352_g2_irl_init_all,
3542 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3543 	.phy_read = mv88e6165_phy_read,
3544 	.phy_write = mv88e6165_phy_write,
3545 	.port_set_link = mv88e6xxx_port_set_link,
3546 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3547 	.port_set_speed = mv88e6185_port_set_speed,
3548 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3549 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3550 	.port_link_state = mv88e6352_port_link_state,
3551 	.port_get_cmode = mv88e6185_port_get_cmode,
3552 	.port_setup_message_port = mv88e6xxx_setup_message_port,
3553 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3554 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3555 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3556 	.stats_get_strings = mv88e6095_stats_get_strings,
3557 	.stats_get_stats = mv88e6095_stats_get_stats,
3558 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3559 	.set_egress_port = mv88e6095_g1_set_egress_port,
3560 	.watchdog_ops = &mv88e6097_watchdog_ops,
3561 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3562 	.pot_clear = mv88e6xxx_g2_pot_clear,
3563 	.reset = mv88e6352_g1_reset,
3564 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
3565 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
3566 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3567 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3568 	.avb_ops = &mv88e6165_avb_ops,
3569 	.ptp_ops = &mv88e6165_ptp_ops,
3570 	.phylink_validate = mv88e6185_phylink_validate,
3571 };
3572 
3573 static const struct mv88e6xxx_ops mv88e6171_ops = {
3574 	/* MV88E6XXX_FAMILY_6351 */
3575 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3576 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3577 	.irl_init_all = mv88e6352_g2_irl_init_all,
3578 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3579 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3580 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3581 	.port_set_link = mv88e6xxx_port_set_link,
3582 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3583 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3584 	.port_set_speed = mv88e6185_port_set_speed,
3585 	.port_tag_remap = mv88e6095_port_tag_remap,
3586 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3587 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3588 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3589 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3590 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3591 	.port_pause_limit = mv88e6097_port_pause_limit,
3592 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3593 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3594 	.port_link_state = mv88e6352_port_link_state,
3595 	.port_get_cmode = mv88e6352_port_get_cmode,
3596 	.port_setup_message_port = mv88e6xxx_setup_message_port,
3597 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3598 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3599 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3600 	.stats_get_strings = mv88e6095_stats_get_strings,
3601 	.stats_get_stats = mv88e6095_stats_get_stats,
3602 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3603 	.set_egress_port = mv88e6095_g1_set_egress_port,
3604 	.watchdog_ops = &mv88e6097_watchdog_ops,
3605 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3606 	.pot_clear = mv88e6xxx_g2_pot_clear,
3607 	.reset = mv88e6352_g1_reset,
3608 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
3609 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
3610 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3611 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3612 	.phylink_validate = mv88e6185_phylink_validate,
3613 };
3614 
3615 static const struct mv88e6xxx_ops mv88e6172_ops = {
3616 	/* MV88E6XXX_FAMILY_6352 */
3617 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3618 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3619 	.irl_init_all = mv88e6352_g2_irl_init_all,
3620 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
3621 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3622 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3623 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3624 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3625 	.port_set_link = mv88e6xxx_port_set_link,
3626 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3627 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3628 	.port_set_speed = mv88e6352_port_set_speed,
3629 	.port_tag_remap = mv88e6095_port_tag_remap,
3630 	.port_set_policy = mv88e6352_port_set_policy,
3631 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3632 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3633 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3634 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3635 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3636 	.port_pause_limit = mv88e6097_port_pause_limit,
3637 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3638 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3639 	.port_link_state = mv88e6352_port_link_state,
3640 	.port_get_cmode = mv88e6352_port_get_cmode,
3641 	.port_setup_message_port = mv88e6xxx_setup_message_port,
3642 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3643 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3644 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3645 	.stats_get_strings = mv88e6095_stats_get_strings,
3646 	.stats_get_stats = mv88e6095_stats_get_stats,
3647 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3648 	.set_egress_port = mv88e6095_g1_set_egress_port,
3649 	.watchdog_ops = &mv88e6097_watchdog_ops,
3650 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3651 	.pot_clear = mv88e6xxx_g2_pot_clear,
3652 	.reset = mv88e6352_g1_reset,
3653 	.rmu_disable = mv88e6352_g1_rmu_disable,
3654 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
3655 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
3656 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3657 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3658 	.serdes_get_lane = mv88e6352_serdes_get_lane,
3659 	.serdes_power = mv88e6352_serdes_power,
3660 	.gpio_ops = &mv88e6352_gpio_ops,
3661 	.phylink_validate = mv88e6352_phylink_validate,
3662 };
3663 
3664 static const struct mv88e6xxx_ops mv88e6175_ops = {
3665 	/* MV88E6XXX_FAMILY_6351 */
3666 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3667 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3668 	.irl_init_all = mv88e6352_g2_irl_init_all,
3669 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3670 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3671 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3672 	.port_set_link = mv88e6xxx_port_set_link,
3673 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3674 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3675 	.port_set_speed = mv88e6185_port_set_speed,
3676 	.port_tag_remap = mv88e6095_port_tag_remap,
3677 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3678 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3679 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3680 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3681 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3682 	.port_pause_limit = mv88e6097_port_pause_limit,
3683 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3684 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3685 	.port_link_state = mv88e6352_port_link_state,
3686 	.port_get_cmode = mv88e6352_port_get_cmode,
3687 	.port_setup_message_port = mv88e6xxx_setup_message_port,
3688 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3689 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3690 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3691 	.stats_get_strings = mv88e6095_stats_get_strings,
3692 	.stats_get_stats = mv88e6095_stats_get_stats,
3693 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3694 	.set_egress_port = mv88e6095_g1_set_egress_port,
3695 	.watchdog_ops = &mv88e6097_watchdog_ops,
3696 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3697 	.pot_clear = mv88e6xxx_g2_pot_clear,
3698 	.reset = mv88e6352_g1_reset,
3699 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
3700 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
3701 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3702 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3703 	.phylink_validate = mv88e6185_phylink_validate,
3704 };
3705 
3706 static const struct mv88e6xxx_ops mv88e6176_ops = {
3707 	/* MV88E6XXX_FAMILY_6352 */
3708 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3709 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3710 	.irl_init_all = mv88e6352_g2_irl_init_all,
3711 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
3712 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3713 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3714 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3715 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3716 	.port_set_link = mv88e6xxx_port_set_link,
3717 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3718 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3719 	.port_set_speed = mv88e6352_port_set_speed,
3720 	.port_tag_remap = mv88e6095_port_tag_remap,
3721 	.port_set_policy = mv88e6352_port_set_policy,
3722 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3723 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3724 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3725 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3726 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3727 	.port_pause_limit = mv88e6097_port_pause_limit,
3728 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3729 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3730 	.port_link_state = mv88e6352_port_link_state,
3731 	.port_get_cmode = mv88e6352_port_get_cmode,
3732 	.port_setup_message_port = mv88e6xxx_setup_message_port,
3733 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3734 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3735 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3736 	.stats_get_strings = mv88e6095_stats_get_strings,
3737 	.stats_get_stats = mv88e6095_stats_get_stats,
3738 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3739 	.set_egress_port = mv88e6095_g1_set_egress_port,
3740 	.watchdog_ops = &mv88e6097_watchdog_ops,
3741 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3742 	.pot_clear = mv88e6xxx_g2_pot_clear,
3743 	.reset = mv88e6352_g1_reset,
3744 	.rmu_disable = mv88e6352_g1_rmu_disable,
3745 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
3746 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
3747 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3748 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3749 	.serdes_get_lane = mv88e6352_serdes_get_lane,
3750 	.serdes_power = mv88e6352_serdes_power,
3751 	.serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3752 	.serdes_irq_enable = mv88e6352_serdes_irq_enable,
3753 	.serdes_irq_status = mv88e6352_serdes_irq_status,
3754 	.gpio_ops = &mv88e6352_gpio_ops,
3755 	.phylink_validate = mv88e6352_phylink_validate,
3756 };
3757 
3758 static const struct mv88e6xxx_ops mv88e6185_ops = {
3759 	/* MV88E6XXX_FAMILY_6185 */
3760 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3761 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3762 	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3763 	.phy_read = mv88e6185_phy_ppu_read,
3764 	.phy_write = mv88e6185_phy_ppu_write,
3765 	.port_set_link = mv88e6xxx_port_set_link,
3766 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3767 	.port_set_speed = mv88e6185_port_set_speed,
3768 	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
3769 	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
3770 	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3771 	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
3772 	.port_set_pause = mv88e6185_port_set_pause,
3773 	.port_link_state = mv88e6185_port_link_state,
3774 	.port_get_cmode = mv88e6185_port_get_cmode,
3775 	.port_setup_message_port = mv88e6xxx_setup_message_port,
3776 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3777 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3778 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3779 	.stats_get_strings = mv88e6095_stats_get_strings,
3780 	.stats_get_stats = mv88e6095_stats_get_stats,
3781 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3782 	.set_egress_port = mv88e6095_g1_set_egress_port,
3783 	.watchdog_ops = &mv88e6097_watchdog_ops,
3784 	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3785 	.set_cascade_port = mv88e6185_g1_set_cascade_port,
3786 	.ppu_enable = mv88e6185_g1_ppu_enable,
3787 	.ppu_disable = mv88e6185_g1_ppu_disable,
3788 	.reset = mv88e6185_g1_reset,
3789 	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3790 	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3791 	.phylink_validate = mv88e6185_phylink_validate,
3792 };
3793 
3794 static const struct mv88e6xxx_ops mv88e6190_ops = {
3795 	/* MV88E6XXX_FAMILY_6390 */
3796 	.setup_errata = mv88e6390_setup_errata,
3797 	.irl_init_all = mv88e6390_g2_irl_init_all,
3798 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
3799 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3800 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3801 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3802 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3803 	.port_set_link = mv88e6xxx_port_set_link,
3804 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3805 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3806 	.port_set_speed = mv88e6390_port_set_speed,
3807 	.port_max_speed_mode = mv88e6390_port_max_speed_mode,
3808 	.port_tag_remap = mv88e6390_port_tag_remap,
3809 	.port_set_policy = mv88e6352_port_set_policy,
3810 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3811 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3812 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3813 	.port_pause_limit = mv88e6390_port_pause_limit,
3814 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3815 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3816 	.port_link_state = mv88e6352_port_link_state,
3817 	.port_get_cmode = mv88e6352_port_get_cmode,
3818 	.port_set_cmode = mv88e6390_port_set_cmode,
3819 	.port_setup_message_port = mv88e6xxx_setup_message_port,
3820 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3821 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3822 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
3823 	.stats_get_strings = mv88e6320_stats_get_strings,
3824 	.stats_get_stats = mv88e6390_stats_get_stats,
3825 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
3826 	.set_egress_port = mv88e6390_g1_set_egress_port,
3827 	.watchdog_ops = &mv88e6390_watchdog_ops,
3828 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3829 	.pot_clear = mv88e6xxx_g2_pot_clear,
3830 	.reset = mv88e6352_g1_reset,
3831 	.rmu_disable = mv88e6390_g1_rmu_disable,
3832 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
3833 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
3834 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3835 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3836 	.serdes_power = mv88e6390_serdes_power,
3837 	.serdes_get_lane = mv88e6390_serdes_get_lane,
3838 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3839 	.serdes_irq_enable = mv88e6390_serdes_irq_enable,
3840 	.serdes_irq_status = mv88e6390_serdes_irq_status,
3841 	.gpio_ops = &mv88e6352_gpio_ops,
3842 	.phylink_validate = mv88e6390_phylink_validate,
3843 };
3844 
3845 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3846 	/* MV88E6XXX_FAMILY_6390 */
3847 	.setup_errata = mv88e6390_setup_errata,
3848 	.irl_init_all = mv88e6390_g2_irl_init_all,
3849 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
3850 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3851 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3852 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3853 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3854 	.port_set_link = mv88e6xxx_port_set_link,
3855 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3856 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3857 	.port_set_speed = mv88e6390x_port_set_speed,
3858 	.port_max_speed_mode = mv88e6390x_port_max_speed_mode,
3859 	.port_tag_remap = mv88e6390_port_tag_remap,
3860 	.port_set_policy = mv88e6352_port_set_policy,
3861 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3862 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3863 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3864 	.port_pause_limit = mv88e6390_port_pause_limit,
3865 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3866 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3867 	.port_link_state = mv88e6352_port_link_state,
3868 	.port_get_cmode = mv88e6352_port_get_cmode,
3869 	.port_set_cmode = mv88e6390x_port_set_cmode,
3870 	.port_setup_message_port = mv88e6xxx_setup_message_port,
3871 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3872 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3873 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
3874 	.stats_get_strings = mv88e6320_stats_get_strings,
3875 	.stats_get_stats = mv88e6390_stats_get_stats,
3876 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
3877 	.set_egress_port = mv88e6390_g1_set_egress_port,
3878 	.watchdog_ops = &mv88e6390_watchdog_ops,
3879 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3880 	.pot_clear = mv88e6xxx_g2_pot_clear,
3881 	.reset = mv88e6352_g1_reset,
3882 	.rmu_disable = mv88e6390_g1_rmu_disable,
3883 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
3884 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
3885 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3886 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3887 	.serdes_power = mv88e6390_serdes_power,
3888 	.serdes_get_lane = mv88e6390x_serdes_get_lane,
3889 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3890 	.serdes_irq_enable = mv88e6390_serdes_irq_enable,
3891 	.serdes_irq_status = mv88e6390_serdes_irq_status,
3892 	.gpio_ops = &mv88e6352_gpio_ops,
3893 	.phylink_validate = mv88e6390x_phylink_validate,
3894 };
3895 
3896 static const struct mv88e6xxx_ops mv88e6191_ops = {
3897 	/* MV88E6XXX_FAMILY_6390 */
3898 	.setup_errata = mv88e6390_setup_errata,
3899 	.irl_init_all = mv88e6390_g2_irl_init_all,
3900 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
3901 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3902 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3903 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3904 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3905 	.port_set_link = mv88e6xxx_port_set_link,
3906 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3907 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3908 	.port_set_speed = mv88e6390_port_set_speed,
3909 	.port_max_speed_mode = mv88e6390_port_max_speed_mode,
3910 	.port_tag_remap = mv88e6390_port_tag_remap,
3911 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3912 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3913 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3914 	.port_pause_limit = mv88e6390_port_pause_limit,
3915 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3916 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3917 	.port_link_state = mv88e6352_port_link_state,
3918 	.port_get_cmode = mv88e6352_port_get_cmode,
3919 	.port_set_cmode = mv88e6390_port_set_cmode,
3920 	.port_setup_message_port = mv88e6xxx_setup_message_port,
3921 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3922 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3923 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
3924 	.stats_get_strings = mv88e6320_stats_get_strings,
3925 	.stats_get_stats = mv88e6390_stats_get_stats,
3926 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
3927 	.set_egress_port = mv88e6390_g1_set_egress_port,
3928 	.watchdog_ops = &mv88e6390_watchdog_ops,
3929 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3930 	.pot_clear = mv88e6xxx_g2_pot_clear,
3931 	.reset = mv88e6352_g1_reset,
3932 	.rmu_disable = mv88e6390_g1_rmu_disable,
3933 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
3934 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
3935 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3936 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3937 	.serdes_power = mv88e6390_serdes_power,
3938 	.serdes_get_lane = mv88e6390_serdes_get_lane,
3939 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3940 	.serdes_irq_enable = mv88e6390_serdes_irq_enable,
3941 	.serdes_irq_status = mv88e6390_serdes_irq_status,
3942 	.avb_ops = &mv88e6390_avb_ops,
3943 	.ptp_ops = &mv88e6352_ptp_ops,
3944 	.phylink_validate = mv88e6390_phylink_validate,
3945 };
3946 
3947 static const struct mv88e6xxx_ops mv88e6240_ops = {
3948 	/* MV88E6XXX_FAMILY_6352 */
3949 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3950 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3951 	.irl_init_all = mv88e6352_g2_irl_init_all,
3952 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
3953 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3954 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3955 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3956 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3957 	.port_set_link = mv88e6xxx_port_set_link,
3958 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3959 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3960 	.port_set_speed = mv88e6352_port_set_speed,
3961 	.port_tag_remap = mv88e6095_port_tag_remap,
3962 	.port_set_policy = mv88e6352_port_set_policy,
3963 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3964 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3965 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3966 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3967 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3968 	.port_pause_limit = mv88e6097_port_pause_limit,
3969 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3970 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3971 	.port_link_state = mv88e6352_port_link_state,
3972 	.port_get_cmode = mv88e6352_port_get_cmode,
3973 	.port_setup_message_port = mv88e6xxx_setup_message_port,
3974 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3975 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3976 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3977 	.stats_get_strings = mv88e6095_stats_get_strings,
3978 	.stats_get_stats = mv88e6095_stats_get_stats,
3979 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3980 	.set_egress_port = mv88e6095_g1_set_egress_port,
3981 	.watchdog_ops = &mv88e6097_watchdog_ops,
3982 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3983 	.pot_clear = mv88e6xxx_g2_pot_clear,
3984 	.reset = mv88e6352_g1_reset,
3985 	.rmu_disable = mv88e6352_g1_rmu_disable,
3986 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
3987 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
3988 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3989 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3990 	.serdes_get_lane = mv88e6352_serdes_get_lane,
3991 	.serdes_power = mv88e6352_serdes_power,
3992 	.serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3993 	.serdes_irq_enable = mv88e6352_serdes_irq_enable,
3994 	.serdes_irq_status = mv88e6352_serdes_irq_status,
3995 	.gpio_ops = &mv88e6352_gpio_ops,
3996 	.avb_ops = &mv88e6352_avb_ops,
3997 	.ptp_ops = &mv88e6352_ptp_ops,
3998 	.phylink_validate = mv88e6352_phylink_validate,
3999 };
4000 
4001 static const struct mv88e6xxx_ops mv88e6250_ops = {
4002 	/* MV88E6XXX_FAMILY_6250 */
4003 	.ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4004 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4005 	.irl_init_all = mv88e6352_g2_irl_init_all,
4006 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
4007 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
4008 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4009 	.phy_read = mv88e6xxx_g2_smi_phy_read,
4010 	.phy_write = mv88e6xxx_g2_smi_phy_write,
4011 	.port_set_link = mv88e6xxx_port_set_link,
4012 	.port_set_duplex = mv88e6xxx_port_set_duplex,
4013 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4014 	.port_set_speed = mv88e6250_port_set_speed,
4015 	.port_tag_remap = mv88e6095_port_tag_remap,
4016 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4017 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
4018 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4019 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4020 	.port_pause_limit = mv88e6097_port_pause_limit,
4021 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4022 	.port_link_state = mv88e6250_port_link_state,
4023 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
4024 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4025 	.stats_get_sset_count = mv88e6250_stats_get_sset_count,
4026 	.stats_get_strings = mv88e6250_stats_get_strings,
4027 	.stats_get_stats = mv88e6250_stats_get_stats,
4028 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
4029 	.set_egress_port = mv88e6095_g1_set_egress_port,
4030 	.watchdog_ops = &mv88e6250_watchdog_ops,
4031 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4032 	.pot_clear = mv88e6xxx_g2_pot_clear,
4033 	.reset = mv88e6250_g1_reset,
4034 	.vtu_getnext = mv88e6250_g1_vtu_getnext,
4035 	.vtu_loadpurge = mv88e6250_g1_vtu_loadpurge,
4036 	.avb_ops = &mv88e6352_avb_ops,
4037 	.ptp_ops = &mv88e6250_ptp_ops,
4038 	.phylink_validate = mv88e6065_phylink_validate,
4039 };
4040 
4041 static const struct mv88e6xxx_ops mv88e6290_ops = {
4042 	/* MV88E6XXX_FAMILY_6390 */
4043 	.setup_errata = mv88e6390_setup_errata,
4044 	.irl_init_all = mv88e6390_g2_irl_init_all,
4045 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
4046 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
4047 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4048 	.phy_read = mv88e6xxx_g2_smi_phy_read,
4049 	.phy_write = mv88e6xxx_g2_smi_phy_write,
4050 	.port_set_link = mv88e6xxx_port_set_link,
4051 	.port_set_duplex = mv88e6xxx_port_set_duplex,
4052 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4053 	.port_set_speed = mv88e6390_port_set_speed,
4054 	.port_max_speed_mode = mv88e6390_port_max_speed_mode,
4055 	.port_tag_remap = mv88e6390_port_tag_remap,
4056 	.port_set_policy = mv88e6352_port_set_policy,
4057 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4058 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
4059 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4060 	.port_pause_limit = mv88e6390_port_pause_limit,
4061 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4062 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4063 	.port_link_state = mv88e6352_port_link_state,
4064 	.port_get_cmode = mv88e6352_port_get_cmode,
4065 	.port_set_cmode = mv88e6390_port_set_cmode,
4066 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4067 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
4068 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4069 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
4070 	.stats_get_strings = mv88e6320_stats_get_strings,
4071 	.stats_get_stats = mv88e6390_stats_get_stats,
4072 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
4073 	.set_egress_port = mv88e6390_g1_set_egress_port,
4074 	.watchdog_ops = &mv88e6390_watchdog_ops,
4075 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4076 	.pot_clear = mv88e6xxx_g2_pot_clear,
4077 	.reset = mv88e6352_g1_reset,
4078 	.rmu_disable = mv88e6390_g1_rmu_disable,
4079 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
4080 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
4081 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
4082 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4083 	.serdes_power = mv88e6390_serdes_power,
4084 	.serdes_get_lane = mv88e6390_serdes_get_lane,
4085 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4086 	.serdes_irq_enable = mv88e6390_serdes_irq_enable,
4087 	.serdes_irq_status = mv88e6390_serdes_irq_status,
4088 	.gpio_ops = &mv88e6352_gpio_ops,
4089 	.avb_ops = &mv88e6390_avb_ops,
4090 	.ptp_ops = &mv88e6352_ptp_ops,
4091 	.phylink_validate = mv88e6390_phylink_validate,
4092 };
4093 
4094 static const struct mv88e6xxx_ops mv88e6320_ops = {
4095 	/* MV88E6XXX_FAMILY_6320 */
4096 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4097 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4098 	.irl_init_all = mv88e6352_g2_irl_init_all,
4099 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
4100 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
4101 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4102 	.phy_read = mv88e6xxx_g2_smi_phy_read,
4103 	.phy_write = mv88e6xxx_g2_smi_phy_write,
4104 	.port_set_link = mv88e6xxx_port_set_link,
4105 	.port_set_duplex = mv88e6xxx_port_set_duplex,
4106 	.port_set_speed = mv88e6185_port_set_speed,
4107 	.port_tag_remap = mv88e6095_port_tag_remap,
4108 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4109 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
4110 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4111 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4112 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4113 	.port_pause_limit = mv88e6097_port_pause_limit,
4114 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4115 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4116 	.port_link_state = mv88e6352_port_link_state,
4117 	.port_get_cmode = mv88e6352_port_get_cmode,
4118 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4119 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
4120 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4121 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
4122 	.stats_get_strings = mv88e6320_stats_get_strings,
4123 	.stats_get_stats = mv88e6320_stats_get_stats,
4124 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
4125 	.set_egress_port = mv88e6095_g1_set_egress_port,
4126 	.watchdog_ops = &mv88e6390_watchdog_ops,
4127 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4128 	.pot_clear = mv88e6xxx_g2_pot_clear,
4129 	.reset = mv88e6352_g1_reset,
4130 	.vtu_getnext = mv88e6185_g1_vtu_getnext,
4131 	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4132 	.gpio_ops = &mv88e6352_gpio_ops,
4133 	.avb_ops = &mv88e6352_avb_ops,
4134 	.ptp_ops = &mv88e6352_ptp_ops,
4135 	.phylink_validate = mv88e6185_phylink_validate,
4136 };
4137 
4138 static const struct mv88e6xxx_ops mv88e6321_ops = {
4139 	/* MV88E6XXX_FAMILY_6320 */
4140 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4141 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4142 	.irl_init_all = mv88e6352_g2_irl_init_all,
4143 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
4144 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
4145 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4146 	.phy_read = mv88e6xxx_g2_smi_phy_read,
4147 	.phy_write = mv88e6xxx_g2_smi_phy_write,
4148 	.port_set_link = mv88e6xxx_port_set_link,
4149 	.port_set_duplex = mv88e6xxx_port_set_duplex,
4150 	.port_set_speed = mv88e6185_port_set_speed,
4151 	.port_tag_remap = mv88e6095_port_tag_remap,
4152 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4153 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
4154 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4155 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4156 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4157 	.port_pause_limit = mv88e6097_port_pause_limit,
4158 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4159 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4160 	.port_link_state = mv88e6352_port_link_state,
4161 	.port_get_cmode = mv88e6352_port_get_cmode,
4162 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4163 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
4164 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4165 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
4166 	.stats_get_strings = mv88e6320_stats_get_strings,
4167 	.stats_get_stats = mv88e6320_stats_get_stats,
4168 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
4169 	.set_egress_port = mv88e6095_g1_set_egress_port,
4170 	.watchdog_ops = &mv88e6390_watchdog_ops,
4171 	.reset = mv88e6352_g1_reset,
4172 	.vtu_getnext = mv88e6185_g1_vtu_getnext,
4173 	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4174 	.gpio_ops = &mv88e6352_gpio_ops,
4175 	.avb_ops = &mv88e6352_avb_ops,
4176 	.ptp_ops = &mv88e6352_ptp_ops,
4177 	.phylink_validate = mv88e6185_phylink_validate,
4178 };
4179 
4180 static const struct mv88e6xxx_ops mv88e6341_ops = {
4181 	/* MV88E6XXX_FAMILY_6341 */
4182 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4183 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4184 	.irl_init_all = mv88e6352_g2_irl_init_all,
4185 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
4186 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
4187 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4188 	.phy_read = mv88e6xxx_g2_smi_phy_read,
4189 	.phy_write = mv88e6xxx_g2_smi_phy_write,
4190 	.port_set_link = mv88e6xxx_port_set_link,
4191 	.port_set_duplex = mv88e6xxx_port_set_duplex,
4192 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4193 	.port_set_speed = mv88e6341_port_set_speed,
4194 	.port_max_speed_mode = mv88e6341_port_max_speed_mode,
4195 	.port_tag_remap = mv88e6095_port_tag_remap,
4196 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4197 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
4198 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4199 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4200 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4201 	.port_pause_limit = mv88e6097_port_pause_limit,
4202 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4203 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4204 	.port_link_state = mv88e6352_port_link_state,
4205 	.port_get_cmode = mv88e6352_port_get_cmode,
4206 	.port_set_cmode = mv88e6341_port_set_cmode,
4207 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4208 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
4209 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4210 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
4211 	.stats_get_strings = mv88e6320_stats_get_strings,
4212 	.stats_get_stats = mv88e6390_stats_get_stats,
4213 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
4214 	.set_egress_port = mv88e6390_g1_set_egress_port,
4215 	.watchdog_ops = &mv88e6390_watchdog_ops,
4216 	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
4217 	.pot_clear = mv88e6xxx_g2_pot_clear,
4218 	.reset = mv88e6352_g1_reset,
4219 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
4220 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4221 	.serdes_power = mv88e6390_serdes_power,
4222 	.serdes_get_lane = mv88e6341_serdes_get_lane,
4223 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4224 	.serdes_irq_enable = mv88e6390_serdes_irq_enable,
4225 	.serdes_irq_status = mv88e6390_serdes_irq_status,
4226 	.gpio_ops = &mv88e6352_gpio_ops,
4227 	.avb_ops = &mv88e6390_avb_ops,
4228 	.ptp_ops = &mv88e6352_ptp_ops,
4229 	.phylink_validate = mv88e6341_phylink_validate,
4230 };
4231 
4232 static const struct mv88e6xxx_ops mv88e6350_ops = {
4233 	/* MV88E6XXX_FAMILY_6351 */
4234 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4235 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4236 	.irl_init_all = mv88e6352_g2_irl_init_all,
4237 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4238 	.phy_read = mv88e6xxx_g2_smi_phy_read,
4239 	.phy_write = mv88e6xxx_g2_smi_phy_write,
4240 	.port_set_link = mv88e6xxx_port_set_link,
4241 	.port_set_duplex = mv88e6xxx_port_set_duplex,
4242 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4243 	.port_set_speed = mv88e6185_port_set_speed,
4244 	.port_tag_remap = mv88e6095_port_tag_remap,
4245 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4246 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
4247 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4248 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4249 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4250 	.port_pause_limit = mv88e6097_port_pause_limit,
4251 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4252 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4253 	.port_link_state = mv88e6352_port_link_state,
4254 	.port_get_cmode = mv88e6352_port_get_cmode,
4255 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4256 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
4257 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4258 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
4259 	.stats_get_strings = mv88e6095_stats_get_strings,
4260 	.stats_get_stats = mv88e6095_stats_get_stats,
4261 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
4262 	.set_egress_port = mv88e6095_g1_set_egress_port,
4263 	.watchdog_ops = &mv88e6097_watchdog_ops,
4264 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4265 	.pot_clear = mv88e6xxx_g2_pot_clear,
4266 	.reset = mv88e6352_g1_reset,
4267 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
4268 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
4269 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
4270 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4271 	.phylink_validate = mv88e6185_phylink_validate,
4272 };
4273 
4274 static const struct mv88e6xxx_ops mv88e6351_ops = {
4275 	/* MV88E6XXX_FAMILY_6351 */
4276 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4277 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4278 	.irl_init_all = mv88e6352_g2_irl_init_all,
4279 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4280 	.phy_read = mv88e6xxx_g2_smi_phy_read,
4281 	.phy_write = mv88e6xxx_g2_smi_phy_write,
4282 	.port_set_link = mv88e6xxx_port_set_link,
4283 	.port_set_duplex = mv88e6xxx_port_set_duplex,
4284 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4285 	.port_set_speed = mv88e6185_port_set_speed,
4286 	.port_tag_remap = mv88e6095_port_tag_remap,
4287 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4288 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
4289 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4290 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4291 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4292 	.port_pause_limit = mv88e6097_port_pause_limit,
4293 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4294 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4295 	.port_link_state = mv88e6352_port_link_state,
4296 	.port_get_cmode = mv88e6352_port_get_cmode,
4297 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4298 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
4299 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4300 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
4301 	.stats_get_strings = mv88e6095_stats_get_strings,
4302 	.stats_get_stats = mv88e6095_stats_get_stats,
4303 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
4304 	.set_egress_port = mv88e6095_g1_set_egress_port,
4305 	.watchdog_ops = &mv88e6097_watchdog_ops,
4306 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4307 	.pot_clear = mv88e6xxx_g2_pot_clear,
4308 	.reset = mv88e6352_g1_reset,
4309 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
4310 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
4311 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
4312 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4313 	.avb_ops = &mv88e6352_avb_ops,
4314 	.ptp_ops = &mv88e6352_ptp_ops,
4315 	.phylink_validate = mv88e6185_phylink_validate,
4316 };
4317 
4318 static const struct mv88e6xxx_ops mv88e6352_ops = {
4319 	/* MV88E6XXX_FAMILY_6352 */
4320 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4321 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4322 	.irl_init_all = mv88e6352_g2_irl_init_all,
4323 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
4324 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
4325 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4326 	.phy_read = mv88e6xxx_g2_smi_phy_read,
4327 	.phy_write = mv88e6xxx_g2_smi_phy_write,
4328 	.port_set_link = mv88e6xxx_port_set_link,
4329 	.port_set_duplex = mv88e6xxx_port_set_duplex,
4330 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4331 	.port_set_speed = mv88e6352_port_set_speed,
4332 	.port_tag_remap = mv88e6095_port_tag_remap,
4333 	.port_set_policy = mv88e6352_port_set_policy,
4334 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4335 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
4336 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4337 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4338 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4339 	.port_pause_limit = mv88e6097_port_pause_limit,
4340 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4341 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4342 	.port_link_state = mv88e6352_port_link_state,
4343 	.port_get_cmode = mv88e6352_port_get_cmode,
4344 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4345 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
4346 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4347 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
4348 	.stats_get_strings = mv88e6095_stats_get_strings,
4349 	.stats_get_stats = mv88e6095_stats_get_stats,
4350 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
4351 	.set_egress_port = mv88e6095_g1_set_egress_port,
4352 	.watchdog_ops = &mv88e6097_watchdog_ops,
4353 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4354 	.pot_clear = mv88e6xxx_g2_pot_clear,
4355 	.reset = mv88e6352_g1_reset,
4356 	.rmu_disable = mv88e6352_g1_rmu_disable,
4357 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
4358 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
4359 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
4360 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4361 	.serdes_get_lane = mv88e6352_serdes_get_lane,
4362 	.serdes_power = mv88e6352_serdes_power,
4363 	.serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4364 	.serdes_irq_enable = mv88e6352_serdes_irq_enable,
4365 	.serdes_irq_status = mv88e6352_serdes_irq_status,
4366 	.gpio_ops = &mv88e6352_gpio_ops,
4367 	.avb_ops = &mv88e6352_avb_ops,
4368 	.ptp_ops = &mv88e6352_ptp_ops,
4369 	.serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4370 	.serdes_get_strings = mv88e6352_serdes_get_strings,
4371 	.serdes_get_stats = mv88e6352_serdes_get_stats,
4372 	.phylink_validate = mv88e6352_phylink_validate,
4373 };
4374 
4375 static const struct mv88e6xxx_ops mv88e6390_ops = {
4376 	/* MV88E6XXX_FAMILY_6390 */
4377 	.setup_errata = mv88e6390_setup_errata,
4378 	.irl_init_all = mv88e6390_g2_irl_init_all,
4379 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
4380 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
4381 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4382 	.phy_read = mv88e6xxx_g2_smi_phy_read,
4383 	.phy_write = mv88e6xxx_g2_smi_phy_write,
4384 	.port_set_link = mv88e6xxx_port_set_link,
4385 	.port_set_duplex = mv88e6xxx_port_set_duplex,
4386 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4387 	.port_set_speed = mv88e6390_port_set_speed,
4388 	.port_max_speed_mode = mv88e6390_port_max_speed_mode,
4389 	.port_tag_remap = mv88e6390_port_tag_remap,
4390 	.port_set_policy = mv88e6352_port_set_policy,
4391 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4392 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
4393 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4394 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4395 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4396 	.port_pause_limit = mv88e6390_port_pause_limit,
4397 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4398 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4399 	.port_link_state = mv88e6352_port_link_state,
4400 	.port_get_cmode = mv88e6352_port_get_cmode,
4401 	.port_set_cmode = mv88e6390_port_set_cmode,
4402 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4403 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
4404 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4405 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
4406 	.stats_get_strings = mv88e6320_stats_get_strings,
4407 	.stats_get_stats = mv88e6390_stats_get_stats,
4408 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
4409 	.set_egress_port = mv88e6390_g1_set_egress_port,
4410 	.watchdog_ops = &mv88e6390_watchdog_ops,
4411 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4412 	.pot_clear = mv88e6xxx_g2_pot_clear,
4413 	.reset = mv88e6352_g1_reset,
4414 	.rmu_disable = mv88e6390_g1_rmu_disable,
4415 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
4416 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
4417 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
4418 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4419 	.serdes_power = mv88e6390_serdes_power,
4420 	.serdes_get_lane = mv88e6390_serdes_get_lane,
4421 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4422 	.serdes_irq_enable = mv88e6390_serdes_irq_enable,
4423 	.serdes_irq_status = mv88e6390_serdes_irq_status,
4424 	.gpio_ops = &mv88e6352_gpio_ops,
4425 	.avb_ops = &mv88e6390_avb_ops,
4426 	.ptp_ops = &mv88e6352_ptp_ops,
4427 	.phylink_validate = mv88e6390_phylink_validate,
4428 };
4429 
4430 static const struct mv88e6xxx_ops mv88e6390x_ops = {
4431 	/* MV88E6XXX_FAMILY_6390 */
4432 	.setup_errata = mv88e6390_setup_errata,
4433 	.irl_init_all = mv88e6390_g2_irl_init_all,
4434 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
4435 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
4436 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4437 	.phy_read = mv88e6xxx_g2_smi_phy_read,
4438 	.phy_write = mv88e6xxx_g2_smi_phy_write,
4439 	.port_set_link = mv88e6xxx_port_set_link,
4440 	.port_set_duplex = mv88e6xxx_port_set_duplex,
4441 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4442 	.port_set_speed = mv88e6390x_port_set_speed,
4443 	.port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4444 	.port_tag_remap = mv88e6390_port_tag_remap,
4445 	.port_set_policy = mv88e6352_port_set_policy,
4446 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4447 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
4448 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4449 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4450 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4451 	.port_pause_limit = mv88e6390_port_pause_limit,
4452 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4453 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4454 	.port_link_state = mv88e6352_port_link_state,
4455 	.port_get_cmode = mv88e6352_port_get_cmode,
4456 	.port_set_cmode = mv88e6390x_port_set_cmode,
4457 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4458 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
4459 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4460 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
4461 	.stats_get_strings = mv88e6320_stats_get_strings,
4462 	.stats_get_stats = mv88e6390_stats_get_stats,
4463 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
4464 	.set_egress_port = mv88e6390_g1_set_egress_port,
4465 	.watchdog_ops = &mv88e6390_watchdog_ops,
4466 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4467 	.pot_clear = mv88e6xxx_g2_pot_clear,
4468 	.reset = mv88e6352_g1_reset,
4469 	.rmu_disable = mv88e6390_g1_rmu_disable,
4470 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
4471 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
4472 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
4473 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4474 	.serdes_power = mv88e6390_serdes_power,
4475 	.serdes_get_lane = mv88e6390x_serdes_get_lane,
4476 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4477 	.serdes_irq_enable = mv88e6390_serdes_irq_enable,
4478 	.serdes_irq_status = mv88e6390_serdes_irq_status,
4479 	.gpio_ops = &mv88e6352_gpio_ops,
4480 	.avb_ops = &mv88e6390_avb_ops,
4481 	.ptp_ops = &mv88e6352_ptp_ops,
4482 	.phylink_validate = mv88e6390x_phylink_validate,
4483 };
4484 
4485 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4486 	[MV88E6085] = {
4487 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
4488 		.family = MV88E6XXX_FAMILY_6097,
4489 		.name = "Marvell 88E6085",
4490 		.num_databases = 4096,
4491 		.num_macs = 8192,
4492 		.num_ports = 10,
4493 		.num_internal_phys = 5,
4494 		.max_vid = 4095,
4495 		.port_base_addr = 0x10,
4496 		.phy_base_addr = 0x0,
4497 		.global1_addr = 0x1b,
4498 		.global2_addr = 0x1c,
4499 		.age_time_coeff = 15000,
4500 		.g1_irqs = 8,
4501 		.g2_irqs = 10,
4502 		.atu_move_port_mask = 0xf,
4503 		.pvt = true,
4504 		.multi_chip = true,
4505 		.tag_protocol = DSA_TAG_PROTO_DSA,
4506 		.ops = &mv88e6085_ops,
4507 	},
4508 
4509 	[MV88E6095] = {
4510 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
4511 		.family = MV88E6XXX_FAMILY_6095,
4512 		.name = "Marvell 88E6095/88E6095F",
4513 		.num_databases = 256,
4514 		.num_macs = 8192,
4515 		.num_ports = 11,
4516 		.num_internal_phys = 0,
4517 		.max_vid = 4095,
4518 		.port_base_addr = 0x10,
4519 		.phy_base_addr = 0x0,
4520 		.global1_addr = 0x1b,
4521 		.global2_addr = 0x1c,
4522 		.age_time_coeff = 15000,
4523 		.g1_irqs = 8,
4524 		.atu_move_port_mask = 0xf,
4525 		.multi_chip = true,
4526 		.tag_protocol = DSA_TAG_PROTO_DSA,
4527 		.ops = &mv88e6095_ops,
4528 	},
4529 
4530 	[MV88E6097] = {
4531 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
4532 		.family = MV88E6XXX_FAMILY_6097,
4533 		.name = "Marvell 88E6097/88E6097F",
4534 		.num_databases = 4096,
4535 		.num_macs = 8192,
4536 		.num_ports = 11,
4537 		.num_internal_phys = 8,
4538 		.max_vid = 4095,
4539 		.port_base_addr = 0x10,
4540 		.phy_base_addr = 0x0,
4541 		.global1_addr = 0x1b,
4542 		.global2_addr = 0x1c,
4543 		.age_time_coeff = 15000,
4544 		.g1_irqs = 8,
4545 		.g2_irqs = 10,
4546 		.atu_move_port_mask = 0xf,
4547 		.pvt = true,
4548 		.multi_chip = true,
4549 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4550 		.ops = &mv88e6097_ops,
4551 	},
4552 
4553 	[MV88E6123] = {
4554 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
4555 		.family = MV88E6XXX_FAMILY_6165,
4556 		.name = "Marvell 88E6123",
4557 		.num_databases = 4096,
4558 		.num_macs = 1024,
4559 		.num_ports = 3,
4560 		.num_internal_phys = 5,
4561 		.max_vid = 4095,
4562 		.port_base_addr = 0x10,
4563 		.phy_base_addr = 0x0,
4564 		.global1_addr = 0x1b,
4565 		.global2_addr = 0x1c,
4566 		.age_time_coeff = 15000,
4567 		.g1_irqs = 9,
4568 		.g2_irqs = 10,
4569 		.atu_move_port_mask = 0xf,
4570 		.pvt = true,
4571 		.multi_chip = true,
4572 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4573 		.ops = &mv88e6123_ops,
4574 	},
4575 
4576 	[MV88E6131] = {
4577 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
4578 		.family = MV88E6XXX_FAMILY_6185,
4579 		.name = "Marvell 88E6131",
4580 		.num_databases = 256,
4581 		.num_macs = 8192,
4582 		.num_ports = 8,
4583 		.num_internal_phys = 0,
4584 		.max_vid = 4095,
4585 		.port_base_addr = 0x10,
4586 		.phy_base_addr = 0x0,
4587 		.global1_addr = 0x1b,
4588 		.global2_addr = 0x1c,
4589 		.age_time_coeff = 15000,
4590 		.g1_irqs = 9,
4591 		.atu_move_port_mask = 0xf,
4592 		.multi_chip = true,
4593 		.tag_protocol = DSA_TAG_PROTO_DSA,
4594 		.ops = &mv88e6131_ops,
4595 	},
4596 
4597 	[MV88E6141] = {
4598 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4599 		.family = MV88E6XXX_FAMILY_6341,
4600 		.name = "Marvell 88E6141",
4601 		.num_databases = 4096,
4602 		.num_macs = 2048,
4603 		.num_ports = 6,
4604 		.num_internal_phys = 5,
4605 		.num_gpio = 11,
4606 		.max_vid = 4095,
4607 		.port_base_addr = 0x10,
4608 		.phy_base_addr = 0x10,
4609 		.global1_addr = 0x1b,
4610 		.global2_addr = 0x1c,
4611 		.age_time_coeff = 3750,
4612 		.atu_move_port_mask = 0x1f,
4613 		.g1_irqs = 9,
4614 		.g2_irqs = 10,
4615 		.pvt = true,
4616 		.multi_chip = true,
4617 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4618 		.ops = &mv88e6141_ops,
4619 	},
4620 
4621 	[MV88E6161] = {
4622 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4623 		.family = MV88E6XXX_FAMILY_6165,
4624 		.name = "Marvell 88E6161",
4625 		.num_databases = 4096,
4626 		.num_macs = 1024,
4627 		.num_ports = 6,
4628 		.num_internal_phys = 5,
4629 		.max_vid = 4095,
4630 		.port_base_addr = 0x10,
4631 		.phy_base_addr = 0x0,
4632 		.global1_addr = 0x1b,
4633 		.global2_addr = 0x1c,
4634 		.age_time_coeff = 15000,
4635 		.g1_irqs = 9,
4636 		.g2_irqs = 10,
4637 		.atu_move_port_mask = 0xf,
4638 		.pvt = true,
4639 		.multi_chip = true,
4640 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4641 		.ptp_support = true,
4642 		.ops = &mv88e6161_ops,
4643 	},
4644 
4645 	[MV88E6165] = {
4646 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4647 		.family = MV88E6XXX_FAMILY_6165,
4648 		.name = "Marvell 88E6165",
4649 		.num_databases = 4096,
4650 		.num_macs = 8192,
4651 		.num_ports = 6,
4652 		.num_internal_phys = 0,
4653 		.max_vid = 4095,
4654 		.port_base_addr = 0x10,
4655 		.phy_base_addr = 0x0,
4656 		.global1_addr = 0x1b,
4657 		.global2_addr = 0x1c,
4658 		.age_time_coeff = 15000,
4659 		.g1_irqs = 9,
4660 		.g2_irqs = 10,
4661 		.atu_move_port_mask = 0xf,
4662 		.pvt = true,
4663 		.multi_chip = true,
4664 		.tag_protocol = DSA_TAG_PROTO_DSA,
4665 		.ptp_support = true,
4666 		.ops = &mv88e6165_ops,
4667 	},
4668 
4669 	[MV88E6171] = {
4670 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4671 		.family = MV88E6XXX_FAMILY_6351,
4672 		.name = "Marvell 88E6171",
4673 		.num_databases = 4096,
4674 		.num_macs = 8192,
4675 		.num_ports = 7,
4676 		.num_internal_phys = 5,
4677 		.max_vid = 4095,
4678 		.port_base_addr = 0x10,
4679 		.phy_base_addr = 0x0,
4680 		.global1_addr = 0x1b,
4681 		.global2_addr = 0x1c,
4682 		.age_time_coeff = 15000,
4683 		.g1_irqs = 9,
4684 		.g2_irqs = 10,
4685 		.atu_move_port_mask = 0xf,
4686 		.pvt = true,
4687 		.multi_chip = true,
4688 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4689 		.ops = &mv88e6171_ops,
4690 	},
4691 
4692 	[MV88E6172] = {
4693 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
4694 		.family = MV88E6XXX_FAMILY_6352,
4695 		.name = "Marvell 88E6172",
4696 		.num_databases = 4096,
4697 		.num_macs = 8192,
4698 		.num_ports = 7,
4699 		.num_internal_phys = 5,
4700 		.num_gpio = 15,
4701 		.max_vid = 4095,
4702 		.port_base_addr = 0x10,
4703 		.phy_base_addr = 0x0,
4704 		.global1_addr = 0x1b,
4705 		.global2_addr = 0x1c,
4706 		.age_time_coeff = 15000,
4707 		.g1_irqs = 9,
4708 		.g2_irqs = 10,
4709 		.atu_move_port_mask = 0xf,
4710 		.pvt = true,
4711 		.multi_chip = true,
4712 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4713 		.ops = &mv88e6172_ops,
4714 	},
4715 
4716 	[MV88E6175] = {
4717 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
4718 		.family = MV88E6XXX_FAMILY_6351,
4719 		.name = "Marvell 88E6175",
4720 		.num_databases = 4096,
4721 		.num_macs = 8192,
4722 		.num_ports = 7,
4723 		.num_internal_phys = 5,
4724 		.max_vid = 4095,
4725 		.port_base_addr = 0x10,
4726 		.phy_base_addr = 0x0,
4727 		.global1_addr = 0x1b,
4728 		.global2_addr = 0x1c,
4729 		.age_time_coeff = 15000,
4730 		.g1_irqs = 9,
4731 		.g2_irqs = 10,
4732 		.atu_move_port_mask = 0xf,
4733 		.pvt = true,
4734 		.multi_chip = true,
4735 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4736 		.ops = &mv88e6175_ops,
4737 	},
4738 
4739 	[MV88E6176] = {
4740 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
4741 		.family = MV88E6XXX_FAMILY_6352,
4742 		.name = "Marvell 88E6176",
4743 		.num_databases = 4096,
4744 		.num_macs = 8192,
4745 		.num_ports = 7,
4746 		.num_internal_phys = 5,
4747 		.num_gpio = 15,
4748 		.max_vid = 4095,
4749 		.port_base_addr = 0x10,
4750 		.phy_base_addr = 0x0,
4751 		.global1_addr = 0x1b,
4752 		.global2_addr = 0x1c,
4753 		.age_time_coeff = 15000,
4754 		.g1_irqs = 9,
4755 		.g2_irqs = 10,
4756 		.atu_move_port_mask = 0xf,
4757 		.pvt = true,
4758 		.multi_chip = true,
4759 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4760 		.ops = &mv88e6176_ops,
4761 	},
4762 
4763 	[MV88E6185] = {
4764 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
4765 		.family = MV88E6XXX_FAMILY_6185,
4766 		.name = "Marvell 88E6185",
4767 		.num_databases = 256,
4768 		.num_macs = 8192,
4769 		.num_ports = 10,
4770 		.num_internal_phys = 0,
4771 		.max_vid = 4095,
4772 		.port_base_addr = 0x10,
4773 		.phy_base_addr = 0x0,
4774 		.global1_addr = 0x1b,
4775 		.global2_addr = 0x1c,
4776 		.age_time_coeff = 15000,
4777 		.g1_irqs = 8,
4778 		.atu_move_port_mask = 0xf,
4779 		.multi_chip = true,
4780 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4781 		.ops = &mv88e6185_ops,
4782 	},
4783 
4784 	[MV88E6190] = {
4785 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
4786 		.family = MV88E6XXX_FAMILY_6390,
4787 		.name = "Marvell 88E6190",
4788 		.num_databases = 4096,
4789 		.num_macs = 16384,
4790 		.num_ports = 11,	/* 10 + Z80 */
4791 		.num_internal_phys = 9,
4792 		.num_gpio = 16,
4793 		.max_vid = 8191,
4794 		.port_base_addr = 0x0,
4795 		.phy_base_addr = 0x0,
4796 		.global1_addr = 0x1b,
4797 		.global2_addr = 0x1c,
4798 		.tag_protocol = DSA_TAG_PROTO_DSA,
4799 		.age_time_coeff = 3750,
4800 		.g1_irqs = 9,
4801 		.g2_irqs = 14,
4802 		.pvt = true,
4803 		.multi_chip = true,
4804 		.atu_move_port_mask = 0x1f,
4805 		.ops = &mv88e6190_ops,
4806 	},
4807 
4808 	[MV88E6190X] = {
4809 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
4810 		.family = MV88E6XXX_FAMILY_6390,
4811 		.name = "Marvell 88E6190X",
4812 		.num_databases = 4096,
4813 		.num_macs = 16384,
4814 		.num_ports = 11,	/* 10 + Z80 */
4815 		.num_internal_phys = 9,
4816 		.num_gpio = 16,
4817 		.max_vid = 8191,
4818 		.port_base_addr = 0x0,
4819 		.phy_base_addr = 0x0,
4820 		.global1_addr = 0x1b,
4821 		.global2_addr = 0x1c,
4822 		.age_time_coeff = 3750,
4823 		.g1_irqs = 9,
4824 		.g2_irqs = 14,
4825 		.atu_move_port_mask = 0x1f,
4826 		.pvt = true,
4827 		.multi_chip = true,
4828 		.tag_protocol = DSA_TAG_PROTO_DSA,
4829 		.ops = &mv88e6190x_ops,
4830 	},
4831 
4832 	[MV88E6191] = {
4833 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
4834 		.family = MV88E6XXX_FAMILY_6390,
4835 		.name = "Marvell 88E6191",
4836 		.num_databases = 4096,
4837 		.num_macs = 16384,
4838 		.num_ports = 11,	/* 10 + Z80 */
4839 		.num_internal_phys = 9,
4840 		.max_vid = 8191,
4841 		.port_base_addr = 0x0,
4842 		.phy_base_addr = 0x0,
4843 		.global1_addr = 0x1b,
4844 		.global2_addr = 0x1c,
4845 		.age_time_coeff = 3750,
4846 		.g1_irqs = 9,
4847 		.g2_irqs = 14,
4848 		.atu_move_port_mask = 0x1f,
4849 		.pvt = true,
4850 		.multi_chip = true,
4851 		.tag_protocol = DSA_TAG_PROTO_DSA,
4852 		.ptp_support = true,
4853 		.ops = &mv88e6191_ops,
4854 	},
4855 
4856 	[MV88E6220] = {
4857 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
4858 		.family = MV88E6XXX_FAMILY_6250,
4859 		.name = "Marvell 88E6220",
4860 		.num_databases = 64,
4861 
4862 		/* Ports 2-4 are not routed to pins
4863 		 * => usable ports 0, 1, 5, 6
4864 		 */
4865 		.num_ports = 7,
4866 		.num_internal_phys = 2,
4867 		.invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
4868 		.max_vid = 4095,
4869 		.port_base_addr = 0x08,
4870 		.phy_base_addr = 0x00,
4871 		.global1_addr = 0x0f,
4872 		.global2_addr = 0x07,
4873 		.age_time_coeff = 15000,
4874 		.g1_irqs = 9,
4875 		.g2_irqs = 10,
4876 		.atu_move_port_mask = 0xf,
4877 		.dual_chip = true,
4878 		.tag_protocol = DSA_TAG_PROTO_DSA,
4879 		.ptp_support = true,
4880 		.ops = &mv88e6250_ops,
4881 	},
4882 
4883 	[MV88E6240] = {
4884 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
4885 		.family = MV88E6XXX_FAMILY_6352,
4886 		.name = "Marvell 88E6240",
4887 		.num_databases = 4096,
4888 		.num_macs = 8192,
4889 		.num_ports = 7,
4890 		.num_internal_phys = 5,
4891 		.num_gpio = 15,
4892 		.max_vid = 4095,
4893 		.port_base_addr = 0x10,
4894 		.phy_base_addr = 0x0,
4895 		.global1_addr = 0x1b,
4896 		.global2_addr = 0x1c,
4897 		.age_time_coeff = 15000,
4898 		.g1_irqs = 9,
4899 		.g2_irqs = 10,
4900 		.atu_move_port_mask = 0xf,
4901 		.pvt = true,
4902 		.multi_chip = true,
4903 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4904 		.ptp_support = true,
4905 		.ops = &mv88e6240_ops,
4906 	},
4907 
4908 	[MV88E6250] = {
4909 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
4910 		.family = MV88E6XXX_FAMILY_6250,
4911 		.name = "Marvell 88E6250",
4912 		.num_databases = 64,
4913 		.num_ports = 7,
4914 		.num_internal_phys = 5,
4915 		.max_vid = 4095,
4916 		.port_base_addr = 0x08,
4917 		.phy_base_addr = 0x00,
4918 		.global1_addr = 0x0f,
4919 		.global2_addr = 0x07,
4920 		.age_time_coeff = 15000,
4921 		.g1_irqs = 9,
4922 		.g2_irqs = 10,
4923 		.atu_move_port_mask = 0xf,
4924 		.dual_chip = true,
4925 		.tag_protocol = DSA_TAG_PROTO_DSA,
4926 		.ptp_support = true,
4927 		.ops = &mv88e6250_ops,
4928 	},
4929 
4930 	[MV88E6290] = {
4931 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
4932 		.family = MV88E6XXX_FAMILY_6390,
4933 		.name = "Marvell 88E6290",
4934 		.num_databases = 4096,
4935 		.num_ports = 11,	/* 10 + Z80 */
4936 		.num_internal_phys = 9,
4937 		.num_gpio = 16,
4938 		.max_vid = 8191,
4939 		.port_base_addr = 0x0,
4940 		.phy_base_addr = 0x0,
4941 		.global1_addr = 0x1b,
4942 		.global2_addr = 0x1c,
4943 		.age_time_coeff = 3750,
4944 		.g1_irqs = 9,
4945 		.g2_irqs = 14,
4946 		.atu_move_port_mask = 0x1f,
4947 		.pvt = true,
4948 		.multi_chip = true,
4949 		.tag_protocol = DSA_TAG_PROTO_DSA,
4950 		.ptp_support = true,
4951 		.ops = &mv88e6290_ops,
4952 	},
4953 
4954 	[MV88E6320] = {
4955 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
4956 		.family = MV88E6XXX_FAMILY_6320,
4957 		.name = "Marvell 88E6320",
4958 		.num_databases = 4096,
4959 		.num_macs = 8192,
4960 		.num_ports = 7,
4961 		.num_internal_phys = 5,
4962 		.num_gpio = 15,
4963 		.max_vid = 4095,
4964 		.port_base_addr = 0x10,
4965 		.phy_base_addr = 0x0,
4966 		.global1_addr = 0x1b,
4967 		.global2_addr = 0x1c,
4968 		.age_time_coeff = 15000,
4969 		.g1_irqs = 8,
4970 		.g2_irqs = 10,
4971 		.atu_move_port_mask = 0xf,
4972 		.pvt = true,
4973 		.multi_chip = true,
4974 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4975 		.ptp_support = true,
4976 		.ops = &mv88e6320_ops,
4977 	},
4978 
4979 	[MV88E6321] = {
4980 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
4981 		.family = MV88E6XXX_FAMILY_6320,
4982 		.name = "Marvell 88E6321",
4983 		.num_databases = 4096,
4984 		.num_macs = 8192,
4985 		.num_ports = 7,
4986 		.num_internal_phys = 5,
4987 		.num_gpio = 15,
4988 		.max_vid = 4095,
4989 		.port_base_addr = 0x10,
4990 		.phy_base_addr = 0x0,
4991 		.global1_addr = 0x1b,
4992 		.global2_addr = 0x1c,
4993 		.age_time_coeff = 15000,
4994 		.g1_irqs = 8,
4995 		.g2_irqs = 10,
4996 		.atu_move_port_mask = 0xf,
4997 		.multi_chip = true,
4998 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4999 		.ptp_support = true,
5000 		.ops = &mv88e6321_ops,
5001 	},
5002 
5003 	[MV88E6341] = {
5004 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
5005 		.family = MV88E6XXX_FAMILY_6341,
5006 		.name = "Marvell 88E6341",
5007 		.num_databases = 4096,
5008 		.num_macs = 2048,
5009 		.num_internal_phys = 5,
5010 		.num_ports = 6,
5011 		.num_gpio = 11,
5012 		.max_vid = 4095,
5013 		.port_base_addr = 0x10,
5014 		.phy_base_addr = 0x10,
5015 		.global1_addr = 0x1b,
5016 		.global2_addr = 0x1c,
5017 		.age_time_coeff = 3750,
5018 		.atu_move_port_mask = 0x1f,
5019 		.g1_irqs = 9,
5020 		.g2_irqs = 10,
5021 		.pvt = true,
5022 		.multi_chip = true,
5023 		.tag_protocol = DSA_TAG_PROTO_EDSA,
5024 		.ptp_support = true,
5025 		.ops = &mv88e6341_ops,
5026 	},
5027 
5028 	[MV88E6350] = {
5029 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
5030 		.family = MV88E6XXX_FAMILY_6351,
5031 		.name = "Marvell 88E6350",
5032 		.num_databases = 4096,
5033 		.num_macs = 8192,
5034 		.num_ports = 7,
5035 		.num_internal_phys = 5,
5036 		.max_vid = 4095,
5037 		.port_base_addr = 0x10,
5038 		.phy_base_addr = 0x0,
5039 		.global1_addr = 0x1b,
5040 		.global2_addr = 0x1c,
5041 		.age_time_coeff = 15000,
5042 		.g1_irqs = 9,
5043 		.g2_irqs = 10,
5044 		.atu_move_port_mask = 0xf,
5045 		.pvt = true,
5046 		.multi_chip = true,
5047 		.tag_protocol = DSA_TAG_PROTO_EDSA,
5048 		.ops = &mv88e6350_ops,
5049 	},
5050 
5051 	[MV88E6351] = {
5052 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
5053 		.family = MV88E6XXX_FAMILY_6351,
5054 		.name = "Marvell 88E6351",
5055 		.num_databases = 4096,
5056 		.num_macs = 8192,
5057 		.num_ports = 7,
5058 		.num_internal_phys = 5,
5059 		.max_vid = 4095,
5060 		.port_base_addr = 0x10,
5061 		.phy_base_addr = 0x0,
5062 		.global1_addr = 0x1b,
5063 		.global2_addr = 0x1c,
5064 		.age_time_coeff = 15000,
5065 		.g1_irqs = 9,
5066 		.g2_irqs = 10,
5067 		.atu_move_port_mask = 0xf,
5068 		.pvt = true,
5069 		.multi_chip = true,
5070 		.tag_protocol = DSA_TAG_PROTO_EDSA,
5071 		.ops = &mv88e6351_ops,
5072 	},
5073 
5074 	[MV88E6352] = {
5075 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
5076 		.family = MV88E6XXX_FAMILY_6352,
5077 		.name = "Marvell 88E6352",
5078 		.num_databases = 4096,
5079 		.num_macs = 8192,
5080 		.num_ports = 7,
5081 		.num_internal_phys = 5,
5082 		.num_gpio = 15,
5083 		.max_vid = 4095,
5084 		.port_base_addr = 0x10,
5085 		.phy_base_addr = 0x0,
5086 		.global1_addr = 0x1b,
5087 		.global2_addr = 0x1c,
5088 		.age_time_coeff = 15000,
5089 		.g1_irqs = 9,
5090 		.g2_irqs = 10,
5091 		.atu_move_port_mask = 0xf,
5092 		.pvt = true,
5093 		.multi_chip = true,
5094 		.tag_protocol = DSA_TAG_PROTO_EDSA,
5095 		.ptp_support = true,
5096 		.ops = &mv88e6352_ops,
5097 	},
5098 	[MV88E6390] = {
5099 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
5100 		.family = MV88E6XXX_FAMILY_6390,
5101 		.name = "Marvell 88E6390",
5102 		.num_databases = 4096,
5103 		.num_macs = 16384,
5104 		.num_ports = 11,	/* 10 + Z80 */
5105 		.num_internal_phys = 9,
5106 		.num_gpio = 16,
5107 		.max_vid = 8191,
5108 		.port_base_addr = 0x0,
5109 		.phy_base_addr = 0x0,
5110 		.global1_addr = 0x1b,
5111 		.global2_addr = 0x1c,
5112 		.age_time_coeff = 3750,
5113 		.g1_irqs = 9,
5114 		.g2_irqs = 14,
5115 		.atu_move_port_mask = 0x1f,
5116 		.pvt = true,
5117 		.multi_chip = true,
5118 		.tag_protocol = DSA_TAG_PROTO_DSA,
5119 		.ptp_support = true,
5120 		.ops = &mv88e6390_ops,
5121 	},
5122 	[MV88E6390X] = {
5123 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
5124 		.family = MV88E6XXX_FAMILY_6390,
5125 		.name = "Marvell 88E6390X",
5126 		.num_databases = 4096,
5127 		.num_macs = 16384,
5128 		.num_ports = 11,	/* 10 + Z80 */
5129 		.num_internal_phys = 9,
5130 		.num_gpio = 16,
5131 		.max_vid = 8191,
5132 		.port_base_addr = 0x0,
5133 		.phy_base_addr = 0x0,
5134 		.global1_addr = 0x1b,
5135 		.global2_addr = 0x1c,
5136 		.age_time_coeff = 3750,
5137 		.g1_irqs = 9,
5138 		.g2_irqs = 14,
5139 		.atu_move_port_mask = 0x1f,
5140 		.pvt = true,
5141 		.multi_chip = true,
5142 		.tag_protocol = DSA_TAG_PROTO_DSA,
5143 		.ptp_support = true,
5144 		.ops = &mv88e6390x_ops,
5145 	},
5146 };
5147 
5148 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
5149 {
5150 	int i;
5151 
5152 	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5153 		if (mv88e6xxx_table[i].prod_num == prod_num)
5154 			return &mv88e6xxx_table[i];
5155 
5156 	return NULL;
5157 }
5158 
5159 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
5160 {
5161 	const struct mv88e6xxx_info *info;
5162 	unsigned int prod_num, rev;
5163 	u16 id;
5164 	int err;
5165 
5166 	mv88e6xxx_reg_lock(chip);
5167 	err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
5168 	mv88e6xxx_reg_unlock(chip);
5169 	if (err)
5170 		return err;
5171 
5172 	prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5173 	rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
5174 
5175 	info = mv88e6xxx_lookup_info(prod_num);
5176 	if (!info)
5177 		return -ENODEV;
5178 
5179 	/* Update the compatible info with the probed one */
5180 	chip->info = info;
5181 
5182 	err = mv88e6xxx_g2_require(chip);
5183 	if (err)
5184 		return err;
5185 
5186 	dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5187 		 chip->info->prod_num, chip->info->name, rev);
5188 
5189 	return 0;
5190 }
5191 
5192 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
5193 {
5194 	struct mv88e6xxx_chip *chip;
5195 
5196 	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5197 	if (!chip)
5198 		return NULL;
5199 
5200 	chip->dev = dev;
5201 
5202 	mutex_init(&chip->reg_lock);
5203 	INIT_LIST_HEAD(&chip->mdios);
5204 	idr_init(&chip->policies);
5205 
5206 	return chip;
5207 }
5208 
5209 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
5210 							int port)
5211 {
5212 	struct mv88e6xxx_chip *chip = ds->priv;
5213 
5214 	return chip->info->tag_protocol;
5215 }
5216 
5217 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
5218 				      const struct switchdev_obj_port_mdb *mdb)
5219 {
5220 	/* We don't need any dynamic resource from the kernel (yet),
5221 	 * so skip the prepare phase.
5222 	 */
5223 
5224 	return 0;
5225 }
5226 
5227 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5228 				   const struct switchdev_obj_port_mdb *mdb)
5229 {
5230 	struct mv88e6xxx_chip *chip = ds->priv;
5231 
5232 	mv88e6xxx_reg_lock(chip);
5233 	if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5234 					 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
5235 		dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
5236 			port);
5237 	mv88e6xxx_reg_unlock(chip);
5238 }
5239 
5240 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5241 				  const struct switchdev_obj_port_mdb *mdb)
5242 {
5243 	struct mv88e6xxx_chip *chip = ds->priv;
5244 	int err;
5245 
5246 	mv88e6xxx_reg_lock(chip);
5247 	err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
5248 	mv88e6xxx_reg_unlock(chip);
5249 
5250 	return err;
5251 }
5252 
5253 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5254 				     struct dsa_mall_mirror_tc_entry *mirror,
5255 				     bool ingress)
5256 {
5257 	enum mv88e6xxx_egress_direction direction = ingress ?
5258 						MV88E6XXX_EGRESS_DIR_INGRESS :
5259 						MV88E6XXX_EGRESS_DIR_EGRESS;
5260 	struct mv88e6xxx_chip *chip = ds->priv;
5261 	bool other_mirrors = false;
5262 	int i;
5263 	int err;
5264 
5265 	if (!chip->info->ops->set_egress_port)
5266 		return -EOPNOTSUPP;
5267 
5268 	mutex_lock(&chip->reg_lock);
5269 	if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5270 	    mirror->to_local_port) {
5271 		for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5272 			other_mirrors |= ingress ?
5273 					 chip->ports[i].mirror_ingress :
5274 					 chip->ports[i].mirror_egress;
5275 
5276 		/* Can't change egress port when other mirror is active */
5277 		if (other_mirrors) {
5278 			err = -EBUSY;
5279 			goto out;
5280 		}
5281 
5282 		err = chip->info->ops->set_egress_port(chip,
5283 						       direction,
5284 						       mirror->to_local_port);
5285 		if (err)
5286 			goto out;
5287 	}
5288 
5289 	err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5290 out:
5291 	mutex_unlock(&chip->reg_lock);
5292 
5293 	return err;
5294 }
5295 
5296 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5297 				      struct dsa_mall_mirror_tc_entry *mirror)
5298 {
5299 	enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5300 						MV88E6XXX_EGRESS_DIR_INGRESS :
5301 						MV88E6XXX_EGRESS_DIR_EGRESS;
5302 	struct mv88e6xxx_chip *chip = ds->priv;
5303 	bool other_mirrors = false;
5304 	int i;
5305 
5306 	mutex_lock(&chip->reg_lock);
5307 	if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5308 		dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5309 
5310 	for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5311 		other_mirrors |= mirror->ingress ?
5312 				 chip->ports[i].mirror_ingress :
5313 				 chip->ports[i].mirror_egress;
5314 
5315 	/* Reset egress port when no other mirror is active */
5316 	if (!other_mirrors) {
5317 		if (chip->info->ops->set_egress_port(chip,
5318 						     direction,
5319 						     dsa_upstream_port(ds,
5320 								       port)))
5321 			dev_err(ds->dev, "failed to set egress port\n");
5322 	}
5323 
5324 	mutex_unlock(&chip->reg_lock);
5325 }
5326 
5327 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
5328 					 bool unicast, bool multicast)
5329 {
5330 	struct mv88e6xxx_chip *chip = ds->priv;
5331 	int err = -EOPNOTSUPP;
5332 
5333 	mv88e6xxx_reg_lock(chip);
5334 	if (chip->info->ops->port_set_egress_floods)
5335 		err = chip->info->ops->port_set_egress_floods(chip, port,
5336 							      unicast,
5337 							      multicast);
5338 	mv88e6xxx_reg_unlock(chip);
5339 
5340 	return err;
5341 }
5342 
5343 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
5344 	.get_tag_protocol	= mv88e6xxx_get_tag_protocol,
5345 	.setup			= mv88e6xxx_setup,
5346 	.teardown		= mv88e6xxx_teardown,
5347 	.phylink_validate	= mv88e6xxx_validate,
5348 	.phylink_mac_link_state	= mv88e6xxx_link_state,
5349 	.phylink_mac_config	= mv88e6xxx_mac_config,
5350 	.phylink_mac_link_down	= mv88e6xxx_mac_link_down,
5351 	.phylink_mac_link_up	= mv88e6xxx_mac_link_up,
5352 	.get_strings		= mv88e6xxx_get_strings,
5353 	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,
5354 	.get_sset_count		= mv88e6xxx_get_sset_count,
5355 	.port_enable		= mv88e6xxx_port_enable,
5356 	.port_disable		= mv88e6xxx_port_disable,
5357 	.get_mac_eee		= mv88e6xxx_get_mac_eee,
5358 	.set_mac_eee		= mv88e6xxx_set_mac_eee,
5359 	.get_eeprom_len		= mv88e6xxx_get_eeprom_len,
5360 	.get_eeprom		= mv88e6xxx_get_eeprom,
5361 	.set_eeprom		= mv88e6xxx_set_eeprom,
5362 	.get_regs_len		= mv88e6xxx_get_regs_len,
5363 	.get_regs		= mv88e6xxx_get_regs,
5364 	.get_rxnfc		= mv88e6xxx_get_rxnfc,
5365 	.set_rxnfc		= mv88e6xxx_set_rxnfc,
5366 	.set_ageing_time	= mv88e6xxx_set_ageing_time,
5367 	.port_bridge_join	= mv88e6xxx_port_bridge_join,
5368 	.port_bridge_leave	= mv88e6xxx_port_bridge_leave,
5369 	.port_egress_floods	= mv88e6xxx_port_egress_floods,
5370 	.port_stp_state_set	= mv88e6xxx_port_stp_state_set,
5371 	.port_fast_age		= mv88e6xxx_port_fast_age,
5372 	.port_vlan_filtering	= mv88e6xxx_port_vlan_filtering,
5373 	.port_vlan_prepare	= mv88e6xxx_port_vlan_prepare,
5374 	.port_vlan_add		= mv88e6xxx_port_vlan_add,
5375 	.port_vlan_del		= mv88e6xxx_port_vlan_del,
5376 	.port_fdb_add           = mv88e6xxx_port_fdb_add,
5377 	.port_fdb_del           = mv88e6xxx_port_fdb_del,
5378 	.port_fdb_dump          = mv88e6xxx_port_fdb_dump,
5379 	.port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
5380 	.port_mdb_add           = mv88e6xxx_port_mdb_add,
5381 	.port_mdb_del           = mv88e6xxx_port_mdb_del,
5382 	.port_mirror_add	= mv88e6xxx_port_mirror_add,
5383 	.port_mirror_del	= mv88e6xxx_port_mirror_del,
5384 	.crosschip_bridge_join	= mv88e6xxx_crosschip_bridge_join,
5385 	.crosschip_bridge_leave	= mv88e6xxx_crosschip_bridge_leave,
5386 	.port_hwtstamp_set	= mv88e6xxx_port_hwtstamp_set,
5387 	.port_hwtstamp_get	= mv88e6xxx_port_hwtstamp_get,
5388 	.port_txtstamp		= mv88e6xxx_port_txtstamp,
5389 	.port_rxtstamp		= mv88e6xxx_port_rxtstamp,
5390 	.get_ts_info		= mv88e6xxx_get_ts_info,
5391 	.devlink_param_get	= mv88e6xxx_devlink_param_get,
5392 	.devlink_param_set	= mv88e6xxx_devlink_param_set,
5393 };
5394 
5395 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
5396 {
5397 	struct device *dev = chip->dev;
5398 	struct dsa_switch *ds;
5399 
5400 	ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
5401 	if (!ds)
5402 		return -ENOMEM;
5403 
5404 	ds->dev = dev;
5405 	ds->num_ports = mv88e6xxx_num_ports(chip);
5406 	ds->priv = chip;
5407 	ds->dev = dev;
5408 	ds->ops = &mv88e6xxx_switch_ops;
5409 	ds->ageing_time_min = chip->info->age_time_coeff;
5410 	ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
5411 
5412 	dev_set_drvdata(dev, ds);
5413 
5414 	return dsa_register_switch(ds);
5415 }
5416 
5417 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
5418 {
5419 	dsa_unregister_switch(chip->ds);
5420 }
5421 
5422 static const void *pdata_device_get_match_data(struct device *dev)
5423 {
5424 	const struct of_device_id *matches = dev->driver->of_match_table;
5425 	const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
5426 
5427 	for (; matches->name[0] || matches->type[0] || matches->compatible[0];
5428 	     matches++) {
5429 		if (!strcmp(pdata->compatible, matches->compatible))
5430 			return matches->data;
5431 	}
5432 	return NULL;
5433 }
5434 
5435 /* There is no suspend to RAM support at DSA level yet, the switch configuration
5436  * would be lost after a power cycle so prevent it to be suspended.
5437  */
5438 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
5439 {
5440 	return -EOPNOTSUPP;
5441 }
5442 
5443 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
5444 {
5445 	return 0;
5446 }
5447 
5448 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
5449 
5450 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
5451 {
5452 	struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
5453 	const struct mv88e6xxx_info *compat_info = NULL;
5454 	struct device *dev = &mdiodev->dev;
5455 	struct device_node *np = dev->of_node;
5456 	struct mv88e6xxx_chip *chip;
5457 	int port;
5458 	int err;
5459 
5460 	if (!np && !pdata)
5461 		return -EINVAL;
5462 
5463 	if (np)
5464 		compat_info = of_device_get_match_data(dev);
5465 
5466 	if (pdata) {
5467 		compat_info = pdata_device_get_match_data(dev);
5468 
5469 		if (!pdata->netdev)
5470 			return -EINVAL;
5471 
5472 		for (port = 0; port < DSA_MAX_PORTS; port++) {
5473 			if (!(pdata->enabled_ports & (1 << port)))
5474 				continue;
5475 			if (strcmp(pdata->cd.port_names[port], "cpu"))
5476 				continue;
5477 			pdata->cd.netdev[port] = &pdata->netdev->dev;
5478 			break;
5479 		}
5480 	}
5481 
5482 	if (!compat_info)
5483 		return -EINVAL;
5484 
5485 	chip = mv88e6xxx_alloc_chip(dev);
5486 	if (!chip) {
5487 		err = -ENOMEM;
5488 		goto out;
5489 	}
5490 
5491 	chip->info = compat_info;
5492 
5493 	err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
5494 	if (err)
5495 		goto out;
5496 
5497 	chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
5498 	if (IS_ERR(chip->reset)) {
5499 		err = PTR_ERR(chip->reset);
5500 		goto out;
5501 	}
5502 	if (chip->reset)
5503 		usleep_range(1000, 2000);
5504 
5505 	err = mv88e6xxx_detect(chip);
5506 	if (err)
5507 		goto out;
5508 
5509 	mv88e6xxx_phy_init(chip);
5510 
5511 	if (chip->info->ops->get_eeprom) {
5512 		if (np)
5513 			of_property_read_u32(np, "eeprom-length",
5514 					     &chip->eeprom_len);
5515 		else
5516 			chip->eeprom_len = pdata->eeprom_len;
5517 	}
5518 
5519 	mv88e6xxx_reg_lock(chip);
5520 	err = mv88e6xxx_switch_reset(chip);
5521 	mv88e6xxx_reg_unlock(chip);
5522 	if (err)
5523 		goto out;
5524 
5525 	if (np) {
5526 		chip->irq = of_irq_get(np, 0);
5527 		if (chip->irq == -EPROBE_DEFER) {
5528 			err = chip->irq;
5529 			goto out;
5530 		}
5531 	}
5532 
5533 	if (pdata)
5534 		chip->irq = pdata->irq;
5535 
5536 	/* Has to be performed before the MDIO bus is created, because
5537 	 * the PHYs will link their interrupts to these interrupt
5538 	 * controllers
5539 	 */
5540 	mv88e6xxx_reg_lock(chip);
5541 	if (chip->irq > 0)
5542 		err = mv88e6xxx_g1_irq_setup(chip);
5543 	else
5544 		err = mv88e6xxx_irq_poll_setup(chip);
5545 	mv88e6xxx_reg_unlock(chip);
5546 
5547 	if (err)
5548 		goto out;
5549 
5550 	if (chip->info->g2_irqs > 0) {
5551 		err = mv88e6xxx_g2_irq_setup(chip);
5552 		if (err)
5553 			goto out_g1_irq;
5554 	}
5555 
5556 	err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
5557 	if (err)
5558 		goto out_g2_irq;
5559 
5560 	err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
5561 	if (err)
5562 		goto out_g1_atu_prob_irq;
5563 
5564 	err = mv88e6xxx_mdios_register(chip, np);
5565 	if (err)
5566 		goto out_g1_vtu_prob_irq;
5567 
5568 	err = mv88e6xxx_register_switch(chip);
5569 	if (err)
5570 		goto out_mdio;
5571 
5572 	return 0;
5573 
5574 out_mdio:
5575 	mv88e6xxx_mdios_unregister(chip);
5576 out_g1_vtu_prob_irq:
5577 	mv88e6xxx_g1_vtu_prob_irq_free(chip);
5578 out_g1_atu_prob_irq:
5579 	mv88e6xxx_g1_atu_prob_irq_free(chip);
5580 out_g2_irq:
5581 	if (chip->info->g2_irqs > 0)
5582 		mv88e6xxx_g2_irq_free(chip);
5583 out_g1_irq:
5584 	if (chip->irq > 0)
5585 		mv88e6xxx_g1_irq_free(chip);
5586 	else
5587 		mv88e6xxx_irq_poll_free(chip);
5588 out:
5589 	if (pdata)
5590 		dev_put(pdata->netdev);
5591 
5592 	return err;
5593 }
5594 
5595 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
5596 {
5597 	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
5598 	struct mv88e6xxx_chip *chip = ds->priv;
5599 
5600 	if (chip->info->ptp_support) {
5601 		mv88e6xxx_hwtstamp_free(chip);
5602 		mv88e6xxx_ptp_free(chip);
5603 	}
5604 
5605 	mv88e6xxx_phy_destroy(chip);
5606 	mv88e6xxx_unregister_switch(chip);
5607 	mv88e6xxx_mdios_unregister(chip);
5608 
5609 	mv88e6xxx_g1_vtu_prob_irq_free(chip);
5610 	mv88e6xxx_g1_atu_prob_irq_free(chip);
5611 
5612 	if (chip->info->g2_irqs > 0)
5613 		mv88e6xxx_g2_irq_free(chip);
5614 
5615 	if (chip->irq > 0)
5616 		mv88e6xxx_g1_irq_free(chip);
5617 	else
5618 		mv88e6xxx_irq_poll_free(chip);
5619 }
5620 
5621 static const struct of_device_id mv88e6xxx_of_match[] = {
5622 	{
5623 		.compatible = "marvell,mv88e6085",
5624 		.data = &mv88e6xxx_table[MV88E6085],
5625 	},
5626 	{
5627 		.compatible = "marvell,mv88e6190",
5628 		.data = &mv88e6xxx_table[MV88E6190],
5629 	},
5630 	{
5631 		.compatible = "marvell,mv88e6250",
5632 		.data = &mv88e6xxx_table[MV88E6250],
5633 	},
5634 	{ /* sentinel */ },
5635 };
5636 
5637 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
5638 
5639 static struct mdio_driver mv88e6xxx_driver = {
5640 	.probe	= mv88e6xxx_probe,
5641 	.remove = mv88e6xxx_remove,
5642 	.mdiodrv.driver = {
5643 		.name = "mv88e6085",
5644 		.of_match_table = mv88e6xxx_of_match,
5645 		.pm = &mv88e6xxx_pm_ops,
5646 	},
5647 };
5648 
5649 mdio_module_driver(mv88e6xxx_driver);
5650 
5651 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
5652 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
5653 MODULE_LICENSE("GPL");
5654