1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/etherdevice.h> 16 #include <linux/ethtool.h> 17 #include <linux/if_bridge.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/platform_data/mv88e6xxx.h> 29 #include <linux/netdevice.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/phylink.h> 32 #include <net/dsa.h> 33 34 #include "chip.h" 35 #include "devlink.h" 36 #include "global1.h" 37 #include "global2.h" 38 #include "hwtstamp.h" 39 #include "phy.h" 40 #include "port.h" 41 #include "ptp.h" 42 #include "serdes.h" 43 #include "smi.h" 44 45 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 46 { 47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 48 dev_err(chip->dev, "Switch registers lock not held!\n"); 49 dump_stack(); 50 } 51 } 52 53 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 54 { 55 int err; 56 57 assert_reg_lock(chip); 58 59 err = mv88e6xxx_smi_read(chip, addr, reg, val); 60 if (err) 61 return err; 62 63 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 64 addr, reg, *val); 65 66 return 0; 67 } 68 69 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 70 { 71 int err; 72 73 assert_reg_lock(chip); 74 75 err = mv88e6xxx_smi_write(chip, addr, reg, val); 76 if (err) 77 return err; 78 79 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 80 addr, reg, val); 81 82 return 0; 83 } 84 85 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 86 u16 mask, u16 val) 87 { 88 u16 data; 89 int err; 90 int i; 91 92 /* There's no bus specific operation to wait for a mask */ 93 for (i = 0; i < 16; i++) { 94 err = mv88e6xxx_read(chip, addr, reg, &data); 95 if (err) 96 return err; 97 98 if ((data & mask) == val) 99 return 0; 100 101 usleep_range(1000, 2000); 102 } 103 104 dev_err(chip->dev, "Timeout while waiting for switch\n"); 105 return -ETIMEDOUT; 106 } 107 108 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 109 int bit, int val) 110 { 111 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 112 val ? BIT(bit) : 0x0000); 113 } 114 115 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 116 { 117 struct mv88e6xxx_mdio_bus *mdio_bus; 118 119 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 120 list); 121 if (!mdio_bus) 122 return NULL; 123 124 return mdio_bus->bus; 125 } 126 127 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 128 { 129 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 130 unsigned int n = d->hwirq; 131 132 chip->g1_irq.masked |= (1 << n); 133 } 134 135 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 136 { 137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 138 unsigned int n = d->hwirq; 139 140 chip->g1_irq.masked &= ~(1 << n); 141 } 142 143 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 144 { 145 unsigned int nhandled = 0; 146 unsigned int sub_irq; 147 unsigned int n; 148 u16 reg; 149 u16 ctl1; 150 int err; 151 152 mv88e6xxx_reg_lock(chip); 153 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 154 mv88e6xxx_reg_unlock(chip); 155 156 if (err) 157 goto out; 158 159 do { 160 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 161 if (reg & (1 << n)) { 162 sub_irq = irq_find_mapping(chip->g1_irq.domain, 163 n); 164 handle_nested_irq(sub_irq); 165 ++nhandled; 166 } 167 } 168 169 mv88e6xxx_reg_lock(chip); 170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 171 if (err) 172 goto unlock; 173 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 174 unlock: 175 mv88e6xxx_reg_unlock(chip); 176 if (err) 177 goto out; 178 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 179 } while (reg & ctl1); 180 181 out: 182 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 183 } 184 185 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 186 { 187 struct mv88e6xxx_chip *chip = dev_id; 188 189 return mv88e6xxx_g1_irq_thread_work(chip); 190 } 191 192 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 193 { 194 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 195 196 mv88e6xxx_reg_lock(chip); 197 } 198 199 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 200 { 201 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 202 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 203 u16 reg; 204 int err; 205 206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 207 if (err) 208 goto out; 209 210 reg &= ~mask; 211 reg |= (~chip->g1_irq.masked & mask); 212 213 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 214 if (err) 215 goto out; 216 217 out: 218 mv88e6xxx_reg_unlock(chip); 219 } 220 221 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 222 .name = "mv88e6xxx-g1", 223 .irq_mask = mv88e6xxx_g1_irq_mask, 224 .irq_unmask = mv88e6xxx_g1_irq_unmask, 225 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 226 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 227 }; 228 229 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 230 unsigned int irq, 231 irq_hw_number_t hwirq) 232 { 233 struct mv88e6xxx_chip *chip = d->host_data; 234 235 irq_set_chip_data(irq, d->host_data); 236 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 237 irq_set_noprobe(irq); 238 239 return 0; 240 } 241 242 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 243 .map = mv88e6xxx_g1_irq_domain_map, 244 .xlate = irq_domain_xlate_twocell, 245 }; 246 247 /* To be called with reg_lock held */ 248 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 249 { 250 int irq, virq; 251 u16 mask; 252 253 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 254 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 255 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 256 257 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 258 virq = irq_find_mapping(chip->g1_irq.domain, irq); 259 irq_dispose_mapping(virq); 260 } 261 262 irq_domain_remove(chip->g1_irq.domain); 263 } 264 265 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 266 { 267 /* 268 * free_irq must be called without reg_lock taken because the irq 269 * handler takes this lock, too. 270 */ 271 free_irq(chip->irq, chip); 272 273 mv88e6xxx_reg_lock(chip); 274 mv88e6xxx_g1_irq_free_common(chip); 275 mv88e6xxx_reg_unlock(chip); 276 } 277 278 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 279 { 280 int err, irq, virq; 281 u16 reg, mask; 282 283 chip->g1_irq.nirqs = chip->info->g1_irqs; 284 chip->g1_irq.domain = irq_domain_add_simple( 285 NULL, chip->g1_irq.nirqs, 0, 286 &mv88e6xxx_g1_irq_domain_ops, chip); 287 if (!chip->g1_irq.domain) 288 return -ENOMEM; 289 290 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 291 irq_create_mapping(chip->g1_irq.domain, irq); 292 293 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 294 chip->g1_irq.masked = ~0; 295 296 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 297 if (err) 298 goto out_mapping; 299 300 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 301 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 303 if (err) 304 goto out_disable; 305 306 /* Reading the interrupt status clears (most of) them */ 307 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 308 if (err) 309 goto out_disable; 310 311 return 0; 312 313 out_disable: 314 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 315 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 316 317 out_mapping: 318 for (irq = 0; irq < 16; irq++) { 319 virq = irq_find_mapping(chip->g1_irq.domain, irq); 320 irq_dispose_mapping(virq); 321 } 322 323 irq_domain_remove(chip->g1_irq.domain); 324 325 return err; 326 } 327 328 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 329 { 330 static struct lock_class_key lock_key; 331 static struct lock_class_key request_key; 332 int err; 333 334 err = mv88e6xxx_g1_irq_setup_common(chip); 335 if (err) 336 return err; 337 338 /* These lock classes tells lockdep that global 1 irqs are in 339 * a different category than their parent GPIO, so it won't 340 * report false recursion. 341 */ 342 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 343 344 snprintf(chip->irq_name, sizeof(chip->irq_name), 345 "mv88e6xxx-%s", dev_name(chip->dev)); 346 347 mv88e6xxx_reg_unlock(chip); 348 err = request_threaded_irq(chip->irq, NULL, 349 mv88e6xxx_g1_irq_thread_fn, 350 IRQF_ONESHOT | IRQF_SHARED, 351 chip->irq_name, chip); 352 mv88e6xxx_reg_lock(chip); 353 if (err) 354 mv88e6xxx_g1_irq_free_common(chip); 355 356 return err; 357 } 358 359 static void mv88e6xxx_irq_poll(struct kthread_work *work) 360 { 361 struct mv88e6xxx_chip *chip = container_of(work, 362 struct mv88e6xxx_chip, 363 irq_poll_work.work); 364 mv88e6xxx_g1_irq_thread_work(chip); 365 366 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 367 msecs_to_jiffies(100)); 368 } 369 370 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 371 { 372 int err; 373 374 err = mv88e6xxx_g1_irq_setup_common(chip); 375 if (err) 376 return err; 377 378 kthread_init_delayed_work(&chip->irq_poll_work, 379 mv88e6xxx_irq_poll); 380 381 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 382 if (IS_ERR(chip->kworker)) 383 return PTR_ERR(chip->kworker); 384 385 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 386 msecs_to_jiffies(100)); 387 388 return 0; 389 } 390 391 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 392 { 393 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 394 kthread_destroy_worker(chip->kworker); 395 396 mv88e6xxx_reg_lock(chip); 397 mv88e6xxx_g1_irq_free_common(chip); 398 mv88e6xxx_reg_unlock(chip); 399 } 400 401 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 402 int port, phy_interface_t interface) 403 { 404 int err; 405 406 if (chip->info->ops->port_set_rgmii_delay) { 407 err = chip->info->ops->port_set_rgmii_delay(chip, port, 408 interface); 409 if (err && err != -EOPNOTSUPP) 410 return err; 411 } 412 413 if (chip->info->ops->port_set_cmode) { 414 err = chip->info->ops->port_set_cmode(chip, port, 415 interface); 416 if (err && err != -EOPNOTSUPP) 417 return err; 418 } 419 420 return 0; 421 } 422 423 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 424 int link, int speed, int duplex, int pause, 425 phy_interface_t mode) 426 { 427 int err; 428 429 if (!chip->info->ops->port_set_link) 430 return 0; 431 432 /* Port's MAC control must not be changed unless the link is down */ 433 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 434 if (err) 435 return err; 436 437 if (chip->info->ops->port_set_speed_duplex) { 438 err = chip->info->ops->port_set_speed_duplex(chip, port, 439 speed, duplex); 440 if (err && err != -EOPNOTSUPP) 441 goto restore_link; 442 } 443 444 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 445 mode = chip->info->ops->port_max_speed_mode(port); 446 447 if (chip->info->ops->port_set_pause) { 448 err = chip->info->ops->port_set_pause(chip, port, pause); 449 if (err) 450 goto restore_link; 451 } 452 453 err = mv88e6xxx_port_config_interface(chip, port, mode); 454 restore_link: 455 if (chip->info->ops->port_set_link(chip, port, link)) 456 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 457 458 return err; 459 } 460 461 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 462 { 463 struct mv88e6xxx_chip *chip = ds->priv; 464 465 return port < chip->info->num_internal_phys; 466 } 467 468 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 469 { 470 u16 reg; 471 int err; 472 473 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 474 if (err) { 475 dev_err(chip->dev, 476 "p%d: %s: failed to read port status\n", 477 port, __func__); 478 return err; 479 } 480 481 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 482 } 483 484 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 485 struct phylink_link_state *state) 486 { 487 struct mv88e6xxx_chip *chip = ds->priv; 488 u8 lane; 489 int err; 490 491 mv88e6xxx_reg_lock(chip); 492 lane = mv88e6xxx_serdes_get_lane(chip, port); 493 if (lane && chip->info->ops->serdes_pcs_get_state) 494 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 495 state); 496 else 497 err = -EOPNOTSUPP; 498 mv88e6xxx_reg_unlock(chip); 499 500 return err; 501 } 502 503 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 504 unsigned int mode, 505 phy_interface_t interface, 506 const unsigned long *advertise) 507 { 508 const struct mv88e6xxx_ops *ops = chip->info->ops; 509 u8 lane; 510 511 if (ops->serdes_pcs_config) { 512 lane = mv88e6xxx_serdes_get_lane(chip, port); 513 if (lane) 514 return ops->serdes_pcs_config(chip, port, lane, mode, 515 interface, advertise); 516 } 517 518 return 0; 519 } 520 521 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 522 { 523 struct mv88e6xxx_chip *chip = ds->priv; 524 const struct mv88e6xxx_ops *ops; 525 int err = 0; 526 u8 lane; 527 528 ops = chip->info->ops; 529 530 if (ops->serdes_pcs_an_restart) { 531 mv88e6xxx_reg_lock(chip); 532 lane = mv88e6xxx_serdes_get_lane(chip, port); 533 if (lane) 534 err = ops->serdes_pcs_an_restart(chip, port, lane); 535 mv88e6xxx_reg_unlock(chip); 536 537 if (err) 538 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 539 } 540 } 541 542 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 543 unsigned int mode, 544 int speed, int duplex) 545 { 546 const struct mv88e6xxx_ops *ops = chip->info->ops; 547 u8 lane; 548 549 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 550 lane = mv88e6xxx_serdes_get_lane(chip, port); 551 if (lane) 552 return ops->serdes_pcs_link_up(chip, port, lane, 553 speed, duplex); 554 } 555 556 return 0; 557 } 558 559 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 560 unsigned long *mask, 561 struct phylink_link_state *state) 562 { 563 if (!phy_interface_mode_is_8023z(state->interface)) { 564 /* 10M and 100M are only supported in non-802.3z mode */ 565 phylink_set(mask, 10baseT_Half); 566 phylink_set(mask, 10baseT_Full); 567 phylink_set(mask, 100baseT_Half); 568 phylink_set(mask, 100baseT_Full); 569 } 570 } 571 572 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 573 unsigned long *mask, 574 struct phylink_link_state *state) 575 { 576 /* FIXME: if the port is in 1000Base-X mode, then it only supports 577 * 1000M FD speeds. In this case, CMODE will indicate 5. 578 */ 579 phylink_set(mask, 1000baseT_Full); 580 phylink_set(mask, 1000baseX_Full); 581 582 mv88e6065_phylink_validate(chip, port, mask, state); 583 } 584 585 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 586 unsigned long *mask, 587 struct phylink_link_state *state) 588 { 589 if (port >= 5) 590 phylink_set(mask, 2500baseX_Full); 591 592 /* No ethtool bits for 200Mbps */ 593 phylink_set(mask, 1000baseT_Full); 594 phylink_set(mask, 1000baseX_Full); 595 596 mv88e6065_phylink_validate(chip, port, mask, state); 597 } 598 599 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 600 unsigned long *mask, 601 struct phylink_link_state *state) 602 { 603 /* No ethtool bits for 200Mbps */ 604 phylink_set(mask, 1000baseT_Full); 605 phylink_set(mask, 1000baseX_Full); 606 607 mv88e6065_phylink_validate(chip, port, mask, state); 608 } 609 610 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 611 unsigned long *mask, 612 struct phylink_link_state *state) 613 { 614 if (port >= 9) { 615 phylink_set(mask, 2500baseX_Full); 616 phylink_set(mask, 2500baseT_Full); 617 } 618 619 /* No ethtool bits for 200Mbps */ 620 phylink_set(mask, 1000baseT_Full); 621 phylink_set(mask, 1000baseX_Full); 622 623 mv88e6065_phylink_validate(chip, port, mask, state); 624 } 625 626 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 627 unsigned long *mask, 628 struct phylink_link_state *state) 629 { 630 if (port >= 9) { 631 phylink_set(mask, 10000baseT_Full); 632 phylink_set(mask, 10000baseKR_Full); 633 } 634 635 mv88e6390_phylink_validate(chip, port, mask, state); 636 } 637 638 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 639 unsigned long *supported, 640 struct phylink_link_state *state) 641 { 642 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 643 struct mv88e6xxx_chip *chip = ds->priv; 644 645 /* Allow all the expected bits */ 646 phylink_set(mask, Autoneg); 647 phylink_set(mask, Pause); 648 phylink_set_port_modes(mask); 649 650 if (chip->info->ops->phylink_validate) 651 chip->info->ops->phylink_validate(chip, port, mask, state); 652 653 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 654 bitmap_and(state->advertising, state->advertising, mask, 655 __ETHTOOL_LINK_MODE_MASK_NBITS); 656 657 /* We can only operate at 2500BaseX or 1000BaseX. If requested 658 * to advertise both, only report advertising at 2500BaseX. 659 */ 660 phylink_helper_basex_speed(state); 661 } 662 663 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 664 unsigned int mode, 665 const struct phylink_link_state *state) 666 { 667 struct mv88e6xxx_chip *chip = ds->priv; 668 struct mv88e6xxx_port *p; 669 int err; 670 671 p = &chip->ports[port]; 672 673 /* FIXME: is this the correct test? If we're in fixed mode on an 674 * internal port, why should we process this any different from 675 * PHY mode? On the other hand, the port may be automedia between 676 * an internal PHY and the serdes... 677 */ 678 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 679 return; 680 681 mv88e6xxx_reg_lock(chip); 682 /* In inband mode, the link may come up at any time while the link 683 * is not forced down. Force the link down while we reconfigure the 684 * interface mode. 685 */ 686 if (mode == MLO_AN_INBAND && p->interface != state->interface && 687 chip->info->ops->port_set_link) 688 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 689 690 err = mv88e6xxx_port_config_interface(chip, port, state->interface); 691 if (err && err != -EOPNOTSUPP) 692 goto err_unlock; 693 694 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface, 695 state->advertising); 696 /* FIXME: we should restart negotiation if something changed - which 697 * is something we get if we convert to using phylinks PCS operations. 698 */ 699 if (err > 0) 700 err = 0; 701 702 /* Undo the forced down state above after completing configuration 703 * irrespective of its state on entry, which allows the link to come up. 704 */ 705 if (mode == MLO_AN_INBAND && p->interface != state->interface && 706 chip->info->ops->port_set_link) 707 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 708 709 p->interface = state->interface; 710 711 err_unlock: 712 mv88e6xxx_reg_unlock(chip); 713 714 if (err && err != -EOPNOTSUPP) 715 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 716 } 717 718 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 719 unsigned int mode, 720 phy_interface_t interface) 721 { 722 struct mv88e6xxx_chip *chip = ds->priv; 723 const struct mv88e6xxx_ops *ops; 724 int err = 0; 725 726 ops = chip->info->ops; 727 728 mv88e6xxx_reg_lock(chip); 729 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 730 mode == MLO_AN_FIXED) && ops->port_sync_link) 731 err = ops->port_sync_link(chip, port, mode, false); 732 mv88e6xxx_reg_unlock(chip); 733 734 if (err) 735 dev_err(chip->dev, 736 "p%d: failed to force MAC link down\n", port); 737 } 738 739 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 740 unsigned int mode, phy_interface_t interface, 741 struct phy_device *phydev, 742 int speed, int duplex, 743 bool tx_pause, bool rx_pause) 744 { 745 struct mv88e6xxx_chip *chip = ds->priv; 746 const struct mv88e6xxx_ops *ops; 747 int err = 0; 748 749 ops = chip->info->ops; 750 751 mv88e6xxx_reg_lock(chip); 752 if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) { 753 /* FIXME: for an automedia port, should we force the link 754 * down here - what if the link comes up due to "other" media 755 * while we're bringing the port up, how is the exclusivity 756 * handled in the Marvell hardware? E.g. port 2 on 88E6390 757 * shared between internal PHY and Serdes. 758 */ 759 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 760 duplex); 761 if (err) 762 goto error; 763 764 if (ops->port_set_speed_duplex) { 765 err = ops->port_set_speed_duplex(chip, port, 766 speed, duplex); 767 if (err && err != -EOPNOTSUPP) 768 goto error; 769 } 770 771 if (ops->port_sync_link) 772 err = ops->port_sync_link(chip, port, mode, true); 773 } 774 error: 775 mv88e6xxx_reg_unlock(chip); 776 777 if (err && err != -EOPNOTSUPP) 778 dev_err(ds->dev, 779 "p%d: failed to configure MAC link up\n", port); 780 } 781 782 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 783 { 784 if (!chip->info->ops->stats_snapshot) 785 return -EOPNOTSUPP; 786 787 return chip->info->ops->stats_snapshot(chip, port); 788 } 789 790 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 791 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 792 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 793 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 794 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 795 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 796 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 797 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 798 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 799 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 800 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 801 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 802 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 803 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 804 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 805 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 806 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 807 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 808 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 809 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 810 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 811 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 812 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 813 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 814 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 815 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 816 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 817 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 818 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 819 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 820 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 821 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 822 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 823 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 824 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 825 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 826 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 827 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 828 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 829 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 830 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 831 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 832 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 833 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 834 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 835 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 836 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 837 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 838 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 839 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 840 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 841 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 842 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 843 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 844 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 845 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 846 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 847 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 848 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 849 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 850 }; 851 852 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 853 struct mv88e6xxx_hw_stat *s, 854 int port, u16 bank1_select, 855 u16 histogram) 856 { 857 u32 low; 858 u32 high = 0; 859 u16 reg = 0; 860 int err; 861 u64 value; 862 863 switch (s->type) { 864 case STATS_TYPE_PORT: 865 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 866 if (err) 867 return U64_MAX; 868 869 low = reg; 870 if (s->size == 4) { 871 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 872 if (err) 873 return U64_MAX; 874 low |= ((u32)reg) << 16; 875 } 876 break; 877 case STATS_TYPE_BANK1: 878 reg = bank1_select; 879 fallthrough; 880 case STATS_TYPE_BANK0: 881 reg |= s->reg | histogram; 882 mv88e6xxx_g1_stats_read(chip, reg, &low); 883 if (s->size == 8) 884 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 885 break; 886 default: 887 return U64_MAX; 888 } 889 value = (((u64)high) << 32) | low; 890 return value; 891 } 892 893 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 894 uint8_t *data, int types) 895 { 896 struct mv88e6xxx_hw_stat *stat; 897 int i, j; 898 899 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 900 stat = &mv88e6xxx_hw_stats[i]; 901 if (stat->type & types) { 902 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 903 ETH_GSTRING_LEN); 904 j++; 905 } 906 } 907 908 return j; 909 } 910 911 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 912 uint8_t *data) 913 { 914 return mv88e6xxx_stats_get_strings(chip, data, 915 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 916 } 917 918 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 919 uint8_t *data) 920 { 921 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 922 } 923 924 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 925 uint8_t *data) 926 { 927 return mv88e6xxx_stats_get_strings(chip, data, 928 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 929 } 930 931 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 932 "atu_member_violation", 933 "atu_miss_violation", 934 "atu_full_violation", 935 "vtu_member_violation", 936 "vtu_miss_violation", 937 }; 938 939 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 940 { 941 unsigned int i; 942 943 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 944 strlcpy(data + i * ETH_GSTRING_LEN, 945 mv88e6xxx_atu_vtu_stats_strings[i], 946 ETH_GSTRING_LEN); 947 } 948 949 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 950 u32 stringset, uint8_t *data) 951 { 952 struct mv88e6xxx_chip *chip = ds->priv; 953 int count = 0; 954 955 if (stringset != ETH_SS_STATS) 956 return; 957 958 mv88e6xxx_reg_lock(chip); 959 960 if (chip->info->ops->stats_get_strings) 961 count = chip->info->ops->stats_get_strings(chip, data); 962 963 if (chip->info->ops->serdes_get_strings) { 964 data += count * ETH_GSTRING_LEN; 965 count = chip->info->ops->serdes_get_strings(chip, port, data); 966 } 967 968 data += count * ETH_GSTRING_LEN; 969 mv88e6xxx_atu_vtu_get_strings(data); 970 971 mv88e6xxx_reg_unlock(chip); 972 } 973 974 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 975 int types) 976 { 977 struct mv88e6xxx_hw_stat *stat; 978 int i, j; 979 980 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 981 stat = &mv88e6xxx_hw_stats[i]; 982 if (stat->type & types) 983 j++; 984 } 985 return j; 986 } 987 988 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 989 { 990 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 991 STATS_TYPE_PORT); 992 } 993 994 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 995 { 996 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 997 } 998 999 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1000 { 1001 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1002 STATS_TYPE_BANK1); 1003 } 1004 1005 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1006 { 1007 struct mv88e6xxx_chip *chip = ds->priv; 1008 int serdes_count = 0; 1009 int count = 0; 1010 1011 if (sset != ETH_SS_STATS) 1012 return 0; 1013 1014 mv88e6xxx_reg_lock(chip); 1015 if (chip->info->ops->stats_get_sset_count) 1016 count = chip->info->ops->stats_get_sset_count(chip); 1017 if (count < 0) 1018 goto out; 1019 1020 if (chip->info->ops->serdes_get_sset_count) 1021 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1022 port); 1023 if (serdes_count < 0) { 1024 count = serdes_count; 1025 goto out; 1026 } 1027 count += serdes_count; 1028 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1029 1030 out: 1031 mv88e6xxx_reg_unlock(chip); 1032 1033 return count; 1034 } 1035 1036 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1037 uint64_t *data, int types, 1038 u16 bank1_select, u16 histogram) 1039 { 1040 struct mv88e6xxx_hw_stat *stat; 1041 int i, j; 1042 1043 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1044 stat = &mv88e6xxx_hw_stats[i]; 1045 if (stat->type & types) { 1046 mv88e6xxx_reg_lock(chip); 1047 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1048 bank1_select, 1049 histogram); 1050 mv88e6xxx_reg_unlock(chip); 1051 1052 j++; 1053 } 1054 } 1055 return j; 1056 } 1057 1058 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1059 uint64_t *data) 1060 { 1061 return mv88e6xxx_stats_get_stats(chip, port, data, 1062 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1063 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1064 } 1065 1066 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1067 uint64_t *data) 1068 { 1069 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1070 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1071 } 1072 1073 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1074 uint64_t *data) 1075 { 1076 return mv88e6xxx_stats_get_stats(chip, port, data, 1077 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1078 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1079 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1080 } 1081 1082 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1083 uint64_t *data) 1084 { 1085 return mv88e6xxx_stats_get_stats(chip, port, data, 1086 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1087 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1088 0); 1089 } 1090 1091 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1092 uint64_t *data) 1093 { 1094 *data++ = chip->ports[port].atu_member_violation; 1095 *data++ = chip->ports[port].atu_miss_violation; 1096 *data++ = chip->ports[port].atu_full_violation; 1097 *data++ = chip->ports[port].vtu_member_violation; 1098 *data++ = chip->ports[port].vtu_miss_violation; 1099 } 1100 1101 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1102 uint64_t *data) 1103 { 1104 int count = 0; 1105 1106 if (chip->info->ops->stats_get_stats) 1107 count = chip->info->ops->stats_get_stats(chip, port, data); 1108 1109 mv88e6xxx_reg_lock(chip); 1110 if (chip->info->ops->serdes_get_stats) { 1111 data += count; 1112 count = chip->info->ops->serdes_get_stats(chip, port, data); 1113 } 1114 data += count; 1115 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1116 mv88e6xxx_reg_unlock(chip); 1117 } 1118 1119 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1120 uint64_t *data) 1121 { 1122 struct mv88e6xxx_chip *chip = ds->priv; 1123 int ret; 1124 1125 mv88e6xxx_reg_lock(chip); 1126 1127 ret = mv88e6xxx_stats_snapshot(chip, port); 1128 mv88e6xxx_reg_unlock(chip); 1129 1130 if (ret < 0) 1131 return; 1132 1133 mv88e6xxx_get_stats(chip, port, data); 1134 1135 } 1136 1137 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1138 { 1139 struct mv88e6xxx_chip *chip = ds->priv; 1140 int len; 1141 1142 len = 32 * sizeof(u16); 1143 if (chip->info->ops->serdes_get_regs_len) 1144 len += chip->info->ops->serdes_get_regs_len(chip, port); 1145 1146 return len; 1147 } 1148 1149 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1150 struct ethtool_regs *regs, void *_p) 1151 { 1152 struct mv88e6xxx_chip *chip = ds->priv; 1153 int err; 1154 u16 reg; 1155 u16 *p = _p; 1156 int i; 1157 1158 regs->version = chip->info->prod_num; 1159 1160 memset(p, 0xff, 32 * sizeof(u16)); 1161 1162 mv88e6xxx_reg_lock(chip); 1163 1164 for (i = 0; i < 32; i++) { 1165 1166 err = mv88e6xxx_port_read(chip, port, i, ®); 1167 if (!err) 1168 p[i] = reg; 1169 } 1170 1171 if (chip->info->ops->serdes_get_regs) 1172 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1173 1174 mv88e6xxx_reg_unlock(chip); 1175 } 1176 1177 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1178 struct ethtool_eee *e) 1179 { 1180 /* Nothing to do on the port's MAC */ 1181 return 0; 1182 } 1183 1184 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1185 struct ethtool_eee *e) 1186 { 1187 /* Nothing to do on the port's MAC */ 1188 return 0; 1189 } 1190 1191 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1192 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1193 { 1194 struct dsa_switch *ds = chip->ds; 1195 struct dsa_switch_tree *dst = ds->dst; 1196 struct net_device *br; 1197 struct dsa_port *dp; 1198 bool found = false; 1199 u16 pvlan; 1200 1201 list_for_each_entry(dp, &dst->ports, list) { 1202 if (dp->ds->index == dev && dp->index == port) { 1203 found = true; 1204 break; 1205 } 1206 } 1207 1208 /* Prevent frames from unknown switch or port */ 1209 if (!found) 1210 return 0; 1211 1212 /* Frames from DSA links and CPU ports can egress any local port */ 1213 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1214 return mv88e6xxx_port_mask(chip); 1215 1216 br = dp->bridge_dev; 1217 pvlan = 0; 1218 1219 /* Frames from user ports can egress any local DSA links and CPU ports, 1220 * as well as any local member of their bridge group. 1221 */ 1222 list_for_each_entry(dp, &dst->ports, list) 1223 if (dp->ds == ds && 1224 (dp->type == DSA_PORT_TYPE_CPU || 1225 dp->type == DSA_PORT_TYPE_DSA || 1226 (br && dp->bridge_dev == br))) 1227 pvlan |= BIT(dp->index); 1228 1229 return pvlan; 1230 } 1231 1232 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1233 { 1234 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1235 1236 /* prevent frames from going back out of the port they came in on */ 1237 output_ports &= ~BIT(port); 1238 1239 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1240 } 1241 1242 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1243 u8 state) 1244 { 1245 struct mv88e6xxx_chip *chip = ds->priv; 1246 int err; 1247 1248 mv88e6xxx_reg_lock(chip); 1249 err = mv88e6xxx_port_set_state(chip, port, state); 1250 mv88e6xxx_reg_unlock(chip); 1251 1252 if (err) 1253 dev_err(ds->dev, "p%d: failed to update state\n", port); 1254 } 1255 1256 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1257 { 1258 int err; 1259 1260 if (chip->info->ops->ieee_pri_map) { 1261 err = chip->info->ops->ieee_pri_map(chip); 1262 if (err) 1263 return err; 1264 } 1265 1266 if (chip->info->ops->ip_pri_map) { 1267 err = chip->info->ops->ip_pri_map(chip); 1268 if (err) 1269 return err; 1270 } 1271 1272 return 0; 1273 } 1274 1275 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1276 { 1277 struct dsa_switch *ds = chip->ds; 1278 int target, port; 1279 int err; 1280 1281 if (!chip->info->global2_addr) 1282 return 0; 1283 1284 /* Initialize the routing port to the 32 possible target devices */ 1285 for (target = 0; target < 32; target++) { 1286 port = dsa_routing_port(ds, target); 1287 if (port == ds->num_ports) 1288 port = 0x1f; 1289 1290 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1291 if (err) 1292 return err; 1293 } 1294 1295 if (chip->info->ops->set_cascade_port) { 1296 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1297 err = chip->info->ops->set_cascade_port(chip, port); 1298 if (err) 1299 return err; 1300 } 1301 1302 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1303 if (err) 1304 return err; 1305 1306 return 0; 1307 } 1308 1309 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1310 { 1311 /* Clear all trunk masks and mapping */ 1312 if (chip->info->global2_addr) 1313 return mv88e6xxx_g2_trunk_clear(chip); 1314 1315 return 0; 1316 } 1317 1318 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1319 { 1320 if (chip->info->ops->rmu_disable) 1321 return chip->info->ops->rmu_disable(chip); 1322 1323 return 0; 1324 } 1325 1326 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1327 { 1328 if (chip->info->ops->pot_clear) 1329 return chip->info->ops->pot_clear(chip); 1330 1331 return 0; 1332 } 1333 1334 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1335 { 1336 if (chip->info->ops->mgmt_rsvd2cpu) 1337 return chip->info->ops->mgmt_rsvd2cpu(chip); 1338 1339 return 0; 1340 } 1341 1342 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1343 { 1344 int err; 1345 1346 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1347 if (err) 1348 return err; 1349 1350 /* The chips that have a "learn2all" bit in Global1, ATU 1351 * Control are precisely those whose port registers have a 1352 * Message Port bit in Port Control 1 and hence implement 1353 * ->port_setup_message_port. 1354 */ 1355 if (chip->info->ops->port_setup_message_port) { 1356 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1357 if (err) 1358 return err; 1359 } 1360 1361 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1362 } 1363 1364 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1365 { 1366 int port; 1367 int err; 1368 1369 if (!chip->info->ops->irl_init_all) 1370 return 0; 1371 1372 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1373 /* Disable ingress rate limiting by resetting all per port 1374 * ingress rate limit resources to their initial state. 1375 */ 1376 err = chip->info->ops->irl_init_all(chip, port); 1377 if (err) 1378 return err; 1379 } 1380 1381 return 0; 1382 } 1383 1384 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1385 { 1386 if (chip->info->ops->set_switch_mac) { 1387 u8 addr[ETH_ALEN]; 1388 1389 eth_random_addr(addr); 1390 1391 return chip->info->ops->set_switch_mac(chip, addr); 1392 } 1393 1394 return 0; 1395 } 1396 1397 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1398 { 1399 struct dsa_switch_tree *dst = chip->ds->dst; 1400 struct dsa_switch *ds; 1401 struct dsa_port *dp; 1402 u16 pvlan = 0; 1403 1404 if (!mv88e6xxx_has_pvt(chip)) 1405 return 0; 1406 1407 /* Skip the local source device, which uses in-chip port VLAN */ 1408 if (dev != chip->ds->index) { 1409 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1410 1411 ds = dsa_switch_find(dst->index, dev); 1412 dp = ds ? dsa_to_port(ds, port) : NULL; 1413 if (dp && dp->lag_dev) { 1414 /* As the PVT is used to limit flooding of 1415 * FORWARD frames, which use the LAG ID as the 1416 * source port, we must translate dev/port to 1417 * the special "LAG device" in the PVT, using 1418 * the LAG ID as the port number. 1419 */ 1420 dev = MV88E6XXX_G2_PVT_ADRR_DEV_TRUNK; 1421 port = dsa_lag_id(dst, dp->lag_dev); 1422 } 1423 } 1424 1425 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1426 } 1427 1428 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1429 { 1430 int dev, port; 1431 int err; 1432 1433 if (!mv88e6xxx_has_pvt(chip)) 1434 return 0; 1435 1436 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1437 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1438 */ 1439 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1440 if (err) 1441 return err; 1442 1443 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1444 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1445 err = mv88e6xxx_pvt_map(chip, dev, port); 1446 if (err) 1447 return err; 1448 } 1449 } 1450 1451 return 0; 1452 } 1453 1454 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1455 { 1456 struct mv88e6xxx_chip *chip = ds->priv; 1457 int err; 1458 1459 mv88e6xxx_reg_lock(chip); 1460 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1461 mv88e6xxx_reg_unlock(chip); 1462 1463 if (err) 1464 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1465 } 1466 1467 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1468 { 1469 if (!mv88e6xxx_max_vid(chip)) 1470 return 0; 1471 1472 return mv88e6xxx_g1_vtu_flush(chip); 1473 } 1474 1475 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1476 struct mv88e6xxx_vtu_entry *entry) 1477 { 1478 if (!chip->info->ops->vtu_getnext) 1479 return -EOPNOTSUPP; 1480 1481 return chip->info->ops->vtu_getnext(chip, entry); 1482 } 1483 1484 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1485 struct mv88e6xxx_vtu_entry *entry) 1486 { 1487 if (!chip->info->ops->vtu_loadpurge) 1488 return -EOPNOTSUPP; 1489 1490 return chip->info->ops->vtu_loadpurge(chip, entry); 1491 } 1492 1493 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1494 { 1495 struct mv88e6xxx_vtu_entry vlan; 1496 int i, err; 1497 u16 fid; 1498 1499 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1500 1501 /* Set every FID bit used by the (un)bridged ports */ 1502 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1503 err = mv88e6xxx_port_get_fid(chip, i, &fid); 1504 if (err) 1505 return err; 1506 1507 set_bit(fid, fid_bitmap); 1508 } 1509 1510 /* Set every FID bit used by the VLAN entries */ 1511 vlan.vid = mv88e6xxx_max_vid(chip); 1512 vlan.valid = false; 1513 1514 do { 1515 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1516 if (err) 1517 return err; 1518 1519 if (!vlan.valid) 1520 break; 1521 1522 set_bit(vlan.fid, fid_bitmap); 1523 } while (vlan.vid < mv88e6xxx_max_vid(chip)); 1524 1525 return 0; 1526 } 1527 1528 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1529 { 1530 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1531 int err; 1532 1533 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1534 if (err) 1535 return err; 1536 1537 /* The reset value 0x000 is used to indicate that multiple address 1538 * databases are not needed. Return the next positive available. 1539 */ 1540 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1541 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1542 return -ENOSPC; 1543 1544 /* Clear the database */ 1545 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1546 } 1547 1548 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1549 u16 vid) 1550 { 1551 struct mv88e6xxx_chip *chip = ds->priv; 1552 struct mv88e6xxx_vtu_entry vlan; 1553 int i, err; 1554 1555 if (!vid) 1556 return -EOPNOTSUPP; 1557 1558 /* DSA and CPU ports have to be members of multiple vlans */ 1559 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1560 return 0; 1561 1562 vlan.vid = vid - 1; 1563 vlan.valid = false; 1564 1565 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1566 if (err) 1567 return err; 1568 1569 if (!vlan.valid) 1570 return 0; 1571 1572 if (vlan.vid != vid) 1573 return 0; 1574 1575 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1576 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1577 continue; 1578 1579 if (!dsa_to_port(ds, i)->slave) 1580 continue; 1581 1582 if (vlan.member[i] == 1583 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1584 continue; 1585 1586 if (dsa_to_port(ds, i)->bridge_dev == 1587 dsa_to_port(ds, port)->bridge_dev) 1588 break; /* same bridge, check next VLAN */ 1589 1590 if (!dsa_to_port(ds, i)->bridge_dev) 1591 continue; 1592 1593 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1594 port, vlan.vid, i, 1595 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1596 return -EOPNOTSUPP; 1597 } 1598 1599 return 0; 1600 } 1601 1602 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1603 bool vlan_filtering, 1604 struct netlink_ext_ack *extack) 1605 { 1606 struct mv88e6xxx_chip *chip = ds->priv; 1607 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1608 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1609 int err; 1610 1611 if (!mv88e6xxx_max_vid(chip)) 1612 return -EOPNOTSUPP; 1613 1614 mv88e6xxx_reg_lock(chip); 1615 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1616 mv88e6xxx_reg_unlock(chip); 1617 1618 return err; 1619 } 1620 1621 static int 1622 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1623 const struct switchdev_obj_port_vlan *vlan) 1624 { 1625 struct mv88e6xxx_chip *chip = ds->priv; 1626 int err; 1627 1628 if (!mv88e6xxx_max_vid(chip)) 1629 return -EOPNOTSUPP; 1630 1631 /* If the requested port doesn't belong to the same bridge as the VLAN 1632 * members, do not support it (yet) and fallback to software VLAN. 1633 */ 1634 mv88e6xxx_reg_lock(chip); 1635 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 1636 mv88e6xxx_reg_unlock(chip); 1637 1638 return err; 1639 } 1640 1641 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1642 const unsigned char *addr, u16 vid, 1643 u8 state) 1644 { 1645 struct mv88e6xxx_atu_entry entry; 1646 struct mv88e6xxx_vtu_entry vlan; 1647 u16 fid; 1648 int err; 1649 1650 /* Null VLAN ID corresponds to the port private database */ 1651 if (vid == 0) { 1652 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1653 if (err) 1654 return err; 1655 } else { 1656 vlan.vid = vid - 1; 1657 vlan.valid = false; 1658 1659 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1660 if (err) 1661 return err; 1662 1663 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1664 if (vlan.vid != vid || !vlan.valid) 1665 return -EOPNOTSUPP; 1666 1667 fid = vlan.fid; 1668 } 1669 1670 entry.state = 0; 1671 ether_addr_copy(entry.mac, addr); 1672 eth_addr_dec(entry.mac); 1673 1674 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1675 if (err) 1676 return err; 1677 1678 /* Initialize a fresh ATU entry if it isn't found */ 1679 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1680 memset(&entry, 0, sizeof(entry)); 1681 ether_addr_copy(entry.mac, addr); 1682 } 1683 1684 /* Purge the ATU entry only if no port is using it anymore */ 1685 if (!state) { 1686 entry.portvec &= ~BIT(port); 1687 if (!entry.portvec) 1688 entry.state = 0; 1689 } else { 1690 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 1691 entry.portvec = BIT(port); 1692 else 1693 entry.portvec |= BIT(port); 1694 1695 entry.state = state; 1696 } 1697 1698 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1699 } 1700 1701 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1702 const struct mv88e6xxx_policy *policy) 1703 { 1704 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1705 enum mv88e6xxx_policy_action action = policy->action; 1706 const u8 *addr = policy->addr; 1707 u16 vid = policy->vid; 1708 u8 state; 1709 int err; 1710 int id; 1711 1712 if (!chip->info->ops->port_set_policy) 1713 return -EOPNOTSUPP; 1714 1715 switch (mapping) { 1716 case MV88E6XXX_POLICY_MAPPING_DA: 1717 case MV88E6XXX_POLICY_MAPPING_SA: 1718 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1719 state = 0; /* Dissociate the port and address */ 1720 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1721 is_multicast_ether_addr(addr)) 1722 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1723 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1724 is_unicast_ether_addr(addr)) 1725 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1726 else 1727 return -EOPNOTSUPP; 1728 1729 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1730 state); 1731 if (err) 1732 return err; 1733 break; 1734 default: 1735 return -EOPNOTSUPP; 1736 } 1737 1738 /* Skip the port's policy clearing if the mapping is still in use */ 1739 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1740 idr_for_each_entry(&chip->policies, policy, id) 1741 if (policy->port == port && 1742 policy->mapping == mapping && 1743 policy->action != action) 1744 return 0; 1745 1746 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1747 } 1748 1749 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1750 struct ethtool_rx_flow_spec *fs) 1751 { 1752 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1753 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1754 enum mv88e6xxx_policy_mapping mapping; 1755 enum mv88e6xxx_policy_action action; 1756 struct mv88e6xxx_policy *policy; 1757 u16 vid = 0; 1758 u8 *addr; 1759 int err; 1760 int id; 1761 1762 if (fs->location != RX_CLS_LOC_ANY) 1763 return -EINVAL; 1764 1765 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1766 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1767 else 1768 return -EOPNOTSUPP; 1769 1770 switch (fs->flow_type & ~FLOW_EXT) { 1771 case ETHER_FLOW: 1772 if (!is_zero_ether_addr(mac_mask->h_dest) && 1773 is_zero_ether_addr(mac_mask->h_source)) { 1774 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1775 addr = mac_entry->h_dest; 1776 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1777 !is_zero_ether_addr(mac_mask->h_source)) { 1778 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1779 addr = mac_entry->h_source; 1780 } else { 1781 /* Cannot support DA and SA mapping in the same rule */ 1782 return -EOPNOTSUPP; 1783 } 1784 break; 1785 default: 1786 return -EOPNOTSUPP; 1787 } 1788 1789 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1790 if (fs->m_ext.vlan_tci != htons(0xffff)) 1791 return -EOPNOTSUPP; 1792 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1793 } 1794 1795 idr_for_each_entry(&chip->policies, policy, id) { 1796 if (policy->port == port && policy->mapping == mapping && 1797 policy->action == action && policy->vid == vid && 1798 ether_addr_equal(policy->addr, addr)) 1799 return -EEXIST; 1800 } 1801 1802 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1803 if (!policy) 1804 return -ENOMEM; 1805 1806 fs->location = 0; 1807 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1808 GFP_KERNEL); 1809 if (err) { 1810 devm_kfree(chip->dev, policy); 1811 return err; 1812 } 1813 1814 memcpy(&policy->fs, fs, sizeof(*fs)); 1815 ether_addr_copy(policy->addr, addr); 1816 policy->mapping = mapping; 1817 policy->action = action; 1818 policy->port = port; 1819 policy->vid = vid; 1820 1821 err = mv88e6xxx_policy_apply(chip, port, policy); 1822 if (err) { 1823 idr_remove(&chip->policies, fs->location); 1824 devm_kfree(chip->dev, policy); 1825 return err; 1826 } 1827 1828 return 0; 1829 } 1830 1831 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1832 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1833 { 1834 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1835 struct mv88e6xxx_chip *chip = ds->priv; 1836 struct mv88e6xxx_policy *policy; 1837 int err; 1838 int id; 1839 1840 mv88e6xxx_reg_lock(chip); 1841 1842 switch (rxnfc->cmd) { 1843 case ETHTOOL_GRXCLSRLCNT: 1844 rxnfc->data = 0; 1845 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1846 rxnfc->rule_cnt = 0; 1847 idr_for_each_entry(&chip->policies, policy, id) 1848 if (policy->port == port) 1849 rxnfc->rule_cnt++; 1850 err = 0; 1851 break; 1852 case ETHTOOL_GRXCLSRULE: 1853 err = -ENOENT; 1854 policy = idr_find(&chip->policies, fs->location); 1855 if (policy) { 1856 memcpy(fs, &policy->fs, sizeof(*fs)); 1857 err = 0; 1858 } 1859 break; 1860 case ETHTOOL_GRXCLSRLALL: 1861 rxnfc->data = 0; 1862 rxnfc->rule_cnt = 0; 1863 idr_for_each_entry(&chip->policies, policy, id) 1864 if (policy->port == port) 1865 rule_locs[rxnfc->rule_cnt++] = id; 1866 err = 0; 1867 break; 1868 default: 1869 err = -EOPNOTSUPP; 1870 break; 1871 } 1872 1873 mv88e6xxx_reg_unlock(chip); 1874 1875 return err; 1876 } 1877 1878 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 1879 struct ethtool_rxnfc *rxnfc) 1880 { 1881 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1882 struct mv88e6xxx_chip *chip = ds->priv; 1883 struct mv88e6xxx_policy *policy; 1884 int err; 1885 1886 mv88e6xxx_reg_lock(chip); 1887 1888 switch (rxnfc->cmd) { 1889 case ETHTOOL_SRXCLSRLINS: 1890 err = mv88e6xxx_policy_insert(chip, port, fs); 1891 break; 1892 case ETHTOOL_SRXCLSRLDEL: 1893 err = -ENOENT; 1894 policy = idr_remove(&chip->policies, fs->location); 1895 if (policy) { 1896 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 1897 err = mv88e6xxx_policy_apply(chip, port, policy); 1898 devm_kfree(chip->dev, policy); 1899 } 1900 break; 1901 default: 1902 err = -EOPNOTSUPP; 1903 break; 1904 } 1905 1906 mv88e6xxx_reg_unlock(chip); 1907 1908 return err; 1909 } 1910 1911 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1912 u16 vid) 1913 { 1914 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1915 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1916 1917 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1918 } 1919 1920 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1921 { 1922 int port; 1923 int err; 1924 1925 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1926 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1927 if (err) 1928 return err; 1929 } 1930 1931 return 0; 1932 } 1933 1934 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 1935 u16 vid, u8 member, bool warn) 1936 { 1937 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1938 struct mv88e6xxx_vtu_entry vlan; 1939 int i, err; 1940 1941 vlan.vid = vid - 1; 1942 vlan.valid = false; 1943 1944 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1945 if (err) 1946 return err; 1947 1948 if (vlan.vid != vid || !vlan.valid) { 1949 memset(&vlan, 0, sizeof(vlan)); 1950 1951 err = mv88e6xxx_atu_new(chip, &vlan.fid); 1952 if (err) 1953 return err; 1954 1955 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1956 if (i == port) 1957 vlan.member[i] = member; 1958 else 1959 vlan.member[i] = non_member; 1960 1961 vlan.vid = vid; 1962 vlan.valid = true; 1963 1964 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1965 if (err) 1966 return err; 1967 1968 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 1969 if (err) 1970 return err; 1971 } else if (vlan.member[port] != member) { 1972 vlan.member[port] = member; 1973 1974 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1975 if (err) 1976 return err; 1977 } else if (warn) { 1978 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 1979 port, vid); 1980 } 1981 1982 return 0; 1983 } 1984 1985 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1986 const struct switchdev_obj_port_vlan *vlan, 1987 struct netlink_ext_ack *extack) 1988 { 1989 struct mv88e6xxx_chip *chip = ds->priv; 1990 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1991 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1992 bool warn; 1993 u8 member; 1994 int err; 1995 1996 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 1997 if (err) 1998 return err; 1999 2000 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2001 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2002 else if (untagged) 2003 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2004 else 2005 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2006 2007 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2008 * and then the CPU port. Do not warn for duplicates for the CPU port. 2009 */ 2010 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2011 2012 mv88e6xxx_reg_lock(chip); 2013 2014 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2015 if (err) { 2016 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2017 vlan->vid, untagged ? 'u' : 't'); 2018 goto out; 2019 } 2020 2021 if (pvid) { 2022 err = mv88e6xxx_port_set_pvid(chip, port, vlan->vid); 2023 if (err) { 2024 dev_err(ds->dev, "p%d: failed to set PVID %d\n", 2025 port, vlan->vid); 2026 goto out; 2027 } 2028 } 2029 out: 2030 mv88e6xxx_reg_unlock(chip); 2031 2032 return err; 2033 } 2034 2035 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2036 int port, u16 vid) 2037 { 2038 struct mv88e6xxx_vtu_entry vlan; 2039 int i, err; 2040 2041 if (!vid) 2042 return -EOPNOTSUPP; 2043 2044 vlan.vid = vid - 1; 2045 vlan.valid = false; 2046 2047 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2048 if (err) 2049 return err; 2050 2051 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2052 * tell switchdev that this VLAN is likely handled in software. 2053 */ 2054 if (vlan.vid != vid || !vlan.valid || 2055 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2056 return -EOPNOTSUPP; 2057 2058 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2059 2060 /* keep the VLAN unless all ports are excluded */ 2061 vlan.valid = false; 2062 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2063 if (vlan.member[i] != 2064 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2065 vlan.valid = true; 2066 break; 2067 } 2068 } 2069 2070 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2071 if (err) 2072 return err; 2073 2074 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2075 } 2076 2077 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2078 const struct switchdev_obj_port_vlan *vlan) 2079 { 2080 struct mv88e6xxx_chip *chip = ds->priv; 2081 int err = 0; 2082 u16 pvid; 2083 2084 if (!mv88e6xxx_max_vid(chip)) 2085 return -EOPNOTSUPP; 2086 2087 mv88e6xxx_reg_lock(chip); 2088 2089 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2090 if (err) 2091 goto unlock; 2092 2093 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2094 if (err) 2095 goto unlock; 2096 2097 if (vlan->vid == pvid) { 2098 err = mv88e6xxx_port_set_pvid(chip, port, 0); 2099 if (err) 2100 goto unlock; 2101 } 2102 2103 unlock: 2104 mv88e6xxx_reg_unlock(chip); 2105 2106 return err; 2107 } 2108 2109 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2110 const unsigned char *addr, u16 vid) 2111 { 2112 struct mv88e6xxx_chip *chip = ds->priv; 2113 int err; 2114 2115 mv88e6xxx_reg_lock(chip); 2116 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2117 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2118 mv88e6xxx_reg_unlock(chip); 2119 2120 return err; 2121 } 2122 2123 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2124 const unsigned char *addr, u16 vid) 2125 { 2126 struct mv88e6xxx_chip *chip = ds->priv; 2127 int err; 2128 2129 mv88e6xxx_reg_lock(chip); 2130 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2131 mv88e6xxx_reg_unlock(chip); 2132 2133 return err; 2134 } 2135 2136 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2137 u16 fid, u16 vid, int port, 2138 dsa_fdb_dump_cb_t *cb, void *data) 2139 { 2140 struct mv88e6xxx_atu_entry addr; 2141 bool is_static; 2142 int err; 2143 2144 addr.state = 0; 2145 eth_broadcast_addr(addr.mac); 2146 2147 do { 2148 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2149 if (err) 2150 return err; 2151 2152 if (!addr.state) 2153 break; 2154 2155 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2156 continue; 2157 2158 if (!is_unicast_ether_addr(addr.mac)) 2159 continue; 2160 2161 is_static = (addr.state == 2162 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2163 err = cb(addr.mac, vid, is_static, data); 2164 if (err) 2165 return err; 2166 } while (!is_broadcast_ether_addr(addr.mac)); 2167 2168 return err; 2169 } 2170 2171 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2172 dsa_fdb_dump_cb_t *cb, void *data) 2173 { 2174 struct mv88e6xxx_vtu_entry vlan; 2175 u16 fid; 2176 int err; 2177 2178 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2179 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2180 if (err) 2181 return err; 2182 2183 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2184 if (err) 2185 return err; 2186 2187 /* Dump VLANs' Filtering Information Databases */ 2188 vlan.vid = mv88e6xxx_max_vid(chip); 2189 vlan.valid = false; 2190 2191 do { 2192 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2193 if (err) 2194 return err; 2195 2196 if (!vlan.valid) 2197 break; 2198 2199 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 2200 cb, data); 2201 if (err) 2202 return err; 2203 } while (vlan.vid < mv88e6xxx_max_vid(chip)); 2204 2205 return err; 2206 } 2207 2208 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2209 dsa_fdb_dump_cb_t *cb, void *data) 2210 { 2211 struct mv88e6xxx_chip *chip = ds->priv; 2212 int err; 2213 2214 mv88e6xxx_reg_lock(chip); 2215 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2216 mv88e6xxx_reg_unlock(chip); 2217 2218 return err; 2219 } 2220 2221 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2222 struct net_device *br) 2223 { 2224 struct dsa_switch *ds = chip->ds; 2225 struct dsa_switch_tree *dst = ds->dst; 2226 struct dsa_port *dp; 2227 int err; 2228 2229 list_for_each_entry(dp, &dst->ports, list) { 2230 if (dp->bridge_dev == br) { 2231 if (dp->ds == ds) { 2232 /* This is a local bridge group member, 2233 * remap its Port VLAN Map. 2234 */ 2235 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2236 if (err) 2237 return err; 2238 } else { 2239 /* This is an external bridge group member, 2240 * remap its cross-chip Port VLAN Table entry. 2241 */ 2242 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2243 dp->index); 2244 if (err) 2245 return err; 2246 } 2247 } 2248 } 2249 2250 return 0; 2251 } 2252 2253 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2254 struct net_device *br) 2255 { 2256 struct mv88e6xxx_chip *chip = ds->priv; 2257 int err; 2258 2259 mv88e6xxx_reg_lock(chip); 2260 err = mv88e6xxx_bridge_map(chip, br); 2261 mv88e6xxx_reg_unlock(chip); 2262 2263 return err; 2264 } 2265 2266 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2267 struct net_device *br) 2268 { 2269 struct mv88e6xxx_chip *chip = ds->priv; 2270 2271 mv88e6xxx_reg_lock(chip); 2272 if (mv88e6xxx_bridge_map(chip, br) || 2273 mv88e6xxx_port_vlan_map(chip, port)) 2274 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2275 mv88e6xxx_reg_unlock(chip); 2276 } 2277 2278 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2279 int tree_index, int sw_index, 2280 int port, struct net_device *br) 2281 { 2282 struct mv88e6xxx_chip *chip = ds->priv; 2283 int err; 2284 2285 if (tree_index != ds->dst->index) 2286 return 0; 2287 2288 mv88e6xxx_reg_lock(chip); 2289 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2290 mv88e6xxx_reg_unlock(chip); 2291 2292 return err; 2293 } 2294 2295 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2296 int tree_index, int sw_index, 2297 int port, struct net_device *br) 2298 { 2299 struct mv88e6xxx_chip *chip = ds->priv; 2300 2301 if (tree_index != ds->dst->index) 2302 return; 2303 2304 mv88e6xxx_reg_lock(chip); 2305 if (mv88e6xxx_pvt_map(chip, sw_index, port)) 2306 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2307 mv88e6xxx_reg_unlock(chip); 2308 } 2309 2310 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2311 { 2312 if (chip->info->ops->reset) 2313 return chip->info->ops->reset(chip); 2314 2315 return 0; 2316 } 2317 2318 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2319 { 2320 struct gpio_desc *gpiod = chip->reset; 2321 2322 /* If there is a GPIO connected to the reset pin, toggle it */ 2323 if (gpiod) { 2324 gpiod_set_value_cansleep(gpiod, 1); 2325 usleep_range(10000, 20000); 2326 gpiod_set_value_cansleep(gpiod, 0); 2327 usleep_range(10000, 20000); 2328 2329 mv88e6xxx_g1_wait_eeprom_done(chip); 2330 } 2331 } 2332 2333 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2334 { 2335 int i, err; 2336 2337 /* Set all ports to the Disabled state */ 2338 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2339 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2340 if (err) 2341 return err; 2342 } 2343 2344 /* Wait for transmit queues to drain, 2345 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2346 */ 2347 usleep_range(2000, 4000); 2348 2349 return 0; 2350 } 2351 2352 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2353 { 2354 int err; 2355 2356 err = mv88e6xxx_disable_ports(chip); 2357 if (err) 2358 return err; 2359 2360 mv88e6xxx_hardware_reset(chip); 2361 2362 return mv88e6xxx_software_reset(chip); 2363 } 2364 2365 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2366 enum mv88e6xxx_frame_mode frame, 2367 enum mv88e6xxx_egress_mode egress, u16 etype) 2368 { 2369 int err; 2370 2371 if (!chip->info->ops->port_set_frame_mode) 2372 return -EOPNOTSUPP; 2373 2374 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2375 if (err) 2376 return err; 2377 2378 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2379 if (err) 2380 return err; 2381 2382 if (chip->info->ops->port_set_ether_type) 2383 return chip->info->ops->port_set_ether_type(chip, port, etype); 2384 2385 return 0; 2386 } 2387 2388 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2389 { 2390 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2391 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2392 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2393 } 2394 2395 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2396 { 2397 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2398 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2399 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2400 } 2401 2402 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2403 { 2404 return mv88e6xxx_set_port_mode(chip, port, 2405 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2406 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2407 ETH_P_EDSA); 2408 } 2409 2410 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2411 { 2412 if (dsa_is_dsa_port(chip->ds, port)) 2413 return mv88e6xxx_set_port_mode_dsa(chip, port); 2414 2415 if (dsa_is_user_port(chip->ds, port)) 2416 return mv88e6xxx_set_port_mode_normal(chip, port); 2417 2418 /* Setup CPU port mode depending on its supported tag format */ 2419 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2420 return mv88e6xxx_set_port_mode_dsa(chip, port); 2421 2422 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2423 return mv88e6xxx_set_port_mode_edsa(chip, port); 2424 2425 return -EINVAL; 2426 } 2427 2428 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2429 { 2430 bool message = dsa_is_dsa_port(chip->ds, port); 2431 2432 return mv88e6xxx_port_set_message_port(chip, port, message); 2433 } 2434 2435 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2436 { 2437 struct dsa_switch *ds = chip->ds; 2438 bool flood; 2439 int err; 2440 2441 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2442 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2443 if (chip->info->ops->port_set_ucast_flood) { 2444 err = chip->info->ops->port_set_ucast_flood(chip, port, flood); 2445 if (err) 2446 return err; 2447 } 2448 if (chip->info->ops->port_set_mcast_flood) { 2449 err = chip->info->ops->port_set_mcast_flood(chip, port, flood); 2450 if (err) 2451 return err; 2452 } 2453 2454 return 0; 2455 } 2456 2457 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2458 { 2459 struct mv88e6xxx_port *mvp = dev_id; 2460 struct mv88e6xxx_chip *chip = mvp->chip; 2461 irqreturn_t ret = IRQ_NONE; 2462 int port = mvp->port; 2463 u8 lane; 2464 2465 mv88e6xxx_reg_lock(chip); 2466 lane = mv88e6xxx_serdes_get_lane(chip, port); 2467 if (lane) 2468 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2469 mv88e6xxx_reg_unlock(chip); 2470 2471 return ret; 2472 } 2473 2474 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2475 u8 lane) 2476 { 2477 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2478 unsigned int irq; 2479 int err; 2480 2481 /* Nothing to request if this SERDES port has no IRQ */ 2482 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2483 if (!irq) 2484 return 0; 2485 2486 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2487 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2488 2489 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2490 mv88e6xxx_reg_unlock(chip); 2491 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2492 IRQF_ONESHOT, dev_id->serdes_irq_name, 2493 dev_id); 2494 mv88e6xxx_reg_lock(chip); 2495 if (err) 2496 return err; 2497 2498 dev_id->serdes_irq = irq; 2499 2500 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2501 } 2502 2503 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2504 u8 lane) 2505 { 2506 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2507 unsigned int irq = dev_id->serdes_irq; 2508 int err; 2509 2510 /* Nothing to free if no IRQ has been requested */ 2511 if (!irq) 2512 return 0; 2513 2514 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2515 2516 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2517 mv88e6xxx_reg_unlock(chip); 2518 free_irq(irq, dev_id); 2519 mv88e6xxx_reg_lock(chip); 2520 2521 dev_id->serdes_irq = 0; 2522 2523 return err; 2524 } 2525 2526 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2527 bool on) 2528 { 2529 u8 lane; 2530 int err; 2531 2532 lane = mv88e6xxx_serdes_get_lane(chip, port); 2533 if (!lane) 2534 return 0; 2535 2536 if (on) { 2537 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2538 if (err) 2539 return err; 2540 2541 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2542 } else { 2543 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2544 if (err) 2545 return err; 2546 2547 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2548 } 2549 2550 return err; 2551 } 2552 2553 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2554 { 2555 struct dsa_switch *ds = chip->ds; 2556 int upstream_port; 2557 int err; 2558 2559 upstream_port = dsa_upstream_port(ds, port); 2560 if (chip->info->ops->port_set_upstream_port) { 2561 err = chip->info->ops->port_set_upstream_port(chip, port, 2562 upstream_port); 2563 if (err) 2564 return err; 2565 } 2566 2567 if (port == upstream_port) { 2568 if (chip->info->ops->set_cpu_port) { 2569 err = chip->info->ops->set_cpu_port(chip, 2570 upstream_port); 2571 if (err) 2572 return err; 2573 } 2574 2575 if (chip->info->ops->set_egress_port) { 2576 err = chip->info->ops->set_egress_port(chip, 2577 MV88E6XXX_EGRESS_DIR_INGRESS, 2578 upstream_port); 2579 if (err) 2580 return err; 2581 2582 err = chip->info->ops->set_egress_port(chip, 2583 MV88E6XXX_EGRESS_DIR_EGRESS, 2584 upstream_port); 2585 if (err) 2586 return err; 2587 } 2588 } 2589 2590 return 0; 2591 } 2592 2593 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2594 { 2595 struct dsa_switch *ds = chip->ds; 2596 int err; 2597 u16 reg; 2598 2599 chip->ports[port].chip = chip; 2600 chip->ports[port].port = port; 2601 2602 /* MAC Forcing register: don't force link, speed, duplex or flow control 2603 * state to any particular values on physical ports, but force the CPU 2604 * port and all DSA ports to their maximum bandwidth and full duplex. 2605 */ 2606 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2607 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2608 SPEED_MAX, DUPLEX_FULL, 2609 PAUSE_OFF, 2610 PHY_INTERFACE_MODE_NA); 2611 else 2612 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2613 SPEED_UNFORCED, DUPLEX_UNFORCED, 2614 PAUSE_ON, 2615 PHY_INTERFACE_MODE_NA); 2616 if (err) 2617 return err; 2618 2619 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2620 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2621 * tunneling, determine priority by looking at 802.1p and IP 2622 * priority fields (IP prio has precedence), and set STP state 2623 * to Forwarding. 2624 * 2625 * If this is the CPU link, use DSA or EDSA tagging depending 2626 * on which tagging mode was configured. 2627 * 2628 * If this is a link to another switch, use DSA tagging mode. 2629 * 2630 * If this is the upstream port for this switch, enable 2631 * forwarding of unknown unicasts and multicasts. 2632 */ 2633 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2634 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2635 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2636 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2637 if (err) 2638 return err; 2639 2640 err = mv88e6xxx_setup_port_mode(chip, port); 2641 if (err) 2642 return err; 2643 2644 err = mv88e6xxx_setup_egress_floods(chip, port); 2645 if (err) 2646 return err; 2647 2648 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2649 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2650 * untagged frames on this port, do a destination address lookup on all 2651 * received packets as usual, disable ARP mirroring and don't send a 2652 * copy of all transmitted/received frames on this port to the CPU. 2653 */ 2654 err = mv88e6xxx_port_set_map_da(chip, port); 2655 if (err) 2656 return err; 2657 2658 err = mv88e6xxx_setup_upstream_port(chip, port); 2659 if (err) 2660 return err; 2661 2662 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2663 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2664 if (err) 2665 return err; 2666 2667 if (chip->info->ops->port_set_jumbo_size) { 2668 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2669 if (err) 2670 return err; 2671 } 2672 2673 /* Port Association Vector: when learning source addresses 2674 * of packets, add the address to the address database using 2675 * a port bitmap that has only the bit for this port set and 2676 * the other bits clear. 2677 */ 2678 reg = 1 << port; 2679 /* Disable learning for CPU port */ 2680 if (dsa_is_cpu_port(ds, port)) 2681 reg = 0; 2682 2683 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2684 reg); 2685 if (err) 2686 return err; 2687 2688 /* Egress rate control 2: disable egress rate control. */ 2689 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2690 0x0000); 2691 if (err) 2692 return err; 2693 2694 if (chip->info->ops->port_pause_limit) { 2695 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2696 if (err) 2697 return err; 2698 } 2699 2700 if (chip->info->ops->port_disable_learn_limit) { 2701 err = chip->info->ops->port_disable_learn_limit(chip, port); 2702 if (err) 2703 return err; 2704 } 2705 2706 if (chip->info->ops->port_disable_pri_override) { 2707 err = chip->info->ops->port_disable_pri_override(chip, port); 2708 if (err) 2709 return err; 2710 } 2711 2712 if (chip->info->ops->port_tag_remap) { 2713 err = chip->info->ops->port_tag_remap(chip, port); 2714 if (err) 2715 return err; 2716 } 2717 2718 if (chip->info->ops->port_egress_rate_limiting) { 2719 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2720 if (err) 2721 return err; 2722 } 2723 2724 if (chip->info->ops->port_setup_message_port) { 2725 err = chip->info->ops->port_setup_message_port(chip, port); 2726 if (err) 2727 return err; 2728 } 2729 2730 /* Port based VLAN map: give each port the same default address 2731 * database, and allow bidirectional communication between the 2732 * CPU and DSA port(s), and the other ports. 2733 */ 2734 err = mv88e6xxx_port_set_fid(chip, port, 0); 2735 if (err) 2736 return err; 2737 2738 err = mv88e6xxx_port_vlan_map(chip, port); 2739 if (err) 2740 return err; 2741 2742 /* Default VLAN ID and priority: don't set a default VLAN 2743 * ID, and set the default packet priority to zero. 2744 */ 2745 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2746 } 2747 2748 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 2749 { 2750 struct mv88e6xxx_chip *chip = ds->priv; 2751 2752 if (chip->info->ops->port_set_jumbo_size) 2753 return 10240; 2754 else if (chip->info->ops->set_max_frame_size) 2755 return 1632; 2756 return 1522; 2757 } 2758 2759 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 2760 { 2761 struct mv88e6xxx_chip *chip = ds->priv; 2762 int ret = 0; 2763 2764 mv88e6xxx_reg_lock(chip); 2765 if (chip->info->ops->port_set_jumbo_size) 2766 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 2767 else if (chip->info->ops->set_max_frame_size) 2768 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 2769 else 2770 if (new_mtu > 1522) 2771 ret = -EINVAL; 2772 mv88e6xxx_reg_unlock(chip); 2773 2774 return ret; 2775 } 2776 2777 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2778 struct phy_device *phydev) 2779 { 2780 struct mv88e6xxx_chip *chip = ds->priv; 2781 int err; 2782 2783 mv88e6xxx_reg_lock(chip); 2784 err = mv88e6xxx_serdes_power(chip, port, true); 2785 mv88e6xxx_reg_unlock(chip); 2786 2787 return err; 2788 } 2789 2790 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2791 { 2792 struct mv88e6xxx_chip *chip = ds->priv; 2793 2794 mv88e6xxx_reg_lock(chip); 2795 if (mv88e6xxx_serdes_power(chip, port, false)) 2796 dev_err(chip->dev, "failed to power off SERDES\n"); 2797 mv88e6xxx_reg_unlock(chip); 2798 } 2799 2800 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2801 unsigned int ageing_time) 2802 { 2803 struct mv88e6xxx_chip *chip = ds->priv; 2804 int err; 2805 2806 mv88e6xxx_reg_lock(chip); 2807 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2808 mv88e6xxx_reg_unlock(chip); 2809 2810 return err; 2811 } 2812 2813 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2814 { 2815 int err; 2816 2817 /* Initialize the statistics unit */ 2818 if (chip->info->ops->stats_set_histogram) { 2819 err = chip->info->ops->stats_set_histogram(chip); 2820 if (err) 2821 return err; 2822 } 2823 2824 return mv88e6xxx_g1_stats_clear(chip); 2825 } 2826 2827 /* Check if the errata has already been applied. */ 2828 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2829 { 2830 int port; 2831 int err; 2832 u16 val; 2833 2834 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2835 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 2836 if (err) { 2837 dev_err(chip->dev, 2838 "Error reading hidden register: %d\n", err); 2839 return false; 2840 } 2841 if (val != 0x01c0) 2842 return false; 2843 } 2844 2845 return true; 2846 } 2847 2848 /* The 6390 copper ports have an errata which require poking magic 2849 * values into undocumented hidden registers and then performing a 2850 * software reset. 2851 */ 2852 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2853 { 2854 int port; 2855 int err; 2856 2857 if (mv88e6390_setup_errata_applied(chip)) 2858 return 0; 2859 2860 /* Set the ports into blocking mode */ 2861 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2862 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2863 if (err) 2864 return err; 2865 } 2866 2867 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2868 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 2869 if (err) 2870 return err; 2871 } 2872 2873 return mv88e6xxx_software_reset(chip); 2874 } 2875 2876 static void mv88e6xxx_teardown(struct dsa_switch *ds) 2877 { 2878 mv88e6xxx_teardown_devlink_params(ds); 2879 dsa_devlink_resources_unregister(ds); 2880 mv88e6xxx_teardown_devlink_regions(ds); 2881 } 2882 2883 static int mv88e6xxx_setup(struct dsa_switch *ds) 2884 { 2885 struct mv88e6xxx_chip *chip = ds->priv; 2886 u8 cmode; 2887 int err; 2888 int i; 2889 2890 chip->ds = ds; 2891 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2892 2893 mv88e6xxx_reg_lock(chip); 2894 2895 if (chip->info->ops->setup_errata) { 2896 err = chip->info->ops->setup_errata(chip); 2897 if (err) 2898 goto unlock; 2899 } 2900 2901 /* Cache the cmode of each port. */ 2902 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2903 if (chip->info->ops->port_get_cmode) { 2904 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 2905 if (err) 2906 goto unlock; 2907 2908 chip->ports[i].cmode = cmode; 2909 } 2910 } 2911 2912 /* Setup Switch Port Registers */ 2913 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2914 if (dsa_is_unused_port(ds, i)) 2915 continue; 2916 2917 /* Prevent the use of an invalid port. */ 2918 if (mv88e6xxx_is_invalid_port(chip, i)) { 2919 dev_err(chip->dev, "port %d is invalid\n", i); 2920 err = -EINVAL; 2921 goto unlock; 2922 } 2923 2924 err = mv88e6xxx_setup_port(chip, i); 2925 if (err) 2926 goto unlock; 2927 } 2928 2929 err = mv88e6xxx_irl_setup(chip); 2930 if (err) 2931 goto unlock; 2932 2933 err = mv88e6xxx_mac_setup(chip); 2934 if (err) 2935 goto unlock; 2936 2937 err = mv88e6xxx_phy_setup(chip); 2938 if (err) 2939 goto unlock; 2940 2941 err = mv88e6xxx_vtu_setup(chip); 2942 if (err) 2943 goto unlock; 2944 2945 err = mv88e6xxx_pvt_setup(chip); 2946 if (err) 2947 goto unlock; 2948 2949 err = mv88e6xxx_atu_setup(chip); 2950 if (err) 2951 goto unlock; 2952 2953 err = mv88e6xxx_broadcast_setup(chip, 0); 2954 if (err) 2955 goto unlock; 2956 2957 err = mv88e6xxx_pot_setup(chip); 2958 if (err) 2959 goto unlock; 2960 2961 err = mv88e6xxx_rmu_setup(chip); 2962 if (err) 2963 goto unlock; 2964 2965 err = mv88e6xxx_rsvd2cpu_setup(chip); 2966 if (err) 2967 goto unlock; 2968 2969 err = mv88e6xxx_trunk_setup(chip); 2970 if (err) 2971 goto unlock; 2972 2973 err = mv88e6xxx_devmap_setup(chip); 2974 if (err) 2975 goto unlock; 2976 2977 err = mv88e6xxx_pri_setup(chip); 2978 if (err) 2979 goto unlock; 2980 2981 /* Setup PTP Hardware Clock and timestamping */ 2982 if (chip->info->ptp_support) { 2983 err = mv88e6xxx_ptp_setup(chip); 2984 if (err) 2985 goto unlock; 2986 2987 err = mv88e6xxx_hwtstamp_setup(chip); 2988 if (err) 2989 goto unlock; 2990 } 2991 2992 err = mv88e6xxx_stats_setup(chip); 2993 if (err) 2994 goto unlock; 2995 2996 unlock: 2997 mv88e6xxx_reg_unlock(chip); 2998 2999 if (err) 3000 return err; 3001 3002 /* Have to be called without holding the register lock, since 3003 * they take the devlink lock, and we later take the locks in 3004 * the reverse order when getting/setting parameters or 3005 * resource occupancy. 3006 */ 3007 err = mv88e6xxx_setup_devlink_resources(ds); 3008 if (err) 3009 return err; 3010 3011 err = mv88e6xxx_setup_devlink_params(ds); 3012 if (err) 3013 goto out_resources; 3014 3015 err = mv88e6xxx_setup_devlink_regions(ds); 3016 if (err) 3017 goto out_params; 3018 3019 return 0; 3020 3021 out_params: 3022 mv88e6xxx_teardown_devlink_params(ds); 3023 out_resources: 3024 dsa_devlink_resources_unregister(ds); 3025 3026 return err; 3027 } 3028 3029 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3030 { 3031 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3032 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3033 u16 val; 3034 int err; 3035 3036 if (!chip->info->ops->phy_read) 3037 return -EOPNOTSUPP; 3038 3039 mv88e6xxx_reg_lock(chip); 3040 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3041 mv88e6xxx_reg_unlock(chip); 3042 3043 if (reg == MII_PHYSID2) { 3044 /* Some internal PHYs don't have a model number. */ 3045 if (chip->info->family != MV88E6XXX_FAMILY_6165) 3046 /* Then there is the 6165 family. It gets is 3047 * PHYs correct. But it can also have two 3048 * SERDES interfaces in the PHY address 3049 * space. And these don't have a model 3050 * number. But they are not PHYs, so we don't 3051 * want to give them something a PHY driver 3052 * will recognise. 3053 * 3054 * Use the mv88e6390 family model number 3055 * instead, for anything which really could be 3056 * a PHY, 3057 */ 3058 if (!(val & 0x3f0)) 3059 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 3060 } 3061 3062 return err ? err : val; 3063 } 3064 3065 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3066 { 3067 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3068 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3069 int err; 3070 3071 if (!chip->info->ops->phy_write) 3072 return -EOPNOTSUPP; 3073 3074 mv88e6xxx_reg_lock(chip); 3075 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3076 mv88e6xxx_reg_unlock(chip); 3077 3078 return err; 3079 } 3080 3081 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3082 struct device_node *np, 3083 bool external) 3084 { 3085 static int index; 3086 struct mv88e6xxx_mdio_bus *mdio_bus; 3087 struct mii_bus *bus; 3088 int err; 3089 3090 if (external) { 3091 mv88e6xxx_reg_lock(chip); 3092 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3093 mv88e6xxx_reg_unlock(chip); 3094 3095 if (err) 3096 return err; 3097 } 3098 3099 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3100 if (!bus) 3101 return -ENOMEM; 3102 3103 mdio_bus = bus->priv; 3104 mdio_bus->bus = bus; 3105 mdio_bus->chip = chip; 3106 INIT_LIST_HEAD(&mdio_bus->list); 3107 mdio_bus->external = external; 3108 3109 if (np) { 3110 bus->name = np->full_name; 3111 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3112 } else { 3113 bus->name = "mv88e6xxx SMI"; 3114 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3115 } 3116 3117 bus->read = mv88e6xxx_mdio_read; 3118 bus->write = mv88e6xxx_mdio_write; 3119 bus->parent = chip->dev; 3120 3121 if (!external) { 3122 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3123 if (err) 3124 return err; 3125 } 3126 3127 err = of_mdiobus_register(bus, np); 3128 if (err) { 3129 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3130 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3131 return err; 3132 } 3133 3134 if (external) 3135 list_add_tail(&mdio_bus->list, &chip->mdios); 3136 else 3137 list_add(&mdio_bus->list, &chip->mdios); 3138 3139 return 0; 3140 } 3141 3142 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3143 3144 { 3145 struct mv88e6xxx_mdio_bus *mdio_bus; 3146 struct mii_bus *bus; 3147 3148 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3149 bus = mdio_bus->bus; 3150 3151 if (!mdio_bus->external) 3152 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3153 3154 mdiobus_unregister(bus); 3155 } 3156 } 3157 3158 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3159 struct device_node *np) 3160 { 3161 struct device_node *child; 3162 int err; 3163 3164 /* Always register one mdio bus for the internal/default mdio 3165 * bus. This maybe represented in the device tree, but is 3166 * optional. 3167 */ 3168 child = of_get_child_by_name(np, "mdio"); 3169 err = mv88e6xxx_mdio_register(chip, child, false); 3170 if (err) 3171 return err; 3172 3173 /* Walk the device tree, and see if there are any other nodes 3174 * which say they are compatible with the external mdio 3175 * bus. 3176 */ 3177 for_each_available_child_of_node(np, child) { 3178 if (of_device_is_compatible( 3179 child, "marvell,mv88e6xxx-mdio-external")) { 3180 err = mv88e6xxx_mdio_register(chip, child, true); 3181 if (err) { 3182 mv88e6xxx_mdios_unregister(chip); 3183 of_node_put(child); 3184 return err; 3185 } 3186 } 3187 } 3188 3189 return 0; 3190 } 3191 3192 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3193 { 3194 struct mv88e6xxx_chip *chip = ds->priv; 3195 3196 return chip->eeprom_len; 3197 } 3198 3199 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3200 struct ethtool_eeprom *eeprom, u8 *data) 3201 { 3202 struct mv88e6xxx_chip *chip = ds->priv; 3203 int err; 3204 3205 if (!chip->info->ops->get_eeprom) 3206 return -EOPNOTSUPP; 3207 3208 mv88e6xxx_reg_lock(chip); 3209 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3210 mv88e6xxx_reg_unlock(chip); 3211 3212 if (err) 3213 return err; 3214 3215 eeprom->magic = 0xc3ec4951; 3216 3217 return 0; 3218 } 3219 3220 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3221 struct ethtool_eeprom *eeprom, u8 *data) 3222 { 3223 struct mv88e6xxx_chip *chip = ds->priv; 3224 int err; 3225 3226 if (!chip->info->ops->set_eeprom) 3227 return -EOPNOTSUPP; 3228 3229 if (eeprom->magic != 0xc3ec4951) 3230 return -EINVAL; 3231 3232 mv88e6xxx_reg_lock(chip); 3233 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3234 mv88e6xxx_reg_unlock(chip); 3235 3236 return err; 3237 } 3238 3239 static const struct mv88e6xxx_ops mv88e6085_ops = { 3240 /* MV88E6XXX_FAMILY_6097 */ 3241 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3242 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3243 .irl_init_all = mv88e6352_g2_irl_init_all, 3244 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3245 .phy_read = mv88e6185_phy_ppu_read, 3246 .phy_write = mv88e6185_phy_ppu_write, 3247 .port_set_link = mv88e6xxx_port_set_link, 3248 .port_sync_link = mv88e6xxx_port_sync_link, 3249 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3250 .port_tag_remap = mv88e6095_port_tag_remap, 3251 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3252 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3253 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3254 .port_set_ether_type = mv88e6351_port_set_ether_type, 3255 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3256 .port_pause_limit = mv88e6097_port_pause_limit, 3257 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3258 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3259 .port_get_cmode = mv88e6185_port_get_cmode, 3260 .port_setup_message_port = mv88e6xxx_setup_message_port, 3261 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3262 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3263 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3264 .stats_get_strings = mv88e6095_stats_get_strings, 3265 .stats_get_stats = mv88e6095_stats_get_stats, 3266 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3267 .set_egress_port = mv88e6095_g1_set_egress_port, 3268 .watchdog_ops = &mv88e6097_watchdog_ops, 3269 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3270 .pot_clear = mv88e6xxx_g2_pot_clear, 3271 .ppu_enable = mv88e6185_g1_ppu_enable, 3272 .ppu_disable = mv88e6185_g1_ppu_disable, 3273 .reset = mv88e6185_g1_reset, 3274 .rmu_disable = mv88e6085_g1_rmu_disable, 3275 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3276 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3277 .phylink_validate = mv88e6185_phylink_validate, 3278 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3279 }; 3280 3281 static const struct mv88e6xxx_ops mv88e6095_ops = { 3282 /* MV88E6XXX_FAMILY_6095 */ 3283 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3284 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3285 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3286 .phy_read = mv88e6185_phy_ppu_read, 3287 .phy_write = mv88e6185_phy_ppu_write, 3288 .port_set_link = mv88e6xxx_port_set_link, 3289 .port_sync_link = mv88e6185_port_sync_link, 3290 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3291 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3292 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3293 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3294 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3295 .port_get_cmode = mv88e6185_port_get_cmode, 3296 .port_setup_message_port = mv88e6xxx_setup_message_port, 3297 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3298 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3299 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3300 .stats_get_strings = mv88e6095_stats_get_strings, 3301 .stats_get_stats = mv88e6095_stats_get_stats, 3302 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3303 .serdes_power = mv88e6185_serdes_power, 3304 .serdes_get_lane = mv88e6185_serdes_get_lane, 3305 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3306 .ppu_enable = mv88e6185_g1_ppu_enable, 3307 .ppu_disable = mv88e6185_g1_ppu_disable, 3308 .reset = mv88e6185_g1_reset, 3309 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3310 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3311 .phylink_validate = mv88e6185_phylink_validate, 3312 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3313 }; 3314 3315 static const struct mv88e6xxx_ops mv88e6097_ops = { 3316 /* MV88E6XXX_FAMILY_6097 */ 3317 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3318 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3319 .irl_init_all = mv88e6352_g2_irl_init_all, 3320 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3321 .phy_read = mv88e6xxx_g2_smi_phy_read, 3322 .phy_write = mv88e6xxx_g2_smi_phy_write, 3323 .port_set_link = mv88e6xxx_port_set_link, 3324 .port_sync_link = mv88e6185_port_sync_link, 3325 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3326 .port_tag_remap = mv88e6095_port_tag_remap, 3327 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3328 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3329 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3330 .port_set_ether_type = mv88e6351_port_set_ether_type, 3331 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3332 .port_pause_limit = mv88e6097_port_pause_limit, 3333 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3334 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3335 .port_get_cmode = mv88e6185_port_get_cmode, 3336 .port_setup_message_port = mv88e6xxx_setup_message_port, 3337 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3338 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3339 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3340 .stats_get_strings = mv88e6095_stats_get_strings, 3341 .stats_get_stats = mv88e6095_stats_get_stats, 3342 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3343 .set_egress_port = mv88e6095_g1_set_egress_port, 3344 .watchdog_ops = &mv88e6097_watchdog_ops, 3345 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3346 .serdes_power = mv88e6185_serdes_power, 3347 .serdes_get_lane = mv88e6185_serdes_get_lane, 3348 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3349 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3350 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 3351 .serdes_irq_status = mv88e6097_serdes_irq_status, 3352 .pot_clear = mv88e6xxx_g2_pot_clear, 3353 .reset = mv88e6352_g1_reset, 3354 .rmu_disable = mv88e6085_g1_rmu_disable, 3355 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3356 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3357 .phylink_validate = mv88e6185_phylink_validate, 3358 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3359 }; 3360 3361 static const struct mv88e6xxx_ops mv88e6123_ops = { 3362 /* MV88E6XXX_FAMILY_6165 */ 3363 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3364 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3365 .irl_init_all = mv88e6352_g2_irl_init_all, 3366 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3367 .phy_read = mv88e6xxx_g2_smi_phy_read, 3368 .phy_write = mv88e6xxx_g2_smi_phy_write, 3369 .port_set_link = mv88e6xxx_port_set_link, 3370 .port_sync_link = mv88e6xxx_port_sync_link, 3371 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3372 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3373 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3374 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3375 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3376 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3377 .port_get_cmode = mv88e6185_port_get_cmode, 3378 .port_setup_message_port = mv88e6xxx_setup_message_port, 3379 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3380 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3381 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3382 .stats_get_strings = mv88e6095_stats_get_strings, 3383 .stats_get_stats = mv88e6095_stats_get_stats, 3384 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3385 .set_egress_port = mv88e6095_g1_set_egress_port, 3386 .watchdog_ops = &mv88e6097_watchdog_ops, 3387 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3388 .pot_clear = mv88e6xxx_g2_pot_clear, 3389 .reset = mv88e6352_g1_reset, 3390 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3391 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3392 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3393 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3394 .phylink_validate = mv88e6185_phylink_validate, 3395 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3396 }; 3397 3398 static const struct mv88e6xxx_ops mv88e6131_ops = { 3399 /* MV88E6XXX_FAMILY_6185 */ 3400 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3401 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3402 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3403 .phy_read = mv88e6185_phy_ppu_read, 3404 .phy_write = mv88e6185_phy_ppu_write, 3405 .port_set_link = mv88e6xxx_port_set_link, 3406 .port_sync_link = mv88e6xxx_port_sync_link, 3407 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3408 .port_tag_remap = mv88e6095_port_tag_remap, 3409 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3410 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3411 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3412 .port_set_ether_type = mv88e6351_port_set_ether_type, 3413 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3414 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3415 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3416 .port_pause_limit = mv88e6097_port_pause_limit, 3417 .port_set_pause = mv88e6185_port_set_pause, 3418 .port_get_cmode = mv88e6185_port_get_cmode, 3419 .port_setup_message_port = mv88e6xxx_setup_message_port, 3420 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3421 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3422 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3423 .stats_get_strings = mv88e6095_stats_get_strings, 3424 .stats_get_stats = mv88e6095_stats_get_stats, 3425 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3426 .set_egress_port = mv88e6095_g1_set_egress_port, 3427 .watchdog_ops = &mv88e6097_watchdog_ops, 3428 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3429 .ppu_enable = mv88e6185_g1_ppu_enable, 3430 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3431 .ppu_disable = mv88e6185_g1_ppu_disable, 3432 .reset = mv88e6185_g1_reset, 3433 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3434 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3435 .phylink_validate = mv88e6185_phylink_validate, 3436 }; 3437 3438 static const struct mv88e6xxx_ops mv88e6141_ops = { 3439 /* MV88E6XXX_FAMILY_6341 */ 3440 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3441 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3442 .irl_init_all = mv88e6352_g2_irl_init_all, 3443 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3444 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3445 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3446 .phy_read = mv88e6xxx_g2_smi_phy_read, 3447 .phy_write = mv88e6xxx_g2_smi_phy_write, 3448 .port_set_link = mv88e6xxx_port_set_link, 3449 .port_sync_link = mv88e6xxx_port_sync_link, 3450 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3451 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3452 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3453 .port_tag_remap = mv88e6095_port_tag_remap, 3454 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3455 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3456 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3457 .port_set_ether_type = mv88e6351_port_set_ether_type, 3458 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3459 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3460 .port_pause_limit = mv88e6097_port_pause_limit, 3461 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3462 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3463 .port_get_cmode = mv88e6352_port_get_cmode, 3464 .port_set_cmode = mv88e6341_port_set_cmode, 3465 .port_setup_message_port = mv88e6xxx_setup_message_port, 3466 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3467 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3468 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3469 .stats_get_strings = mv88e6320_stats_get_strings, 3470 .stats_get_stats = mv88e6390_stats_get_stats, 3471 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3472 .set_egress_port = mv88e6390_g1_set_egress_port, 3473 .watchdog_ops = &mv88e6390_watchdog_ops, 3474 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3475 .pot_clear = mv88e6xxx_g2_pot_clear, 3476 .reset = mv88e6352_g1_reset, 3477 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3478 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3479 .serdes_power = mv88e6390_serdes_power, 3480 .serdes_get_lane = mv88e6341_serdes_get_lane, 3481 /* Check status register pause & lpa register */ 3482 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3483 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3484 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3485 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3486 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3487 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3488 .serdes_irq_status = mv88e6390_serdes_irq_status, 3489 .gpio_ops = &mv88e6352_gpio_ops, 3490 .phylink_validate = mv88e6341_phylink_validate, 3491 }; 3492 3493 static const struct mv88e6xxx_ops mv88e6161_ops = { 3494 /* MV88E6XXX_FAMILY_6165 */ 3495 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3496 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3497 .irl_init_all = mv88e6352_g2_irl_init_all, 3498 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3499 .phy_read = mv88e6xxx_g2_smi_phy_read, 3500 .phy_write = mv88e6xxx_g2_smi_phy_write, 3501 .port_set_link = mv88e6xxx_port_set_link, 3502 .port_sync_link = mv88e6xxx_port_sync_link, 3503 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3504 .port_tag_remap = mv88e6095_port_tag_remap, 3505 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3506 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3507 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3508 .port_set_ether_type = mv88e6351_port_set_ether_type, 3509 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3510 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3511 .port_pause_limit = mv88e6097_port_pause_limit, 3512 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3513 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3514 .port_get_cmode = mv88e6185_port_get_cmode, 3515 .port_setup_message_port = mv88e6xxx_setup_message_port, 3516 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3517 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3518 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3519 .stats_get_strings = mv88e6095_stats_get_strings, 3520 .stats_get_stats = mv88e6095_stats_get_stats, 3521 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3522 .set_egress_port = mv88e6095_g1_set_egress_port, 3523 .watchdog_ops = &mv88e6097_watchdog_ops, 3524 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3525 .pot_clear = mv88e6xxx_g2_pot_clear, 3526 .reset = mv88e6352_g1_reset, 3527 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3528 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3529 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3530 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3531 .avb_ops = &mv88e6165_avb_ops, 3532 .ptp_ops = &mv88e6165_ptp_ops, 3533 .phylink_validate = mv88e6185_phylink_validate, 3534 }; 3535 3536 static const struct mv88e6xxx_ops mv88e6165_ops = { 3537 /* MV88E6XXX_FAMILY_6165 */ 3538 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3539 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3540 .irl_init_all = mv88e6352_g2_irl_init_all, 3541 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3542 .phy_read = mv88e6165_phy_read, 3543 .phy_write = mv88e6165_phy_write, 3544 .port_set_link = mv88e6xxx_port_set_link, 3545 .port_sync_link = mv88e6xxx_port_sync_link, 3546 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3547 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3548 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3549 .port_get_cmode = mv88e6185_port_get_cmode, 3550 .port_setup_message_port = mv88e6xxx_setup_message_port, 3551 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3552 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3553 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3554 .stats_get_strings = mv88e6095_stats_get_strings, 3555 .stats_get_stats = mv88e6095_stats_get_stats, 3556 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3557 .set_egress_port = mv88e6095_g1_set_egress_port, 3558 .watchdog_ops = &mv88e6097_watchdog_ops, 3559 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3560 .pot_clear = mv88e6xxx_g2_pot_clear, 3561 .reset = mv88e6352_g1_reset, 3562 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3563 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3564 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3565 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3566 .avb_ops = &mv88e6165_avb_ops, 3567 .ptp_ops = &mv88e6165_ptp_ops, 3568 .phylink_validate = mv88e6185_phylink_validate, 3569 }; 3570 3571 static const struct mv88e6xxx_ops mv88e6171_ops = { 3572 /* MV88E6XXX_FAMILY_6351 */ 3573 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3574 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3575 .irl_init_all = mv88e6352_g2_irl_init_all, 3576 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3577 .phy_read = mv88e6xxx_g2_smi_phy_read, 3578 .phy_write = mv88e6xxx_g2_smi_phy_write, 3579 .port_set_link = mv88e6xxx_port_set_link, 3580 .port_sync_link = mv88e6xxx_port_sync_link, 3581 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3582 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3583 .port_tag_remap = mv88e6095_port_tag_remap, 3584 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3585 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3586 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3587 .port_set_ether_type = mv88e6351_port_set_ether_type, 3588 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3589 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3590 .port_pause_limit = mv88e6097_port_pause_limit, 3591 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3592 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3593 .port_get_cmode = mv88e6352_port_get_cmode, 3594 .port_setup_message_port = mv88e6xxx_setup_message_port, 3595 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3596 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3597 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3598 .stats_get_strings = mv88e6095_stats_get_strings, 3599 .stats_get_stats = mv88e6095_stats_get_stats, 3600 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3601 .set_egress_port = mv88e6095_g1_set_egress_port, 3602 .watchdog_ops = &mv88e6097_watchdog_ops, 3603 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3604 .pot_clear = mv88e6xxx_g2_pot_clear, 3605 .reset = mv88e6352_g1_reset, 3606 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3607 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3608 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3609 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3610 .phylink_validate = mv88e6185_phylink_validate, 3611 }; 3612 3613 static const struct mv88e6xxx_ops mv88e6172_ops = { 3614 /* MV88E6XXX_FAMILY_6352 */ 3615 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3616 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3617 .irl_init_all = mv88e6352_g2_irl_init_all, 3618 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3619 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3620 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3621 .phy_read = mv88e6xxx_g2_smi_phy_read, 3622 .phy_write = mv88e6xxx_g2_smi_phy_write, 3623 .port_set_link = mv88e6xxx_port_set_link, 3624 .port_sync_link = mv88e6xxx_port_sync_link, 3625 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3626 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3627 .port_tag_remap = mv88e6095_port_tag_remap, 3628 .port_set_policy = mv88e6352_port_set_policy, 3629 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3630 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3631 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3632 .port_set_ether_type = mv88e6351_port_set_ether_type, 3633 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3634 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3635 .port_pause_limit = mv88e6097_port_pause_limit, 3636 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3637 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3638 .port_get_cmode = mv88e6352_port_get_cmode, 3639 .port_setup_message_port = mv88e6xxx_setup_message_port, 3640 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3641 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3642 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3643 .stats_get_strings = mv88e6095_stats_get_strings, 3644 .stats_get_stats = mv88e6095_stats_get_stats, 3645 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3646 .set_egress_port = mv88e6095_g1_set_egress_port, 3647 .watchdog_ops = &mv88e6097_watchdog_ops, 3648 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3649 .pot_clear = mv88e6xxx_g2_pot_clear, 3650 .reset = mv88e6352_g1_reset, 3651 .rmu_disable = mv88e6352_g1_rmu_disable, 3652 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3653 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3654 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3655 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3656 .serdes_get_lane = mv88e6352_serdes_get_lane, 3657 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3658 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3659 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3660 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3661 .serdes_power = mv88e6352_serdes_power, 3662 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3663 .serdes_get_regs = mv88e6352_serdes_get_regs, 3664 .gpio_ops = &mv88e6352_gpio_ops, 3665 .phylink_validate = mv88e6352_phylink_validate, 3666 }; 3667 3668 static const struct mv88e6xxx_ops mv88e6175_ops = { 3669 /* MV88E6XXX_FAMILY_6351 */ 3670 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3671 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3672 .irl_init_all = mv88e6352_g2_irl_init_all, 3673 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3674 .phy_read = mv88e6xxx_g2_smi_phy_read, 3675 .phy_write = mv88e6xxx_g2_smi_phy_write, 3676 .port_set_link = mv88e6xxx_port_set_link, 3677 .port_sync_link = mv88e6xxx_port_sync_link, 3678 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3679 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3680 .port_tag_remap = mv88e6095_port_tag_remap, 3681 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3682 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3683 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3684 .port_set_ether_type = mv88e6351_port_set_ether_type, 3685 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3686 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3687 .port_pause_limit = mv88e6097_port_pause_limit, 3688 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3689 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3690 .port_get_cmode = mv88e6352_port_get_cmode, 3691 .port_setup_message_port = mv88e6xxx_setup_message_port, 3692 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3693 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3694 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3695 .stats_get_strings = mv88e6095_stats_get_strings, 3696 .stats_get_stats = mv88e6095_stats_get_stats, 3697 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3698 .set_egress_port = mv88e6095_g1_set_egress_port, 3699 .watchdog_ops = &mv88e6097_watchdog_ops, 3700 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3701 .pot_clear = mv88e6xxx_g2_pot_clear, 3702 .reset = mv88e6352_g1_reset, 3703 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3704 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3705 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3706 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3707 .phylink_validate = mv88e6185_phylink_validate, 3708 }; 3709 3710 static const struct mv88e6xxx_ops mv88e6176_ops = { 3711 /* MV88E6XXX_FAMILY_6352 */ 3712 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3713 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3714 .irl_init_all = mv88e6352_g2_irl_init_all, 3715 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3716 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3717 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3718 .phy_read = mv88e6xxx_g2_smi_phy_read, 3719 .phy_write = mv88e6xxx_g2_smi_phy_write, 3720 .port_set_link = mv88e6xxx_port_set_link, 3721 .port_sync_link = mv88e6xxx_port_sync_link, 3722 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3723 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3724 .port_tag_remap = mv88e6095_port_tag_remap, 3725 .port_set_policy = mv88e6352_port_set_policy, 3726 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3727 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3728 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3729 .port_set_ether_type = mv88e6351_port_set_ether_type, 3730 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3731 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3732 .port_pause_limit = mv88e6097_port_pause_limit, 3733 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3734 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3735 .port_get_cmode = mv88e6352_port_get_cmode, 3736 .port_setup_message_port = mv88e6xxx_setup_message_port, 3737 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3738 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3739 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3740 .stats_get_strings = mv88e6095_stats_get_strings, 3741 .stats_get_stats = mv88e6095_stats_get_stats, 3742 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3743 .set_egress_port = mv88e6095_g1_set_egress_port, 3744 .watchdog_ops = &mv88e6097_watchdog_ops, 3745 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3746 .pot_clear = mv88e6xxx_g2_pot_clear, 3747 .reset = mv88e6352_g1_reset, 3748 .rmu_disable = mv88e6352_g1_rmu_disable, 3749 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3750 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3751 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3752 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3753 .serdes_get_lane = mv88e6352_serdes_get_lane, 3754 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3755 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3756 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3757 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3758 .serdes_power = mv88e6352_serdes_power, 3759 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3760 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3761 .serdes_irq_status = mv88e6352_serdes_irq_status, 3762 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3763 .serdes_get_regs = mv88e6352_serdes_get_regs, 3764 .gpio_ops = &mv88e6352_gpio_ops, 3765 .phylink_validate = mv88e6352_phylink_validate, 3766 }; 3767 3768 static const struct mv88e6xxx_ops mv88e6185_ops = { 3769 /* MV88E6XXX_FAMILY_6185 */ 3770 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3771 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3772 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3773 .phy_read = mv88e6185_phy_ppu_read, 3774 .phy_write = mv88e6185_phy_ppu_write, 3775 .port_set_link = mv88e6xxx_port_set_link, 3776 .port_sync_link = mv88e6185_port_sync_link, 3777 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3778 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3779 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3780 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3781 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3782 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3783 .port_set_pause = mv88e6185_port_set_pause, 3784 .port_get_cmode = mv88e6185_port_get_cmode, 3785 .port_setup_message_port = mv88e6xxx_setup_message_port, 3786 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3787 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3788 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3789 .stats_get_strings = mv88e6095_stats_get_strings, 3790 .stats_get_stats = mv88e6095_stats_get_stats, 3791 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3792 .set_egress_port = mv88e6095_g1_set_egress_port, 3793 .watchdog_ops = &mv88e6097_watchdog_ops, 3794 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3795 .serdes_power = mv88e6185_serdes_power, 3796 .serdes_get_lane = mv88e6185_serdes_get_lane, 3797 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3798 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3799 .ppu_enable = mv88e6185_g1_ppu_enable, 3800 .ppu_disable = mv88e6185_g1_ppu_disable, 3801 .reset = mv88e6185_g1_reset, 3802 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3803 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3804 .phylink_validate = mv88e6185_phylink_validate, 3805 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3806 }; 3807 3808 static const struct mv88e6xxx_ops mv88e6190_ops = { 3809 /* MV88E6XXX_FAMILY_6390 */ 3810 .setup_errata = mv88e6390_setup_errata, 3811 .irl_init_all = mv88e6390_g2_irl_init_all, 3812 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3813 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3814 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3815 .phy_read = mv88e6xxx_g2_smi_phy_read, 3816 .phy_write = mv88e6xxx_g2_smi_phy_write, 3817 .port_set_link = mv88e6xxx_port_set_link, 3818 .port_sync_link = mv88e6xxx_port_sync_link, 3819 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3820 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 3821 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3822 .port_tag_remap = mv88e6390_port_tag_remap, 3823 .port_set_policy = mv88e6352_port_set_policy, 3824 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3825 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3826 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3827 .port_set_ether_type = mv88e6351_port_set_ether_type, 3828 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3829 .port_pause_limit = mv88e6390_port_pause_limit, 3830 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3831 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3832 .port_get_cmode = mv88e6352_port_get_cmode, 3833 .port_set_cmode = mv88e6390_port_set_cmode, 3834 .port_setup_message_port = mv88e6xxx_setup_message_port, 3835 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3836 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3837 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3838 .stats_get_strings = mv88e6320_stats_get_strings, 3839 .stats_get_stats = mv88e6390_stats_get_stats, 3840 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3841 .set_egress_port = mv88e6390_g1_set_egress_port, 3842 .watchdog_ops = &mv88e6390_watchdog_ops, 3843 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3844 .pot_clear = mv88e6xxx_g2_pot_clear, 3845 .reset = mv88e6352_g1_reset, 3846 .rmu_disable = mv88e6390_g1_rmu_disable, 3847 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3848 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3849 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3850 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3851 .serdes_power = mv88e6390_serdes_power, 3852 .serdes_get_lane = mv88e6390_serdes_get_lane, 3853 /* Check status register pause & lpa register */ 3854 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3855 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3856 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3857 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3858 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3859 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3860 .serdes_irq_status = mv88e6390_serdes_irq_status, 3861 .serdes_get_strings = mv88e6390_serdes_get_strings, 3862 .serdes_get_stats = mv88e6390_serdes_get_stats, 3863 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3864 .serdes_get_regs = mv88e6390_serdes_get_regs, 3865 .gpio_ops = &mv88e6352_gpio_ops, 3866 .phylink_validate = mv88e6390_phylink_validate, 3867 }; 3868 3869 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3870 /* MV88E6XXX_FAMILY_6390 */ 3871 .setup_errata = mv88e6390_setup_errata, 3872 .irl_init_all = mv88e6390_g2_irl_init_all, 3873 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3874 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3875 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3876 .phy_read = mv88e6xxx_g2_smi_phy_read, 3877 .phy_write = mv88e6xxx_g2_smi_phy_write, 3878 .port_set_link = mv88e6xxx_port_set_link, 3879 .port_sync_link = mv88e6xxx_port_sync_link, 3880 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3881 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 3882 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3883 .port_tag_remap = mv88e6390_port_tag_remap, 3884 .port_set_policy = mv88e6352_port_set_policy, 3885 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3886 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3887 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3888 .port_set_ether_type = mv88e6351_port_set_ether_type, 3889 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3890 .port_pause_limit = mv88e6390_port_pause_limit, 3891 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3892 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3893 .port_get_cmode = mv88e6352_port_get_cmode, 3894 .port_set_cmode = mv88e6390x_port_set_cmode, 3895 .port_setup_message_port = mv88e6xxx_setup_message_port, 3896 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3897 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3898 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3899 .stats_get_strings = mv88e6320_stats_get_strings, 3900 .stats_get_stats = mv88e6390_stats_get_stats, 3901 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3902 .set_egress_port = mv88e6390_g1_set_egress_port, 3903 .watchdog_ops = &mv88e6390_watchdog_ops, 3904 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3905 .pot_clear = mv88e6xxx_g2_pot_clear, 3906 .reset = mv88e6352_g1_reset, 3907 .rmu_disable = mv88e6390_g1_rmu_disable, 3908 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3909 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3910 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3911 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3912 .serdes_power = mv88e6390_serdes_power, 3913 .serdes_get_lane = mv88e6390x_serdes_get_lane, 3914 /* Check status register pause & lpa register */ 3915 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3916 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3917 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3918 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3919 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3920 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3921 .serdes_irq_status = mv88e6390_serdes_irq_status, 3922 .serdes_get_strings = mv88e6390_serdes_get_strings, 3923 .serdes_get_stats = mv88e6390_serdes_get_stats, 3924 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3925 .serdes_get_regs = mv88e6390_serdes_get_regs, 3926 .gpio_ops = &mv88e6352_gpio_ops, 3927 .phylink_validate = mv88e6390x_phylink_validate, 3928 }; 3929 3930 static const struct mv88e6xxx_ops mv88e6191_ops = { 3931 /* MV88E6XXX_FAMILY_6390 */ 3932 .setup_errata = mv88e6390_setup_errata, 3933 .irl_init_all = mv88e6390_g2_irl_init_all, 3934 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3935 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3936 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3937 .phy_read = mv88e6xxx_g2_smi_phy_read, 3938 .phy_write = mv88e6xxx_g2_smi_phy_write, 3939 .port_set_link = mv88e6xxx_port_set_link, 3940 .port_sync_link = mv88e6xxx_port_sync_link, 3941 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3942 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 3943 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3944 .port_tag_remap = mv88e6390_port_tag_remap, 3945 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3946 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3947 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3948 .port_set_ether_type = mv88e6351_port_set_ether_type, 3949 .port_pause_limit = mv88e6390_port_pause_limit, 3950 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3951 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3952 .port_get_cmode = mv88e6352_port_get_cmode, 3953 .port_set_cmode = mv88e6390_port_set_cmode, 3954 .port_setup_message_port = mv88e6xxx_setup_message_port, 3955 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3956 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3957 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3958 .stats_get_strings = mv88e6320_stats_get_strings, 3959 .stats_get_stats = mv88e6390_stats_get_stats, 3960 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3961 .set_egress_port = mv88e6390_g1_set_egress_port, 3962 .watchdog_ops = &mv88e6390_watchdog_ops, 3963 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3964 .pot_clear = mv88e6xxx_g2_pot_clear, 3965 .reset = mv88e6352_g1_reset, 3966 .rmu_disable = mv88e6390_g1_rmu_disable, 3967 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3968 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3969 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3970 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3971 .serdes_power = mv88e6390_serdes_power, 3972 .serdes_get_lane = mv88e6390_serdes_get_lane, 3973 /* Check status register pause & lpa register */ 3974 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3975 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3976 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3977 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3978 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3979 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3980 .serdes_irq_status = mv88e6390_serdes_irq_status, 3981 .serdes_get_strings = mv88e6390_serdes_get_strings, 3982 .serdes_get_stats = mv88e6390_serdes_get_stats, 3983 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3984 .serdes_get_regs = mv88e6390_serdes_get_regs, 3985 .avb_ops = &mv88e6390_avb_ops, 3986 .ptp_ops = &mv88e6352_ptp_ops, 3987 .phylink_validate = mv88e6390_phylink_validate, 3988 }; 3989 3990 static const struct mv88e6xxx_ops mv88e6240_ops = { 3991 /* MV88E6XXX_FAMILY_6352 */ 3992 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3993 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3994 .irl_init_all = mv88e6352_g2_irl_init_all, 3995 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3996 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3997 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3998 .phy_read = mv88e6xxx_g2_smi_phy_read, 3999 .phy_write = mv88e6xxx_g2_smi_phy_write, 4000 .port_set_link = mv88e6xxx_port_set_link, 4001 .port_sync_link = mv88e6xxx_port_sync_link, 4002 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4003 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4004 .port_tag_remap = mv88e6095_port_tag_remap, 4005 .port_set_policy = mv88e6352_port_set_policy, 4006 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4007 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4008 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4009 .port_set_ether_type = mv88e6351_port_set_ether_type, 4010 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4011 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4012 .port_pause_limit = mv88e6097_port_pause_limit, 4013 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4014 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4015 .port_get_cmode = mv88e6352_port_get_cmode, 4016 .port_setup_message_port = mv88e6xxx_setup_message_port, 4017 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4018 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4019 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4020 .stats_get_strings = mv88e6095_stats_get_strings, 4021 .stats_get_stats = mv88e6095_stats_get_stats, 4022 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4023 .set_egress_port = mv88e6095_g1_set_egress_port, 4024 .watchdog_ops = &mv88e6097_watchdog_ops, 4025 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4026 .pot_clear = mv88e6xxx_g2_pot_clear, 4027 .reset = mv88e6352_g1_reset, 4028 .rmu_disable = mv88e6352_g1_rmu_disable, 4029 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4030 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4031 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4032 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4033 .serdes_get_lane = mv88e6352_serdes_get_lane, 4034 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4035 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4036 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4037 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4038 .serdes_power = mv88e6352_serdes_power, 4039 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4040 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4041 .serdes_irq_status = mv88e6352_serdes_irq_status, 4042 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4043 .serdes_get_regs = mv88e6352_serdes_get_regs, 4044 .gpio_ops = &mv88e6352_gpio_ops, 4045 .avb_ops = &mv88e6352_avb_ops, 4046 .ptp_ops = &mv88e6352_ptp_ops, 4047 .phylink_validate = mv88e6352_phylink_validate, 4048 }; 4049 4050 static const struct mv88e6xxx_ops mv88e6250_ops = { 4051 /* MV88E6XXX_FAMILY_6250 */ 4052 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4053 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4054 .irl_init_all = mv88e6352_g2_irl_init_all, 4055 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4056 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4057 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4058 .phy_read = mv88e6xxx_g2_smi_phy_read, 4059 .phy_write = mv88e6xxx_g2_smi_phy_write, 4060 .port_set_link = mv88e6xxx_port_set_link, 4061 .port_sync_link = mv88e6xxx_port_sync_link, 4062 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4063 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4064 .port_tag_remap = mv88e6095_port_tag_remap, 4065 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4066 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4067 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4068 .port_set_ether_type = mv88e6351_port_set_ether_type, 4069 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4070 .port_pause_limit = mv88e6097_port_pause_limit, 4071 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4072 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4073 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4074 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4075 .stats_get_strings = mv88e6250_stats_get_strings, 4076 .stats_get_stats = mv88e6250_stats_get_stats, 4077 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4078 .set_egress_port = mv88e6095_g1_set_egress_port, 4079 .watchdog_ops = &mv88e6250_watchdog_ops, 4080 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4081 .pot_clear = mv88e6xxx_g2_pot_clear, 4082 .reset = mv88e6250_g1_reset, 4083 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4084 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4085 .avb_ops = &mv88e6352_avb_ops, 4086 .ptp_ops = &mv88e6250_ptp_ops, 4087 .phylink_validate = mv88e6065_phylink_validate, 4088 }; 4089 4090 static const struct mv88e6xxx_ops mv88e6290_ops = { 4091 /* MV88E6XXX_FAMILY_6390 */ 4092 .setup_errata = mv88e6390_setup_errata, 4093 .irl_init_all = mv88e6390_g2_irl_init_all, 4094 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4095 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4096 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4097 .phy_read = mv88e6xxx_g2_smi_phy_read, 4098 .phy_write = mv88e6xxx_g2_smi_phy_write, 4099 .port_set_link = mv88e6xxx_port_set_link, 4100 .port_sync_link = mv88e6xxx_port_sync_link, 4101 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4102 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4103 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4104 .port_tag_remap = mv88e6390_port_tag_remap, 4105 .port_set_policy = mv88e6352_port_set_policy, 4106 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4107 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4108 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4109 .port_set_ether_type = mv88e6351_port_set_ether_type, 4110 .port_pause_limit = mv88e6390_port_pause_limit, 4111 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4112 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4113 .port_get_cmode = mv88e6352_port_get_cmode, 4114 .port_set_cmode = mv88e6390_port_set_cmode, 4115 .port_setup_message_port = mv88e6xxx_setup_message_port, 4116 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4117 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4118 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4119 .stats_get_strings = mv88e6320_stats_get_strings, 4120 .stats_get_stats = mv88e6390_stats_get_stats, 4121 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4122 .set_egress_port = mv88e6390_g1_set_egress_port, 4123 .watchdog_ops = &mv88e6390_watchdog_ops, 4124 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4125 .pot_clear = mv88e6xxx_g2_pot_clear, 4126 .reset = mv88e6352_g1_reset, 4127 .rmu_disable = mv88e6390_g1_rmu_disable, 4128 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4129 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4130 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4131 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4132 .serdes_power = mv88e6390_serdes_power, 4133 .serdes_get_lane = mv88e6390_serdes_get_lane, 4134 /* Check status register pause & lpa register */ 4135 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4136 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4137 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4138 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4139 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4140 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4141 .serdes_irq_status = mv88e6390_serdes_irq_status, 4142 .serdes_get_strings = mv88e6390_serdes_get_strings, 4143 .serdes_get_stats = mv88e6390_serdes_get_stats, 4144 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4145 .serdes_get_regs = mv88e6390_serdes_get_regs, 4146 .gpio_ops = &mv88e6352_gpio_ops, 4147 .avb_ops = &mv88e6390_avb_ops, 4148 .ptp_ops = &mv88e6352_ptp_ops, 4149 .phylink_validate = mv88e6390_phylink_validate, 4150 }; 4151 4152 static const struct mv88e6xxx_ops mv88e6320_ops = { 4153 /* MV88E6XXX_FAMILY_6320 */ 4154 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4155 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4156 .irl_init_all = mv88e6352_g2_irl_init_all, 4157 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4158 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4159 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4160 .phy_read = mv88e6xxx_g2_smi_phy_read, 4161 .phy_write = mv88e6xxx_g2_smi_phy_write, 4162 .port_set_link = mv88e6xxx_port_set_link, 4163 .port_sync_link = mv88e6xxx_port_sync_link, 4164 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4165 .port_tag_remap = mv88e6095_port_tag_remap, 4166 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4167 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4168 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4169 .port_set_ether_type = mv88e6351_port_set_ether_type, 4170 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4171 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4172 .port_pause_limit = mv88e6097_port_pause_limit, 4173 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4174 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4175 .port_get_cmode = mv88e6352_port_get_cmode, 4176 .port_setup_message_port = mv88e6xxx_setup_message_port, 4177 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4178 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4179 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4180 .stats_get_strings = mv88e6320_stats_get_strings, 4181 .stats_get_stats = mv88e6320_stats_get_stats, 4182 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4183 .set_egress_port = mv88e6095_g1_set_egress_port, 4184 .watchdog_ops = &mv88e6390_watchdog_ops, 4185 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4186 .pot_clear = mv88e6xxx_g2_pot_clear, 4187 .reset = mv88e6352_g1_reset, 4188 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4189 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4190 .gpio_ops = &mv88e6352_gpio_ops, 4191 .avb_ops = &mv88e6352_avb_ops, 4192 .ptp_ops = &mv88e6352_ptp_ops, 4193 .phylink_validate = mv88e6185_phylink_validate, 4194 }; 4195 4196 static const struct mv88e6xxx_ops mv88e6321_ops = { 4197 /* MV88E6XXX_FAMILY_6320 */ 4198 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4199 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4200 .irl_init_all = mv88e6352_g2_irl_init_all, 4201 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4202 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4203 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4204 .phy_read = mv88e6xxx_g2_smi_phy_read, 4205 .phy_write = mv88e6xxx_g2_smi_phy_write, 4206 .port_set_link = mv88e6xxx_port_set_link, 4207 .port_sync_link = mv88e6xxx_port_sync_link, 4208 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4209 .port_tag_remap = mv88e6095_port_tag_remap, 4210 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4211 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4212 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4213 .port_set_ether_type = mv88e6351_port_set_ether_type, 4214 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4215 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4216 .port_pause_limit = mv88e6097_port_pause_limit, 4217 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4218 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4219 .port_get_cmode = mv88e6352_port_get_cmode, 4220 .port_setup_message_port = mv88e6xxx_setup_message_port, 4221 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4222 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4223 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4224 .stats_get_strings = mv88e6320_stats_get_strings, 4225 .stats_get_stats = mv88e6320_stats_get_stats, 4226 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4227 .set_egress_port = mv88e6095_g1_set_egress_port, 4228 .watchdog_ops = &mv88e6390_watchdog_ops, 4229 .reset = mv88e6352_g1_reset, 4230 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4231 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4232 .gpio_ops = &mv88e6352_gpio_ops, 4233 .avb_ops = &mv88e6352_avb_ops, 4234 .ptp_ops = &mv88e6352_ptp_ops, 4235 .phylink_validate = mv88e6185_phylink_validate, 4236 }; 4237 4238 static const struct mv88e6xxx_ops mv88e6341_ops = { 4239 /* MV88E6XXX_FAMILY_6341 */ 4240 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4241 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4242 .irl_init_all = mv88e6352_g2_irl_init_all, 4243 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4244 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4245 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4246 .phy_read = mv88e6xxx_g2_smi_phy_read, 4247 .phy_write = mv88e6xxx_g2_smi_phy_write, 4248 .port_set_link = mv88e6xxx_port_set_link, 4249 .port_sync_link = mv88e6xxx_port_sync_link, 4250 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4251 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4252 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4253 .port_tag_remap = mv88e6095_port_tag_remap, 4254 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4255 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4256 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4257 .port_set_ether_type = mv88e6351_port_set_ether_type, 4258 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4259 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4260 .port_pause_limit = mv88e6097_port_pause_limit, 4261 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4262 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4263 .port_get_cmode = mv88e6352_port_get_cmode, 4264 .port_set_cmode = mv88e6341_port_set_cmode, 4265 .port_setup_message_port = mv88e6xxx_setup_message_port, 4266 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4267 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4268 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4269 .stats_get_strings = mv88e6320_stats_get_strings, 4270 .stats_get_stats = mv88e6390_stats_get_stats, 4271 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4272 .set_egress_port = mv88e6390_g1_set_egress_port, 4273 .watchdog_ops = &mv88e6390_watchdog_ops, 4274 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4275 .pot_clear = mv88e6xxx_g2_pot_clear, 4276 .reset = mv88e6352_g1_reset, 4277 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4278 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4279 .serdes_power = mv88e6390_serdes_power, 4280 .serdes_get_lane = mv88e6341_serdes_get_lane, 4281 /* Check status register pause & lpa register */ 4282 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4283 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4284 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4285 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4286 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4287 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4288 .serdes_irq_status = mv88e6390_serdes_irq_status, 4289 .gpio_ops = &mv88e6352_gpio_ops, 4290 .avb_ops = &mv88e6390_avb_ops, 4291 .ptp_ops = &mv88e6352_ptp_ops, 4292 .phylink_validate = mv88e6341_phylink_validate, 4293 }; 4294 4295 static const struct mv88e6xxx_ops mv88e6350_ops = { 4296 /* MV88E6XXX_FAMILY_6351 */ 4297 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4298 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4299 .irl_init_all = mv88e6352_g2_irl_init_all, 4300 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4301 .phy_read = mv88e6xxx_g2_smi_phy_read, 4302 .phy_write = mv88e6xxx_g2_smi_phy_write, 4303 .port_set_link = mv88e6xxx_port_set_link, 4304 .port_sync_link = mv88e6xxx_port_sync_link, 4305 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4306 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4307 .port_tag_remap = mv88e6095_port_tag_remap, 4308 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4309 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4310 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4311 .port_set_ether_type = mv88e6351_port_set_ether_type, 4312 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4313 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4314 .port_pause_limit = mv88e6097_port_pause_limit, 4315 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4316 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4317 .port_get_cmode = mv88e6352_port_get_cmode, 4318 .port_setup_message_port = mv88e6xxx_setup_message_port, 4319 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4320 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4321 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4322 .stats_get_strings = mv88e6095_stats_get_strings, 4323 .stats_get_stats = mv88e6095_stats_get_stats, 4324 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4325 .set_egress_port = mv88e6095_g1_set_egress_port, 4326 .watchdog_ops = &mv88e6097_watchdog_ops, 4327 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4328 .pot_clear = mv88e6xxx_g2_pot_clear, 4329 .reset = mv88e6352_g1_reset, 4330 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4331 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4332 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4333 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4334 .phylink_validate = mv88e6185_phylink_validate, 4335 }; 4336 4337 static const struct mv88e6xxx_ops mv88e6351_ops = { 4338 /* MV88E6XXX_FAMILY_6351 */ 4339 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4340 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4341 .irl_init_all = mv88e6352_g2_irl_init_all, 4342 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4343 .phy_read = mv88e6xxx_g2_smi_phy_read, 4344 .phy_write = mv88e6xxx_g2_smi_phy_write, 4345 .port_set_link = mv88e6xxx_port_set_link, 4346 .port_sync_link = mv88e6xxx_port_sync_link, 4347 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4348 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4349 .port_tag_remap = mv88e6095_port_tag_remap, 4350 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4351 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4352 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4353 .port_set_ether_type = mv88e6351_port_set_ether_type, 4354 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4355 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4356 .port_pause_limit = mv88e6097_port_pause_limit, 4357 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4358 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4359 .port_get_cmode = mv88e6352_port_get_cmode, 4360 .port_setup_message_port = mv88e6xxx_setup_message_port, 4361 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4362 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4363 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4364 .stats_get_strings = mv88e6095_stats_get_strings, 4365 .stats_get_stats = mv88e6095_stats_get_stats, 4366 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4367 .set_egress_port = mv88e6095_g1_set_egress_port, 4368 .watchdog_ops = &mv88e6097_watchdog_ops, 4369 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4370 .pot_clear = mv88e6xxx_g2_pot_clear, 4371 .reset = mv88e6352_g1_reset, 4372 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4373 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4374 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4375 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4376 .avb_ops = &mv88e6352_avb_ops, 4377 .ptp_ops = &mv88e6352_ptp_ops, 4378 .phylink_validate = mv88e6185_phylink_validate, 4379 }; 4380 4381 static const struct mv88e6xxx_ops mv88e6352_ops = { 4382 /* MV88E6XXX_FAMILY_6352 */ 4383 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4384 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4385 .irl_init_all = mv88e6352_g2_irl_init_all, 4386 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4387 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4388 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4389 .phy_read = mv88e6xxx_g2_smi_phy_read, 4390 .phy_write = mv88e6xxx_g2_smi_phy_write, 4391 .port_set_link = mv88e6xxx_port_set_link, 4392 .port_sync_link = mv88e6xxx_port_sync_link, 4393 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4394 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4395 .port_tag_remap = mv88e6095_port_tag_remap, 4396 .port_set_policy = mv88e6352_port_set_policy, 4397 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4398 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4399 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4400 .port_set_ether_type = mv88e6351_port_set_ether_type, 4401 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4402 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4403 .port_pause_limit = mv88e6097_port_pause_limit, 4404 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4405 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4406 .port_get_cmode = mv88e6352_port_get_cmode, 4407 .port_setup_message_port = mv88e6xxx_setup_message_port, 4408 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4409 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4410 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4411 .stats_get_strings = mv88e6095_stats_get_strings, 4412 .stats_get_stats = mv88e6095_stats_get_stats, 4413 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4414 .set_egress_port = mv88e6095_g1_set_egress_port, 4415 .watchdog_ops = &mv88e6097_watchdog_ops, 4416 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4417 .pot_clear = mv88e6xxx_g2_pot_clear, 4418 .reset = mv88e6352_g1_reset, 4419 .rmu_disable = mv88e6352_g1_rmu_disable, 4420 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4421 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4422 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4423 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4424 .serdes_get_lane = mv88e6352_serdes_get_lane, 4425 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4426 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4427 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4428 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4429 .serdes_power = mv88e6352_serdes_power, 4430 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4431 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4432 .serdes_irq_status = mv88e6352_serdes_irq_status, 4433 .gpio_ops = &mv88e6352_gpio_ops, 4434 .avb_ops = &mv88e6352_avb_ops, 4435 .ptp_ops = &mv88e6352_ptp_ops, 4436 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4437 .serdes_get_strings = mv88e6352_serdes_get_strings, 4438 .serdes_get_stats = mv88e6352_serdes_get_stats, 4439 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4440 .serdes_get_regs = mv88e6352_serdes_get_regs, 4441 .phylink_validate = mv88e6352_phylink_validate, 4442 }; 4443 4444 static const struct mv88e6xxx_ops mv88e6390_ops = { 4445 /* MV88E6XXX_FAMILY_6390 */ 4446 .setup_errata = mv88e6390_setup_errata, 4447 .irl_init_all = mv88e6390_g2_irl_init_all, 4448 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4449 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4450 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4451 .phy_read = mv88e6xxx_g2_smi_phy_read, 4452 .phy_write = mv88e6xxx_g2_smi_phy_write, 4453 .port_set_link = mv88e6xxx_port_set_link, 4454 .port_sync_link = mv88e6xxx_port_sync_link, 4455 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4456 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4457 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4458 .port_tag_remap = mv88e6390_port_tag_remap, 4459 .port_set_policy = mv88e6352_port_set_policy, 4460 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4461 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4462 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4463 .port_set_ether_type = mv88e6351_port_set_ether_type, 4464 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4465 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4466 .port_pause_limit = mv88e6390_port_pause_limit, 4467 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4468 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4469 .port_get_cmode = mv88e6352_port_get_cmode, 4470 .port_set_cmode = mv88e6390_port_set_cmode, 4471 .port_setup_message_port = mv88e6xxx_setup_message_port, 4472 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4473 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4474 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4475 .stats_get_strings = mv88e6320_stats_get_strings, 4476 .stats_get_stats = mv88e6390_stats_get_stats, 4477 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4478 .set_egress_port = mv88e6390_g1_set_egress_port, 4479 .watchdog_ops = &mv88e6390_watchdog_ops, 4480 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4481 .pot_clear = mv88e6xxx_g2_pot_clear, 4482 .reset = mv88e6352_g1_reset, 4483 .rmu_disable = mv88e6390_g1_rmu_disable, 4484 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4485 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4486 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4487 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4488 .serdes_power = mv88e6390_serdes_power, 4489 .serdes_get_lane = mv88e6390_serdes_get_lane, 4490 /* Check status register pause & lpa register */ 4491 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4492 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4493 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4494 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4495 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4496 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4497 .serdes_irq_status = mv88e6390_serdes_irq_status, 4498 .gpio_ops = &mv88e6352_gpio_ops, 4499 .avb_ops = &mv88e6390_avb_ops, 4500 .ptp_ops = &mv88e6352_ptp_ops, 4501 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4502 .serdes_get_strings = mv88e6390_serdes_get_strings, 4503 .serdes_get_stats = mv88e6390_serdes_get_stats, 4504 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4505 .serdes_get_regs = mv88e6390_serdes_get_regs, 4506 .phylink_validate = mv88e6390_phylink_validate, 4507 }; 4508 4509 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4510 /* MV88E6XXX_FAMILY_6390 */ 4511 .setup_errata = mv88e6390_setup_errata, 4512 .irl_init_all = mv88e6390_g2_irl_init_all, 4513 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4514 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4515 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4516 .phy_read = mv88e6xxx_g2_smi_phy_read, 4517 .phy_write = mv88e6xxx_g2_smi_phy_write, 4518 .port_set_link = mv88e6xxx_port_set_link, 4519 .port_sync_link = mv88e6xxx_port_sync_link, 4520 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4521 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4522 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4523 .port_tag_remap = mv88e6390_port_tag_remap, 4524 .port_set_policy = mv88e6352_port_set_policy, 4525 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4526 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4527 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4528 .port_set_ether_type = mv88e6351_port_set_ether_type, 4529 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4530 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4531 .port_pause_limit = mv88e6390_port_pause_limit, 4532 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4533 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4534 .port_get_cmode = mv88e6352_port_get_cmode, 4535 .port_set_cmode = mv88e6390x_port_set_cmode, 4536 .port_setup_message_port = mv88e6xxx_setup_message_port, 4537 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4538 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4539 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4540 .stats_get_strings = mv88e6320_stats_get_strings, 4541 .stats_get_stats = mv88e6390_stats_get_stats, 4542 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4543 .set_egress_port = mv88e6390_g1_set_egress_port, 4544 .watchdog_ops = &mv88e6390_watchdog_ops, 4545 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4546 .pot_clear = mv88e6xxx_g2_pot_clear, 4547 .reset = mv88e6352_g1_reset, 4548 .rmu_disable = mv88e6390_g1_rmu_disable, 4549 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4550 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4551 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4552 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4553 .serdes_power = mv88e6390_serdes_power, 4554 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4555 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4556 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4557 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4558 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4559 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4560 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4561 .serdes_irq_status = mv88e6390_serdes_irq_status, 4562 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4563 .serdes_get_strings = mv88e6390_serdes_get_strings, 4564 .serdes_get_stats = mv88e6390_serdes_get_stats, 4565 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4566 .serdes_get_regs = mv88e6390_serdes_get_regs, 4567 .gpio_ops = &mv88e6352_gpio_ops, 4568 .avb_ops = &mv88e6390_avb_ops, 4569 .ptp_ops = &mv88e6352_ptp_ops, 4570 .phylink_validate = mv88e6390x_phylink_validate, 4571 }; 4572 4573 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4574 [MV88E6085] = { 4575 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4576 .family = MV88E6XXX_FAMILY_6097, 4577 .name = "Marvell 88E6085", 4578 .num_databases = 4096, 4579 .num_macs = 8192, 4580 .num_ports = 10, 4581 .num_internal_phys = 5, 4582 .max_vid = 4095, 4583 .port_base_addr = 0x10, 4584 .phy_base_addr = 0x0, 4585 .global1_addr = 0x1b, 4586 .global2_addr = 0x1c, 4587 .age_time_coeff = 15000, 4588 .g1_irqs = 8, 4589 .g2_irqs = 10, 4590 .atu_move_port_mask = 0xf, 4591 .pvt = true, 4592 .multi_chip = true, 4593 .tag_protocol = DSA_TAG_PROTO_DSA, 4594 .ops = &mv88e6085_ops, 4595 }, 4596 4597 [MV88E6095] = { 4598 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4599 .family = MV88E6XXX_FAMILY_6095, 4600 .name = "Marvell 88E6095/88E6095F", 4601 .num_databases = 256, 4602 .num_macs = 8192, 4603 .num_ports = 11, 4604 .num_internal_phys = 0, 4605 .max_vid = 4095, 4606 .port_base_addr = 0x10, 4607 .phy_base_addr = 0x0, 4608 .global1_addr = 0x1b, 4609 .global2_addr = 0x1c, 4610 .age_time_coeff = 15000, 4611 .g1_irqs = 8, 4612 .atu_move_port_mask = 0xf, 4613 .multi_chip = true, 4614 .tag_protocol = DSA_TAG_PROTO_DSA, 4615 .ops = &mv88e6095_ops, 4616 }, 4617 4618 [MV88E6097] = { 4619 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4620 .family = MV88E6XXX_FAMILY_6097, 4621 .name = "Marvell 88E6097/88E6097F", 4622 .num_databases = 4096, 4623 .num_macs = 8192, 4624 .num_ports = 11, 4625 .num_internal_phys = 8, 4626 .max_vid = 4095, 4627 .port_base_addr = 0x10, 4628 .phy_base_addr = 0x0, 4629 .global1_addr = 0x1b, 4630 .global2_addr = 0x1c, 4631 .age_time_coeff = 15000, 4632 .g1_irqs = 8, 4633 .g2_irqs = 10, 4634 .atu_move_port_mask = 0xf, 4635 .pvt = true, 4636 .multi_chip = true, 4637 .tag_protocol = DSA_TAG_PROTO_EDSA, 4638 .ops = &mv88e6097_ops, 4639 }, 4640 4641 [MV88E6123] = { 4642 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4643 .family = MV88E6XXX_FAMILY_6165, 4644 .name = "Marvell 88E6123", 4645 .num_databases = 4096, 4646 .num_macs = 1024, 4647 .num_ports = 3, 4648 .num_internal_phys = 5, 4649 .max_vid = 4095, 4650 .port_base_addr = 0x10, 4651 .phy_base_addr = 0x0, 4652 .global1_addr = 0x1b, 4653 .global2_addr = 0x1c, 4654 .age_time_coeff = 15000, 4655 .g1_irqs = 9, 4656 .g2_irqs = 10, 4657 .atu_move_port_mask = 0xf, 4658 .pvt = true, 4659 .multi_chip = true, 4660 .tag_protocol = DSA_TAG_PROTO_EDSA, 4661 .ops = &mv88e6123_ops, 4662 }, 4663 4664 [MV88E6131] = { 4665 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4666 .family = MV88E6XXX_FAMILY_6185, 4667 .name = "Marvell 88E6131", 4668 .num_databases = 256, 4669 .num_macs = 8192, 4670 .num_ports = 8, 4671 .num_internal_phys = 0, 4672 .max_vid = 4095, 4673 .port_base_addr = 0x10, 4674 .phy_base_addr = 0x0, 4675 .global1_addr = 0x1b, 4676 .global2_addr = 0x1c, 4677 .age_time_coeff = 15000, 4678 .g1_irqs = 9, 4679 .atu_move_port_mask = 0xf, 4680 .multi_chip = true, 4681 .tag_protocol = DSA_TAG_PROTO_DSA, 4682 .ops = &mv88e6131_ops, 4683 }, 4684 4685 [MV88E6141] = { 4686 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4687 .family = MV88E6XXX_FAMILY_6341, 4688 .name = "Marvell 88E6141", 4689 .num_databases = 4096, 4690 .num_macs = 2048, 4691 .num_ports = 6, 4692 .num_internal_phys = 5, 4693 .num_gpio = 11, 4694 .max_vid = 4095, 4695 .port_base_addr = 0x10, 4696 .phy_base_addr = 0x10, 4697 .global1_addr = 0x1b, 4698 .global2_addr = 0x1c, 4699 .age_time_coeff = 3750, 4700 .atu_move_port_mask = 0x1f, 4701 .g1_irqs = 9, 4702 .g2_irqs = 10, 4703 .pvt = true, 4704 .multi_chip = true, 4705 .tag_protocol = DSA_TAG_PROTO_EDSA, 4706 .ops = &mv88e6141_ops, 4707 }, 4708 4709 [MV88E6161] = { 4710 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4711 .family = MV88E6XXX_FAMILY_6165, 4712 .name = "Marvell 88E6161", 4713 .num_databases = 4096, 4714 .num_macs = 1024, 4715 .num_ports = 6, 4716 .num_internal_phys = 5, 4717 .max_vid = 4095, 4718 .port_base_addr = 0x10, 4719 .phy_base_addr = 0x0, 4720 .global1_addr = 0x1b, 4721 .global2_addr = 0x1c, 4722 .age_time_coeff = 15000, 4723 .g1_irqs = 9, 4724 .g2_irqs = 10, 4725 .atu_move_port_mask = 0xf, 4726 .pvt = true, 4727 .multi_chip = true, 4728 .tag_protocol = DSA_TAG_PROTO_EDSA, 4729 .ptp_support = true, 4730 .ops = &mv88e6161_ops, 4731 }, 4732 4733 [MV88E6165] = { 4734 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4735 .family = MV88E6XXX_FAMILY_6165, 4736 .name = "Marvell 88E6165", 4737 .num_databases = 4096, 4738 .num_macs = 8192, 4739 .num_ports = 6, 4740 .num_internal_phys = 0, 4741 .max_vid = 4095, 4742 .port_base_addr = 0x10, 4743 .phy_base_addr = 0x0, 4744 .global1_addr = 0x1b, 4745 .global2_addr = 0x1c, 4746 .age_time_coeff = 15000, 4747 .g1_irqs = 9, 4748 .g2_irqs = 10, 4749 .atu_move_port_mask = 0xf, 4750 .pvt = true, 4751 .multi_chip = true, 4752 .tag_protocol = DSA_TAG_PROTO_DSA, 4753 .ptp_support = true, 4754 .ops = &mv88e6165_ops, 4755 }, 4756 4757 [MV88E6171] = { 4758 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4759 .family = MV88E6XXX_FAMILY_6351, 4760 .name = "Marvell 88E6171", 4761 .num_databases = 4096, 4762 .num_macs = 8192, 4763 .num_ports = 7, 4764 .num_internal_phys = 5, 4765 .max_vid = 4095, 4766 .port_base_addr = 0x10, 4767 .phy_base_addr = 0x0, 4768 .global1_addr = 0x1b, 4769 .global2_addr = 0x1c, 4770 .age_time_coeff = 15000, 4771 .g1_irqs = 9, 4772 .g2_irqs = 10, 4773 .atu_move_port_mask = 0xf, 4774 .pvt = true, 4775 .multi_chip = true, 4776 .tag_protocol = DSA_TAG_PROTO_EDSA, 4777 .ops = &mv88e6171_ops, 4778 }, 4779 4780 [MV88E6172] = { 4781 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4782 .family = MV88E6XXX_FAMILY_6352, 4783 .name = "Marvell 88E6172", 4784 .num_databases = 4096, 4785 .num_macs = 8192, 4786 .num_ports = 7, 4787 .num_internal_phys = 5, 4788 .num_gpio = 15, 4789 .max_vid = 4095, 4790 .port_base_addr = 0x10, 4791 .phy_base_addr = 0x0, 4792 .global1_addr = 0x1b, 4793 .global2_addr = 0x1c, 4794 .age_time_coeff = 15000, 4795 .g1_irqs = 9, 4796 .g2_irqs = 10, 4797 .atu_move_port_mask = 0xf, 4798 .pvt = true, 4799 .multi_chip = true, 4800 .tag_protocol = DSA_TAG_PROTO_EDSA, 4801 .ops = &mv88e6172_ops, 4802 }, 4803 4804 [MV88E6175] = { 4805 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4806 .family = MV88E6XXX_FAMILY_6351, 4807 .name = "Marvell 88E6175", 4808 .num_databases = 4096, 4809 .num_macs = 8192, 4810 .num_ports = 7, 4811 .num_internal_phys = 5, 4812 .max_vid = 4095, 4813 .port_base_addr = 0x10, 4814 .phy_base_addr = 0x0, 4815 .global1_addr = 0x1b, 4816 .global2_addr = 0x1c, 4817 .age_time_coeff = 15000, 4818 .g1_irqs = 9, 4819 .g2_irqs = 10, 4820 .atu_move_port_mask = 0xf, 4821 .pvt = true, 4822 .multi_chip = true, 4823 .tag_protocol = DSA_TAG_PROTO_EDSA, 4824 .ops = &mv88e6175_ops, 4825 }, 4826 4827 [MV88E6176] = { 4828 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4829 .family = MV88E6XXX_FAMILY_6352, 4830 .name = "Marvell 88E6176", 4831 .num_databases = 4096, 4832 .num_macs = 8192, 4833 .num_ports = 7, 4834 .num_internal_phys = 5, 4835 .num_gpio = 15, 4836 .max_vid = 4095, 4837 .port_base_addr = 0x10, 4838 .phy_base_addr = 0x0, 4839 .global1_addr = 0x1b, 4840 .global2_addr = 0x1c, 4841 .age_time_coeff = 15000, 4842 .g1_irqs = 9, 4843 .g2_irqs = 10, 4844 .atu_move_port_mask = 0xf, 4845 .pvt = true, 4846 .multi_chip = true, 4847 .tag_protocol = DSA_TAG_PROTO_EDSA, 4848 .ops = &mv88e6176_ops, 4849 }, 4850 4851 [MV88E6185] = { 4852 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4853 .family = MV88E6XXX_FAMILY_6185, 4854 .name = "Marvell 88E6185", 4855 .num_databases = 256, 4856 .num_macs = 8192, 4857 .num_ports = 10, 4858 .num_internal_phys = 0, 4859 .max_vid = 4095, 4860 .port_base_addr = 0x10, 4861 .phy_base_addr = 0x0, 4862 .global1_addr = 0x1b, 4863 .global2_addr = 0x1c, 4864 .age_time_coeff = 15000, 4865 .g1_irqs = 8, 4866 .atu_move_port_mask = 0xf, 4867 .multi_chip = true, 4868 .tag_protocol = DSA_TAG_PROTO_EDSA, 4869 .ops = &mv88e6185_ops, 4870 }, 4871 4872 [MV88E6190] = { 4873 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4874 .family = MV88E6XXX_FAMILY_6390, 4875 .name = "Marvell 88E6190", 4876 .num_databases = 4096, 4877 .num_macs = 16384, 4878 .num_ports = 11, /* 10 + Z80 */ 4879 .num_internal_phys = 9, 4880 .num_gpio = 16, 4881 .max_vid = 8191, 4882 .port_base_addr = 0x0, 4883 .phy_base_addr = 0x0, 4884 .global1_addr = 0x1b, 4885 .global2_addr = 0x1c, 4886 .tag_protocol = DSA_TAG_PROTO_DSA, 4887 .age_time_coeff = 3750, 4888 .g1_irqs = 9, 4889 .g2_irqs = 14, 4890 .pvt = true, 4891 .multi_chip = true, 4892 .atu_move_port_mask = 0x1f, 4893 .ops = &mv88e6190_ops, 4894 }, 4895 4896 [MV88E6190X] = { 4897 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4898 .family = MV88E6XXX_FAMILY_6390, 4899 .name = "Marvell 88E6190X", 4900 .num_databases = 4096, 4901 .num_macs = 16384, 4902 .num_ports = 11, /* 10 + Z80 */ 4903 .num_internal_phys = 9, 4904 .num_gpio = 16, 4905 .max_vid = 8191, 4906 .port_base_addr = 0x0, 4907 .phy_base_addr = 0x0, 4908 .global1_addr = 0x1b, 4909 .global2_addr = 0x1c, 4910 .age_time_coeff = 3750, 4911 .g1_irqs = 9, 4912 .g2_irqs = 14, 4913 .atu_move_port_mask = 0x1f, 4914 .pvt = true, 4915 .multi_chip = true, 4916 .tag_protocol = DSA_TAG_PROTO_DSA, 4917 .ops = &mv88e6190x_ops, 4918 }, 4919 4920 [MV88E6191] = { 4921 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4922 .family = MV88E6XXX_FAMILY_6390, 4923 .name = "Marvell 88E6191", 4924 .num_databases = 4096, 4925 .num_macs = 16384, 4926 .num_ports = 11, /* 10 + Z80 */ 4927 .num_internal_phys = 9, 4928 .max_vid = 8191, 4929 .port_base_addr = 0x0, 4930 .phy_base_addr = 0x0, 4931 .global1_addr = 0x1b, 4932 .global2_addr = 0x1c, 4933 .age_time_coeff = 3750, 4934 .g1_irqs = 9, 4935 .g2_irqs = 14, 4936 .atu_move_port_mask = 0x1f, 4937 .pvt = true, 4938 .multi_chip = true, 4939 .tag_protocol = DSA_TAG_PROTO_DSA, 4940 .ptp_support = true, 4941 .ops = &mv88e6191_ops, 4942 }, 4943 4944 [MV88E6220] = { 4945 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 4946 .family = MV88E6XXX_FAMILY_6250, 4947 .name = "Marvell 88E6220", 4948 .num_databases = 64, 4949 4950 /* Ports 2-4 are not routed to pins 4951 * => usable ports 0, 1, 5, 6 4952 */ 4953 .num_ports = 7, 4954 .num_internal_phys = 2, 4955 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 4956 .max_vid = 4095, 4957 .port_base_addr = 0x08, 4958 .phy_base_addr = 0x00, 4959 .global1_addr = 0x0f, 4960 .global2_addr = 0x07, 4961 .age_time_coeff = 15000, 4962 .g1_irqs = 9, 4963 .g2_irqs = 10, 4964 .atu_move_port_mask = 0xf, 4965 .dual_chip = true, 4966 .tag_protocol = DSA_TAG_PROTO_DSA, 4967 .ptp_support = true, 4968 .ops = &mv88e6250_ops, 4969 }, 4970 4971 [MV88E6240] = { 4972 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 4973 .family = MV88E6XXX_FAMILY_6352, 4974 .name = "Marvell 88E6240", 4975 .num_databases = 4096, 4976 .num_macs = 8192, 4977 .num_ports = 7, 4978 .num_internal_phys = 5, 4979 .num_gpio = 15, 4980 .max_vid = 4095, 4981 .port_base_addr = 0x10, 4982 .phy_base_addr = 0x0, 4983 .global1_addr = 0x1b, 4984 .global2_addr = 0x1c, 4985 .age_time_coeff = 15000, 4986 .g1_irqs = 9, 4987 .g2_irqs = 10, 4988 .atu_move_port_mask = 0xf, 4989 .pvt = true, 4990 .multi_chip = true, 4991 .tag_protocol = DSA_TAG_PROTO_EDSA, 4992 .ptp_support = true, 4993 .ops = &mv88e6240_ops, 4994 }, 4995 4996 [MV88E6250] = { 4997 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 4998 .family = MV88E6XXX_FAMILY_6250, 4999 .name = "Marvell 88E6250", 5000 .num_databases = 64, 5001 .num_ports = 7, 5002 .num_internal_phys = 5, 5003 .max_vid = 4095, 5004 .port_base_addr = 0x08, 5005 .phy_base_addr = 0x00, 5006 .global1_addr = 0x0f, 5007 .global2_addr = 0x07, 5008 .age_time_coeff = 15000, 5009 .g1_irqs = 9, 5010 .g2_irqs = 10, 5011 .atu_move_port_mask = 0xf, 5012 .dual_chip = true, 5013 .tag_protocol = DSA_TAG_PROTO_DSA, 5014 .ptp_support = true, 5015 .ops = &mv88e6250_ops, 5016 }, 5017 5018 [MV88E6290] = { 5019 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5020 .family = MV88E6XXX_FAMILY_6390, 5021 .name = "Marvell 88E6290", 5022 .num_databases = 4096, 5023 .num_ports = 11, /* 10 + Z80 */ 5024 .num_internal_phys = 9, 5025 .num_gpio = 16, 5026 .max_vid = 8191, 5027 .port_base_addr = 0x0, 5028 .phy_base_addr = 0x0, 5029 .global1_addr = 0x1b, 5030 .global2_addr = 0x1c, 5031 .age_time_coeff = 3750, 5032 .g1_irqs = 9, 5033 .g2_irqs = 14, 5034 .atu_move_port_mask = 0x1f, 5035 .pvt = true, 5036 .multi_chip = true, 5037 .tag_protocol = DSA_TAG_PROTO_DSA, 5038 .ptp_support = true, 5039 .ops = &mv88e6290_ops, 5040 }, 5041 5042 [MV88E6320] = { 5043 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5044 .family = MV88E6XXX_FAMILY_6320, 5045 .name = "Marvell 88E6320", 5046 .num_databases = 4096, 5047 .num_macs = 8192, 5048 .num_ports = 7, 5049 .num_internal_phys = 5, 5050 .num_gpio = 15, 5051 .max_vid = 4095, 5052 .port_base_addr = 0x10, 5053 .phy_base_addr = 0x0, 5054 .global1_addr = 0x1b, 5055 .global2_addr = 0x1c, 5056 .age_time_coeff = 15000, 5057 .g1_irqs = 8, 5058 .g2_irqs = 10, 5059 .atu_move_port_mask = 0xf, 5060 .pvt = true, 5061 .multi_chip = true, 5062 .tag_protocol = DSA_TAG_PROTO_EDSA, 5063 .ptp_support = true, 5064 .ops = &mv88e6320_ops, 5065 }, 5066 5067 [MV88E6321] = { 5068 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5069 .family = MV88E6XXX_FAMILY_6320, 5070 .name = "Marvell 88E6321", 5071 .num_databases = 4096, 5072 .num_macs = 8192, 5073 .num_ports = 7, 5074 .num_internal_phys = 5, 5075 .num_gpio = 15, 5076 .max_vid = 4095, 5077 .port_base_addr = 0x10, 5078 .phy_base_addr = 0x0, 5079 .global1_addr = 0x1b, 5080 .global2_addr = 0x1c, 5081 .age_time_coeff = 15000, 5082 .g1_irqs = 8, 5083 .g2_irqs = 10, 5084 .atu_move_port_mask = 0xf, 5085 .multi_chip = true, 5086 .tag_protocol = DSA_TAG_PROTO_EDSA, 5087 .ptp_support = true, 5088 .ops = &mv88e6321_ops, 5089 }, 5090 5091 [MV88E6341] = { 5092 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5093 .family = MV88E6XXX_FAMILY_6341, 5094 .name = "Marvell 88E6341", 5095 .num_databases = 4096, 5096 .num_macs = 2048, 5097 .num_internal_phys = 5, 5098 .num_ports = 6, 5099 .num_gpio = 11, 5100 .max_vid = 4095, 5101 .port_base_addr = 0x10, 5102 .phy_base_addr = 0x10, 5103 .global1_addr = 0x1b, 5104 .global2_addr = 0x1c, 5105 .age_time_coeff = 3750, 5106 .atu_move_port_mask = 0x1f, 5107 .g1_irqs = 9, 5108 .g2_irqs = 10, 5109 .pvt = true, 5110 .multi_chip = true, 5111 .tag_protocol = DSA_TAG_PROTO_EDSA, 5112 .ptp_support = true, 5113 .ops = &mv88e6341_ops, 5114 }, 5115 5116 [MV88E6350] = { 5117 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5118 .family = MV88E6XXX_FAMILY_6351, 5119 .name = "Marvell 88E6350", 5120 .num_databases = 4096, 5121 .num_macs = 8192, 5122 .num_ports = 7, 5123 .num_internal_phys = 5, 5124 .max_vid = 4095, 5125 .port_base_addr = 0x10, 5126 .phy_base_addr = 0x0, 5127 .global1_addr = 0x1b, 5128 .global2_addr = 0x1c, 5129 .age_time_coeff = 15000, 5130 .g1_irqs = 9, 5131 .g2_irqs = 10, 5132 .atu_move_port_mask = 0xf, 5133 .pvt = true, 5134 .multi_chip = true, 5135 .tag_protocol = DSA_TAG_PROTO_EDSA, 5136 .ops = &mv88e6350_ops, 5137 }, 5138 5139 [MV88E6351] = { 5140 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5141 .family = MV88E6XXX_FAMILY_6351, 5142 .name = "Marvell 88E6351", 5143 .num_databases = 4096, 5144 .num_macs = 8192, 5145 .num_ports = 7, 5146 .num_internal_phys = 5, 5147 .max_vid = 4095, 5148 .port_base_addr = 0x10, 5149 .phy_base_addr = 0x0, 5150 .global1_addr = 0x1b, 5151 .global2_addr = 0x1c, 5152 .age_time_coeff = 15000, 5153 .g1_irqs = 9, 5154 .g2_irqs = 10, 5155 .atu_move_port_mask = 0xf, 5156 .pvt = true, 5157 .multi_chip = true, 5158 .tag_protocol = DSA_TAG_PROTO_EDSA, 5159 .ops = &mv88e6351_ops, 5160 }, 5161 5162 [MV88E6352] = { 5163 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5164 .family = MV88E6XXX_FAMILY_6352, 5165 .name = "Marvell 88E6352", 5166 .num_databases = 4096, 5167 .num_macs = 8192, 5168 .num_ports = 7, 5169 .num_internal_phys = 5, 5170 .num_gpio = 15, 5171 .max_vid = 4095, 5172 .port_base_addr = 0x10, 5173 .phy_base_addr = 0x0, 5174 .global1_addr = 0x1b, 5175 .global2_addr = 0x1c, 5176 .age_time_coeff = 15000, 5177 .g1_irqs = 9, 5178 .g2_irqs = 10, 5179 .atu_move_port_mask = 0xf, 5180 .pvt = true, 5181 .multi_chip = true, 5182 .tag_protocol = DSA_TAG_PROTO_EDSA, 5183 .ptp_support = true, 5184 .ops = &mv88e6352_ops, 5185 }, 5186 [MV88E6390] = { 5187 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5188 .family = MV88E6XXX_FAMILY_6390, 5189 .name = "Marvell 88E6390", 5190 .num_databases = 4096, 5191 .num_macs = 16384, 5192 .num_ports = 11, /* 10 + Z80 */ 5193 .num_internal_phys = 9, 5194 .num_gpio = 16, 5195 .max_vid = 8191, 5196 .port_base_addr = 0x0, 5197 .phy_base_addr = 0x0, 5198 .global1_addr = 0x1b, 5199 .global2_addr = 0x1c, 5200 .age_time_coeff = 3750, 5201 .g1_irqs = 9, 5202 .g2_irqs = 14, 5203 .atu_move_port_mask = 0x1f, 5204 .pvt = true, 5205 .multi_chip = true, 5206 .tag_protocol = DSA_TAG_PROTO_DSA, 5207 .ptp_support = true, 5208 .ops = &mv88e6390_ops, 5209 }, 5210 [MV88E6390X] = { 5211 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5212 .family = MV88E6XXX_FAMILY_6390, 5213 .name = "Marvell 88E6390X", 5214 .num_databases = 4096, 5215 .num_macs = 16384, 5216 .num_ports = 11, /* 10 + Z80 */ 5217 .num_internal_phys = 9, 5218 .num_gpio = 16, 5219 .max_vid = 8191, 5220 .port_base_addr = 0x0, 5221 .phy_base_addr = 0x0, 5222 .global1_addr = 0x1b, 5223 .global2_addr = 0x1c, 5224 .age_time_coeff = 3750, 5225 .g1_irqs = 9, 5226 .g2_irqs = 14, 5227 .atu_move_port_mask = 0x1f, 5228 .pvt = true, 5229 .multi_chip = true, 5230 .tag_protocol = DSA_TAG_PROTO_DSA, 5231 .ptp_support = true, 5232 .ops = &mv88e6390x_ops, 5233 }, 5234 }; 5235 5236 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5237 { 5238 int i; 5239 5240 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5241 if (mv88e6xxx_table[i].prod_num == prod_num) 5242 return &mv88e6xxx_table[i]; 5243 5244 return NULL; 5245 } 5246 5247 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5248 { 5249 const struct mv88e6xxx_info *info; 5250 unsigned int prod_num, rev; 5251 u16 id; 5252 int err; 5253 5254 mv88e6xxx_reg_lock(chip); 5255 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5256 mv88e6xxx_reg_unlock(chip); 5257 if (err) 5258 return err; 5259 5260 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5261 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5262 5263 info = mv88e6xxx_lookup_info(prod_num); 5264 if (!info) 5265 return -ENODEV; 5266 5267 /* Update the compatible info with the probed one */ 5268 chip->info = info; 5269 5270 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5271 chip->info->prod_num, chip->info->name, rev); 5272 5273 return 0; 5274 } 5275 5276 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5277 { 5278 struct mv88e6xxx_chip *chip; 5279 5280 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5281 if (!chip) 5282 return NULL; 5283 5284 chip->dev = dev; 5285 5286 mutex_init(&chip->reg_lock); 5287 INIT_LIST_HEAD(&chip->mdios); 5288 idr_init(&chip->policies); 5289 5290 return chip; 5291 } 5292 5293 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5294 int port, 5295 enum dsa_tag_protocol m) 5296 { 5297 struct mv88e6xxx_chip *chip = ds->priv; 5298 5299 return chip->info->tag_protocol; 5300 } 5301 5302 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5303 const struct switchdev_obj_port_mdb *mdb) 5304 { 5305 struct mv88e6xxx_chip *chip = ds->priv; 5306 int err; 5307 5308 mv88e6xxx_reg_lock(chip); 5309 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5310 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 5311 mv88e6xxx_reg_unlock(chip); 5312 5313 return err; 5314 } 5315 5316 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5317 const struct switchdev_obj_port_mdb *mdb) 5318 { 5319 struct mv88e6xxx_chip *chip = ds->priv; 5320 int err; 5321 5322 mv88e6xxx_reg_lock(chip); 5323 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5324 mv88e6xxx_reg_unlock(chip); 5325 5326 return err; 5327 } 5328 5329 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5330 struct dsa_mall_mirror_tc_entry *mirror, 5331 bool ingress) 5332 { 5333 enum mv88e6xxx_egress_direction direction = ingress ? 5334 MV88E6XXX_EGRESS_DIR_INGRESS : 5335 MV88E6XXX_EGRESS_DIR_EGRESS; 5336 struct mv88e6xxx_chip *chip = ds->priv; 5337 bool other_mirrors = false; 5338 int i; 5339 int err; 5340 5341 if (!chip->info->ops->set_egress_port) 5342 return -EOPNOTSUPP; 5343 5344 mutex_lock(&chip->reg_lock); 5345 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5346 mirror->to_local_port) { 5347 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5348 other_mirrors |= ingress ? 5349 chip->ports[i].mirror_ingress : 5350 chip->ports[i].mirror_egress; 5351 5352 /* Can't change egress port when other mirror is active */ 5353 if (other_mirrors) { 5354 err = -EBUSY; 5355 goto out; 5356 } 5357 5358 err = chip->info->ops->set_egress_port(chip, 5359 direction, 5360 mirror->to_local_port); 5361 if (err) 5362 goto out; 5363 } 5364 5365 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5366 out: 5367 mutex_unlock(&chip->reg_lock); 5368 5369 return err; 5370 } 5371 5372 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5373 struct dsa_mall_mirror_tc_entry *mirror) 5374 { 5375 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5376 MV88E6XXX_EGRESS_DIR_INGRESS : 5377 MV88E6XXX_EGRESS_DIR_EGRESS; 5378 struct mv88e6xxx_chip *chip = ds->priv; 5379 bool other_mirrors = false; 5380 int i; 5381 5382 mutex_lock(&chip->reg_lock); 5383 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5384 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5385 5386 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5387 other_mirrors |= mirror->ingress ? 5388 chip->ports[i].mirror_ingress : 5389 chip->ports[i].mirror_egress; 5390 5391 /* Reset egress port when no other mirror is active */ 5392 if (!other_mirrors) { 5393 if (chip->info->ops->set_egress_port(chip, 5394 direction, 5395 dsa_upstream_port(ds, 5396 port))) 5397 dev_err(ds->dev, "failed to set egress port\n"); 5398 } 5399 5400 mutex_unlock(&chip->reg_lock); 5401 } 5402 5403 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 5404 struct switchdev_brport_flags flags, 5405 struct netlink_ext_ack *extack) 5406 { 5407 struct mv88e6xxx_chip *chip = ds->priv; 5408 const struct mv88e6xxx_ops *ops; 5409 5410 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD)) 5411 return -EINVAL; 5412 5413 ops = chip->info->ops; 5414 5415 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 5416 return -EINVAL; 5417 5418 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 5419 return -EINVAL; 5420 5421 return 0; 5422 } 5423 5424 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 5425 struct switchdev_brport_flags flags, 5426 struct netlink_ext_ack *extack) 5427 { 5428 struct mv88e6xxx_chip *chip = ds->priv; 5429 int err = -EOPNOTSUPP; 5430 5431 mv88e6xxx_reg_lock(chip); 5432 5433 if (flags.mask & BR_FLOOD) { 5434 bool unicast = !!(flags.val & BR_FLOOD); 5435 5436 err = chip->info->ops->port_set_ucast_flood(chip, port, 5437 unicast); 5438 if (err) 5439 goto out; 5440 } 5441 5442 if (flags.mask & BR_MCAST_FLOOD) { 5443 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 5444 5445 err = chip->info->ops->port_set_mcast_flood(chip, port, 5446 multicast); 5447 if (err) 5448 goto out; 5449 } 5450 5451 out: 5452 mv88e6xxx_reg_unlock(chip); 5453 5454 return err; 5455 } 5456 5457 static int mv88e6xxx_port_set_mrouter(struct dsa_switch *ds, int port, 5458 bool mrouter, 5459 struct netlink_ext_ack *extack) 5460 { 5461 struct mv88e6xxx_chip *chip = ds->priv; 5462 int err; 5463 5464 if (!chip->info->ops->port_set_mcast_flood) 5465 return -EOPNOTSUPP; 5466 5467 mv88e6xxx_reg_lock(chip); 5468 err = chip->info->ops->port_set_mcast_flood(chip, port, mrouter); 5469 mv88e6xxx_reg_unlock(chip); 5470 5471 return err; 5472 } 5473 5474 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 5475 struct net_device *lag, 5476 struct netdev_lag_upper_info *info) 5477 { 5478 struct mv88e6xxx_chip *chip = ds->priv; 5479 struct dsa_port *dp; 5480 int id, members = 0; 5481 5482 if (!mv88e6xxx_has_lag(chip)) 5483 return false; 5484 5485 id = dsa_lag_id(ds->dst, lag); 5486 if (id < 0 || id >= ds->num_lag_ids) 5487 return false; 5488 5489 dsa_lag_foreach_port(dp, ds->dst, lag) 5490 /* Includes the port joining the LAG */ 5491 members++; 5492 5493 if (members > 8) 5494 return false; 5495 5496 /* We could potentially relax this to include active 5497 * backup in the future. 5498 */ 5499 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 5500 return false; 5501 5502 /* Ideally we would also validate that the hash type matches 5503 * the hardware. Alas, this is always set to unknown on team 5504 * interfaces. 5505 */ 5506 return true; 5507 } 5508 5509 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag) 5510 { 5511 struct mv88e6xxx_chip *chip = ds->priv; 5512 struct dsa_port *dp; 5513 u16 map = 0; 5514 int id; 5515 5516 id = dsa_lag_id(ds->dst, lag); 5517 5518 /* Build the map of all ports to distribute flows destined for 5519 * this LAG. This can be either a local user port, or a DSA 5520 * port if the LAG port is on a remote chip. 5521 */ 5522 dsa_lag_foreach_port(dp, ds->dst, lag) 5523 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 5524 5525 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 5526 } 5527 5528 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 5529 /* Row number corresponds to the number of active members in a 5530 * LAG. Each column states which of the eight hash buckets are 5531 * mapped to the column:th port in the LAG. 5532 * 5533 * Example: In a LAG with three active ports, the second port 5534 * ([2][1]) would be selected for traffic mapped to buckets 5535 * 3,4,5 (0x38). 5536 */ 5537 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 5538 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 5539 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 5540 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 5541 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 5542 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 5543 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 5544 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 5545 }; 5546 5547 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 5548 int num_tx, int nth) 5549 { 5550 u8 active = 0; 5551 int i; 5552 5553 num_tx = num_tx <= 8 ? num_tx : 8; 5554 if (nth < num_tx) 5555 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 5556 5557 for (i = 0; i < 8; i++) { 5558 if (BIT(i) & active) 5559 mask[i] |= BIT(port); 5560 } 5561 } 5562 5563 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 5564 { 5565 struct mv88e6xxx_chip *chip = ds->priv; 5566 unsigned int id, num_tx; 5567 struct net_device *lag; 5568 struct dsa_port *dp; 5569 int i, err, nth; 5570 u16 mask[8]; 5571 u16 ivec; 5572 5573 /* Assume no port is a member of any LAG. */ 5574 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 5575 5576 /* Disable all masks for ports that _are_ members of a LAG. */ 5577 list_for_each_entry(dp, &ds->dst->ports, list) { 5578 if (!dp->lag_dev || dp->ds != ds) 5579 continue; 5580 5581 ivec &= ~BIT(dp->index); 5582 } 5583 5584 for (i = 0; i < 8; i++) 5585 mask[i] = ivec; 5586 5587 /* Enable the correct subset of masks for all LAG ports that 5588 * are in the Tx set. 5589 */ 5590 dsa_lags_foreach_id(id, ds->dst) { 5591 lag = dsa_lag_dev(ds->dst, id); 5592 if (!lag) 5593 continue; 5594 5595 num_tx = 0; 5596 dsa_lag_foreach_port(dp, ds->dst, lag) { 5597 if (dp->lag_tx_enabled) 5598 num_tx++; 5599 } 5600 5601 if (!num_tx) 5602 continue; 5603 5604 nth = 0; 5605 dsa_lag_foreach_port(dp, ds->dst, lag) { 5606 if (!dp->lag_tx_enabled) 5607 continue; 5608 5609 if (dp->ds == ds) 5610 mv88e6xxx_lag_set_port_mask(mask, dp->index, 5611 num_tx, nth); 5612 5613 nth++; 5614 } 5615 } 5616 5617 for (i = 0; i < 8; i++) { 5618 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 5619 if (err) 5620 return err; 5621 } 5622 5623 return 0; 5624 } 5625 5626 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 5627 struct net_device *lag) 5628 { 5629 int err; 5630 5631 err = mv88e6xxx_lag_sync_masks(ds); 5632 5633 if (!err) 5634 err = mv88e6xxx_lag_sync_map(ds, lag); 5635 5636 return err; 5637 } 5638 5639 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 5640 { 5641 struct mv88e6xxx_chip *chip = ds->priv; 5642 int err; 5643 5644 mv88e6xxx_reg_lock(chip); 5645 err = mv88e6xxx_lag_sync_masks(ds); 5646 mv88e6xxx_reg_unlock(chip); 5647 return err; 5648 } 5649 5650 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 5651 struct net_device *lag, 5652 struct netdev_lag_upper_info *info) 5653 { 5654 struct mv88e6xxx_chip *chip = ds->priv; 5655 int err, id; 5656 5657 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 5658 return -EOPNOTSUPP; 5659 5660 id = dsa_lag_id(ds->dst, lag); 5661 5662 mv88e6xxx_reg_lock(chip); 5663 5664 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 5665 if (err) 5666 goto err_unlock; 5667 5668 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 5669 if (err) 5670 goto err_clear_trunk; 5671 5672 mv88e6xxx_reg_unlock(chip); 5673 return 0; 5674 5675 err_clear_trunk: 5676 mv88e6xxx_port_set_trunk(chip, port, false, 0); 5677 err_unlock: 5678 mv88e6xxx_reg_unlock(chip); 5679 return err; 5680 } 5681 5682 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 5683 struct net_device *lag) 5684 { 5685 struct mv88e6xxx_chip *chip = ds->priv; 5686 int err_sync, err_trunk; 5687 5688 mv88e6xxx_reg_lock(chip); 5689 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 5690 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 5691 mv88e6xxx_reg_unlock(chip); 5692 return err_sync ? : err_trunk; 5693 } 5694 5695 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 5696 int port) 5697 { 5698 struct mv88e6xxx_chip *chip = ds->priv; 5699 int err; 5700 5701 mv88e6xxx_reg_lock(chip); 5702 err = mv88e6xxx_lag_sync_masks(ds); 5703 mv88e6xxx_reg_unlock(chip); 5704 return err; 5705 } 5706 5707 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 5708 int port, struct net_device *lag, 5709 struct netdev_lag_upper_info *info) 5710 { 5711 struct mv88e6xxx_chip *chip = ds->priv; 5712 int err; 5713 5714 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 5715 return -EOPNOTSUPP; 5716 5717 mv88e6xxx_reg_lock(chip); 5718 5719 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 5720 if (err) 5721 goto unlock; 5722 5723 err = mv88e6xxx_pvt_map(chip, sw_index, port); 5724 5725 unlock: 5726 mv88e6xxx_reg_unlock(chip); 5727 return err; 5728 } 5729 5730 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 5731 int port, struct net_device *lag) 5732 { 5733 struct mv88e6xxx_chip *chip = ds->priv; 5734 int err_sync, err_pvt; 5735 5736 mv88e6xxx_reg_lock(chip); 5737 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 5738 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 5739 mv88e6xxx_reg_unlock(chip); 5740 return err_sync ? : err_pvt; 5741 } 5742 5743 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 5744 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 5745 .setup = mv88e6xxx_setup, 5746 .teardown = mv88e6xxx_teardown, 5747 .phylink_validate = mv88e6xxx_validate, 5748 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 5749 .phylink_mac_config = mv88e6xxx_mac_config, 5750 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 5751 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 5752 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 5753 .get_strings = mv88e6xxx_get_strings, 5754 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 5755 .get_sset_count = mv88e6xxx_get_sset_count, 5756 .port_enable = mv88e6xxx_port_enable, 5757 .port_disable = mv88e6xxx_port_disable, 5758 .port_max_mtu = mv88e6xxx_get_max_mtu, 5759 .port_change_mtu = mv88e6xxx_change_mtu, 5760 .get_mac_eee = mv88e6xxx_get_mac_eee, 5761 .set_mac_eee = mv88e6xxx_set_mac_eee, 5762 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 5763 .get_eeprom = mv88e6xxx_get_eeprom, 5764 .set_eeprom = mv88e6xxx_set_eeprom, 5765 .get_regs_len = mv88e6xxx_get_regs_len, 5766 .get_regs = mv88e6xxx_get_regs, 5767 .get_rxnfc = mv88e6xxx_get_rxnfc, 5768 .set_rxnfc = mv88e6xxx_set_rxnfc, 5769 .set_ageing_time = mv88e6xxx_set_ageing_time, 5770 .port_bridge_join = mv88e6xxx_port_bridge_join, 5771 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 5772 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 5773 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 5774 .port_set_mrouter = mv88e6xxx_port_set_mrouter, 5775 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 5776 .port_fast_age = mv88e6xxx_port_fast_age, 5777 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 5778 .port_vlan_add = mv88e6xxx_port_vlan_add, 5779 .port_vlan_del = mv88e6xxx_port_vlan_del, 5780 .port_fdb_add = mv88e6xxx_port_fdb_add, 5781 .port_fdb_del = mv88e6xxx_port_fdb_del, 5782 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 5783 .port_mdb_add = mv88e6xxx_port_mdb_add, 5784 .port_mdb_del = mv88e6xxx_port_mdb_del, 5785 .port_mirror_add = mv88e6xxx_port_mirror_add, 5786 .port_mirror_del = mv88e6xxx_port_mirror_del, 5787 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 5788 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 5789 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 5790 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 5791 .port_txtstamp = mv88e6xxx_port_txtstamp, 5792 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 5793 .get_ts_info = mv88e6xxx_get_ts_info, 5794 .devlink_param_get = mv88e6xxx_devlink_param_get, 5795 .devlink_param_set = mv88e6xxx_devlink_param_set, 5796 .devlink_info_get = mv88e6xxx_devlink_info_get, 5797 .port_lag_change = mv88e6xxx_port_lag_change, 5798 .port_lag_join = mv88e6xxx_port_lag_join, 5799 .port_lag_leave = mv88e6xxx_port_lag_leave, 5800 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 5801 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 5802 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 5803 }; 5804 5805 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 5806 { 5807 struct device *dev = chip->dev; 5808 struct dsa_switch *ds; 5809 5810 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 5811 if (!ds) 5812 return -ENOMEM; 5813 5814 ds->dev = dev; 5815 ds->num_ports = mv88e6xxx_num_ports(chip); 5816 ds->priv = chip; 5817 ds->dev = dev; 5818 ds->ops = &mv88e6xxx_switch_ops; 5819 ds->ageing_time_min = chip->info->age_time_coeff; 5820 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 5821 5822 /* Some chips support up to 32, but that requires enabling the 5823 * 5-bit port mode, which we do not support. 640k^W16 ought to 5824 * be enough for anyone. 5825 */ 5826 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 5827 5828 dev_set_drvdata(dev, ds); 5829 5830 return dsa_register_switch(ds); 5831 } 5832 5833 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 5834 { 5835 dsa_unregister_switch(chip->ds); 5836 } 5837 5838 static const void *pdata_device_get_match_data(struct device *dev) 5839 { 5840 const struct of_device_id *matches = dev->driver->of_match_table; 5841 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 5842 5843 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 5844 matches++) { 5845 if (!strcmp(pdata->compatible, matches->compatible)) 5846 return matches->data; 5847 } 5848 return NULL; 5849 } 5850 5851 /* There is no suspend to RAM support at DSA level yet, the switch configuration 5852 * would be lost after a power cycle so prevent it to be suspended. 5853 */ 5854 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 5855 { 5856 return -EOPNOTSUPP; 5857 } 5858 5859 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 5860 { 5861 return 0; 5862 } 5863 5864 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 5865 5866 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 5867 { 5868 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 5869 const struct mv88e6xxx_info *compat_info = NULL; 5870 struct device *dev = &mdiodev->dev; 5871 struct device_node *np = dev->of_node; 5872 struct mv88e6xxx_chip *chip; 5873 int port; 5874 int err; 5875 5876 if (!np && !pdata) 5877 return -EINVAL; 5878 5879 if (np) 5880 compat_info = of_device_get_match_data(dev); 5881 5882 if (pdata) { 5883 compat_info = pdata_device_get_match_data(dev); 5884 5885 if (!pdata->netdev) 5886 return -EINVAL; 5887 5888 for (port = 0; port < DSA_MAX_PORTS; port++) { 5889 if (!(pdata->enabled_ports & (1 << port))) 5890 continue; 5891 if (strcmp(pdata->cd.port_names[port], "cpu")) 5892 continue; 5893 pdata->cd.netdev[port] = &pdata->netdev->dev; 5894 break; 5895 } 5896 } 5897 5898 if (!compat_info) 5899 return -EINVAL; 5900 5901 chip = mv88e6xxx_alloc_chip(dev); 5902 if (!chip) { 5903 err = -ENOMEM; 5904 goto out; 5905 } 5906 5907 chip->info = compat_info; 5908 5909 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 5910 if (err) 5911 goto out; 5912 5913 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 5914 if (IS_ERR(chip->reset)) { 5915 err = PTR_ERR(chip->reset); 5916 goto out; 5917 } 5918 if (chip->reset) 5919 usleep_range(1000, 2000); 5920 5921 err = mv88e6xxx_detect(chip); 5922 if (err) 5923 goto out; 5924 5925 mv88e6xxx_phy_init(chip); 5926 5927 if (chip->info->ops->get_eeprom) { 5928 if (np) 5929 of_property_read_u32(np, "eeprom-length", 5930 &chip->eeprom_len); 5931 else 5932 chip->eeprom_len = pdata->eeprom_len; 5933 } 5934 5935 mv88e6xxx_reg_lock(chip); 5936 err = mv88e6xxx_switch_reset(chip); 5937 mv88e6xxx_reg_unlock(chip); 5938 if (err) 5939 goto out; 5940 5941 if (np) { 5942 chip->irq = of_irq_get(np, 0); 5943 if (chip->irq == -EPROBE_DEFER) { 5944 err = chip->irq; 5945 goto out; 5946 } 5947 } 5948 5949 if (pdata) 5950 chip->irq = pdata->irq; 5951 5952 /* Has to be performed before the MDIO bus is created, because 5953 * the PHYs will link their interrupts to these interrupt 5954 * controllers 5955 */ 5956 mv88e6xxx_reg_lock(chip); 5957 if (chip->irq > 0) 5958 err = mv88e6xxx_g1_irq_setup(chip); 5959 else 5960 err = mv88e6xxx_irq_poll_setup(chip); 5961 mv88e6xxx_reg_unlock(chip); 5962 5963 if (err) 5964 goto out; 5965 5966 if (chip->info->g2_irqs > 0) { 5967 err = mv88e6xxx_g2_irq_setup(chip); 5968 if (err) 5969 goto out_g1_irq; 5970 } 5971 5972 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 5973 if (err) 5974 goto out_g2_irq; 5975 5976 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 5977 if (err) 5978 goto out_g1_atu_prob_irq; 5979 5980 err = mv88e6xxx_mdios_register(chip, np); 5981 if (err) 5982 goto out_g1_vtu_prob_irq; 5983 5984 err = mv88e6xxx_register_switch(chip); 5985 if (err) 5986 goto out_mdio; 5987 5988 return 0; 5989 5990 out_mdio: 5991 mv88e6xxx_mdios_unregister(chip); 5992 out_g1_vtu_prob_irq: 5993 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5994 out_g1_atu_prob_irq: 5995 mv88e6xxx_g1_atu_prob_irq_free(chip); 5996 out_g2_irq: 5997 if (chip->info->g2_irqs > 0) 5998 mv88e6xxx_g2_irq_free(chip); 5999 out_g1_irq: 6000 if (chip->irq > 0) 6001 mv88e6xxx_g1_irq_free(chip); 6002 else 6003 mv88e6xxx_irq_poll_free(chip); 6004 out: 6005 if (pdata) 6006 dev_put(pdata->netdev); 6007 6008 return err; 6009 } 6010 6011 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 6012 { 6013 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6014 struct mv88e6xxx_chip *chip = ds->priv; 6015 6016 if (chip->info->ptp_support) { 6017 mv88e6xxx_hwtstamp_free(chip); 6018 mv88e6xxx_ptp_free(chip); 6019 } 6020 6021 mv88e6xxx_phy_destroy(chip); 6022 mv88e6xxx_unregister_switch(chip); 6023 mv88e6xxx_mdios_unregister(chip); 6024 6025 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6026 mv88e6xxx_g1_atu_prob_irq_free(chip); 6027 6028 if (chip->info->g2_irqs > 0) 6029 mv88e6xxx_g2_irq_free(chip); 6030 6031 if (chip->irq > 0) 6032 mv88e6xxx_g1_irq_free(chip); 6033 else 6034 mv88e6xxx_irq_poll_free(chip); 6035 } 6036 6037 static const struct of_device_id mv88e6xxx_of_match[] = { 6038 { 6039 .compatible = "marvell,mv88e6085", 6040 .data = &mv88e6xxx_table[MV88E6085], 6041 }, 6042 { 6043 .compatible = "marvell,mv88e6190", 6044 .data = &mv88e6xxx_table[MV88E6190], 6045 }, 6046 { 6047 .compatible = "marvell,mv88e6250", 6048 .data = &mv88e6xxx_table[MV88E6250], 6049 }, 6050 { /* sentinel */ }, 6051 }; 6052 6053 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 6054 6055 static struct mdio_driver mv88e6xxx_driver = { 6056 .probe = mv88e6xxx_probe, 6057 .remove = mv88e6xxx_remove, 6058 .mdiodrv.driver = { 6059 .name = "mv88e6085", 6060 .of_match_table = mv88e6xxx_of_match, 6061 .pm = &mv88e6xxx_pm_ops, 6062 }, 6063 }; 6064 6065 mdio_module_driver(mv88e6xxx_driver); 6066 6067 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 6068 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 6069 MODULE_LICENSE("GPL"); 6070